2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __FSL_SATA_H__
22 #define __FSL_SATA_H__
24 #define DWC_AHSATA_MAX_CMD_SLOTS 32
26 /* Max host controller numbers */
27 #define SATA_HC_MAX_NUM 4
28 /* Max command queue depth per host controller */
29 #define DWC_AHSATA_HC_MAX_CMD 32
30 /* Max port number per host controller */
31 #define SATA_HC_MAX_PORT 16
33 /* Generic Host Register */
35 /* HBA Capabilities Register */
36 #define SATA_HOST_CAP_S64A 0x80000000
37 #define SATA_HOST_CAP_SNCQ 0x40000000
38 #define SATA_HOST_CAP_SSNTF 0x20000000
39 #define SATA_HOST_CAP_SMPS 0x10000000
40 #define SATA_HOST_CAP_SSS 0x08000000
41 #define SATA_HOST_CAP_SALP 0x04000000
42 #define SATA_HOST_CAP_SAL 0x02000000
43 #define SATA_HOST_CAP_SCLO 0x01000000
44 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
45 #define SATA_HOST_CAP_ISS_OFFSET 20
46 #define SATA_HOST_CAP_SNZO 0x00080000
47 #define SATA_HOST_CAP_SAM 0x00040000
48 #define SATA_HOST_CAP_SPM 0x00020000
49 #define SATA_HOST_CAP_PMD 0x00008000
50 #define SATA_HOST_CAP_SSC 0x00004000
51 #define SATA_HOST_CAP_PSC 0x00002000
52 #define SATA_HOST_CAP_NCS 0x00001f00
53 #define SATA_HOST_CAP_CCCS 0x00000080
54 #define SATA_HOST_CAP_EMS 0x00000040
55 #define SATA_HOST_CAP_SXS 0x00000020
56 #define SATA_HOST_CAP_NP_MASK 0x0000001f
58 /* Global HBA Control Register */
59 #define SATA_HOST_GHC_AE 0x80000000
60 #define SATA_HOST_GHC_IE 0x00000002
61 #define SATA_HOST_GHC_HR 0x00000001
63 /* Interrupt Status Register */
65 /* Ports Implemented Register */
67 /* AHCI Version Register */
68 #define SATA_HOST_VS_MJR_MASK 0xffff0000
69 #define SATA_HOST_VS_MJR_OFFSET 16
70 #define SATA_HOST_VS_MJR_MNR 0x0000ffff
72 /* Command Completion Coalescing Control */
73 #define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000
74 #define SATA_HOST_CCC_CTL_TV_OFFSET 16
75 #define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00
76 #define SATA_HOST_CCC_CTL_CC_OFFSET 8
77 #define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8
78 #define SATA_HOST_CCC_CTL_INT_OFFSET 3
79 #define SATA_HOST_CCC_CTL_EN 0x00000001
81 /* Command Completion Coalescing Ports */
83 /* HBA Capabilities Extended Register */
84 #define SATA_HOST_CAP2_APST 0x00000004
86 /* BIST Activate FIS Register */
87 #define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00
88 #define SATA_HOST_BISTAFR_NCP_OFFSET 8
89 #define SATA_HOST_BISTAFR_PD_MASK 0x000000ff
90 #define SATA_HOST_BISTAFR_PD_OFFSET 0
92 /* BIST Control Register */
93 #define SATA_HOST_BISTCR_FERLB 0x00100000
94 #define SATA_HOST_BISTCR_TXO 0x00040000
95 #define SATA_HOST_BISTCR_CNTCLR 0x00020000
96 #define SATA_HOST_BISTCR_NEALB 0x00010000
97 #define SATA_HOST_BISTCR_LLC_MASK 0x00000700
98 #define SATA_HOST_BISTCR_LLC_OFFSET 8
99 #define SATA_HOST_BISTCR_ERREN 0x00000040
100 #define SATA_HOST_BISTCR_FLIP 0x00000020
101 #define SATA_HOST_BISTCR_PV 0x00000010
102 #define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f
103 #define SATA_HOST_BISTCR_PATTERN_OFFSET 0
105 /* BIST FIS Count Register */
107 /* BIST Status Register */
108 #define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff
109 #define SATA_HOST_BISTSR_FRAMERR_OFFSET 0
110 #define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000
111 #define SATA_HOST_BISTSR_BRSTERR_OFFSET 16
113 /* BIST DWORD Error Count Register */
116 #define SATA_HOST_OOBR_WE 0x80000000
117 #define SATA_HOST_OOBR_cwMin_MASK 0x7f000000
118 #define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000
119 #define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00
120 #define SATA_HOST_OOBR_ciMax_MASK 0x000000ff
122 /* Timer 1-ms Register */
124 /* Global Parameter 1 Register */
125 #define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000
126 #define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000
127 #define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000
128 #define SATA_HOST_GPARAM1R_PHY_RST 0x08000000
129 #define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000
130 #define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000
131 #define SATA_HOST_GPARAM1R_LATCH_M 0x00004000
132 #define SATA_HOST_GPARAM1R_BIST_M 0x00002000
133 #define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000
134 #define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400
135 #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300
136 #define SATA_HOST_GPARAM1R_S_HADDR 0X00000080
137 #define SATA_HOST_GPARAM1R_M_HADDR 0X00000040
139 /* Global Parameter 2 Register */
140 #define SATA_HOST_GPARAM2R_DEV_CP 0x00004000
141 #define SATA_HOST_GPARAM2R_DEV_MP 0x00002000
142 #define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000
143 #define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800
144 #define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400
145 #define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200
146 #define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff
148 /* Port Parameter Register */
149 #define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200
150 #define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100
151 #define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080
152 #define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040
153 #define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038
154 #define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007
157 #define SATA_HOST_TESTR_PSEL_MASK 0x00070000
158 #define SATA_HOST_TESTR_TEST_IF 0x00000001
160 /* Port Register Descriptions */
161 /* Port# Command List Base Address Register */
162 #define SATA_PORT_CLB_CLB_MASK 0xfffffc00
164 /* Port# Command List Base Address Upper 32-Bits Register */
166 /* Port# FIS Base Address Register */
167 #define SATA_PORT_FB_FB_MASK 0xfffffff0
169 /* Port# FIS Base Address Upper 32-Bits Register */
171 /* Port# Interrupt Status Register */
172 #define SATA_PORT_IS_CPDS 0x80000000
173 #define SATA_PORT_IS_TFES 0x40000000
174 #define SATA_PORT_IS_HBFS 0x20000000
175 #define SATA_PORT_IS_HBDS 0x10000000
176 #define SATA_PORT_IS_IFS 0x08000000
177 #define SATA_PORT_IS_INFS 0x04000000
178 #define SATA_PORT_IS_OFS 0x01000000
179 #define SATA_PORT_IS_IPMS 0x00800000
180 #define SATA_PORT_IS_PRCS 0x00400000
181 #define SATA_PORT_IS_DMPS 0x00000080
182 #define SATA_PORT_IS_PCS 0x00000040
183 #define SATA_PORT_IS_DPS 0x00000020
184 #define SATA_PORT_IS_UFS 0x00000010
185 #define SATA_PORT_IS_SDBS 0x00000008
186 #define SATA_PORT_IS_DSS 0x00000004
187 #define SATA_PORT_IS_PSS 0x00000002
188 #define SATA_PORT_IS_DHRS 0x00000001
190 /* Port# Interrupt Enable Register */
191 #define SATA_PORT_IE_CPDE 0x80000000
192 #define SATA_PORT_IE_TFEE 0x40000000
193 #define SATA_PORT_IE_HBFE 0x20000000
194 #define SATA_PORT_IE_HBDE 0x10000000
195 #define SATA_PORT_IE_IFE 0x08000000
196 #define SATA_PORT_IE_INFE 0x04000000
197 #define SATA_PORT_IE_OFE 0x01000000
198 #define SATA_PORT_IE_IPME 0x00800000
199 #define SATA_PORT_IE_PRCE 0x00400000
200 #define SATA_PORT_IE_DMPE 0x00000080
201 #define SATA_PORT_IE_PCE 0x00000040
202 #define SATA_PORT_IE_DPE 0x00000020
203 #define SATA_PORT_IE_UFE 0x00000010
204 #define SATA_PORT_IE_SDBE 0x00000008
205 #define SATA_PORT_IE_DSE 0x00000004
206 #define SATA_PORT_IE_PSE 0x00000002
207 #define SATA_PORT_IE_DHRE 0x00000001
209 /* Port# Command Register */
210 #define SATA_PORT_CMD_ICC_MASK 0xf0000000
211 #define SATA_PORT_CMD_ASP 0x08000000
212 #define SATA_PORT_CMD_ALPE 0x04000000
213 #define SATA_PORT_CMD_DLAE 0x02000000
214 #define SATA_PORT_CMD_ATAPI 0x01000000
215 #define SATA_PORT_CMD_APSTE 0x00800000
216 #define SATA_PORT_CMD_ESP 0x00200000
217 #define SATA_PORT_CMD_CPD 0x00100000
218 #define SATA_PORT_CMD_MPSP 0x00080000
219 #define SATA_PORT_CMD_HPCP 0x00040000
220 #define SATA_PORT_CMD_PMA 0x00020000
221 #define SATA_PORT_CMD_CPS 0x00010000
222 #define SATA_PORT_CMD_CR 0x00008000
223 #define SATA_PORT_CMD_FR 0x00004000
224 #define SATA_PORT_CMD_MPSS 0x00002000
225 #define SATA_PORT_CMD_CCS_MASK 0x00001f00
226 #define SATA_PORT_CMD_FRE 0x00000010
227 #define SATA_PORT_CMD_CLO 0x00000008
228 #define SATA_PORT_CMD_POD 0x00000004
229 #define SATA_PORT_CMD_SUD 0x00000002
230 #define SATA_PORT_CMD_ST 0x00000001
232 /* Port# Task File Data Register */
233 #define SATA_PORT_TFD_ERR_MASK 0x0000ff00
234 #define SATA_PORT_TFD_STS_MASK 0x000000ff
235 #define SATA_PORT_TFD_STS_ERR 0x00000001
236 #define SATA_PORT_TFD_STS_DRQ 0x00000008
237 #define SATA_PORT_TFD_STS_BSY 0x00000080
239 /* Port# Signature Register */
241 /* Port# Serial ATA Status {SStatus} Register */
242 #define SATA_PORT_SSTS_IPM_MASK 0x00000f00
243 #define SATA_PORT_SSTS_SPD_MASK 0x000000f0
244 #define SATA_PORT_SSTS_DET_MASK 0x0000000f
246 /* Port# Serial ATA Control {SControl} Register */
247 #define SATA_PORT_SCTL_IPM_MASK 0x00000f00
248 #define SATA_PORT_SCTL_SPD_MASK 0x000000f0
249 #define SATA_PORT_SCTL_DET_MASK 0x0000000f
251 /* Port# Serial ATA Error {SError} Register */
252 #define SATA_PORT_SERR_DIAG_X 0x04000000
253 #define SATA_PORT_SERR_DIAG_F 0x02000000
254 #define SATA_PORT_SERR_DIAG_T 0x01000000
255 #define SATA_PORT_SERR_DIAG_S 0x00800000
256 #define SATA_PORT_SERR_DIAG_H 0x00400000
257 #define SATA_PORT_SERR_DIAG_C 0x00200000
258 #define SATA_PORT_SERR_DIAG_D 0x00100000
259 #define SATA_PORT_SERR_DIAG_B 0x00080000
260 #define SATA_PORT_SERR_DIAG_W 0x00040000
261 #define SATA_PORT_SERR_DIAG_I 0x00020000
262 #define SATA_PORT_SERR_DIAG_N 0x00010000
263 #define SATA_PORT_SERR_ERR_E 0x00000800
264 #define SATA_PORT_SERR_ERR_P 0x00000400
265 #define SATA_PORT_SERR_ERR_C 0x00000200
266 #define SATA_PORT_SERR_ERR_T 0x00000100
267 #define SATA_PORT_SERR_ERR_M 0x00000002
268 #define SATA_PORT_SERR_ERR_I 0x00000001
270 /* Port# Serial ATA Active {SActive} Register */
272 /* Port# Command Issue Register */
274 /* Port# Serial ATA Notification Register */
276 /* Port# DMA Control Register */
277 #define SATA_PORT_DMACR_RXABL_MASK 0x0000f000
278 #define SATA_PORT_DMACR_TXABL_MASK 0x00000f00
279 #define SATA_PORT_DMACR_RXTS_MASK 0x000000f0
280 #define SATA_PORT_DMACR_TXTS_MASK 0x0000000f
282 /* Port# PHY Control Register */
284 /* Port# PHY Status Register */
286 #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
290 #define CMD_HDR_DI_CFL_MASK 0x0000001f
291 #define CMD_HDR_DI_CFL_OFFSET 0
292 #define CMD_HDR_DI_A 0x00000020
293 #define CMD_HDR_DI_W 0x00000040
294 #define CMD_HDR_DI_P 0x00000080
295 #define CMD_HDR_DI_R 0x00000100
296 #define CMD_HDR_DI_B 0x00000200
297 #define CMD_HDR_DI_C 0x00000400
298 #define CMD_HDR_DI_PMP_MASK 0x0000f000
299 #define CMD_HDR_DI_PMP_OFFSET 12
300 #define CMD_HDR_DI_PRDTL 0xffff0000
301 #define CMD_HDR_DI_PRDTL_OFFSET 16
305 #define CMD_HDR_PRD_ENTRY_SHIFT 16
306 #define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
307 #define CMD_HDR_FIS_LEN_SHIFT 2
311 #define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */
312 #define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */
313 /* Snoop enable for all descriptor */
314 #define CMD_HDR_ATTR_SNOOP 0x00000200
315 #define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */
316 #define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */
317 /* BIST - require the host to enter BIST mode */
318 #define CMD_HDR_ATTR_BIST 0x00000040
319 #define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */
320 #define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */
322 #define FLAGS_DMA 0x00000000
323 #define FLAGS_FPDMA 0x00000001
325 #define SATA_FLAG_Q_DEP_MASK 0x0000000f
326 #define SATA_FLAG_WCACHE 0x00000100
327 #define SATA_FLAG_FLUSH 0x00000200
328 #define SATA_FLAG_FLUSH_EXT 0x00000400
333 #endif /* __FSL_SATA_H__ */