2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 struct ahci_probe_ent *probe_ent = NULL;
41 hd_driveid_t *ataid[AHCI_MAX_PORTS];
43 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46 * Some controllers limit number of blocks they can read/write at once.
47 * Contemporary SSD devices work much faster if the read/write size is aligned
48 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
51 #ifndef MAX_SATA_BLOCKS_READ_WRITE
52 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
55 /* Maximum timeouts for each event */
56 #define WAIT_MS_DATAIO 5000
57 #define WAIT_MS_LINKUP 4
59 static inline u32 ahci_port_base(u32 base, u32 port)
61 return base + 0x100 + (port * 0x80);
65 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
66 unsigned int port_idx)
68 base = ahci_port_base(base, port_idx);
70 port->cmd_addr = base;
71 port->scr_addr = base + PORT_SCR;
75 #define msleep(a) udelay(a * 1000)
77 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
79 const unsigned long start = begin;
80 const unsigned long end = start + len;
82 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
83 flush_dcache_range(start, end);
87 * SATA controller DMAs to physical RAM. Ensure data from the
88 * controller is invalidated from dcache; next access comes from
91 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
93 const unsigned long start = begin;
94 const unsigned long end = start + len;
96 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
97 invalidate_dcache_range(start, end);
101 * Ensure data for SATA controller is flushed out of dcache and
102 * written to physical memory.
104 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
106 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
107 AHCI_PORT_PRIV_DMA_SZ);
110 static int waiting_for_cmd_completed(volatile u8 *offset,
117 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
120 return (i < timeout_msec) ? 0 : -1;
124 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
126 #ifndef CONFIG_SCSI_AHCI_PLAT
127 pci_dev_t pdev = probe_ent->dev;
129 unsigned short vendor;
131 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
134 volatile u8 *port_mmio;
136 debug("ahci_host_init: start\n");
138 cap_save = readl(mmio + HOST_CAP);
139 cap_save &= ((1 << 28) | (1 << 17));
140 cap_save |= (1 << 27);
142 /* global controller reset */
143 tmp = readl(mmio + HOST_CTL);
144 if ((tmp & HOST_RESET) == 0)
145 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
147 /* reset must complete within 1 second, or
148 * the hardware should be considered fried.
153 tmp = readl(mmio + HOST_CTL);
155 debug("controller reset failed (0x%x)\n", tmp);
158 } while (tmp & HOST_RESET);
160 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
161 writel(cap_save, mmio + HOST_CAP);
162 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
164 #ifndef CONFIG_SCSI_AHCI_PLAT
165 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
167 if (vendor == PCI_VENDOR_ID_INTEL) {
169 pci_read_config_word(pdev, 0x92, &tmp16);
171 pci_write_config_word(pdev, 0x92, tmp16);
174 probe_ent->cap = readl(mmio + HOST_CAP);
175 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
176 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
178 debug("cap 0x%x port_map 0x%x n_ports %d\n",
179 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
181 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
182 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
184 for (i = 0; i < probe_ent->n_ports; i++) {
185 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
186 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
187 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
189 /* make sure port is not active */
190 tmp = readl(port_mmio + PORT_CMD);
191 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
192 PORT_CMD_FIS_RX | PORT_CMD_START)) {
193 debug("Port %d is active. Deactivating.\n", i);
194 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
195 PORT_CMD_FIS_RX | PORT_CMD_START);
196 writel_with_flush(tmp, port_mmio + PORT_CMD);
198 /* spec says 500 msecs for each bit, so
199 * this is slightly incorrect.
204 debug("Spinning up port %d... ", i);
205 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
208 while (j < WAIT_MS_LINKUP) {
209 tmp = readl(port_mmio + PORT_SCR_STAT);
210 if ((tmp & 0xf) == 0x3)
215 if (j == WAIT_MS_LINKUP)
220 tmp = readl(port_mmio + PORT_SCR_ERR);
221 debug("PORT_SCR_ERR 0x%x\n", tmp);
222 writel(tmp, port_mmio + PORT_SCR_ERR);
224 /* ack any pending irq events for this port */
225 tmp = readl(port_mmio + PORT_IRQ_STAT);
226 debug("PORT_IRQ_STAT 0x%x\n", tmp);
228 writel(tmp, port_mmio + PORT_IRQ_STAT);
230 writel(1 << i, mmio + HOST_IRQ_STAT);
232 /* set irq mask (enables interrupts) */
233 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
235 /* register linkup ports */
236 tmp = readl(port_mmio + PORT_SCR_STAT);
237 debug("Port %d status: 0x%x\n", i, tmp);
238 if ((tmp & 0xf) == 0x03)
239 probe_ent->link_port_map |= (0x01 << i);
242 tmp = readl(mmio + HOST_CTL);
243 debug("HOST_CTL 0x%x\n", tmp);
244 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
245 tmp = readl(mmio + HOST_CTL);
246 debug("HOST_CTL 0x%x\n", tmp);
247 #ifndef CONFIG_SCSI_AHCI_PLAT
248 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
249 tmp |= PCI_COMMAND_MASTER;
250 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
256 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
258 #ifndef CONFIG_SCSI_AHCI_PLAT
259 pci_dev_t pdev = probe_ent->dev;
262 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
263 u32 vers, cap, cap2, impl, speed;
267 vers = readl(mmio + HOST_VERSION);
268 cap = probe_ent->cap;
269 cap2 = readl(mmio + HOST_CAP2);
270 impl = probe_ent->port_map;
272 speed = (cap >> 20) & 0xf;
282 #ifdef CONFIG_SCSI_AHCI_PLAT
285 pci_read_config_word(pdev, 0x0a, &cc);
288 else if (cc == 0x0106)
290 else if (cc == 0x0104)
295 printf("AHCI %02x%02x.%02x%02x "
296 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
301 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
307 cap & (1 << 31) ? "64bit " : "",
308 cap & (1 << 30) ? "ncq " : "",
309 cap & (1 << 28) ? "ilck " : "",
310 cap & (1 << 27) ? "stag " : "",
311 cap & (1 << 26) ? "pm " : "",
312 cap & (1 << 25) ? "led " : "",
313 cap & (1 << 24) ? "clo " : "",
314 cap & (1 << 19) ? "nz " : "",
315 cap & (1 << 18) ? "only " : "",
316 cap & (1 << 17) ? "pmp " : "",
317 cap & (1 << 16) ? "fbss " : "",
318 cap & (1 << 15) ? "pio " : "",
319 cap & (1 << 14) ? "slum " : "",
320 cap & (1 << 13) ? "part " : "",
321 cap & (1 << 7) ? "ccc " : "",
322 cap & (1 << 6) ? "ems " : "",
323 cap & (1 << 5) ? "sxs " : "",
324 cap2 & (1 << 2) ? "apst " : "",
325 cap2 & (1 << 1) ? "nvmp " : "",
326 cap2 & (1 << 0) ? "boh " : "");
329 #ifndef CONFIG_SCSI_AHCI_PLAT
330 static int ahci_init_one(pci_dev_t pdev)
335 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
337 probe_ent = malloc(sizeof(struct ahci_probe_ent));
338 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
339 probe_ent->dev = pdev;
341 probe_ent->host_flags = ATA_FLAG_SATA
346 probe_ent->pio_mask = 0x1f;
347 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
349 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
350 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
353 * JMicron-specific fixup:
354 * make sure we're in AHCI mode
356 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
357 if (vendor == 0x197b)
358 pci_write_config_byte(pdev, 0x41, 0xa1);
360 /* initialize adapter */
361 rc = ahci_host_init(probe_ent);
365 ahci_print_info(probe_ent);
374 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
376 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
378 struct ahci_ioports *pp = &(probe_ent->port[port]);
379 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
383 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
384 if (sg_count > AHCI_MAX_SG) {
385 printf("Error:Too much sg!\n");
389 for (i = 0; i < sg_count; i++) {
391 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
392 ahci_sg->addr_hi = 0;
393 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
394 (buf_len < MAX_DATA_BYTE_COUNT
396 : (MAX_DATA_BYTE_COUNT - 1)));
398 buf_len -= MAX_DATA_BYTE_COUNT;
405 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
407 pp->cmd_slot->opts = cpu_to_le32(opts);
408 pp->cmd_slot->status = 0;
409 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
410 pp->cmd_slot->tbl_addr_hi = 0;
414 #ifdef CONFIG_AHCI_SETFEATURES_XFER
415 static void ahci_set_feature(u8 port)
417 struct ahci_ioports *pp = &(probe_ent->port[port]);
418 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
419 u32 cmd_fis_len = 5; /* five dwords */
423 memset(fis, 0, sizeof(fis));
426 fis[2] = ATA_CMD_SETF;
427 fis[3] = SETFEATURES_XFER;
428 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
430 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
431 ahci_fill_cmd_slot(pp, cmd_fis_len);
432 ahci_dcache_flush_sata_cmd(pp);
433 writel(1, port_mmio + PORT_CMD_ISSUE);
434 readl(port_mmio + PORT_CMD_ISSUE);
436 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
437 WAIT_MS_DATAIO, 0x1)) {
438 printf("set feature error on port %d!\n", port);
444 static int ahci_port_start(u8 port)
446 struct ahci_ioports *pp = &(probe_ent->port[port]);
447 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
451 debug("Enter start port: %d\n", port);
452 port_status = readl(port_mmio + PORT_SCR_STAT);
453 debug("Port %d status: %x\n", port, port_status);
454 if ((port_status & 0xf) != 0x03) {
455 printf("No Link on this port!\n");
459 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
462 printf("No mem for table!\n");
466 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
467 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
470 * First item in chunk of DMA memory: 32-slot command table,
471 * 32 bytes each in size
474 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
475 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
476 mem += (AHCI_CMD_SLOT_SZ + 224);
479 * Second item: Received-FIS area
481 pp->rx_fis = virt_to_phys((void *)mem);
482 mem += AHCI_RX_FIS_SZ;
485 * Third item: data area for storing a single command
486 * and its scatter-gather table
488 pp->cmd_tbl = virt_to_phys((void *)mem);
489 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
491 mem += AHCI_CMD_TBL_HDR;
493 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
495 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
497 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
499 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
500 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
501 PORT_CMD_START, port_mmio + PORT_CMD);
503 debug("Exit start port %d\n", port);
509 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
510 int buf_len, u8 is_write)
513 struct ahci_ioports *pp = &(probe_ent->port[port]);
514 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
519 debug("Enter %s: for port %d\n", __func__, port);
521 if (port > probe_ent->n_ports) {
522 printf("Invalid port number %d\n", port);
526 port_status = readl(port_mmio + PORT_SCR_STAT);
527 if ((port_status & 0xf) != 0x03) {
528 debug("No Link on port %d!\n", port);
532 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
534 sg_count = ahci_fill_sg(port, buf, buf_len);
535 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
536 ahci_fill_cmd_slot(pp, opts);
538 ahci_dcache_flush_sata_cmd(pp);
539 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
541 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
543 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
544 WAIT_MS_DATAIO, 0x1)) {
545 printf("timeout exit!\n");
549 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
550 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
556 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
559 for (i = 0; i < len / 2; i++)
560 target[i] = swab16(src[i]);
561 return (char *)target;
565 static void dump_ataid(hd_driveid_t *ataid)
567 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
568 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
569 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
570 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
571 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
572 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
573 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
574 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
575 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
576 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
577 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
578 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
579 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
580 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
581 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
586 * SCSI INQUIRY command operation.
588 static int ata_scsiop_inquiry(ccb *pccb)
593 0x5, /* claim SPC-3 version compatibility */
601 /* Clean ccb data buffer */
602 memset(pccb->pdata, 0, pccb->datalen);
604 memcpy(pccb->pdata, hdr, sizeof(hdr));
606 if (pccb->datalen <= 35)
609 memset(fis, 0, sizeof(fis));
610 /* Construct the FIS */
611 fis[0] = 0x27; /* Host to device FIS. */
612 fis[1] = 1 << 7; /* Command FIS. */
613 fis[2] = ATA_CMD_IDENT; /* Command byte. */
615 /* Read id from sata */
617 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
620 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
621 sizeof(hd_driveid_t), 0)) {
622 debug("scsi_ahci: SCSI inquiry command failure.\n");
628 ataid[port] = (hd_driveid_t *) tmpid;
630 memcpy(&pccb->pdata[8], "ATA ", 8);
631 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
632 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
634 dump_ataid(ataid[port]);
640 * SCSI READ10/WRITE10 command operation.
642 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
647 u8 *user_buffer = pccb->pdata;
648 u32 user_buffer_size = pccb->datalen;
650 /* Retrieve the base LBA number from the ccb structure. */
651 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
652 lba = be32_to_cpu(lba);
655 * And the number of blocks.
657 * For 10-byte and 16-byte SCSI R/W commands, transfer
658 * length 0 means transfer 0 block of data.
659 * However, for ATA R/W commands, sector count 0 means
660 * 256 or 65536 sectors, not 0 sectors as in SCSI.
662 * WARNING: one or two older ATA drives treat 0 as 0...
664 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
666 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
667 is_write ? "write" : "read", (unsigned)lba, blocks);
670 memset(fis, 0, sizeof(fis));
671 fis[0] = 0x27; /* Host to device FIS. */
672 fis[1] = 1 << 7; /* Command FIS. */
673 /* Command byte (read/write). */
674 fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA;
677 u16 now_blocks; /* number of blocks per iteration */
678 u32 transfer_size; /* number of bytes per iteration */
680 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
682 transfer_size = ATA_BLOCKSIZE * now_blocks;
683 if (transfer_size > user_buffer_size) {
684 printf("scsi_ahci: Error: buffer too small.\n");
688 /* LBA address, only support LBA28 in this driver */
689 fis[4] = (lba >> 0) & 0xff;
690 fis[5] = (lba >> 8) & 0xff;
691 fis[6] = (lba >> 16) & 0xff;
692 fis[7] = ((lba >> 24) & 0xf) | 0xe0;
694 /* Block (sector) count */
695 fis[12] = (now_blocks >> 0) & 0xff;
696 fis[13] = (now_blocks >> 8) & 0xff;
698 /* Read/Write from ahci */
699 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
700 user_buffer, user_buffer_size,
702 debug("scsi_ahci: SCSI %s10 command failure.\n",
703 is_write ? "WRITE" : "READ");
706 user_buffer += transfer_size;
707 user_buffer_size -= transfer_size;
708 blocks -= now_blocks;
717 * SCSI READ CAPACITY10 command operation.
719 static int ata_scsiop_read_capacity10(ccb *pccb)
724 if (!ataid[pccb->target]) {
725 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
727 "\tPlease run SCSI commmand INQUIRY firstly!\n");
731 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
732 if (cap == 0xfffffff) {
733 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
734 if (cap48[2] || cap48[3]) {
737 cap = (le16_to_cpu(cap48[1]) << 16) |
738 (le16_to_cpu(cap48[0]));
742 cap = cpu_to_be32(cap);
743 memcpy(pccb->pdata, &cap, sizeof(cap));
745 block_size = cpu_to_be32((u32)512);
746 memcpy(&pccb->pdata[4], &block_size, 4);
753 * SCSI READ CAPACITY16 command operation.
755 static int ata_scsiop_read_capacity16(ccb *pccb)
760 if (!ataid[pccb->target]) {
761 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
763 "\tPlease run SCSI commmand INQUIRY firstly!\n");
767 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
768 if (cap == 0xfffffff) {
769 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
770 cap = le64_to_cpu(cap);
773 cap = cpu_to_be64(cap);
774 memcpy(pccb->pdata, &cap, sizeof(cap));
776 block_size = cpu_to_be64((u64)512);
777 memcpy(&pccb->pdata[8], &block_size, 8);
784 * SCSI TEST UNIT READY command operation.
786 static int ata_scsiop_test_unit_ready(ccb *pccb)
788 return (ataid[pccb->target]) ? 0 : -EPERM;
792 int scsi_exec(ccb *pccb)
796 switch (pccb->cmd[0]) {
798 ret = ata_scsiop_read_write(pccb, 0);
801 ret = ata_scsiop_read_write(pccb, 1);
803 case SCSI_RD_CAPAC10:
804 ret = ata_scsiop_read_capacity10(pccb);
806 case SCSI_RD_CAPAC16:
807 ret = ata_scsiop_read_capacity16(pccb);
810 ret = ata_scsiop_test_unit_ready(pccb);
813 ret = ata_scsiop_inquiry(pccb);
816 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
821 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
829 void scsi_low_level_init(int busdevfunc)
834 #ifndef CONFIG_SCSI_AHCI_PLAT
835 ahci_init_one(busdevfunc);
838 linkmap = probe_ent->link_port_map;
840 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
841 if (((linkmap >> i) & 0x01)) {
842 if (ahci_port_start((u8) i)) {
843 printf("Can not start port %d\n", i);
846 #ifdef CONFIG_AHCI_SETFEATURES_XFER
847 ahci_set_feature((u8) i);
853 #ifdef CONFIG_SCSI_AHCI_PLAT
854 int ahci_init(u32 base)
859 memset(ataid, 0, sizeof(ataid));
861 probe_ent = malloc(sizeof(struct ahci_probe_ent));
862 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
864 probe_ent->host_flags = ATA_FLAG_SATA
869 probe_ent->pio_mask = 0x1f;
870 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
872 probe_ent->mmio_base = base;
874 /* initialize adapter */
875 rc = ahci_host_init(probe_ent);
879 ahci_print_info(probe_ent);
881 linkmap = probe_ent->link_port_map;
883 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
884 if (((linkmap >> i) & 0x01)) {
885 if (ahci_port_start((u8) i)) {
886 printf("Can not start port %d\n", i);
889 #ifdef CONFIG_AHCI_SETFEATURES_XFER
890 ahci_set_feature((u8) i);
899 void scsi_bus_reset(void)
905 void scsi_print_error(ccb * pccb)
907 /*The ahci error info can be read in the ahci driver*/