2 * Broadcom specific AMBA
3 * ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/bcm47xx_wdt.h>
14 #include <linux/export.h>
15 #include <linux/platform_device.h>
16 #include <linux/bcma/bcma.h>
18 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
22 value |= bcma_cc_read32(cc, offset) & ~mask;
23 bcma_cc_write32(cc, offset, value);
28 static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
30 if (cc->capabilities & BCMA_CC_CAP_PMU)
31 return bcma_pmu_get_alp_clock(cc);
36 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
38 struct bcma_bus *bus = cc->core->bus;
41 if (cc->capabilities & BCMA_CC_CAP_PMU) {
42 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
44 else if (cc->core->id.rev < 26)
47 nb = (cc->core->id.rev >= 37) ? 32 : 24;
57 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
60 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
62 return bcma_chipco_watchdog_timer_set(cc, ticks);
65 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
68 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
71 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
72 return ticks / cc->ticks_per_ms;
75 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
77 struct bcma_bus *bus = cc->core->bus;
79 if (cc->capabilities & BCMA_CC_CAP_PMU) {
80 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
81 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
82 return bcma_chipco_get_alp_clock(cc) / 4000;
84 /* based on 32KHz ILP clock */
87 return bcma_chipco_get_alp_clock(cc) / 1000;
91 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
93 struct bcm47xx_wdt wdt = {};
94 struct platform_device *pdev;
97 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
98 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
99 wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
101 pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
102 cc->core->bus->num, &wdt,
105 return PTR_ERR(pdev);
112 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
114 if (cc->early_setup_done)
117 if (cc->core->id.rev >= 11)
118 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
119 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
120 if (cc->core->id.rev >= 35)
121 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
123 if (cc->capabilities & BCMA_CC_CAP_PMU)
124 bcma_pmu_early_init(cc);
126 cc->early_setup_done = true;
129 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
137 bcma_core_chipcommon_early_init(cc);
139 if (cc->core->id.rev >= 20) {
140 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
141 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
144 if (cc->capabilities & BCMA_CC_CAP_PMU)
146 if (cc->capabilities & BCMA_CC_CAP_PCTL)
147 bcma_err(cc->core->bus, "Power control not implemented!\n");
149 if (cc->core->id.rev >= 16) {
150 if (cc->core->bus->sprom.leddc_on_time &&
151 cc->core->bus->sprom.leddc_off_time) {
152 leddc_on = cc->core->bus->sprom.leddc_on_time;
153 leddc_off = cc->core->bus->sprom.leddc_off_time;
155 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
156 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
157 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
159 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
161 cc->setup_done = true;
164 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
165 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
168 enum bcma_clkmode clkmode;
170 maxt = bcma_chipco_watchdog_get_max_timer(cc);
171 if (cc->capabilities & BCMA_CC_CAP_PMU) {
174 else if (ticks > maxt)
176 bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
178 clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
179 bcma_core_set_clockmode(cc->core, clkmode);
183 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
188 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
190 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
193 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
195 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
198 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
200 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
203 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
205 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
208 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
210 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
213 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
215 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
217 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
219 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
221 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
224 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
226 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
229 #ifdef CONFIG_BCMA_DRIVER_MIPS
230 void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
235 unsigned int ccrev = cc->core->id.rev;
236 struct bcma_serial_port *ports = cc->serial_ports;
238 if (ccrev >= 11 && ccrev != 15) {
239 baud_base = bcma_chipco_get_alp_clock(cc);
241 /* Turn off UART clock before switching clocksource. */
242 bcma_cc_write32(cc, BCMA_CC_CORECTL,
243 bcma_cc_read32(cc, BCMA_CC_CORECTL)
244 & ~BCMA_CC_CORECTL_UARTCLKEN);
246 /* Set the override bit so we don't divide it */
247 bcma_cc_write32(cc, BCMA_CC_CORECTL,
248 bcma_cc_read32(cc, BCMA_CC_CORECTL)
249 | BCMA_CC_CORECTL_UARTCLK0);
251 /* Re-enable the UART clock. */
252 bcma_cc_write32(cc, BCMA_CC_CORECTL,
253 bcma_cc_read32(cc, BCMA_CC_CORECTL)
254 | BCMA_CC_CORECTL_UARTCLKEN);
257 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
261 irq = bcma_core_mips_irq(cc->core);
263 /* Determine the registers of the UARTs */
264 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
265 for (i = 0; i < cc->nr_serial_ports; i++) {
266 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
269 ports[i].baud_base = baud_base;
270 ports[i].reg_shift = 0;
273 #endif /* CONFIG_BCMA_DRIVER_MIPS */