1 // SPDX-License-Identifier: GPL-2.0
3 // Register cache access API
5 // Copyright 2011 Wolfson Microelectronics plc
7 // Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
9 #include <linux/bsearch.h>
10 #include <linux/device.h>
11 #include <linux/export.h>
12 #include <linux/slab.h>
13 #include <linux/sort.h>
18 static const struct regcache_ops *cache_types[] = {
24 static int regcache_hw_init(struct regmap *map)
29 unsigned int reg, val;
32 if (!map->num_reg_defaults_raw)
35 /* calculate the size of reg_defaults */
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
41 /* all registers are unreadable or volatile, so just bypass */
43 map->cache_bypass = true;
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
50 if (!map->reg_defaults)
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
57 /* Bypass the cache access till data read from HW */
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
64 ret = regmap_raw_read(map, 0, tmp_buf,
66 map->cache_bypass = cache_bypass;
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
75 /* fill the reg_defaults */
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
79 if (!regmap_readable(map, reg))
82 if (regmap_volatile(map, reg))
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
88 bool cache_bypass = map->cache_bypass;
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
94 dev_err(map->dev, "Failed to read %d: %d\n",
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
108 kfree(map->reg_defaults);
113 int regcache_init(struct regmap *map, const struct regmap_config *config)
119 if (map->cache_type == REGCACHE_NONE) {
120 if (config->reg_defaults || config->num_reg_defaults_raw)
122 "No cache used with register defaults set!\n");
124 map->cache_bypass = true;
128 if (config->reg_defaults && !config->num_reg_defaults) {
130 "Register defaults are set without the number!\n");
134 if (config->num_reg_defaults && !config->reg_defaults) {
136 "Register defaults number are set without the reg!\n");
140 for (i = 0; i < config->num_reg_defaults; i++)
141 if (config->reg_defaults[i].reg % map->reg_stride)
144 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
145 if (cache_types[i]->type == map->cache_type)
148 if (i == ARRAY_SIZE(cache_types)) {
149 dev_err(map->dev, "Could not match cache type: %d\n",
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
161 map->cache_ops = cache_types[i];
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
168 /* We still need to ensure that the reg_defaults
169 * won't vanish from under us. We'll need to make
172 if (config->reg_defaults) {
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
174 sizeof(struct reg_default), GFP_KERNEL);
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
179 /* Some devices such as PMICs don't have cache defaults,
180 * we cope with this by reading back the HW registers and
181 * crafting the cache defaults by hand.
183 ret = regcache_hw_init(map);
186 if (map->cache_bypass)
190 if (!map->max_register && map->num_reg_defaults_raw)
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
193 if (map->cache_ops->init) {
194 dev_dbg(map->dev, "Initializing %s cache\n",
195 map->cache_ops->name);
196 ret = map->cache_ops->init(map);
203 kfree(map->reg_defaults);
205 kfree(map->reg_defaults_raw);
210 void regcache_exit(struct regmap *map)
212 if (map->cache_type == REGCACHE_NONE)
215 BUG_ON(!map->cache_ops);
217 kfree(map->reg_defaults);
219 kfree(map->reg_defaults_raw);
221 if (map->cache_ops->exit) {
222 dev_dbg(map->dev, "Destroying %s cache\n",
223 map->cache_ops->name);
224 map->cache_ops->exit(map);
229 * regcache_read - Fetch the value of a given register from the cache.
231 * @map: map to configure.
232 * @reg: The register index.
233 * @value: The value to be returned.
235 * Return a negative value on failure, 0 on success.
237 int regcache_read(struct regmap *map,
238 unsigned int reg, unsigned int *value)
242 if (map->cache_type == REGCACHE_NONE)
245 BUG_ON(!map->cache_ops);
247 if (!regmap_volatile(map, reg)) {
248 ret = map->cache_ops->read(map, reg, value);
251 trace_regmap_reg_read_cache(map, reg, *value);
260 * regcache_write - Set the value of a given register in the cache.
262 * @map: map to configure.
263 * @reg: The register index.
264 * @value: The new register value.
266 * Return a negative value on failure, 0 on success.
268 int regcache_write(struct regmap *map,
269 unsigned int reg, unsigned int value)
271 if (map->cache_type == REGCACHE_NONE)
274 BUG_ON(!map->cache_ops);
276 if (!regmap_volatile(map, reg))
277 return map->cache_ops->write(map, reg, value);
282 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
287 if (!regmap_writeable(map, reg))
290 /* If we don't know the chip just got reset, then sync everything. */
291 if (!map->no_sync_defaults)
294 /* Is this the hardware default? If so skip. */
295 ret = regcache_lookup_reg(map, reg);
296 if (ret >= 0 && val == map->reg_defaults[ret].def)
301 static int regcache_default_sync(struct regmap *map, unsigned int min,
306 for (reg = min; reg <= max; reg += map->reg_stride) {
310 if (regmap_volatile(map, reg) ||
311 !regmap_writeable(map, reg))
314 ret = regcache_read(map, reg, &val);
320 if (!regcache_reg_needs_sync(map, reg, val))
323 map->cache_bypass = true;
324 ret = _regmap_write(map, reg, val);
325 map->cache_bypass = false;
327 dev_err(map->dev, "Unable to sync register %#x. %d\n",
331 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
338 * regcache_sync - Sync the register cache with the hardware.
340 * @map: map to configure.
342 * Any registers that should not be synced should be marked as
343 * volatile. In general drivers can choose not to use the provided
344 * syncing functionality if they so require.
346 * Return a negative value on failure, 0 on success.
348 int regcache_sync(struct regmap *map)
355 if (WARN_ON(map->cache_type == REGCACHE_NONE))
358 BUG_ON(!map->cache_ops);
360 map->lock(map->lock_arg);
361 /* Remember the initial bypass state */
362 bypass = map->cache_bypass;
363 dev_dbg(map->dev, "Syncing %s cache\n",
364 map->cache_ops->name);
365 name = map->cache_ops->name;
366 trace_regcache_sync(map, name, "start");
368 if (!map->cache_dirty)
373 /* Apply any patch first */
374 map->cache_bypass = true;
375 for (i = 0; i < map->patch_regs; i++) {
376 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
378 dev_err(map->dev, "Failed to write %x = %x: %d\n",
379 map->patch[i].reg, map->patch[i].def, ret);
383 map->cache_bypass = false;
385 if (map->cache_ops->sync)
386 ret = map->cache_ops->sync(map, 0, map->max_register);
388 ret = regcache_default_sync(map, 0, map->max_register);
391 map->cache_dirty = false;
394 /* Restore the bypass state */
396 map->cache_bypass = bypass;
397 map->no_sync_defaults = false;
398 map->unlock(map->lock_arg);
400 regmap_async_complete(map);
402 trace_regcache_sync(map, name, "stop");
406 EXPORT_SYMBOL_GPL(regcache_sync);
409 * regcache_sync_region - Sync part of the register cache with the hardware.
412 * @min: first register to sync
413 * @max: last register to sync
415 * Write all non-default register values in the specified region to
418 * Return a negative value on failure, 0 on success.
420 int regcache_sync_region(struct regmap *map, unsigned int min,
427 if (WARN_ON(map->cache_type == REGCACHE_NONE))
430 BUG_ON(!map->cache_ops);
432 map->lock(map->lock_arg);
434 /* Remember the initial bypass state */
435 bypass = map->cache_bypass;
437 name = map->cache_ops->name;
438 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
440 trace_regcache_sync(map, name, "start region");
442 if (!map->cache_dirty)
447 if (map->cache_ops->sync)
448 ret = map->cache_ops->sync(map, min, max);
450 ret = regcache_default_sync(map, min, max);
453 /* Restore the bypass state */
454 map->cache_bypass = bypass;
456 map->no_sync_defaults = false;
457 map->unlock(map->lock_arg);
459 regmap_async_complete(map);
461 trace_regcache_sync(map, name, "stop region");
465 EXPORT_SYMBOL_GPL(regcache_sync_region);
468 * regcache_drop_region - Discard part of the register cache
470 * @map: map to operate on
471 * @min: first register to discard
472 * @max: last register to discard
474 * Discard part of the register cache.
476 * Return a negative value on failure, 0 on success.
478 int regcache_drop_region(struct regmap *map, unsigned int min,
483 if (!map->cache_ops || !map->cache_ops->drop)
486 map->lock(map->lock_arg);
488 trace_regcache_drop_region(map, min, max);
490 ret = map->cache_ops->drop(map, min, max);
492 map->unlock(map->lock_arg);
496 EXPORT_SYMBOL_GPL(regcache_drop_region);
499 * regcache_cache_only - Put a register map into cache only mode
501 * @map: map to configure
502 * @enable: flag if changes should be written to the hardware
504 * When a register map is marked as cache only writes to the register
505 * map API will only update the register cache, they will not cause
506 * any hardware changes. This is useful for allowing portions of
507 * drivers to act as though the device were functioning as normal when
508 * it is disabled for power saving reasons.
510 void regcache_cache_only(struct regmap *map, bool enable)
512 map->lock(map->lock_arg);
513 WARN_ON(map->cache_type != REGCACHE_NONE &&
514 map->cache_bypass && enable);
515 map->cache_only = enable;
516 trace_regmap_cache_only(map, enable);
517 map->unlock(map->lock_arg);
519 EXPORT_SYMBOL_GPL(regcache_cache_only);
522 * regcache_mark_dirty - Indicate that HW registers were reset to default values
526 * Inform regcache that the device has been powered down or reset, so that
527 * on resume, regcache_sync() knows to write out all non-default values
528 * stored in the cache.
530 * If this function is not called, regcache_sync() will assume that
531 * the hardware state still matches the cache state, modulo any writes that
532 * happened when cache_only was true.
534 void regcache_mark_dirty(struct regmap *map)
536 map->lock(map->lock_arg);
537 map->cache_dirty = true;
538 map->no_sync_defaults = true;
539 map->unlock(map->lock_arg);
541 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
544 * regcache_cache_bypass - Put a register map into cache bypass mode
546 * @map: map to configure
547 * @enable: flag if changes should not be written to the cache
549 * When a register map is marked with the cache bypass option, writes
550 * to the register map API will only update the hardware and not
551 * the cache directly. This is useful when syncing the cache back to
554 void regcache_cache_bypass(struct regmap *map, bool enable)
556 map->lock(map->lock_arg);
557 WARN_ON(map->cache_only && enable);
558 map->cache_bypass = enable;
559 trace_regmap_cache_bypass(map, enable);
560 map->unlock(map->lock_arg);
562 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
564 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
567 /* Use device native format if possible */
568 if (map->format.format_val) {
569 map->format.format_val(base + (map->cache_word_size * idx),
574 switch (map->cache_word_size) {
606 unsigned int regcache_get_val(struct regmap *map, const void *base,
612 /* Use device native format if possible */
613 if (map->format.parse_val)
614 return map->format.parse_val(regcache_get_val_addr(map, base,
617 switch (map->cache_word_size) {
619 const u8 *cache = base;
624 const u16 *cache = base;
629 const u32 *cache = base;
635 const u64 *cache = base;
647 static int regcache_default_cmp(const void *a, const void *b)
649 const struct reg_default *_a = a;
650 const struct reg_default *_b = b;
652 return _a->reg - _b->reg;
655 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
657 struct reg_default key;
658 struct reg_default *r;
663 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
664 sizeof(struct reg_default), regcache_default_cmp);
667 return r - map->reg_defaults;
672 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
677 return test_bit(idx, cache_present);
680 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
684 if (!regcache_reg_needs_sync(map, reg, val))
687 map->cache_bypass = true;
689 ret = _regmap_write(map, reg, val);
691 map->cache_bypass = false;
694 dev_err(map->dev, "Unable to sync register %#x. %d\n",
698 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
704 static int regcache_sync_block_single(struct regmap *map, void *block,
705 unsigned long *cache_present,
706 unsigned int block_base,
707 unsigned int start, unsigned int end)
709 unsigned int i, regtmp, val;
712 for (i = start; i < end; i++) {
713 regtmp = block_base + (i * map->reg_stride);
715 if (!regcache_reg_present(cache_present, i) ||
716 !regmap_writeable(map, regtmp))
719 val = regcache_get_val(map, block, i);
720 ret = regcache_sync_val(map, regtmp, val);
728 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
729 unsigned int base, unsigned int cur)
731 size_t val_bytes = map->format.val_bytes;
737 count = (cur - base) / map->reg_stride;
739 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
740 count * val_bytes, count, base, cur - map->reg_stride);
742 map->cache_bypass = true;
744 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
746 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
747 base, cur - map->reg_stride, ret);
749 map->cache_bypass = false;
756 static int regcache_sync_block_raw(struct regmap *map, void *block,
757 unsigned long *cache_present,
758 unsigned int block_base, unsigned int start,
762 unsigned int regtmp = 0;
763 unsigned int base = 0;
764 const void *data = NULL;
767 for (i = start; i < end; i++) {
768 regtmp = block_base + (i * map->reg_stride);
770 if (!regcache_reg_present(cache_present, i) ||
771 !regmap_writeable(map, regtmp)) {
772 ret = regcache_sync_block_raw_flush(map, &data,
779 val = regcache_get_val(map, block, i);
780 if (!regcache_reg_needs_sync(map, regtmp, val)) {
781 ret = regcache_sync_block_raw_flush(map, &data,
789 data = regcache_get_val_addr(map, block, i);
794 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
798 int regcache_sync_block(struct regmap *map, void *block,
799 unsigned long *cache_present,
800 unsigned int block_base, unsigned int start,
803 if (regmap_can_raw_write(map) && !map->use_single_write)
804 return regcache_sync_block_raw(map, block, cache_present,
805 block_base, start, end);
807 return regcache_sync_block_single(map, block, cache_present,
808 block_base, start, end);