2 * @file mipi_dsih_local.h
3 * @brief instance context structure and enumerator definitions:
4 * errors, events, color coding, video modes and driver state
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40 #ifndef MIPI_DSIH_LOCAL_H_
41 #define MIPI_DSIH_LOCAL_H_
44 #include <linux/kernel.h>
47 #define FB_DSIH_VERSION_1P21A
49 #define SPRD_MIPI_DPHY_GEN2
51 //typedef unsigned char uint8_t;
52 //typedef unsigned short uint16_t;
53 //typedef unsigned int uint32_t;
55 #define DSIH_PIXEL_TOLERANCE (2)
56 #define DSIH_FIFO_ACTIVE_WAIT (5000) /* no of tries to access the fifo */
57 #define DSIH_PHY_ACTIVE_WAIT (50000)
58 #define ONE_MS_ACTIVE_WAIT (50000) /* 50MHz processor */
59 #define DEFAULT_BYTE_CLOCK (432000) /* a value to start PHY PLL - random */
60 #define MAX_NULL_SIZE (1023)
61 #define FIFO_DEPTH (1096)
62 #define WORD_LENGTH (4) /* bytes (32bit registers) */
64 /** Define D-PHY type */
66 #ifdef SPRD_MIPI_DPHY_GEN1
67 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP 4 Lanes Gen 1 1GHz */
68 #define DWC_MIPI_DPHY_BIDIR_TSMC40LP
70 #ifdef SPRD_MIPI_DPHY_GEN2
71 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP / GF28LP 4 Lanes Gen 2 1.5GHz */
74 /** 4 Lanes Gen 2 1.5GHz testchips */
76 /** TQL 2 Lane test chip */
77 /* #define DPHY2Btql */
80 * Errors generated by the DSI Host controller driver
88 ERR_DSI_INVALID_INSTANCE,
90 ERR_DSI_CORE_INCOMPATIBLE,
92 ERR_DSI_INVALID_COMMAND,
93 ERR_DSI_INVALID_EVENT,
94 ERR_DSI_INVALID_HANDLE,
97 ERR_DSI_PHY_FREQ_OUT_OF_BOUND,
99 ERR_DSI_PHY_PLL_NOT_LOCKED,
109 VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
110 VIDEO_NON_BURST_WITH_SYNC_EVENTS,
111 VIDEO_BURST_WITH_SYNC_PULSES
115 * Color coding type (depth and pixel configuration)
119 COLOR_CODE_16BIT_CONFIG1 = 0,
120 COLOR_CODE_16BIT_CONFIG2 = 1,
121 COLOR_CODE_16BIT_CONFIG3 = 2,
122 COLOR_CODE_18BIT_CONFIG1 = 3,
123 COLOR_CODE_18BIT_CONFIG2 = 4,
124 COLOR_CODE_24BIT = 5,
125 COLOR_CODE_20BIT_YCC422_LOOSELY = 6,
126 COLOR_CODE_24BIT_YCC422 = 7,
127 COLOR_CODE_16BIT_YCC422 = 8,
128 COLOR_CODE_30BIT = 9,
129 COLOR_CODE_36BIT = 10,
130 COLOR_CODE_12BIT_YCC420 = 11,
135 * Events generated by the DSI Host controller
144 ACK_HS_RX_TIMEOUT_ERR,
145 ACK_FALSE_CONTROL_ERR,
146 ACK_RSVD_DEVICE_ERR_7,
147 ACK_ECC_SINGLE_BIT_ERR,
148 ACK_ECC_MULTI_BIT_ERR,
150 ACK_DSI_TYPE_NOT_RECOGNIZED_ERR,
151 ACK_VC_ID_INVALID_ERR,
152 ACK_INVALID_TX_LENGTH_ERR,
153 ACK_RSVD_DEVICE_ERR_14,
154 ACK_DSI_PROTOCOL_ERR,
157 DPHY_SYNC_ESC_LP_ERR,
158 DPHY_CONTROL_LANE0_ERR,
159 DPHY_CONTENTION_LP0_ERR,
160 DPHY_CONTENTION_LP1_ERR,
169 DPI_PLD_FIFO_FULL_ERR,
170 GEN_TX_CMD_FIFO_FULL_ERR,
171 GEN_TX_PLD_FIFO_FULL_ERR,
172 GEN_TX_PLD_FIFO_EMPTY_ERR,
173 GEN_RX_PLD_FIFO_EMPTY_ERR,
174 GEN_RX_PLD_FIFO_FULL_ERR,
176 DBI_TX_CMD_FIFO_FULL_ERR,
177 DBI_TX_PLD_FIFO_FULL_ERR,
178 DBI_RX_PLD_FIFO_EMPTY_ERR,
179 DBI_RX_PLD_FIFO_FULL_ERR,
185 * DSI Host state machine states
186 * Holds the mapping of D-PHY to the OS, logging I/O, and hardware access layer.
199 * Holds the mapping of API to the OS, logging I/O, and hardware access layer
200 * and HW module information.
202 typedef struct dphy_t
204 /** Physical base address of PHY module - REQUIRED */
206 /** Reference frequency provided to PHY module [KHz] - REQUIRED */
207 uint32_t reference_freq;
208 #ifdef CONFIG_FB_DYNAMIC_FREQ_SCALING
209 /** mark if D-PHY should keep work or not */
210 uint32_t phy_keep_work;
212 /** D-PHY driver state - used internally by driver */
214 /** Function handle of any board function that needs to be called
215 * in order to set up the environment for the D-PHY before it is
217 void (*bsp_pre_config)(struct dphy_t *instance, void* param);
218 /** Register read access function handle - REQUIRED */
219 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
220 /** Register write access function handle - REQUIRED */
221 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
222 /** Log errors function handle */
223 void (*log_error)(const char * string);
224 /** Log information function handle */
225 void (*log_info)(const char *fmt, ...);
230 * MIPI DSI Host Controller
231 * Holds important information for the functioning of the DSI Host Controller API
232 * Holds the mapping of API to the OS, logging I/O, and hardware access layer.
233 * It also holds important information set by the user about the HW considerations
234 * and internal state variables.
236 typedef struct dsih_ctrl_t
238 /** Physical base address of controller - REQUIRED */
240 /** D-PHY instance associated with the DSI host controller - REQUIRED */
242 /** Number of lanes physically connected to controller - REQUIRED */
244 /** Maximum number of byte clock cycles needed by the PHY to perform
245 * the Bus Turn Around operation - REQUIRED */
246 uint16_t max_bta_cycles;
247 /** Describe the color mode pin (dpicolorm) whether it is active high or low - REQUIRED */
248 int color_mode_polarity;
249 /** Describe the shut down pin (dpishutdn) whether it is active high or low - REQUIRED */
250 int shut_down_polarity;
251 /** initialised or not */
253 /** Register read access function handle - REQUIRED */
254 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
255 /** Register write access function handle - REQUIRED */
256 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
257 /** Log errors function handle */
258 void (*log_error)(const char * string);
259 /** Log information function handle */
260 void (*log_info)(const char *fmt, ...);
261 /** Event registry holds handlers of the callbacks of registered events */
262 void (*event_registry[DSI_MAX_EVENT])(struct dsih_ctrl_t *instance, void *handler);
266 * Video configurations
267 * Holds information about the video stream to be sent through the DPI interface.
271 /** Number of lanes used to send current video */
273 /** Virtual channel number to send this video stream */
274 uint8_t virtual_channel;
275 /** Video mode, whether burst with sync pulses, or packets with either sync pulses or events */
276 dsih_video_mode_t video_mode;
277 /** Maximum number of byte clock cycles needed by the PHY to transition
278 * the data lanes from high speed to low power - REQUIRED */
279 uint8_t max_hs_to_lp_cycles;
280 /** Maximum number of byte clock cycles needed by the PHY to transition
281 * the data lanes from low power to high speed - REQUIRED */
282 uint8_t max_lp_to_hs_cycles;
283 /** Maximum number of byte clock cycles needed by the PHY to transition
284 * the clock lane from high speed to low power - REQUIRED */
285 uint8_t max_clk_hs_to_lp_cycles;
286 /** Maximum number of byte clock cycles needed by the PHY to transition
287 * the clock lane from low power to high speed - REQUIRED */
288 uint8_t max_clk_lp_to_hs_cycles;
289 /** Enable non coninuous clock for energy saving
290 * - Clock lane will go to LS while not transmitting video */
291 int non_continuous_clock;
292 /** Enable receiving of ack packets */
293 int receive_ack_packets;
294 /** Byte (lane) clock [KHz] */
296 /** Pixel (DPI) Clock [KHz]*/
297 uint32_t pixel_clock;
298 /** Colour coding - BPP and Pixel configuration */
299 dsih_color_coding_t color_coding;
300 /** Is 18-bit loosely packets (valid only when BPP == 18) */
302 /** Data enable signal (dpidaten) whether it is active high or low */
303 int data_en_polarity;
304 /** Horizontal synchronisation signal (dpihsync) whether it is active high or low */
306 /** Horizontal resolution or Active Pixels */
307 uint16_t h_active_pixels; /* hadr */
308 /** Horizontal Sync Pixels - min 4 for best performance */
309 uint16_t h_sync_pixels;
310 /** Horizontal back porch pixels */
311 uint16_t h_back_porch_pixels; /* hbp */
312 /** Total Horizontal pixels */
313 uint16_t h_total_pixels; /* h_total */
314 /** Vertical synchronisation signal (dpivsync) whether it is active high or low */
316 /** Vertical active lines (resolution) */
317 uint16_t v_active_lines; /* vadr */
318 /** Vertical sync lines */
319 uint16_t v_sync_lines;
320 /** Vertical back porch lines */
321 uint16_t v_back_porch_lines; /* vbp */
322 /** Total no of vertical lines */
323 uint16_t v_total_lines; /* v_total */
329 /** virtual channel */
330 uint8_t virtual_channel;
331 /** Commands to be sent in high speed or low power */
333 /** Colour coding - BPP and Pixel configuration */
334 dsih_color_coding_t color_coding;
335 /** Top horizontal pixel position in the display */
337 /** Horizontal resolution or Active Pixels */
338 uint16_t h_active_pixels; /* hadr */
339 /** Left most line position in the display */
341 /** Vertical active lines (resolution) */
342 uint16_t v_active_lines; /* vadr */
343 /** Whether Tearing effect should be requested */
345 /** packet size of write memory command -
346 * 0 is default (optimum usage of RAM) */
347 uint16_t packet_size;
349 dsih_cmd_mode_video_t;
351 * Register configurations
355 /** Register offset */
357 /** Register data [in or out] */
362 #endif /* MIPI_DSIH_LOCAL_H_ */