2 * @file mipi_dsih_hal.h
\r
8 The Synopsys Software Driver and documentation (hereinafter "Software")
\r
9 is an unsupported proprietary work of Synopsys, Inc. unless otherwise
\r
10 expressly agreed to in writing between Synopsys and you.
\r
12 The Software IS NOT an item of Licensed Software or Licensed Product under
\r
13 any End User Software License Agreement or Agreement for Licensed Product
\r
14 with Synopsys or any supplement thereto. Permission is hereby granted,
\r
15 free of charge, to any person obtaining a copy of this software annotated
\r
16 with this license and the Software, to deal in the Software without
\r
17 restriction, including without limitation the rights to use, copy, modify,
\r
18 merge, publish, distribute, sublicense, and/or sell copies of the Software,
\r
19 and to permit persons to whom the Software is furnished to do so, subject
\r
20 to the following conditions:
\r
22 The above copyright notice and this permission notice shall be included in
\r
23 all copies or substantial portions of the Software.
\r
25 THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
\r
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
\r
28 ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
\r
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
\r
30 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
31 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\r
33 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
\r
34 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
\r
38 #ifndef MIPI_DSIH_HAL_H_
\r
39 #define MIPI_DSIH_HAL_H_
\r
41 #include "mipi_dsih_local.h"
\r
43 #define R_DSI_HOST_VERSION (0x00)
\r
44 #define R_DSI_HOST_PWR_UP (0x04)
\r
45 #define R_DSI_HOST_CLK_MGR (0x08)
\r
46 #define R_DSI_HOST_DPI_VCID (0x0C)
\r
47 #define R_DSI_HOST_DPI_COLOR_CODE (0x10)
\r
48 #define R_DSI_HOST_DPI_CFG_POL (0x14)
\r
49 #define R_DSI_HOST_DPI_LP_CMD_TIM (0x18)
\r
50 #define R_DSI_HOST_DBI_VCID (0x1C)
\r
51 #define R_DSI_HOST_DBI_CFG (0x20)
\r
52 #define R_DSI_HOST_DBI_PARTITION_EN (0x24)
\r
53 #define R_DSI_HOST_DBI_CMDSIZE (0x28)
\r
54 #define R_DSI_HOST_PCKHDL_CFG (0x2C)
\r
55 #define R_DSI_HOST_GEN_VCID (0x30)
\r
56 #define R_DSI_HOST_MODE_CFG (0x34)
\r
57 #define R_DSI_HOST_VID_MODE_CFG (0x38)
\r
58 #define R_DSI_HOST_VID_PKT_SIZE (0x3C)
\r
59 #define R_DSI_HOST_VID_NUM_CHUNKS (0x40)
\r
60 #define R_DSI_HOST_VID_NULL_SIZE (0x44)
\r
61 #define R_DSI_HOST_VID_HSA_TIME (0x48)
\r
62 #define R_DSI_HOST_VID_HBP_TIME (0x4C)
\r
63 #define R_DSI_HOST_VID_HLINE_TIME (0x50)
\r
64 #define R_DSI_HOST_VID_VSA_LINES (0x54)
\r
65 #define R_DSI_HOST_VID_VBP_LINES (0x58)
\r
66 #define R_DSI_HOST_VID_VFP_LINES (0x5C)
\r
67 #define R_DSI_HOST_VID_VACTIVE_LINES (0x60)
\r
68 #define R_DSI_HOST_EDPI_CMD_SIZE (0x64)
\r
69 #define R_DSI_HOST_CMD_MODE_CFG (0x68)
\r
70 #define R_DSI_HOST_GEN_HDR (0x6C)
\r
71 #define R_DSI_HOST_GEN_PLD_DATA (0x70)
\r
72 #define R_DSI_HOST_CMD_PKT_STATUS (0x74)
\r
73 #define R_DSI_HOST_TO_CNT_CFG (0x78)
\r
74 #define R_DSI_HOST_HS_RD_TO_CNT (0x7C)
\r
75 #define R_DSI_HOST_LP_RD_TO_CNT (0x80)
\r
76 #define R_DSI_HOST_HS_WR_TO_CNT (0x84)
\r
77 #define R_DSI_HOST_LP_WR_TO_CNT (0x88)
\r
78 #define R_DSI_HOST_BTA_TO_CNT (0x8C)
\r
80 #define R_DSI_HOST_SDF_3D (0x90)
\r
82 #define R_DSI_HOST_LPCLK_CTRL (0x94)
\r
83 #define R_DSI_HOST_PHY_TMR_LPCLK_CFG (0x98)
\r
84 #define R_DSI_HOST_PHY_TMR_CFG (0x9C)
\r
85 #define R_DSI_HOST_INT_ST0 (0xBC)
\r
86 #define R_DSI_HOST_INT_ST1 (0xC0)
\r
87 #define R_DSI_HOST_INT_MSK0 (0xC4)
\r
88 #define R_DSI_HOST_INT_MSK1 (0xC8)
\r
89 #define R_DSI_HOST_PHY_STATUS (0xB0)
\r
93 typedef enum _Dsi_Int0_Type_ {
\r
118 typedef enum _Dsi_Int1_Type_ {
\r
136 dbi_illegal_comm_err,
\r
139 #define DSI_INT_MASK0_SET(bit,val)\
\r
141 uint32_t reg_val = dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0);\
\r
142 reg_val = (val == 1)?(reg_val | (1UL<<bit)):(reg_val & (~(1UL<<bit)));\
\r
143 dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0, reg_val);\
\r
146 #define DSI_INT_MASK1_SET(bit,val)\
\r
148 uint32_t reg_val = dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1);\
\r
149 reg_val = (val == 1)?(reg_val | (1UL<<bit)):(reg_val & (~(1UL<<bit)));\
\r
150 dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1, reg_val);\
\r
154 //base :0x2180 0000
\r
155 typedef struct _DSIH1P21A_REG_T_
\r
157 union _DSIH1P21A_VERSION_tag_t {
\r
158 struct _DSIH1P21A_VERSION_map_t
\r
160 volatile unsigned int version :
\r
164 volatile unsigned int dwVersion;
\r
167 union _DSIH1P21A_PWR_UP_tag_t {
\r
168 struct _DSIH1P21A_PWR_UP_map_t
\r
170 volatile unsigned int power_up :
\r
171 1; //[0] 1 power up , 0 reset core
\r
172 volatile unsigned int reserved_0 :
\r
173 31; //[31:1] Reserved
\r
176 volatile unsigned int dValue;
\r
180 union _DSIH1P21A_CLKMGR_CFG_tag_t {
\r
181 struct _DSIH1P21A_CLKMGR_CFG_map_t
\r
183 volatile unsigned int tx_esc_clk_division :
\r
184 8; //[7:0] This field indicates the division factor for the TX Escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation
\r
185 volatile unsigned int to_clk_division :
\r
186 8; //[15:8] This field indicates the division factor for the Time Out clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
\r
187 volatile unsigned int reserved_0 :
\r
188 16; //[31:16] Reserved
\r
191 volatile unsigned int dValue;
\r
192 }CLKMGR_CFG;// 0x0008
\r
194 union _DSIH1P21A_DPI_VCID_tag_t {
\r
195 struct _DSIH1P21A_DPI_VCID_map_t
\r
197 volatile unsigned int dpi_vcid :
\r
198 2; //[1:0] This field configures the DPI virtual channel id that is indexed to the Video mode packets.
\r
199 volatile unsigned int reserved_0 :
\r
200 30; //[31:2] Reserved
\r
203 volatile unsigned int dValue;
\r
204 }DPI_VCID;// 0x000C
\r
205 //======================
\r
207 union _DSIH1P21A_DPI_COLOR_CODING_tag_t {
\r
208 struct _DSIH1P21A_DPI_COLOR_CODING_map_t
\r
210 volatile unsigned int dpi_color_coding :
\r
213 This field configures the DPI color coding as follows:
\r
214 0000: 16-bit configuration 1
\r
215 0001: 16-bit configuration 2
\r
216 0010: 16-bit configuration 3
\r
217 0011: 18-bit configuration 1
\r
218 0100: 18-bit configuration 2
\r
220 0110: 20-bit YCbCr 4:2:2 loosely packed
\r
221 0111: 24-bit YCbCr 4:2:2
\r
222 1000: 16-bit YCbCr 4:2:2
\r
225 1011-1111: 12-bit YCbCr 4:2:0
\r
226 Note: If the eDPI interface is chosen and currently works in the
\r
227 Command mode (cmd_video_mode = 1), then
\r
230 volatile unsigned int reserved_0 :
\r
231 4; //[7:4] Reserved
\r
232 volatile unsigned int loosely18_en :
\r
233 1; //[8] When set to 1, this bit activates loosely packed variant to 18-bit configurations.
\r
234 volatile unsigned int reserved_1 :
\r
235 23; //[31:9] Reserved
\r
238 volatile unsigned int dValue;
\r
239 }DPI_COLOR_CODING;// 0x0010
\r
242 union _DSIH1P21A_DPI_CFG_POL_tag_t {
\r
243 struct _DSIH1P21A_DPI_CFG_POL_map_t
\r
245 volatile unsigned int dataen_active_low :
\r
246 1; //[0] When set to 1, this bit configures the data enable pin (dpidataen) asactive low.
\r
247 volatile unsigned int vsync_active_low :
\r
248 1; //[1] When set to 1, this bit configures the vertical synchronism pin (dpivsync) as active low.
\r
249 volatile unsigned int hsync_active_low :
\r
250 1; //[2] When set to 1, this bit configures the horizontal synchronism pin (dpihsync) as active low.
\r
251 volatile unsigned int shutd_active_low :
\r
252 1; //[3] When set to 1, this bit configures the shutdown pin (dpishutdn) as active low
\r
253 volatile unsigned int colorm_active_low :
\r
254 1; //[4] When set to 1, this bit configures the color mode pin (dpicolorm) as active low.
\r
255 volatile unsigned int reserved_0 :
\r
259 volatile unsigned int dValue;
\r
260 }DPI_CFG_POL;// 0x0014
\r
263 union _DSIH1P21A_DPI_LP_CMD_TIM_tag_t {
\r
264 struct _DSIH1P21A_DPI_LP_CMD_TIM_map_t
\r
266 volatile unsigned int invact_lpcmd_time :
\r
267 8; //[7:0] This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during the VACT region.
\r
268 volatile unsigned int reserved_0 :
\r
269 8; //[15:8] Reserved
\r
270 volatile unsigned int outvact_lpcmd_time :
\r
271 8; //[23:16] This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during the VSA, VBP, and VFP regions.
\r
272 volatile unsigned int reserved_1 :
\r
273 8; //[31:24] Reserved
\r
276 volatile unsigned int dValue;
\r
277 }DPI_LP_CMD_TIM;// 0x0018
\r
279 union _DSIH1P21A_DBI_VCID_tag_t {
\r
280 struct _DSIH1P21A_DBI_VCID_map_t
\r
282 volatile unsigned int dbi_vcid :
\r
283 2; //[1:0] This field configures the virtual channel id that is indexed to the DCS packets from DBI.
\r
284 volatile unsigned int reserved_0 :
\r
285 30; //[31:2] Reserved
\r
288 volatile unsigned int dValue;
\r
289 }DBI_VCID;// 0x001C
\r
291 union _DSIH1P21A_DBI_CFG_tag_t {
\r
292 struct _DSIH1P21A_DBI_CFG_map_t
\r
294 volatile unsigned int in_dbi_conf :
\r
297 This field configures the DBI input pixel data as follows:
\r
305 0111: 16-bit 12 bpp
\r
306 1000: 16-bit 16 bpp
\r
307 1001: 16-bit 18 bpp, option 1
\r
308 1010: 16-bit 18 bpp, option 2
\r
309 1011: 16-bit 24 bpp, option 1
\r
310 1100: 16-bit 24 bpp, option 2
\r
312 volatile unsigned int reserved_0 :
\r
313 4; //[7:4] Reserved
\r
314 volatile unsigned int out_dbi_conf :
\r
317 This field configures the DBI output pixel data as follows:
\r
325 0111: 16-bit 12 bpp
\r
326 1000: 16-bit 16 bpp
\r
327 1001: 16-bit 18 bpp, option 1
\r
328 1010: 16-bit 18 bpp, option 2
\r
329 1011: 16-bit 24 bpp, option 1
\r
330 1100: 16-bit 24 bpp, option 2
\r
332 volatile unsigned int reserved_1 :
\r
333 4; //[15:12] Reserved
\r
335 volatile unsigned int lut_size_conf :
\r
338 This field configures the size used to transport the write Lut
\r
339 commands as follows:
\r
340 00: 16-bit color display
\r
341 01: 18-bit color display
\r
342 10: 24-bit color display
\r
343 11: 16-bit color display
\r
346 volatile unsigned int reserved_2 :
\r
347 14; //[31:18] Reserved
\r
350 volatile unsigned int dValue;
\r
353 union _DSIH1P21A_DBI_PARTITIONING_EN_tag_t {
\r
354 struct _DSIH1P21A_DBI_PARTITIONING_EN_map_t
\r
356 volatile unsigned int partitioning_en :
\r
359 When set to 1, this bit enables the use of write_memory_continue
\r
360 input commands (system needs to ensure correct partitioning of Long
\r
361 Write commands). When not set, partitioning is automatically
\r
362 performed in the DWC_mipi_dsi_host.
\r
364 volatile unsigned int reserved_0 :
\r
365 31; //[31:1] Reserved
\r
368 volatile unsigned int dValue;
\r
369 }DBI_PARTITIONING_EN;// 0x0024
\r
371 union _DSIH1P21A_DBI_CMDSIZE_tag_t {
\r
372 struct _DSIH1P21A_DBI_CMDSIZE_map_t
\r
374 volatile unsigned int wr_cmd_size :
\r
377 This field configures the size of the DCS write memory commands.
\r
378 The size of DSI packet payload is the actual payload size minus 1,
\r
379 because the DCS command is in the DSI packet payload
\r
381 volatile unsigned int allowed_cmd_size :
\r
384 This field configures the maximum allowed size for a DCS write
\r
385 memory command. This field is used to partition a write memory
\r
386 command into one write_memory_start and a variable number of
\r
387 write_memory_continue commands. It is only used if the
\r
388 partitioning_en bit of the DBI_CFG register is disabled.
\r
389 The size of the DSI packet payload is the actual payload size minus 1,
\r
390 because the DCS command is in the DSI packet payload.
\r
395 volatile unsigned int dValue;
\r
396 }DBI_CMDSIZE;// 0x0028
\r
398 union _DSIH1P21A_PCKHDL_CFG_tag_t {
\r
399 struct _DSIH1P21A_PCKHDL_CFG_map_t
\r
401 volatile unsigned int eotp_tx_en :
\r
402 1; //[0] When set to 1, this bit enables the EoTp transmission
\r
403 volatile unsigned int eotp_rx_en :
\r
404 1; //[1] When set to 1, this bit enables the EoTp reception.
\r
405 volatile unsigned int bta_en :
\r
406 1; //[2] When set to 1, this bit enables the Bus Turn-Around (BTA) request.
\r
407 volatile unsigned int ecc_rx_en :
\r
408 1; //[3] When set to 1, this bit enables the ECC reception, error correction, and reporting.
\r
409 volatile unsigned int crc_rx_en :
\r
410 1; //[4] When set to 1, this bit enables the CRC reception and error reporting. Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
411 volatile unsigned int reserved_0 :
\r
415 volatile unsigned int dValue;
\r
416 }PCKHDL_CFG;// 0x002C
\r
418 union _DSIH1P21A_GEN_VCID_tag_t {
\r
419 struct _DSIH1P21A_GEN_VCID_map_t
\r
421 volatile unsigned int gen_vcid_rx :
\r
422 2; //[1:0] This field indicates the Generic interface read-back virtual channel identification.
\r
423 volatile unsigned int reserved_0 :
\r
424 30; //[31:2] Reserved
\r
427 volatile unsigned int dValue;
\r
428 }GEN_VCID;// 0x0030
\r
430 union _DSIH1P21A_MODE_CFG_tag_t {
\r
431 struct _DSIH1P21A_MODE_CFG_map_t
\r
433 volatile unsigned int cmd_video_mode :
\r
434 1; //[0] This bit configures the operation mode:0: Video mode ; 1: Command mode
\r
435 volatile unsigned int reserved_0 :
\r
436 31; //[31:1] Reserved
\r
439 volatile unsigned int dValue;
\r
440 }MODE_CFG;// 0x0034
\r
442 union _DSIH1P21A_VID_MODE_CFG_tag_t {
\r
443 struct _DSIH1P21A_VID_MODE_CFG_map_t
\r
445 volatile unsigned int vid_mode_type :
\r
448 This field indicates the video mode transmission type as follows:
\r
449 00: Non-burst with sync pulses
\r
450 01: Non-burst with sync events
\r
451 10 and 11: Burst mode
\r
453 volatile unsigned int reserved_0 :
\r
455 volatile unsigned int lp_vsa_en :
\r
456 1; //[8] When set to 1, this bit enables the return to low-power inside the VSA period when timing allows.
\r
457 volatile unsigned int lp_vbp_en :
\r
458 1; //[9] When set to 1, this bit enables the return to low-power inside the VBP period when timing allows.
\r
459 volatile unsigned int lp_vfp_en :
\r
460 1; //[10] When set to 1, this bit enables the return to low-power inside the VFP period when timing allows.
\r
461 volatile unsigned int lp_vact_en :
\r
462 1; //[11] When set to 1, this bit enables the return to low-power inside the VACT period when timing allows.
\r
463 volatile unsigned int lp_hbp_en :
\r
464 1; //[12] When set to 1, this bit enables the return to low-power inside the HBP period when timing allows.
\r
465 volatile unsigned int lp_hfp_en :
\r
466 1; //[13] When set to 1, this bit enables the return to low-power inside the HFP period when timing allows.
\r
467 volatile unsigned int frame_bta_ack_en :
\r
468 1; //[14] When set to 1, this bit enables the request for an acknowledgeresponse at the end of a frame
\r
469 volatile unsigned int lp_cmd_en :
\r
470 1; //[15] When set to 1, this bit enables the command transmission only in lowpower mode.
\r
471 volatile unsigned int reserved_1 :
\r
475 volatile unsigned int dValue;
\r
476 }VID_MODE_CFG;// 0x0038
\r
478 union _DSIH1P21A_VID_PKT_SIZE_tag_t {
\r
479 struct _DSIH1P21A_VID_PKT_SIZE_map_t
\r
481 volatile unsigned int vid_pkt_size :
\r
482 14; //[13:0] This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2, as described in the DSI specification.
\r
483 volatile unsigned int reserved_0 :
\r
484 18; //[31:14] Reserved
\r
487 volatile unsigned int dValue;
\r
488 }VID_PKT_SIZE;// 0x003C
\r
490 union _DSIH1P21A_VID_NUM_CHUNKS_tag_t {
\r
491 struct _DSIH1P21A_VID_NUM_CHUNKS_map_t
\r
493 volatile unsigned int vid_num_chunks :
\r
496 This register configures the number of chunks to be transmitted during
\r
497 a Line period (a chunk consists of a video packet and a null packet).
\r
498 If set to 0 or 1, the video line is transmitted in a single packet.
\r
499 If set to 1, the packet is part of a chunk, so a null packet follows it if
\r
500 vid_null_size > 0. Otherwise, multiple chunks are used to transmit each video line.
\r
502 volatile unsigned int reserved_0 :
\r
503 19; //[31:13] Reserved
\r
506 volatile unsigned int dValue;
\r
507 }VID_NUM_CHUNKS;// 0x0040
\r
509 union _DSIH1P21A_VID_NULL_SIZE_tag_t {
\r
510 struct _DSIH1P21A_VID_NULL_SIZE_map_t
\r
512 volatile unsigned int vid_null_size :
\r
515 This register configures the number of bytes inside a null packet.
\r
516 Setting it to 0 disables the null packets.
\r
518 volatile unsigned int reserved_0 :
\r
519 19; //[31:13] Reserved
\r
522 volatile unsigned int dValue;
\r
523 }VID_NULL_SIZE;// 0x0044
\r
525 union _DSIH1P21A_VID_HSA_TIME_tag_t {
\r
526 struct _DSIH1P21A_VID_HSA_TIME_map_t
\r
528 volatile unsigned int vid_hsa_time :
\r
529 12; //[11:0] This field configures the Horizontal Synchronism Active period in lane byte clock cycles
\r
530 volatile unsigned int reserved_0 :
\r
531 20; //[31:12] Reserved
\r
534 volatile unsigned int dValue;
\r
535 }VID_HSA_TIME;// 0x0048
\r
537 union _DSIH1P21A_VID_HBP_TIME_tag_t {
\r
538 struct _DSIH1P21A_VID_HBP_TIME_map_t
\r
540 volatile unsigned int vid_hbp_time :
\r
541 12; //[11:0] This field configures the Horizontal Back Porch period in lane byte clock cycles.
\r
542 volatile unsigned int reserved_0 :
\r
543 20; //[31:12] Reserved
\r
546 volatile unsigned int dValue;
\r
547 }VID_HBP_TIME;// 0x004C
\r
549 union _DSIH1P21A_VID_HLINE_TIME_tag_t {
\r
550 struct _DSIH1P21A_VID_HLINE_TIME_map_t
\r
552 volatile unsigned int vid_hline_time :
\r
553 15; //[14:0] This field configures the size of the total line time (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.
\r
554 volatile unsigned int reserved_0 :
\r
555 17; //[31:15] Reserved
\r
558 volatile unsigned int dValue;
\r
559 }VID_HLINE_TIME;// 0x0050
\r
561 union _DSIH1P21A_VID_VSA_LINES_tag_t {
\r
562 struct _DSIH1P21A_VID_VSA_LINES_map_t
\r
564 volatile unsigned int vsa_lines :
\r
565 10; //[9:0] This field configures the Vertical Synchronism Active period measured in number of horizontal lines
\r
566 volatile unsigned int reserved_0 :
\r
567 22; //[31:10] Reserved
\r
570 volatile unsigned int dValue;
\r
571 }VID_VSA_LINES;// 0x0054
\r
573 union _DSIH1P21A_VID_VBP_LINES_tag_t {
\r
574 struct _DSIH1P21A_VID_VBP_LINES_map_t
\r
576 volatile unsigned int vbp_lines :
\r
577 10; //[9:0] This field configures the Vertical Back Porch period measured in number of horizontal lines.
\r
578 volatile unsigned int reserved_0 :
\r
579 22; //[31:10] Reserved
\r
582 volatile unsigned int dValue;
\r
583 }VID_VBP_LINES;// 0x0058
\r
585 union _DSIH1P21A_VID_VFP_LINES_tag_t {
\r
586 struct _DSIH1P21A_VID_VFP_LINES_map_t
\r
588 volatile unsigned int vfp_lines :
\r
589 10; //[9:0] This field configures the Vertical Front Porch period measured in number of horizontal lines.
\r
590 volatile unsigned int reserved_0 :
\r
591 22; //[31:10] Reserved
\r
594 volatile unsigned int dValue;
\r
595 }VID_VFP_LINES;// 0x005C
\r
597 union _DSIH1P21A_VID_VACTIVE_LINES_tag_t {
\r
598 struct _DSIH1P21A_VID_VACTIVE_LINES_map_t
\r
600 volatile unsigned int v_active_lines :
\r
601 14; //[13:0] This field configures the Vertical Active period measured in number of horizontal lines.
\r
602 volatile unsigned int reserved_0 :
\r
603 18; //[31:14] Reserved
\r
606 volatile unsigned int dValue;
\r
607 }VID_VACTIVE_LINES;// 0x0060
\r
609 union _DSIH1P21A_EDPI_CMD_SIZE_tag_t {
\r
610 struct _DSIH1P21A_EDPI_CMD_SIZE_map_t
\r
612 volatile unsigned int edpi_allowed_cmd_size :
\r
613 16; //[15:0] This field configures the maximum allowed size for an eDPI write memory command, measured in pixels. Automatic partitioning of data obtained from eDPI is permanently enabled.
\r
614 volatile unsigned int reserved_0 :
\r
615 16; //[31:16] Reserved
\r
618 volatile unsigned int dValue;
\r
619 }EDPI_CMD_SIZE;// 0x0064
\r
621 union _DSIH1P21A_CMD_MODE_CFG_tag_t {
\r
622 struct _DSIH1P21A_CMD_MODE_CFG_map_t
\r
624 volatile unsigned int tear_fx_en :
\r
625 1; //[0] When set to 1, this bit enables the tearing effect acknowledge request.
\r
626 volatile unsigned int ack_rqst_en :
\r
627 1; //[1] When set to 1, this bit enables the acknowledge request after each packet transmission.
\r
628 volatile unsigned int reserved_0 :
\r
630 volatile unsigned int gen_sw_0p_tx :
\r
631 1; //[8] This bit configures the Generic short write packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
632 volatile unsigned int gen_sw_1p_tx :
\r
633 1; //[9] This bit configures the Generic short write packet with one parameter command transmission type: 0: High-speed 1: Low-power
\r
634 volatile unsigned int gen_sw_2p_tx :
\r
635 1; //[10] This bit configures the Generic short write packet with two parameters command transmission type:0: High-speed 1: Low-power
\r
636 volatile unsigned int gen_sr_0p_tx :
\r
637 1; //[11] This bit configures the Generic short read packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
638 volatile unsigned int gen_sr_1p_tx :
\r
639 1; //[12] This bit configures the Generic short read packet with one parameter command transmission type:0: High-speed 1: Low-power
\r
640 volatile unsigned int gen_sr_2p_tx :
\r
641 1; //[13] This bit configures the Generic short read packet with two parameters command transmission type:0: High-speed 1: Low-power
\r
642 volatile unsigned int gen_lw_tx :
\r
643 1; //[14] This bit configures the Generic long write packet command transmission type:0: High-speed 1: Low-power
\r
644 volatile unsigned int reserved_1 :
\r
646 volatile unsigned int dcs_sw_0p_tx :
\r
647 1; //[16] This bit configures the DCS short write packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
648 volatile unsigned int dcs_sw_1p_tx :
\r
649 1; //[17] This bit configures the DCS short write packet with one parameter command transmission type:0: High-speed 1: Low-power
\r
650 volatile unsigned int dcs_sr_0p_tx :
\r
651 1; //[18] This bit configures the DCS short read packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
652 volatile unsigned int dcs_lw_tx :
\r
653 1; //[19] This bit configures the DCS long write packet command transmission type:0: High-speed 1: Low-power
\r
654 volatile unsigned int reserved_2 :
\r
656 volatile unsigned int max_rd_pkt_size :
\r
657 1; //[24] This bit configures the maximum read packet size command transmission type:0: High-speed 1: Low-power
\r
658 volatile unsigned int reserved_3 :
\r
662 volatile unsigned int dValue;
\r
663 }CMD_MODE_CFG;// 0x0068
\r
665 union _DSIH1P21A_GEN_HDR_tag_t {
\r
666 struct _DSIH1P21A_GEN_HDR_map_t
\r
668 volatile unsigned int gen_dt :
\r
669 6; //[5:0] This field configures the packet data type of the header packet.
\r
670 volatile unsigned int gen_vc :
\r
671 2; //[7:6] Reserved
\r
672 volatile unsigned int gen_wc_lsbyte :
\r
673 8; //[15:8] This field configures the least significant byte of the header packet's Word count for long packets or data 0 for short packets.
\r
674 volatile unsigned int gen_wc_msbyte :
\r
675 8; //[23:16] This field configures the most significant byte of the header packet's word count for long packets or data 1 for short packets.
\r
676 volatile unsigned int reserved_0 :
\r
677 8; //[31:24] Reserved
\r
680 volatile unsigned int dValue;
\r
683 union _DSIH1P21A_GEN_PLD_DATA_tag_t {
\r
684 struct _DSIH1P21A_GEN_PLD_DATA_map_t
\r
686 volatile unsigned int gen_pld_b1 :
\r
687 8; //[7:0] This field indicates byte 1 of the packet payload.
\r
688 volatile unsigned int gen_pld_b2 :
\r
689 8; //[15:8] This field indicates byte 2 of the packet payload.
\r
690 volatile unsigned int gen_pld_b3 :
\r
691 8; //[23:16] This field indicates byte 3 of the packet payload.
\r
692 volatile unsigned int gen_pld_b4 :
\r
693 8; //[31:24] This field indicates byte 4 of the packet payload.
\r
696 volatile unsigned int dValue;
\r
697 }GEN_PLD_DATA;// 0x0070
\r
699 union _DSIH1P21A_CMD_PKT_STATUS_tag_t {
\r
700 struct _DSIH1P21A_CMD_PKT_STATUS_map_t
\r
702 volatile unsigned int gen_cmd_empty :
\r
705 This bit indicates the empty status of the generic command FIFO.
\r
706 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
707 Value after reset: 0x1
\r
709 volatile unsigned int gen_cmd_full :
\r
712 This bit indicates the full status of the generic command FIFO.
\r
713 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
714 Value after reset: 0x0
\r
716 volatile unsigned int gen_pld_w_empty :
\r
719 This bit indicates the empty status of the generic write payload FIFO.
\r
720 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
721 Value after reset: 0x1
\r
723 volatile unsigned int gen_pld_w_full :
\r
726 This bit indicates the full status of the generic write payload FIFO.
\r
727 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
728 Value after reset: 0x0
\r
730 volatile unsigned int gen_pld_r_empty :
\r
733 This bit indicates the empty status of the generic read payload FIFO.
\r
734 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
735 Value after reset: 0x1
\r
737 volatile unsigned int gen_pld_r_full :
\r
740 This bit indicates the full status of the generic read payload FIFO.
\r
741 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
742 Value after reset: 0x0
\r
744 volatile unsigned int gen_rd_cmd_busy :
\r
747 This bit is set when a read command is issued and cleared when the
\r
748 entire response is stored in the FIFO.
\r
749 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
750 Value after reset: 0x0
\r
752 volatile unsigned int reserved_0 :
\r
756 volatile unsigned int dbi_cmd_empy :
\r
759 This bit indicates the empty status of the DBI command FIFO.
\r
760 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
761 Otherwise, this bit is reserved.
\r
762 Value after reset: 0x1
\r
764 volatile unsigned int dbi_cmd_full :
\r
767 This bit indicates the full status of the DBI command FIFO.
\r
768 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
769 Otherwise, this bit is reserved.
\r
770 Value after reset: 0x0
\r
772 volatile unsigned int dbi_pld_w_empty :
\r
775 This bit indicates the empty status of the DBI write payload FIFO.
\r
776 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
777 Otherwise, this bit is reserved.
\r
778 Value after reset: 0x1
\r
780 volatile unsigned int dbi_pld_w_full :
\r
783 This bit indicates the full status of the DBI write payload FIFO.
\r
784 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
785 Otherwise, this bit is reserved.
\r
786 Value after reset: 0x0
\r
788 volatile unsigned int dbi_pld_r_empty :
\r
791 This bit indicates the empty status of the DBI read payload FIFO.
\r
792 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
793 Otherwise, this bit is reserved.
\r
794 Value after reset: 0x1
\r
796 volatile unsigned int dbi_pld_r_full :
\r
799 This bit indicates the full status of the DBI read payload FIFO.
\r
800 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
801 Otherwise, this bit is reserved.
\r
802 Value after reset: 0x0
\r
804 volatile unsigned int dbi_rd_cmd_busy :
\r
807 This bit is set when a read command is issued and cleared when the
\r
808 entire response is stored in the FIFO.
\r
809 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
810 Otherwise, this bit is reserved.
\r
811 Value after reset: 0x0
\r
813 volatile unsigned int reserved_1 :
\r
817 volatile unsigned int dValue;
\r
819 CMD_PKT_STATUS;// 0x0074
\r
821 union _DSIH1P21A_TO_CNT_CFG_tag_t {
\r
822 struct _DSIH1P21A_TO_CNT_CFG_map_t
\r
824 volatile unsigned int lprx_to_cnt :
\r
827 This field configures the timeout counter that triggers a low-power
\r
828 reception timeout contention detection (measured in
\r
829 TO_CLK_DIVISION cycles).
\r
831 volatile unsigned int hstx_to_cnt :
\r
834 This field configures the timeout counter that triggers a high-speed
\r
835 transmission timeout contention detection (measured in
\r
836 TO_CLK_DIVISION cycles).
\r
837 If using the non-burst mode and there is no sufficient time to switch
\r
838 from HS to LP and back in the period which is from one line data
\r
839 finishing to the next line sync start, the DSI link returns the LP state
\r
840 once per frame, then you should configure the TO_CLK_DIVISION
\r
841 and hstx_to_cnt to be in accordance with:
\r
842 hstx_to_cnt * lanebyteclkperiod * TO_CLK_DIVISION >= the time of
\r
843 one FRAME data transmission * (1 + 10%)
\r
844 In burst mode, RGB pixel packets are time-compressed, leaving more
\r
845 time during a scan line. Therefore, if in burst mode and there is
\r
846 sufficient time to switch from HS to LP and back in the period of time
\r
847 from one line data finishing to the next line sync start, the DSI link can
\r
848 return LP mode and back in this time interval to save power. For this,
\r
849 configure the TO_CLK_DIVISION and hstx_to_cnt to be in accordance
\r
851 hstx_to_cnt * lanebyteclkperiod * TO_CLK_DIVISION >= the time of
\r
852 one LINE data transmission * (1 + 10%)
\r
856 volatile unsigned int dValue;
\r
858 TO_CNT_CFG;// 0x0078
\r
860 union _DSIH1P21A_HS_RD_TO_CNT_tag_t {
\r
861 struct _DSIH1P21A_HS_RD_TO_CNT_map_t
\r
863 volatile unsigned int hs_rd_to_cnt :
\r
866 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
867 link still, after sending a high-speed read operation. This period is
\r
868 measured in cycles of lanebyteclk. The counting starts when the
\r
869 D-PHY enters the Stop state and causes no interrupts.
\r
871 volatile unsigned int reserved_0 :
\r
875 volatile unsigned int dValue;
\r
877 HS_RD_TO_CNT;// 0x007C
\r
879 union _DSIH1P21A_LP_RD_TO_CNT_tag_t {
\r
880 struct _DSIH1P21A_LP_RD_TO_CNT_map_t
\r
882 volatile unsigned int lp_rd_to_cnt :
\r
885 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
886 link still, after sending a low-power read operation. This period is
\r
887 measured in cycles of lanebyteclk. The counting starts when the
\r
888 D-PHY enters the Stop state and causes no interrupts.
\r
890 volatile unsigned int reserved_0 :
\r
894 volatile unsigned int dValue;
\r
896 LP_RD_TO_CNT;// 0x0080
\r
898 union _DSIH1P21A_HS_WR_TO_CNT_tag_t {
\r
899 struct _DSIH1P21A_HS_WR_TO_CNT_map_t
\r
901 volatile unsigned int hs_wr_to_cnt :
\r
904 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
905 link inactive after sending a high-speed write operation. This period is
\r
906 measured in cycles of lanebyteclk. The counting starts when the
\r
907 D-PHY enters the Stop state and causes no interrupts.
\r
909 volatile unsigned int reserved_0 :
\r
911 volatile unsigned int presp_to_mode :
\r
914 When set to 1, this bit ensures that the peripheral response timeout
\r
915 caused by hs_wr_to_cnt is used only once per eDPI frame, when both
\r
916 the following conditions are met:
\r
917 dpivsync_edpiwms has risen and fallen.
\r
918 Packets originated from eDPI have been transmitted and its FIFO
\r
920 In this scenario no non-eDPI requests are sent to the D-PHY, even if
\r
921 there is traffic from generic or DBI ready to be sent, making it return to
\r
922 stop state. When it does so, PRESP_TO counter is activated and only
\r
923 when it finishes does the controller send any other traffic that is ready.
\r
924 Dependency: DSI_DATAINTERFACE = 4. Otherwise, this bit is
\r
927 volatile unsigned int reserved_1 :
\r
931 volatile unsigned int dValue;
\r
933 HS_WR_TO_CNT;// 0x0084
\r
935 union _DSIH1P21A_LP_WR_TO_CNT_tag_t {
\r
936 struct _DSIH1P21A_LP_WR_TO_CNT_map_t
\r
938 volatile unsigned int lp_wr_to_cnt :
\r
941 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
942 link still, after sending a low-power write operation. This period is
\r
943 measured in cycles of lanebyteclk. The counting starts when the
\r
944 D-PHY enters the Stop state and causes no interrupts
\r
946 volatile unsigned int reserved_0 :
\r
950 volatile unsigned int dValue;
\r
952 LP_WR_TO_CNT;// 0x0088
\r
954 union _DSIH1P21A_BTA_TO_CNT_tag_t {
\r
955 struct _DSIH1P21A_BTA_TO_CNT_map_t
\r
957 volatile unsigned int bta_to_cnt :
\r
960 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
961 link still, after completing a Bus Turn-Around. This period is measured
\r
962 in cycles of lanebyteclk. The counting starts when the D-PHY enters
\r
963 the Stop state and causes no interrupts.
\r
965 volatile unsigned int reserved_0 :
\r
969 volatile unsigned int dValue;
\r
971 BTA_TO_CNT;// 0x008C
\r
973 union _DSIH1P21A_SDF_3D_tag_t {
\r
974 struct _DSIH1P21A_SDF_3D_map_t
\r
976 volatile unsigned int mode_3d :
\r
979 This field defines the 3D mode on/off and display orientation:
\r
980 00: 3D mode off (2D mode on)
\r
981 01: 3D mode on, portrait orientation
\r
982 10: 3D mode on, landscape orientation
\r
986 volatile unsigned int ormat_3d :
\r
989 This field defines the 3D image format:
\r
990 00: Line (alternating lines of left and right data)
\r
991 01: Frame (alternating frames of left and right data)
\r
992 10: Pixel (alternating pixels of left and right data)
\r
996 volatile unsigned int second_vsync :
\r
999 This field defines whether there is a second VSYNC pulse between
\r
1000 Left and Right Images, when 3D Image Format is Frame-based:
\r
1001 0: No sync pulses between left and right data
\r
1002 1: Sync pulse (HSYNC, VSYNC, blanking) between left and right
\r
1005 volatile unsigned int right_first :
\r
1008 This bit defines the left or right order:
\r
1009 0: Left eye data is sent first, and then the right eye data is sent.
\r
1010 1: Right eye data is sent first, and then the left eye data is sent.
\r
1012 volatile unsigned int reserved_0 :
\r
1014 volatile unsigned int send_3d_cfg :
\r
1017 When set, causes the next VSS packet to include 3D control payload
\r
1018 in every VSS packet.
\r
1020 volatile unsigned int reserved_1 :
\r
1024 volatile unsigned int dValue;
\r
1028 union _DSIH1P21A_LPCLK_CTRL_tag_t {
\r
1029 struct _DSIH1P21A_LPCLK_CTRL_map_t
\r
1031 volatile unsigned int phy_txrequestclkhs :
\r
1032 1; //[0] This bit controls the D-PHY PPI txrequestclkhs signal
\r
1033 volatile unsigned int auto_clklane_ctrl :
\r
1034 1; //[0] This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows
\r
1035 volatile unsigned int reserved_0 :
\r
1039 volatile unsigned int dValue;
\r
1041 LPCLK_CTRL;// 0x0094
\r
1043 union _DSIH1P21A_PHY_TMR_LPCLK_CFG_tag_t {
\r
1044 struct _DSIH1P21A_PHY_TMR_LPCLK_CFG_map_t
\r
1046 volatile unsigned int phy_clklp2hs_time :
\r
1049 This field configures the maximum time that the D-PHY clock lane
\r
1050 takes to go from low-power to high-speed transmission measured in
\r
1051 lane byte clock cycles.
\r
1053 volatile unsigned int reserved_0 :
\r
1055 volatile unsigned int phy_clkhs2lp_time :
\r
1058 This field configures the maximum time that the D-PHY clock lane
\r
1059 takes to go from high-speed to low-power transmission measured in
\r
1060 lane byte clock cycles.
\r
1062 volatile unsigned int reserved_1 :
\r
1066 volatile unsigned int dValue;
\r
1068 PHY_TMR_LPCLK_CFG;// 0x0098
\r
1070 union _DSIH1P21A_PHY_TMR_CFG_tag_t {
\r
1071 struct _DSIH1P21A_PHY_TMR_CFG_map_t
\r
1073 volatile unsigned int max_rd_time :
\r
1076 This field configures the maximum time required to perform a read
\r
1077 command in lane byte clock cycles. This register can only be modified
\r
1078 when no read command is in progress.
\r
1080 volatile unsigned int reserved_0 :
\r
1082 volatile unsigned int phy_lp2hs_time :
\r
1085 This field configures the maximum time that the D-PHY data lanes
\r
1086 take to go from low-power to high-speed transmission measured in
\r
1087 lane byte clock cycles.
\r
1089 volatile unsigned int phy_hs2lp_time :
\r
1092 This field configures the maximum time that the D-PHY data lanes
\r
1093 take to go from high-speed to low-power transmission measured in
\r
1094 lane byte clock cycles.
\r
1098 volatile unsigned int dValue;
\r
1099 } PHY_TMR_CFG;// 0x009C
\r
1101 union _DSIH1P21A_PHY_RSTZ_tag_t {
\r
1102 struct _DSIH1P21A_PHY_RSTZ_map_t
\r
1104 volatile unsigned int phy_shutdownz :
\r
1105 1; //[0] When set to 0, this bit places the D-PHY macro in power-down state
\r
1106 volatile unsigned int phy_rstz :
\r
1107 1; //[1] When set to 0, this bit places the digital section of the D-PHY in the reset state.
\r
1108 volatile unsigned int phy_enableclk :
\r
1109 1; //[2] When set to1, this bit enables the D-PHY Clock Lane module.
\r
1110 volatile unsigned int phy_forcepll :
\r
1113 When the D-PHY is in ULPS, this bit enables the D-PHY PLL.
\r
1114 Dependency: DSI_HOST_FPGA = 0. Otherwise, this bit is reserved
\r
1116 volatile unsigned int reserved_0 :
\r
1120 volatile unsigned int dValue;
\r
1122 } PHY_RSTZ;// 0x00A0
\r
1124 union _DSIH1P21A_PHY_IF_CFG_tag_t {
\r
1125 struct _DSIH1P21A_PHY_IF_CFG_map_t
\r
1127 volatile unsigned int n_lanes :
\r
1130 This field configures the number of active data lanes:
\r
1131 00: One data lane (lane 0)
\r
1132 01: Two data lanes (lanes 0 and 1)
\r
1133 10: Three data lanes (lanes 0, 1, and 2)
\r
1134 11: Four data lanes (lanes 0, 1, 2, and 3)
\r
1136 volatile unsigned int reserved_0 :
\r
1138 volatile unsigned int phy_stop_wait_time :
\r
1139 8; //[15:8] This field configures the minimum wait period to request a high-speed transmission after the Stop state.
\r
1140 volatile unsigned int reserved_1 :
\r
1144 volatile unsigned int dValue;
\r
1145 }PHY_IF_CFG;// 0x00A4
\r
1147 union _DSIH1P21A_PHY_ULPS_CTRL_tag_t {
\r
1148 struct _DSIH1P21A_PHY_ULPS_CTRL_map_t
\r
1150 volatile unsigned int phy_txrequlpsclk :
\r
1151 1; //[0] ULPS mode Request on clock lane.
\r
1152 volatile unsigned int phy_txexitulpsclk :
\r
1153 1; //[1] ULPS mode Exit on clock lane.
\r
1154 volatile unsigned int phy_txrequlpslan :
\r
1155 1; //[2] ULPS mode Request on all active data lanes.
\r
1156 volatile unsigned int phy_txexitulpslan :
\r
1157 1; //[3] ULPS mode Exit on all active data lanes.
\r
1158 volatile unsigned int reserved_0 :
\r
1162 volatile unsigned int dValue;
\r
1164 PHY_ULPS_CTRL;// 0x00A8
\r
1166 union _DSIH1P21A_PHY_TX_TRIGGERS_tag_t {
\r
1167 struct _DSIH1P21A_PHY_TX_TRIGGERS_map_t
\r
1169 volatile unsigned int phy_tx_triggers :
\r
1170 4; //[3:0] This field controls the trigger transmissions
\r
1171 volatile unsigned int reserved_0 :
\r
1175 volatile unsigned int dValue;
\r
1177 PHY_TX_TRIGGERS;// 0x00AC
\r
1179 union _DSIH1P21A_PHY_STATUS_tag_t {
\r
1180 struct _DSIH1P21A_PHY_STATUS_map_t
\r
1182 volatile unsigned int phy_lock :
\r
1183 1; //[0] This bit indicates the status of phylock D-PHY signal.
\r
1184 volatile unsigned int phy_direction :
\r
1185 1; //[1] This bit indicates the status of phydirection D-PHY signal.
\r
1186 volatile unsigned int phy_stopstateclklane :
\r
1187 1; //[2] This bit indicates the status of phystopstateclklane D-PHY signal.
\r
1188 volatile unsigned int phy_ulpsactivenotclk :
\r
1189 1; //[3] This bit indicates the status of phyulpsactivenotclk D-PHY signal.
\r
1190 volatile unsigned int phy_stopstate0lane :
\r
1191 1; //[4] This bit indicates the status of phystopstate0lane D-PHY signal.
\r
1192 volatile unsigned int phy_ulpsactivenot0lane :
\r
1193 1; //[5] This bit indicates the status of ulpsactivenot0lane D-PHY signal.
\r
1194 volatile unsigned int phy_rxulpsesc0lane :
\r
1195 1; //[6] This bit indicates the status of rxulpsesc0lane D-PHY signal.
\r
1196 volatile unsigned int phy_stopstate1lane :
\r
1199 This bit indicates the status of phystopstate1lane D-PHY signal.
\r
1200 Dependency: DSI_HOST_NUMBER_OF_LANES > 1
\r
1201 If DSI_HOST_NUMBER_OF_LANES <= 1, this bit is reserved.
\r
1203 volatile unsigned int phy_ulpsactivenot1lane :
\r
1206 This bit indicates the status of ulpsactivenot1lane D-PHY signal.
\r
1207 Dependency: DSI_HOST_NUMBER_OF_LANES > 1
\r
1208 If DSI_HOST_NUMBER_OF_LANES <= 1, this bit is reserved.
\r
1210 volatile unsigned int phy_stopstate2lane :
\r
1213 This bit indicates the status of phystopstate2lane D-PHY signal.
\r
1214 Dependency: DSI_HOST_NUMBER_OF_LANES > 2
\r
1215 If DSI_HOST_NUMBER_OF_LANES <= 2, this bit is reserved.
\r
1217 volatile unsigned int phy_ulpsactivenot2lane :
\r
1220 This bit indicates the status of ulpsactivenot2lane D-PHY signal.
\r
1221 Dependency: DSI_HOST_NUMBER_OF_LANES > 2
\r
1222 If DSI_HOST_NUMBER_OF_LANES <= 2, this bit is reserved.
\r
1224 volatile unsigned int phy_stopstate3lane :
\r
1227 This bit indicates the status of phystopstate3lane D-PHY signal.
\r
1228 Dependency: DSI_HOST_NUMBER_OF_LANES > 3
\r
1229 If DSI_HOST_NUMBER_OF_LANES <= 3, this bit is reserved
\r
1231 volatile unsigned int phy_ulpsactivenot3lane :
\r
1234 This bit indicates the status of ulpsactivenot3lane D-PHY signal.
\r
1235 Dependency: DSI_HOST_NUMBER_OF_LANES > 3
\r
1236 If DSI_HOST_NUMBER_OF_LANES <= 3, this bit is reserved
\r
1238 volatile unsigned int reserved_0 :
\r
1242 volatile unsigned int dValue;
\r
1243 } PHY_STATUS;// 0x00B0
\r
1245 union _DSIH1P21A_PHY_TST_CTRL0_tag_t {
\r
1246 struct _DSIH1P21A_PHY_TST_CTRL0_map_t
\r
1248 volatile unsigned int phy_testclr :
\r
1249 1; //[0] PHY test interface clear (active high).
\r
1250 volatile unsigned int phy_testclk :
\r
1251 1; //[1] This bit is used to clock the TESTDIN bus into the D-PHY.
\r
1252 volatile unsigned int reserved_0 :
\r
1256 volatile unsigned int dValue;
\r
1258 PHY_TST_CTRL0;// 0x00B4
\r
1260 union _DSIH1P21A_PHY_TST_CTRL1_tag_t {
\r
1261 struct _DSIH1P21A_PHY_TST_CTRL1_map_t
\r
1263 volatile unsigned int phy_testdin :
\r
1264 8; //[7:0] PHY test interface input 8-bit data bus for internal register programming and test functionalities access.
\r
1265 volatile unsigned int pht_testdout :
\r
1266 8; //[15:8] PHY output 8-bit data bus for read-back and internal probing functionalities.
\r
1267 volatile unsigned int phy_testen :
\r
1270 PHY test interface operation selector:
\r
1271 1: The address write operation is set on the falling edge of the testclk signal.
\r
1272 0: The data write operation is set on the rising edge of the testclk signal.
\r
1274 volatile unsigned int reserved_0 :
\r
1278 volatile unsigned int dValue;
\r
1280 PHY_TST_CTRL1;// 0x00B8
\r
1282 union _DSIH1P21A_INT_ST0_tag_t {
\r
1283 struct _DSIH1P21A_INT_ST0_map_t
\r
1285 volatile unsigned int ack_with_err_0 :
\r
1286 1; //[0] This bit retrieves the SoT error from the Acknowledge error report.
\r
1287 volatile unsigned int ack_with_err_1 :
\r
1288 1; //[1] This bit retrieves the SoT Sync error from the Acknowledge error report.
\r
1289 volatile unsigned int ack_with_err_2 :
\r
1290 1; //[2] This bit retrieves the EoT Sync error from the Acknowledge error report.
\r
1291 volatile unsigned int ack_with_err_3 :
\r
1292 1; //[3] This bit retrieves the Escape Mode Entry Command error from the Acknowledge error report.
\r
1293 volatile unsigned int ack_with_err_4 :
\r
1294 1; //[4] This bit retrieves the LP Transmit Sync error from the Acknowledge error report.
\r
1295 volatile unsigned int ack_with_err_5 :
\r
1296 1; //[5] This bit retrieves the Peripheral Timeout error from the Acknowledge Error report.
\r
1297 volatile unsigned int ack_with_err_6 :
\r
1298 1; //[6] This bit retrieves the False Control error from the Acknowledge error report.
\r
1299 volatile unsigned int ack_with_err_7 :
\r
1300 1; //[7] This bit retrieves the reserved (specific to device) from the Acknowledge error report.
\r
1301 volatile unsigned int ack_with_err_8 :
\r
1302 1; //[8] This bit retrieves the ECC error, single-bit (detected and corrected) from the Acknowledge error report.
\r
1303 volatile unsigned int ack_with_err_9 :
\r
1304 1; //[9] This bit retrieves the ECC error, multi-bit (detected, not corrected) from the Acknowledge error report.
\r
1305 volatile unsigned int ack_with_err_10 :
\r
1306 1; //[10]This bit retrieves the checksum error (long packet only) from the Acknowledge error report.
\r
1307 volatile unsigned int ack_with_err_11 :
\r
1308 1; //[11] This bit retrieves the not recognized DSI data type from the Acknowledge error report.
\r
1309 volatile unsigned int ack_with_err_12 :
\r
1310 1; //[12] This bit retrieves the DSI VC ID Invalid from the Acknowledge error report.
\r
1311 volatile unsigned int ack_with_err_13 :
\r
1312 1; //[13] This bit retrieves the invalid transmission length from the Acknowledge error report.
\r
1313 volatile unsigned int ack_with_err_14 :
\r
1314 1; //[14] This bit retrieves the reserved (specific to device) from the Acknowledge error report
\r
1315 volatile unsigned int ack_with_err_15 :
\r
1316 1; //[15] This bit retrieves the DSI protocol violation from the Acknowledge error report.
\r
1317 volatile unsigned int dphy_errors_0 :
\r
1318 1; //[16] This bit indicates ErrEsc escape entry error from Lane 0.
\r
1319 volatile unsigned int dphy_errors_1 :
\r
1320 1; //[17] This bit indicates ErrSyncEsc low-power data transmission synchronization error from Lane 0.
\r
1321 volatile unsigned int dphy_errors_2 :
\r
1322 1; //[18] This bit indicates the ErrControl error from Lane 0.
\r
1323 volatile unsigned int dphy_errors_3 :
\r
1324 1; //[19] This bit indicates the LP0 contention error ErrContentionLP0 from Lane 0.
\r
1325 volatile unsigned int dphy_errors_4 :
\r
1326 1; //[20] This bit indicates the LP1 contention error ErrContentionLP1 from Lane 0.
\r
1327 volatile unsigned int reserved_0 :
\r
1331 volatile unsigned int dValue;
\r
1335 union _DSIH1P21A_INT_ST1_tag_t {
\r
1336 struct _DSIH1P21A_INT_ST1_map_t
\r
1338 volatile unsigned int to_hs_tx :
\r
1341 This bit indicates that the high-speed transmission timeout counter
\r
1342 reached the end and contention is detected.
\r
1344 volatile unsigned int to_lp_rx :
\r
1347 This bit indicates that the low-power reception timeout counter reached
\r
1348 the end and contention is detected.
\r
1350 volatile unsigned int ecc_single_err :
\r
1353 This bit indicates that the ECC single error is detected and corrected in a
\r
1356 volatile unsigned int ecc_multi_err :
\r
1359 This bit indicates that the ECC multiple error is detected in a received
\r
1362 volatile unsigned int crc_err :
\r
1365 This bit indicates that the CRC error is detected in the received packet
\r
1367 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or
\r
1368 DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1370 volatile unsigned int pkt_size_err :
\r
1373 This bit indicates that the packet size error is detected during the packet
\r
1376 volatile unsigned int eopt_err :
\r
1379 This bit indicates that the EoTp packet is not received at the end of the
\r
1380 incoming peripheral transmission
\r
1382 volatile unsigned int dpi_pld_wr_err :
\r
1385 This bit indicates that during a DPI pixel line storage, the payload FIFO
\r
1386 becomes full and the data stored is corrupted.
\r
1387 Dependency: DSI_DATAINTERFACE = 2 or DSI_DATAINTERFACE = 3 or
\r
1388 DSI_DATAINTERFACE = 4. Otherwise, this bit is reserved.
\r
1390 volatile unsigned int gen_cmd_wr_err :
\r
1393 This bit indicates that the system tried to write a command through the
\r
1394 Generic interface and the FIFO is full. Therefore, the command is not
\r
1396 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1398 volatile unsigned int gen_pld_wr_err :
\r
1401 This bit indicates that the system tried to write a payload data through the
\r
1402 Generic interface and the FIFO is full. Therefore, the payload is not
\r
1404 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1406 volatile unsigned int gen_pld_send_err :
\r
1409 This bit indicates that during a Generic interface packet build, the payload
\r
1410 FIFO becomes empty and corrupt data is sent.
\r
1411 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1413 volatile unsigned int gen_pld_rd_err :
\r
1416 This bit indicates that during a DCS read data, the payload FIFO becomes
\r
1417 empty and the data sent to the interface is corrupted.
\r
1418 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1420 volatile unsigned int gen_pld_recev_err :
\r
1423 This bit indicates that during a generic interface packet read back, the
\r
1424 payload FIFO becomes full and the received data is corrupted.
\r
1425 Dependency: DSI_GENERIC = 1
\r
1426 If DSI_GENERIC = 0, this bit is reserved.
\r
1428 volatile unsigned int dbi_cmd_wr_err :
\r
1431 This bit indicates that the system tried to write a command through the
\r
1432 DBI but the command FIFO is full. Therefore, the command is not written.
\r
1433 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1434 Otherwise, this bit is reserved.
\r
1436 volatile unsigned int dbi_pld_wr_err :
\r
1439 This bit indicates that the system tried to write the payload data through
\r
1440 the DBI interface and the FIFO is full. Therefore, the command is not
\r
1442 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1443 Otherwise, this bit is reserved.
\r
1445 volatile unsigned int dbi_pld_rd_err :
\r
1448 This bit indicates that during a DCS read data, the payload FIFO goes
\r
1449 empty and the data sent to the interface is corrupted.
\r
1450 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1451 Otherwise, this bit is reserved.
\r
1453 volatile unsigned int dbi_pld_recv_err :
\r
1456 This bit indicates that during a DBI read back packet, the payload FIFO
\r
1457 becomes full and the received data is corrupted.
\r
1458 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1459 Otherwise, this bit is reserved.
\r
1462 volatile unsigned int dbi_ilegal_comm_err :
\r
1465 This bit indicates that an attempt to write an illegal command on the DBI
\r
1466 interface is made and the core is blocked by transmission.
\r
1467 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1468 Otherwise, this bit is reserved.
\r
1470 volatile unsigned int reserved_0 :
\r
1474 volatile unsigned int dValue;
\r
1479 union _DSIH1P21A_INT_MSK0_tag_t {
\r
1480 struct _DSIH1P21A_INT_MSK0_map_t
\r
1482 volatile unsigned int ack_with_err_0 :
\r
1483 1; //[0] This bit retrieves the SoT error from the Acknowledge error report.
\r
1484 volatile unsigned int ack_with_err_1 :
\r
1485 1; //[1] This bit retrieves the SoT Sync error from the Acknowledge error report.
\r
1486 volatile unsigned int ack_with_err_2 :
\r
1487 1; //[2] This bit retrieves the EoT Sync error from the Acknowledge error report.
\r
1488 volatile unsigned int ack_with_err_3 :
\r
1489 1; //[3] This bit retrieves the Escape Mode Entry Command error from the Acknowledge error report.
\r
1490 volatile unsigned int ack_with_err_4 :
\r
1491 1; //[4] This bit retrieves the LP Transmit Sync error from the Acknowledge error report.
\r
1492 volatile unsigned int ack_with_err_5 :
\r
1493 1; //[5] This bit retrieves the Peripheral Timeout error from the Acknowledge Error report.
\r
1494 volatile unsigned int ack_with_err_6 :
\r
1495 1; //[6] This bit retrieves the False Control error from the Acknowledge error report.
\r
1496 volatile unsigned int ack_with_err_7 :
\r
1497 1; //[7] This bit retrieves the reserved (specific to device) from the Acknowledge error report.
\r
1498 volatile unsigned int ack_with_err_8 :
\r
1499 1; //[8] This bit retrieves the ECC error, single-bit (detected and corrected) from the Acknowledge error report.
\r
1500 volatile unsigned int ack_with_err_9 :
\r
1501 1; //[9] This bit retrieves the ECC error, multi-bit (detected, not corrected) from the Acknowledge error report.
\r
1502 volatile unsigned int ack_with_err_10 :
\r
1503 1; //[10]This bit retrieves the checksum error (long packet only) from the Acknowledge error report.
\r
1504 volatile unsigned int ack_with_err_11 :
\r
1505 1; //[11] This bit retrieves the not recognized DSI data type from the Acknowledge error report.
\r
1506 volatile unsigned int ack_with_err_12 :
\r
1507 1; //[12] This bit retrieves the DSI VC ID Invalid from the Acknowledge error report.
\r
1508 volatile unsigned int ack_with_err_13 :
\r
1509 1; //[13] This bit retrieves the invalid transmission length from the Acknowledge error report.
\r
1510 volatile unsigned int ack_with_err_14 :
\r
1511 1; //[14] This bit retrieves the reserved (specific to device) from the Acknowledge error report
\r
1512 volatile unsigned int ack_with_err_15 :
\r
1513 1; //[15] This bit retrieves the DSI protocol violation from the Acknowledge error report.
\r
1514 volatile unsigned int dphy_errors_0 :
\r
1515 1; //[16] This bit indicates ErrEsc escape entry error from Lane 0.
\r
1516 volatile unsigned int dphy_errors_1 :
\r
1517 1; //[17] This bit indicates ErrSyncEsc low-power data transmission synchronization error from Lane 0.
\r
1518 volatile unsigned int dphy_errors_2 :
\r
1519 1; //[18] This bit indicates the ErrControl error from Lane 0.
\r
1520 volatile unsigned int dphy_errors_3 :
\r
1521 1; //[19] This bit indicates the LP0 contention error ErrContentionLP0 from Lane 0.
\r
1522 volatile unsigned int dphy_errors_4 :
\r
1523 1; //[20] This bit indicates the LP1 contention error ErrContentionLP1 from Lane 0.
\r
1524 volatile unsigned int reserved_0 :
\r
1528 volatile unsigned int dValue;
\r
1530 INT_MSK0;// 0x00C4
\r
1533 union _DSIH1P21A_INT_MSK1_tag_t {
\r
1534 struct _DSIH1P21A_INT_MSK1_map_t
\r
1536 volatile unsigned int to_hs_tx :
\r
1539 This bit indicates that the high-speed transmission timeout counter
\r
1540 reached the end and contention is detected.
\r
1542 volatile unsigned int to_lp_rx :
\r
1545 This bit indicates that the low-power reception timeout counter reached
\r
1546 the end and contention is detected.
\r
1548 volatile unsigned int ecc_single_err :
\r
1551 This bit indicates that the ECC single error is detected and corrected in a
\r
1554 volatile unsigned int ecc_multi_err :
\r
1557 This bit indicates that the ECC multiple error is detected in a received
\r
1560 volatile unsigned int crc_err :
\r
1563 This bit indicates that the CRC error is detected in the received packet
\r
1565 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or
\r
1566 DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1568 volatile unsigned int pkt_size_err :
\r
1571 This bit indicates that the packet size error is detected during the packet
\r
1574 volatile unsigned int eopt_err :
\r
1577 This bit indicates that the EoTp packet is not received at the end of the
\r
1578 incoming peripheral transmission
\r
1580 volatile unsigned int dpi_pld_wr_err :
\r
1583 This bit indicates that during a DPI pixel line storage, the payload FIFO
\r
1584 becomes full and the data stored is corrupted.
\r
1585 Dependency: DSI_DATAINTERFACE = 2 or DSI_DATAINTERFACE = 3 or
\r
1586 DSI_DATAINTERFACE = 4. Otherwise, this bit is reserved.
\r
1588 volatile unsigned int gen_cmd_wr_err :
\r
1591 This bit indicates that the system tried to write a command through the
\r
1592 Generic interface and the FIFO is full. Therefore, the command is not
\r
1594 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1596 volatile unsigned int gen_pld_wr_err :
\r
1599 This bit indicates that the system tried to write a payload data through the
\r
1600 Generic interface and the FIFO is full. Therefore, the payload is not
\r
1602 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1604 volatile unsigned int gen_pld_send_err :
\r
1607 This bit indicates that during a Generic interface packet build, the payload
\r
1608 FIFO becomes empty and corrupt data is sent.
\r
1609 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1611 volatile unsigned int gen_pld_rd_err :
\r
1614 This bit indicates that during a DCS read data, the payload FIFO becomes
\r
1615 empty and the data sent to the interface is corrupted.
\r
1616 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1618 volatile unsigned int gen_pld_recev_err :
\r
1621 This bit indicates that during a generic interface packet read back, the
\r
1622 payload FIFO becomes full and the received data is corrupted.
\r
1623 Dependency: DSI_GENERIC = 1
\r
1624 If DSI_GENERIC = 0, this bit is reserved.
\r
1626 volatile unsigned int dbi_cmd_wr_err :
\r
1629 This bit indicates that the system tried to write a command through the
\r
1630 DBI but the command FIFO is full. Therefore, the command is not written.
\r
1631 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1632 Otherwise, this bit is reserved.
\r
1634 volatile unsigned int dbi_pld_wr_err :
\r
1637 This bit indicates that the system tried to write the payload data through
\r
1638 the DBI interface and the FIFO is full. Therefore, the command is not
\r
1640 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1641 Otherwise, this bit is reserved.
\r
1643 volatile unsigned int dbi_pld_rd_err :
\r
1646 This bit indicates that during a DCS read data, the payload FIFO goes
\r
1647 empty and the data sent to the interface is corrupted.
\r
1648 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1649 Otherwise, this bit is reserved.
\r
1651 volatile unsigned int dbi_pld_recv_err :
\r
1654 This bit indicates that during a DBI read back packet, the payload FIFO
\r
1655 becomes full and the received data is corrupted.
\r
1656 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1657 Otherwise, this bit is reserved.
\r
1660 volatile unsigned int dbi_ilegal_comm_err :
\r
1663 This bit indicates that an attempt to write an illegal command on the DBI
\r
1664 interface is made and the core is blocked by transmission.
\r
1665 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1666 Otherwise, this bit is reserved.
\r
1668 volatile unsigned int reserved_0 :
\r
1672 volatile unsigned int dValue;
\r
1674 INT_MSK1;// 0x00C8
\r
1677 uint32_t mipi_dsih_hal_get_version(dsih_ctrl_t * instance);
\r
1679 void mipi_dsih_hal_power(dsih_ctrl_t * instance, int on);
\r
1681 int mipi_dsih_hal_get_power(dsih_ctrl_t * instance);
\r
1683 void mipi_dsih_hal_tx_escape_division(dsih_ctrl_t * instance, uint8_t tx_escape_division);
\r
1685 void mipi_dsih_hal_dpi_video_vc(dsih_ctrl_t * instance, uint8_t vc);
\r
1687 uint8_t mipi_dsih_hal_dpi_get_video_vc(dsih_ctrl_t * instance);
\r
1689 dsih_error_t mipi_dsih_hal_dpi_color_coding(dsih_ctrl_t * instance, dsih_color_coding_t color_coding);
\r
1690 dsih_color_coding_t mipi_dsih_hal_dpi_get_color_coding(dsih_ctrl_t * instance);
\r
1691 uint8_t mipi_dsih_hal_dpi_get_color_depth(dsih_ctrl_t * instance);
\r
1692 uint8_t mipi_dsih_hal_dpi_get_color_config(dsih_ctrl_t * instance);
\r
1693 void mipi_dsih_hal_dpi_18_loosely_packet_en(dsih_ctrl_t * instance, int enable);
\r
1694 void mipi_dsih_hal_dpi_color_mode_pol(dsih_ctrl_t * instance, int active_low);
\r
1695 void mipi_dsih_hal_dpi_shut_down_pol(dsih_ctrl_t * instance, int active_low);
\r
1696 void mipi_dsih_hal_dpi_hsync_pol(dsih_ctrl_t * instance, int active_low);
\r
1697 void mipi_dsih_hal_dpi_vsync_pol(dsih_ctrl_t * instance, int active_low);
\r
1698 void mipi_dsih_hal_dpi_dataen_pol(dsih_ctrl_t * instance, int active_low);
\r
1699 void mipi_dsih_hal_dpi_frame_ack_en(dsih_ctrl_t * instance, int enable);
\r
1700 void mipi_dsih_hal_dpi_null_packet_en(dsih_ctrl_t * instance, int enable);
\r
1701 void mipi_dsih_hal_dpi_multi_packet_en(dsih_ctrl_t * instance, int enable);
\r
1702 void mipi_dsih_hal_dpi_lp_during_hfp(dsih_ctrl_t * instance, int enable);
\r
1703 void mipi_dsih_hal_dpi_lp_during_hbp(dsih_ctrl_t * instance, int enable);
\r
1704 void mipi_dsih_hal_dpi_lp_during_vactive(dsih_ctrl_t * instance, int enable);
\r
1705 void mipi_dsih_hal_dpi_lp_during_vfp(dsih_ctrl_t * instance, int enable);
\r
1706 void mipi_dsih_hal_dpi_lp_during_vbp(dsih_ctrl_t * instance, int enable);
\r
1707 void mipi_dsih_hal_dpi_lp_during_vsync(dsih_ctrl_t * instance, int enable);
\r
1709 dsih_error_t mipi_dsih_hal_dpi_video_mode_type(dsih_ctrl_t * instance, dsih_video_mode_t type);
\r
1710 void mipi_dsih_hal_dpi_video_mode_en(dsih_ctrl_t * instance, int enable);
\r
1711 int mipi_dsih_hal_dpi_is_video_mode(dsih_ctrl_t * instance);
\r
1712 dsih_error_t mipi_dsih_hal_dpi_null_packet_size(dsih_ctrl_t * instance, uint16_t size);
\r
1713 dsih_error_t mipi_dsih_hal_dpi_chunks_no(dsih_ctrl_t * instance, uint16_t no);
\r
1714 dsih_error_t mipi_dsih_hal_dpi_video_packet_size(dsih_ctrl_t * instance, uint16_t size);
\r
1716 void mipi_dsih_hal_tear_effect_ack_en(dsih_ctrl_t * instance, int enable);
\r
1718 void mipi_dsih_hal_cmd_ack_en(dsih_ctrl_t * instance, int enable);
\r
1719 dsih_error_t mipi_dsih_hal_dcs_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1720 dsih_error_t mipi_dsih_hal_dcs_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1721 /*Jessica add to support max rd packet size command*/
\r
1722 dsih_error_t mipi_dsih_hal_max_rd_packet_size_type(dsih_ctrl_t * instance, int lp);
\r
1723 dsih_error_t mipi_dsih_hal_gen_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1724 dsih_error_t mipi_dsih_hal_gen_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1725 void mipi_dsih_hal_max_rd_size_type(dsih_ctrl_t * instance, int lp);
\r
1726 void mipi_dsih_hal_gen_cmd_mode_en(dsih_ctrl_t * instance, int enable);
\r
1727 int mipi_dsih_hal_gen_is_cmd_mode(dsih_ctrl_t * instance);
\r
1729 void mipi_dsih_hal_dpi_hline(dsih_ctrl_t * instance, uint16_t time);
\r
1730 void mipi_dsih_hal_dpi_hbp(dsih_ctrl_t * instance, uint16_t time);
\r
1731 void mipi_dsih_hal_dpi_hsa(dsih_ctrl_t * instance, uint16_t time);
\r
1732 void mipi_dsih_hal_dpi_vactive(dsih_ctrl_t * instance, uint16_t lines);
\r
1733 void mipi_dsih_hal_dpi_vfp(dsih_ctrl_t * instance, uint16_t lines);
\r
1734 void mipi_dsih_hal_dpi_vbp(dsih_ctrl_t * instance, uint16_t lines);
\r
1735 void mipi_dsih_hal_dpi_vsync(dsih_ctrl_t * instance, uint16_t lines);
\r
1737 void mipi_dsih_hal_edpi_max_allowed_size(dsih_ctrl_t * instance, uint16_t size);
\r
1739 dsih_error_t mipi_dsih_hal_gen_packet_header(dsih_ctrl_t * instance, uint8_t vc, uint8_t packet_type, uint8_t ms_byte, uint8_t ls_byte);
\r
1740 dsih_error_t mipi_dsih_hal_gen_packet_payload(dsih_ctrl_t * instance, uint32_t payload);
\r
1741 dsih_error_t mipi_dsih_hal_gen_read_payload(dsih_ctrl_t * instance, uint32_t* payload);
\r
1743 void mipi_dsih_hal_timeout_clock_division(dsih_ctrl_t * instance, uint8_t byte_clk_division_factor);
\r
1744 void mipi_dsih_hal_lp_rx_timeout(dsih_ctrl_t * instance, uint16_t count);
\r
1745 void mipi_dsih_hal_hs_tx_timeout(dsih_ctrl_t * instance, uint16_t count);
\r
1747 uint32_t mipi_dsih_hal_int_status_0(dsih_ctrl_t * instance, uint32_t mask);
\r
1748 uint32_t mipi_dsih_hal_int_status_1(dsih_ctrl_t * instance, uint32_t mask);
\r
1749 void mipi_dsih_hal_int_mask_0(dsih_ctrl_t * instance, uint32_t mask);
\r
1750 void mipi_dsih_hal_int_mask_1(dsih_ctrl_t * instance, uint32_t mask);
\r
1751 uint32_t mipi_dsih_hal_int_get_mask_0(dsih_ctrl_t * instance, uint32_t mask);
\r
1752 uint32_t mipi_dsih_hal_int_get_mask_1(dsih_ctrl_t * instance, uint32_t mask);
\r
1753 /* DBI command interface */
\r
1754 void mipi_dsih_hal_dbi_out_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);
\r
1755 void mipi_dsih_hal_dbi_in_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);
\r
1756 void mipi_dsih_hal_dbi_lut_size(dsih_ctrl_t * instance, uint8_t size);
\r
1757 void mipi_dsih_hal_dbi_partitioning_en(dsih_ctrl_t * instance, int enable);
\r
1758 void mipi_dsih_hal_dbi_dcs_vc(dsih_ctrl_t * instance, uint8_t vc);
\r
1760 void mipi_dsih_hal_dbi_cmd_size(dsih_ctrl_t * instance, uint16_t size);
\r
1761 void mipi_dsih_hal_dbi_max_cmd_size(dsih_ctrl_t * instance, uint16_t size);
\r
1762 int mipi_dsih_hal_dbi_rd_cmd_busy(dsih_ctrl_t * instance);
\r
1763 int mipi_dsih_hal_dbi_read_fifo_full(dsih_ctrl_t * instance);
\r
1764 int mipi_dsih_hal_dbi_read_fifo_empty(dsih_ctrl_t * instance);
\r
1765 int mipi_dsih_hal_dbi_write_fifo_full(dsih_ctrl_t * instance);
\r
1766 int mipi_dsih_hal_dbi_write_fifo_empty(dsih_ctrl_t * instance);
\r
1767 int mipi_dsih_hal_dbi_cmd_fifo_full(dsih_ctrl_t * instance);
\r
1768 int mipi_dsih_hal_dbi_cmd_fifo_empty(dsih_ctrl_t * instance);
\r
1769 /* Generic command interface */
\r
1770 void mipi_dsih_hal_gen_rd_vc(dsih_ctrl_t * instance, uint8_t vc);
\r
1771 void mipi_dsih_hal_gen_eotp_rx_en(dsih_ctrl_t * instance, int enable);
\r
1772 void mipi_dsih_hal_gen_eotp_tx_en(dsih_ctrl_t * instance, int enable);
\r
1773 void mipi_dsih_hal_bta_en(dsih_ctrl_t * instance, int enable);
\r
1774 void mipi_dsih_hal_gen_ecc_rx_en(dsih_ctrl_t * instance, int enable);
\r
1775 void mipi_dsih_hal_gen_crc_rx_en(dsih_ctrl_t * instance, int enable);
\r
1776 int mipi_dsih_hal_gen_rd_cmd_busy(dsih_ctrl_t * instance);
\r
1777 int mipi_dsih_hal_gen_read_fifo_full(dsih_ctrl_t * instance);
\r
1778 int mipi_dsih_hal_gen_read_fifo_empty(dsih_ctrl_t * instance);
\r
1779 int mipi_dsih_hal_gen_write_fifo_full(dsih_ctrl_t * instance);
\r
1780 int mipi_dsih_hal_gen_write_fifo_empty(dsih_ctrl_t * instance);
\r
1781 int mipi_dsih_hal_gen_cmd_fifo_full(dsih_ctrl_t * instance);
\r
1782 int mipi_dsih_hal_gen_cmd_fifo_empty(dsih_ctrl_t * instance);
\r
1785 dsih_error_t mipi_dsih_phy_hs2lp_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
\r
1786 dsih_error_t mipi_dsih_phy_lp2hs_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
\r
1787 dsih_error_t mipi_dsih_phy_clk_lp2hs_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
\r
1788 dsih_error_t mipi_dsih_phy_clk_hs2lp_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
\r
1789 dsih_error_t mipi_dsih_phy_bta_time(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1790 void mipi_dsih_non_continuous_clock(dsih_ctrl_t * instance, int enable);
\r
1791 int mipi_dsih_non_continuous_clock_status(dsih_ctrl_t * instance);
\r
1792 /* PRESP Time outs */
\r
1793 void mipi_dsih_hal_presp_timeout_low_power_write(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1794 void mipi_dsih_hal_presp_timeout_low_power_read(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1795 void mipi_dsih_hal_presp_timeout_high_speed_write(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1796 void mipi_dsih_hal_presp_timeout_high_speed_read(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1797 void mipi_dsih_hal_presp_timeout_bta(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
\r
1798 /* bsp abstraction */
\r
1799 void mipi_dsih_write_word(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data);
\r
1800 void mipi_dsih_write_part(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data, uint8_t shift, uint8_t width);
\r
1801 uint32_t mipi_dsih_read_word(dsih_ctrl_t * instance, uint32_t reg_address);
\r
1802 uint32_t mipi_dsih_read_part(dsih_ctrl_t * instance, uint32_t reg_address, uint8_t shift, uint8_t width);
\r
1804 #endif /* MIPI_DSI_API_H_ */
\r