2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 #include <soc/sprd/hardware.h>
19 #define AHB_CTL0 (SPRD_AHB_BASE + 0x200)
20 #define AHB_SOFT_RST (SPRD_AHB_BASE + 0x210)
22 /* LCDC regs offset */
23 #define LCDC_CTRL (0x0000)
24 #define LCDC_DISP_SIZE (0x0004)
25 #define LCDC_LCM_START (0x0008)
26 #define LCDC_LCM_SIZE (0x000c)
27 #define LCDC_BG_COLOR (0x0010)
28 #define LCDC_FIFO_STATUS (0x0014)
30 #define LCDC_IMG_CTRL (0x0020)
31 #define LCDC_IMG_Y_BASE_ADDR (0x0024)
32 #define LCDC_IMG_UV_BASE_ADDR (0x0028)
33 #define LCDC_IMG_SIZE_XY (0x002c)
34 #define LCDC_IMG_PITCH (0x0030)
35 #define LCDC_IMG_DISP_XY (0x0034)
37 #define LCDC_OSD1_CTRL (0x0050)
38 #define LCDC_OSD2_CTRL (0x0080)
39 #define LCDC_OSD3_CTRL (0x00b0)
40 #define LCDC_OSD4_CTRL (0x00e0)
41 #define LCDC_OSD5_CTRL (0x0110)
43 #define LCDC_OSD1_BASE_ADDR (0x0054)
44 #define LCDC_OSD1_ALPHA_BASE_ADDR (0x0058)
45 #define LCDC_OSD1_SIZE_XY (0x005c)
46 #define LCDC_OSD1_PITCH (0x0060)
47 #define LCDC_OSD1_DISP_XY (0x0064)
48 #define LCDC_OSD1_ALPHA (0x0068)
49 #define LCDC_OSD1_GREY_RGB (0x006c)
50 #define LCDC_OSD1_CK (0x0070)
52 #define LCDC_OSD2_BASE_ADDR (0x0084)
53 #define LCDC_OSD2_SIZE_XY (0x008c)
54 #define LCDC_OSD2_PITCH (0x0090)
55 #define LCDC_OSD2_DISP_XY (0x0094)
56 #define LCDC_OSD2_ALPHA (0x0098)
57 #define LCDC_OSD2_GREY_RGB (0x009c)
58 #define LCDC_OSD2_CK (0x00a0)
60 #define LCDC_IRQ_EN (0x0170)
61 #define LCDC_IRQ_CLR (0x0174)
62 #define LCDC_IRQ_STATUS (0x0178)
63 #define LCDC_IRQ_RAW (0x017c)
65 #define LCM_CTRL (0x0180)
66 #define LCM_TIMING0 (0x0184)
67 #define LCM_TIMING1 (0x0188)
68 #define LCM_RDDATA (0x018c)
69 #define LCM_RSTN (0x0190)
70 #define LCM_CMD (0x01A0)
71 #define LCM_DATA (0x01A4)
73 extern unsigned long g_dispc_base_addr;
75 static inline uint32_t lcdc_read(uint32_t reg)
77 return __raw_readl(SPRD_LCDC_BASE + reg);
80 static inline void lcdc_write(uint32_t value, uint32_t reg)
82 __raw_writel(value, (SPRD_LCDC_BASE + reg));
85 static inline void lcdc_set_bits(uint32_t bits, uint32_t reg)
87 lcdc_write(lcdc_read(reg) | bits, reg);
90 static inline void lcdc_clear_bits(uint32_t bits, uint32_t reg)
92 lcdc_write(lcdc_read(reg) & ~bits, reg);