drivers/autotst/dispc_reg.h

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _DISPC_REG_H_
  15 #define _DISPC_REG_H_
  16
  17 #include <asm/io.h>
  18 #include <soc/sprd/sci.h>
  19 #include <soc/sprd/hardware.h>
  20 #include <soc/sprd/sci_glb_regs.h>
  21
  22 /* DISPC regs offset */
  23 #define DISPC_CTRL              (0x0000)
  24 #define DISPC_SIZE_XY           (0x0004)
  25 #define DISPC_RSTN              (0x0008)
  26
  27 #define DISPC_STS                       (0x0010)
  28
  29 #define DISPC_IMG_CTRL                  (0x0020)
  30 #define DISPC_IMG_Y_BASE_ADDR   (0x0024)
  31 #define DISPC_IMG_UV_BASE_ADDR  (0x0028)
  32 #define DISPC_IMG_V_BASE_ADDR   (0x002c)
  33 #define DISPC_IMG_SIZE_XY                       (0x0030)
  34 #define DISPC_IMG_PITCH                 (0x0034)
  35 #define DISPC_IMG_DISP_XY                       (0x0038)
  36 #define DISPC_BG_COLOR                  (0x003c)
  37
  38 #define DISPC_OSD_CTRL          (0x0040)
  39 #define DISPC_OSD_BASE_ADDR     (0x0044)
  40 #define DISPC_OSD_SIZE_XY               (0x0048)
  41 #define DISPC_OSD_PITCH         (0x004c)
  42 #define DISPC_OSD_DISP_XY               (0x0050)
  43 #define DISPC_OSD_ALPHA         (0x0054)
  44 #define DISPC_OSD_CK                    (0x0058)
  45
  46 #define DISPC_Y2R_CTRL                  (0x0060)
  47 #define DISPC_Y2R_CONTRAST              (0x0064)
  48 #define DISPC_Y2R_SATURATION            (0x0068)
  49 #define DISPC_Y2R_BRIGHTNESS            (0x006c)
  50
  51 #define DISPC_INT_EN                    (0x0070)
  52 #define DISPC_INT_CLR                   (0x0074)
  53 #define DISPC_INT_STATUS                (0x0078)
  54 #define DISPC_INT_RAW           (0x007c)
  55
  56 #define DISPC_DPI_CTRL          (0x0080)
  57 #define DISPC_DPI_H_TIMING      (0x0084)
  58 #define DISPC_DPI_V_TIMING      (0x0088)
  59 #define DISPC_DPI_STS0          (0x008c)
  60 #define DISPC_DPI_STS1          (0x0090)
  61
  62 #define DISPC_DBI_CTRL          (0x00a0)
  63 #define DISPC_DBI_TIMING0               (0x00a4)
  64 #define DISPC_DBI_TIMING1               (0x00a8)
  65 #define DISPC_DBI_RDATA         (0x00ac)
  66 #define DISPC_DBI_CMD           (0x00b0)
  67 #define DISPC_DBI_DATA          (0x00b4)
  68 #define DISPC_DBI_QUEUE         (0x00b8)
  69
  70
  71
  72 //shadow register , read only
  73 #define SHDW_IMG_CTRL                           (0x00C0)
  74 #define SHDW_IMG_Y_BASE_ADDR            (0x00C4)
  75 #define SHDW_IMG_UV_BASE_ADDR           (0x00C8)
  76 #define SHDW_IMG_V_BASE_ADDR            (0x00CC)
  77 #define SHDW_IMG_SIZE_XY                        (0x00D0)
  78 #define SHDW_IMG_PITCH                          (0x00D4)
  79 #define SHDW_IMG_DISP_XY                        (0x00D8)
  80 #define SHDW_BG_COLOR                           (0x00DC)
  81 #define SHDW_OSD_CTRL                           (0x00E0)
  82 #define SHDW_OSD_BASE_ADDR                      (0x00E4)
  83 #define SHDW_OSD_SIZE_XY                        (0x00E8)
  84 #define SHDW_OSD_PITCH                          (0x00EC)
  85 #define SHDW_OSD_DISP_XY                        (0x00F0)
  86 #define SHDW_OSD_ALPHA                          (0x00F4)
  87 #define SHDW_OSD_CK                                     (0x00F8)
  88 #define SHDW_Y2R_CTRL                           (0x0100)
  89 #define SHDW_Y2R_CONTRAST                       (0x0104)
  90 #define SHDW_Y2R_SATURATION                     (0x0108)
  91 #define SHDW_Y2R_BRIGHTNESS                     (0x010C)
  92 #define SHDW_DPI_H_TIMING                       (0x0110)
  93 #define SHDW_DPI_V_TIMING                       (0x0114)
  94 #define DISPC_TE_SYNC_DELAY     (0x00bc)
  95
  96 #define SPRD_LCDC_BASE                  g_dispc_base_addr
  97
  98 #define SPRD_DISPC_BASE                 SPRD_LCDC_BASE
  99 #define IRQ_DISPC_INT                   IRQ_DISPC0_INT
 100
 101 #define REG_AHB_SOFT_RST                        (0x4 + SPRD_AHB_BASE)
 102
 103 #define DISPC_CORE_EN                   (REG_AP_APB_APB_EB)
 104 #define BIT_DISPC_CORE_EN                       (BIT_AP_CKG_EB)
 105
 106 extern unsigned long g_dispc_base_addr;
 107
 108
 109 enum{
 110         DISPC_IF_DBI = 0,
 111         DISPC_IF_DPI,
 112         DISPC_IF_EDPI,
 113         DISPC_IF_LIMIT
 114 };
 115
 116 static inline uint32_t dispc_read(uint32_t reg)
 117 {
 118         return sci_glb_read(SPRD_DISPC_BASE + reg, 0xffffffff);
 119 }
 120
 121 static inline void dispc_write(uint32_t value, uint32_t reg)
 122 {
 123         sci_glb_write((SPRD_DISPC_BASE + reg), value, 0xffffffff);
 124 }
 125
 126 static inline void dispc_set_bits(uint32_t bits, uint32_t reg)
 127 {
 128         dispc_write(dispc_read(reg) | bits, reg);
 129 }
 130
 131 static inline void dispc_clear_bits(uint32_t bits, uint32_t reg)
 132 {
 133         dispc_write(dispc_read(reg) & ~bits, reg);
 134 }
 135
 136 #endif