1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
4 * Author: Tor Krill <tor@excito.com>
6 * This is a driver for Silicon Image sil3114 sata chip modelled on
17 #include <asm/byteorder.h>
22 #include "sata_sil3114.h"
24 /* Convert sectorsize to wordsize */
25 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
28 u8 sil3114_spin_up (int num);
29 u8 sil3114_spin_down (int num);
30 static int sata_bus_softreset (int num);
31 static void sata_identify (int num, int dev);
32 static u8 check_power_mode (int num);
33 static void sata_port (struct sata_ioports *ioport);
34 static void set_Feature_cmd (int num, int dev);
35 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
36 unsigned int max, u8 usealtstatus);
37 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
38 static void msleep (int count);
40 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
42 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
44 static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
47 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
51 static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
54 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
59 static int sata_bus_softreset (int num)
63 port[num].dev_mask = 1;
65 port[num].ctl_reg = 0x08; /*Default value of control reg */
66 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
68 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
70 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
72 /* spec mandates ">= 2ms" before checking status.
73 * We wait 150ms, because that was the magic delay used for
74 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
75 * between when the ATA command register is written, and then
76 * status is checked. Because waiting for "a while" before
77 * checking status is fine, post SRST, we perform this magic
81 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
82 while ((status & ATA_BUSY)) {
84 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
87 if (status & ATA_BUSY) {
88 printf ("ata%u is slow to respond,plz be patient\n", num);
91 while ((status & ATA_BUSY)) {
93 status = sata_chk_status (&port[num].ioaddr, 0);
96 if (status & ATA_BUSY) {
97 printf ("ata%u failed to respond : ", num);
98 printf ("bus reset failed\n");
99 port[num].dev_mask = 0;
105 static void sata_identify (int num, int dev)
107 u8 cmd = 0, status = 0, devno = num;
108 u16 iobuf[ATA_SECTOR_WORDS];
111 memset (iobuf, 0, sizeof (iobuf));
113 if (!(port[num].dev_mask & 0x01)) {
114 printf ("dev%d is not present on port#%d\n", dev, num);
118 debug ("port=%d dev=%d\n", num, dev);
121 cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
122 writeb (cmd, port[num].ioaddr.command_addr);
123 readb (port[num].ioaddr.altstatus_addr);
126 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
127 if (status & ATA_ERR) {
128 printf ("\ndevice not responding\n");
129 port[num].dev_mask &= ~0x01;
133 input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
135 ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
137 debug ("Specific config: %x\n", iobuf[2]);
139 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
140 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
141 debug ("ata%u: no dma/lba\n", num);
146 n_sectors = ata_id_n_sectors (iobuf);
148 if (n_sectors == 0) {
149 port[num].dev_mask &= ~0x01;
152 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
153 ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
154 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
155 ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
156 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
157 ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
159 /* TODO - atm we asume harddisk ie not removable */
160 sata_dev_desc[devno].removable = 0;
162 sata_dev_desc[devno].lba = (u32) n_sectors;
163 debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
166 if (iobuf[83] & (1 << 10)) {
167 sata_dev_desc[devno].lba48 = 1;
169 sata_dev_desc[devno].lba48 = 0;
174 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
175 sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
176 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
179 static void set_Feature_cmd (int num, int dev)
183 if (!(port[num].dev_mask & 0x01)) {
184 debug ("dev%d is not present on port#%d\n", dev, num);
188 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
189 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
190 writeb (0, port[num].ioaddr.lbal_addr);
191 writeb (0, port[num].ioaddr.lbam_addr);
192 writeb (0, port[num].ioaddr.lbah_addr);
194 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
195 writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
200 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
201 if ((status & (ATA_BUSY | ATA_ERR))) {
202 printf ("Error : status 0x%02x\n", status);
203 port[num].dev_mask &= ~0x01;
207 u8 sil3114_spin_down (int num)
211 debug ("Spin down disk\n");
213 if (!(port[num].dev_mask & 0x01)) {
214 debug ("Device ata%d is not present\n", num);
218 if ((status = check_power_mode (num)) == 0x00) {
219 debug ("Already in standby\n");
223 if (status == 0x01) {
224 printf ("Failed to check power mode on ata%d\n", num);
228 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
229 printf ("Device ata%d not ready\n", num);
233 writeb (0x00, port[num].ioaddr.feature_addr);
235 writeb (0x00, port[num].ioaddr.nsect_addr);
236 writeb (0x00, port[num].ioaddr.lbal_addr);
237 writeb (0x00, port[num].ioaddr.lbam_addr);
238 writeb (0x00, port[num].ioaddr.lbah_addr);
240 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
241 writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
243 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
244 if ((status & (ATA_BUSY | ATA_ERR))) {
245 printf ("Error waiting for disk spin down: status 0x%02x\n",
247 port[num].dev_mask &= ~0x01;
253 u8 sil3114_spin_up (int num)
257 debug ("Spin up disk\n");
259 if (!(port[num].dev_mask & 0x01)) {
260 debug ("Device ata%d is not present\n", num);
264 if ((status = check_power_mode (num)) != 0x00) {
265 if (status == 0x01) {
266 printf ("Failed to check power mode on ata%d\n", num);
269 /* should be up and running already */
274 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
275 printf ("Device ata%d not ready\n", num);
279 debug ("Stautus of device check: %d\n", status);
281 writeb (0x00, port[num].ioaddr.feature_addr);
283 writeb (0x00, port[num].ioaddr.nsect_addr);
284 writeb (0x00, port[num].ioaddr.lbal_addr);
285 writeb (0x00, port[num].ioaddr.lbam_addr);
286 writeb (0x00, port[num].ioaddr.lbah_addr);
288 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
289 writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
291 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
292 if ((status & (ATA_BUSY | ATA_ERR))) {
293 printf ("Error waiting for disk spin up: status 0x%02x\n",
295 port[num].dev_mask &= ~0x01;
299 /* Wait for disk to enter Active state */
302 status = check_power_mode (num);
303 } while ((status == 0x00) || (status == 0x80));
305 if (status == 0x01) {
306 printf ("Falied waiting for disk to spin up\n");
313 /* Return value is not the usual here
314 * 0x00 - Device stand by
315 * 0x01 - Operation failed
317 * 0xff - Device active
319 static u8 check_power_mode (int num)
323 if (!(port[num].dev_mask & 0x01)) {
324 debug ("Device ata%d is not present\n", num);
328 if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
329 printf ("Device ata%d not ready\n", num);
333 writeb (0, port[num].ioaddr.feature_addr);
334 writeb (0, port[num].ioaddr.nsect_addr);
335 writeb (0, port[num].ioaddr.lbal_addr);
336 writeb (0, port[num].ioaddr.lbam_addr);
337 writeb (0, port[num].ioaddr.lbah_addr);
339 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
340 writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
342 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
343 if ((status & (ATA_BUSY | ATA_ERR))) {
345 ("Error waiting for check power mode complete : status 0x%02x\n",
347 port[num].dev_mask &= ~0x01;
350 res = readb (port[num].ioaddr.nsect_addr);
351 debug ("Check powermode: %d\n", res);
356 static void sata_port (struct sata_ioports *ioport)
358 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
359 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
360 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
361 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
362 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
363 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
364 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
365 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
366 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
367 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
370 static u8 wait_for_irq (int num, unsigned int max)
373 u32 port = iobase[5];
376 port += VND_TF_CNST_CH0;
379 port += VND_TF_CNST_CH1;
382 port += VND_TF_CNST_CH2;
385 port += VND_TF_CNST_CH3;
392 if (readl (port) & VND_TF_CNST_INTST) {
402 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
403 unsigned int max, u8 usealtstatus)
408 if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
413 } while ((status & bits) && (max > 0));
418 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
421 return readb (ioaddr->status_addr);
423 return readb (ioaddr->altstatus_addr);
427 static void msleep (int count)
431 for (i = 0; i < count; i++)
435 /* Read up to 255 sectors
437 * Returns sectors read
439 static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
445 u64 blknr = (u64) block;
447 if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
448 printf ("Device ata%d not ready\n", device);
452 /* Set up transfer */
455 /* write high bits */
456 writeb (0, port[device].ioaddr.nsect_addr);
457 writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
458 writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
459 writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
462 writeb (blkcnt, port[device].ioaddr.nsect_addr);
463 writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
464 writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
465 writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
469 writeb (ATA_LBA, port[device].ioaddr.device_addr);
470 writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
474 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
475 port[device].ioaddr.device_addr);
476 writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
479 status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
481 if (status & ATA_BUSY) {
484 printf ("Device %d not responding status %d\n", device, status);
485 err = readb (port[device].ioaddr.error_addr);
486 printf ("Error reg = 0x%x\n", err);
492 if (wait_for_irq (device, 500)) {
493 printf ("ata%u irq failed\n", device);
497 status = sata_chk_status (&port[device].ioaddr, 0);
498 if (status & ATA_ERR) {
499 printf ("ata%u error %d\n", device,
500 readb (port[device].ioaddr.error_addr));
503 /* Read one sector */
504 input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
505 buff += ATA_SECTOR_WORDS;
512 ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
515 u16 *buffer = (u16 *) buff;
517 u64 blknr = (u64) block;
518 unsigned char lba48 = 0;
521 if (blknr > 0xfffffff) {
522 if (!sata_dev_desc[device].lba48) {
523 printf ("Drive doesn't support 48-bit addressing\n");
526 /* more than 28 bits used, use 48bit mode */
539 status = do_one_read (device, blknr, sread, buffer, lba48);
540 if (status != sread) {
541 printf ("Read failed\n");
548 buffer += sread * ATA_SECTOR_WORDS;
553 ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
556 u16 *buffer = (u16 *) buff;
557 unsigned char status = 0, num = 0;
558 u64 blknr = (u64) block;
560 unsigned char lba48 = 0;
562 if (blknr > 0xfffffff) {
563 if (!sata_dev_desc[device].lba48) {
564 printf ("Drive doesn't support 48-bit addressing\n");
567 /* more than 28 bits used, use 48bit mode */
574 while (blkcnt-- > 0) {
575 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
576 if (status & ATA_BUSY) {
577 printf ("ata%u failed to respond\n", port[num].port_no);
582 /* write high bits */
583 writeb (0, port[num].ioaddr.nsect_addr);
584 writeb ((blknr >> 24) & 0xFF,
585 port[num].ioaddr.lbal_addr);
586 writeb ((blknr >> 32) & 0xFF,
587 port[num].ioaddr.lbam_addr);
588 writeb ((blknr >> 40) & 0xFF,
589 port[num].ioaddr.lbah_addr);
592 writeb (1, port[num].ioaddr.nsect_addr);
593 writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
594 writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
595 writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
598 writeb (ATA_LBA, port[num].ioaddr.device_addr);
599 writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
603 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
604 port[num].ioaddr.device_addr);
605 writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
609 /*may take up to 4 sec */
610 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
611 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
612 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
613 device, (ulong) blknr, status);
617 output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
618 readb (port[num].ioaddr.altstatus_addr);
623 buffer += ATA_SECTOR_WORDS;
628 /* Driver implementation */
629 static u8 sil_get_device_cache_line (pci_dev_t pdev)
632 pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
636 int init_sata (int dev)
638 static u8 init_done = 0;
651 if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
656 /* Read out all BARs, even though we only use MMIO from BAR5 */
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
660 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
661 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
662 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
664 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
665 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
666 (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
667 printf ("Error no base addr for SATA controller\n");
672 /* mask off unused bits */
673 iobase[0] &= 0xfffffffc;
674 iobase[1] &= 0xfffffff8;
675 iobase[2] &= 0xfffffffc;
676 iobase[3] &= 0xfffffff8;
677 iobase[4] &= 0xfffffff0;
678 iobase[5] &= 0xfffffc00;
680 /* from sata_sil in Linux kernel */
681 cls = sil_get_device_cache_line (devno);
684 cls++; /* cls = (line_size/8)+1 */
685 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
686 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
687 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
688 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
690 printf ("Cache line not set. Driver may not function\n");
693 /* Enable operation */
694 pci_read_config_word (devno, PCI_COMMAND, &cmd);
695 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
696 pci_write_config_word (devno, PCI_COMMAND, cmd);
698 /* Disable interrupt usage */
699 pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
700 sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
701 pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
707 int reset_sata(int dev)
712 /* Check if device is connected to port */
713 int sata_bus_probe (int portno)
715 u32 port = iobase[5];
719 port += VND_SSTATUS_CH0;
722 port += VND_SSTATUS_CH1;
725 port += VND_SSTATUS_CH2;
728 port += VND_SSTATUS_CH3;
734 if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
741 int sata_phy_reset (int portno)
743 u32 port = iobase[5];
747 port += VND_SCONTROL_CH0;
750 port += VND_SCONTROL_CH1;
753 port += VND_SCONTROL_CH2;
756 port += VND_SCONTROL_CH3;
762 writel (val | SATA_SC_DET_RST, port);
764 writel (val & ~SATA_SC_DET_RST, port);
768 int scan_sata (int dev)
770 /* A bit brain dead, but the code has a legacy */
774 port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
775 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
776 (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
777 port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
779 #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
782 port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
783 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
784 (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
785 port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
787 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
790 port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
791 port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
792 (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
793 port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
795 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
798 port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
799 port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
800 (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
801 port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
805 printf ("Tried to scan unknown port: ata%d\n", dev);
809 /* Initialize other registers */
810 sata_port (&port[dev].ioaddr);
812 /* Check for attached device */
813 if (!sata_bus_probe (dev)) {
814 port[dev].port_state = 0;
815 debug ("SATA#%d port is not present\n", dev);
817 debug ("SATA#%d port is present\n", dev);
818 if (sata_bus_softreset (dev)) {
819 /* soft reset failed, try a hard one */
820 sata_phy_reset (dev);
821 if (sata_bus_softreset (dev)) {
822 port[dev].port_state = 0;
824 port[dev].port_state = 1;
827 port[dev].port_state = 1;
830 if (port[dev].port_state == 1) {
831 /* Probe device and set xfer mode */
832 sata_identify (dev, 0);
833 set_Feature_cmd (dev, 0);