2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
36 * Port request block (PRB) 32 bytes
46 * Scatter gather entry (SGE) 16 bytes
57 struct sil24_port_multiplier {
66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
82 * Global controller registers (128 bytes @ BAR0)
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
118 PORT_REGS_SIZE = 0x2000,
120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
150 PORT_CONTEXT = 0x1e04,
151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
256 ATA_FLAG_AN | ATA_FLAG_PMP,
257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
259 IRQ_STAT_4PORTS = 0xf,
262 struct sil24_ata_block {
263 struct sil24_prb prb;
264 struct sil24_sge sge[SIL24_MAX_SGE];
267 struct sil24_atapi_block {
268 struct sil24_prb prb;
270 struct sil24_sge sge[SIL24_MAX_SGE];
273 union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
278 static struct sil24_cerr_info {
279 unsigned int err_mask, action;
281 } sil24_cerr_db[] = {
282 [0] = { AC_ERR_DEV, 0,
284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
285 "device error via D2H FIS" },
286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
287 "device error via SDB FIS" },
288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
289 "error in data FIS" },
290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
291 "failed to transmit command FIS" },
292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
293 "protocol mismatch" },
294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
295 "data directon mismatch" },
296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
297 "ran out of SGEs while writing" },
298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
299 "ran out of SGEs while reading" },
300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
301 "invalid data directon for ATAPI CDB" },
302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
303 "SGT not on qword boundary" },
304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
305 "PCI target abort while fetching SGT" },
306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
307 "PCI master abort while fetching SGT" },
308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
309 "PCI parity error while fetching SGT" },
310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
311 "PRB not on qword boundary" },
312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
313 "PCI target abort while fetching PRB" },
314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
315 "PCI master abort while fetching PRB" },
316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
317 "PCI parity error while fetching PRB" },
318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
319 "undefined error while transferring data" },
320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
321 "PCI target abort while transferring data" },
322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
323 "PCI master abort while transferring data" },
324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
325 "PCI parity error while transferring data" },
326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
327 "FIS received while sending service FIS" },
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
336 struct sil24_port_priv {
337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
342 static void sil24_dev_config(struct ata_device *dev);
343 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
344 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
345 static int sil24_qc_defer(struct ata_queued_cmd *qc);
346 static void sil24_qc_prep(struct ata_queued_cmd *qc);
347 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
348 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
349 static void sil24_pmp_attach(struct ata_port *ap);
350 static void sil24_pmp_detach(struct ata_port *ap);
351 static void sil24_freeze(struct ata_port *ap);
352 static void sil24_thaw(struct ata_port *ap);
353 static int sil24_softreset(struct ata_link *link, unsigned int *class,
354 unsigned long deadline);
355 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
356 unsigned long deadline);
357 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
358 unsigned long deadline);
359 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
360 unsigned long deadline);
361 static void sil24_error_handler(struct ata_port *ap);
362 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
363 static int sil24_port_start(struct ata_port *ap);
364 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
366 static int sil24_pci_device_resume(struct pci_dev *pdev);
367 static int sil24_port_resume(struct ata_port *ap);
370 static const struct pci_device_id sil24_pci_tbl[] = {
371 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
372 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
373 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
374 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
375 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
376 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
378 { } /* terminate list */
381 static struct pci_driver sil24_pci_driver = {
383 .id_table = sil24_pci_tbl,
384 .probe = sil24_init_one,
385 .remove = ata_pci_remove_one,
387 .suspend = ata_pci_device_suspend,
388 .resume = sil24_pci_device_resume,
392 static struct scsi_host_template sil24_sht = {
393 ATA_NCQ_SHT(DRV_NAME),
394 .can_queue = SIL24_MAX_CMDS,
395 .sg_tablesize = SIL24_MAX_SGE,
396 .dma_boundary = ATA_DMA_BOUNDARY,
399 static struct ata_port_operations sil24_ops = {
400 .inherits = &sata_pmp_port_ops,
402 .qc_defer = sil24_qc_defer,
403 .qc_prep = sil24_qc_prep,
404 .qc_issue = sil24_qc_issue,
405 .qc_fill_rtf = sil24_qc_fill_rtf,
407 .freeze = sil24_freeze,
409 .softreset = sil24_softreset,
410 .hardreset = sil24_hardreset,
411 .pmp_softreset = sil24_pmp_softreset,
412 .pmp_hardreset = sil24_pmp_hardreset,
413 .error_handler = sil24_error_handler,
414 .post_internal_cmd = sil24_post_internal_cmd,
415 .dev_config = sil24_dev_config,
417 .scr_read = sil24_scr_read,
418 .scr_write = sil24_scr_write,
419 .pmp_attach = sil24_pmp_attach,
420 .pmp_detach = sil24_pmp_detach,
422 .port_start = sil24_port_start,
424 .port_resume = sil24_port_resume,
429 * Use bits 30-31 of port_flags to encode available port numbers.
430 * Current maxium is 4.
432 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
433 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
435 static const struct ata_port_info sil24_port_info[] = {
438 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
439 SIL24_FLAG_PCIX_IRQ_WOC,
440 .pio_mask = 0x1f, /* pio0-4 */
441 .mwdma_mask = 0x07, /* mwdma0-2 */
442 .udma_mask = ATA_UDMA5, /* udma0-5 */
443 .port_ops = &sil24_ops,
447 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
448 .pio_mask = 0x1f, /* pio0-4 */
449 .mwdma_mask = 0x07, /* mwdma0-2 */
450 .udma_mask = ATA_UDMA5, /* udma0-5 */
451 .port_ops = &sil24_ops,
453 /* sil_3131/sil_3531 */
455 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
456 .pio_mask = 0x1f, /* pio0-4 */
457 .mwdma_mask = 0x07, /* mwdma0-2 */
458 .udma_mask = ATA_UDMA5, /* udma0-5 */
459 .port_ops = &sil24_ops,
463 static int sil24_tag(int tag)
465 if (unlikely(ata_tag_internal(tag)))
470 static void sil24_dev_config(struct ata_device *dev)
472 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
474 if (dev->cdb_len == 16)
475 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
477 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
480 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
482 void __iomem *port = ap->ioaddr.cmd_addr;
483 struct sil24_prb __iomem *prb;
486 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
487 memcpy_fromio(fis, prb->fis, sizeof(fis));
488 ata_tf_from_fis(fis, tf);
491 static int sil24_scr_map[] = {
498 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
500 void __iomem *scr_addr = ap->ioaddr.scr_addr;
502 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
504 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
505 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
511 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
513 void __iomem *scr_addr = ap->ioaddr.scr_addr;
515 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
517 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
518 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
524 static void sil24_config_port(struct ata_port *ap)
526 void __iomem *port = ap->ioaddr.cmd_addr;
528 /* configure IRQ WoC */
529 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
530 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
532 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
534 /* zero error counters. */
535 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
536 writel(0x8000, port + PORT_CRC_ERR_THRESH);
537 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
538 writel(0x0000, port + PORT_DECODE_ERR_CNT);
539 writel(0x0000, port + PORT_CRC_ERR_CNT);
540 writel(0x0000, port + PORT_HSHK_ERR_CNT);
542 /* always use 64bit activation */
543 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
545 /* clear port multiplier enable and resume bits */
546 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
549 static void sil24_config_pmp(struct ata_port *ap, int attached)
551 void __iomem *port = ap->ioaddr.cmd_addr;
554 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
556 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
559 static void sil24_clear_pmp(struct ata_port *ap)
561 void __iomem *port = ap->ioaddr.cmd_addr;
564 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
566 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
567 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
569 writel(0, pmp_base + PORT_PMP_STATUS);
570 writel(0, pmp_base + PORT_PMP_QACTIVE);
574 static int sil24_init_port(struct ata_port *ap)
576 void __iomem *port = ap->ioaddr.cmd_addr;
577 struct sil24_port_priv *pp = ap->private_data;
580 /* clear PMP error status */
581 if (ap->nr_pmp_links)
584 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
585 ata_wait_register(port + PORT_CTRL_STAT,
586 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
587 tmp = ata_wait_register(port + PORT_CTRL_STAT,
588 PORT_CS_RDY, 0, 10, 100);
590 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
592 ap->link.eh_context.i.action |= ATA_EH_RESET;
599 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
600 const struct ata_taskfile *tf,
601 int is_cmd, u32 ctrl,
602 unsigned long timeout_msec)
604 void __iomem *port = ap->ioaddr.cmd_addr;
605 struct sil24_port_priv *pp = ap->private_data;
606 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
607 dma_addr_t paddr = pp->cmd_block_dma;
608 u32 irq_enabled, irq_mask, irq_stat;
611 prb->ctrl = cpu_to_le16(ctrl);
612 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
614 /* temporarily plug completion and error interrupts */
615 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
616 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
618 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
619 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
621 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
622 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
625 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
626 irq_stat >>= PORT_IRQ_RAW_SHIFT;
628 if (irq_stat & PORT_IRQ_COMPLETE)
631 /* force port into known state */
634 if (irq_stat & PORT_IRQ_ERROR)
640 /* restore IRQ enabled */
641 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
646 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
647 int pmp, unsigned long deadline)
649 struct ata_port *ap = link->ap;
650 unsigned long timeout_msec = 0;
651 struct ata_taskfile tf;
657 if (ata_link_offline(link)) {
658 DPRINTK("PHY reports no device\n");
659 *class = ATA_DEV_NONE;
663 /* put the port into known state */
664 if (sil24_init_port(ap)) {
665 reason = "port not ready";
670 if (time_after(deadline, jiffies))
671 timeout_msec = jiffies_to_msecs(deadline - jiffies);
673 ata_tf_init(link->device, &tf); /* doesn't really matter */
674 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
680 reason = "SRST command error";
684 sil24_read_tf(ap, 0, &tf);
685 *class = ata_dev_classify(&tf);
687 if (*class == ATA_DEV_UNKNOWN)
688 *class = ATA_DEV_NONE;
691 DPRINTK("EXIT, class=%u\n", *class);
695 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
699 static int sil24_softreset(struct ata_link *link, unsigned int *class,
700 unsigned long deadline)
702 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
705 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
706 unsigned long deadline)
708 struct ata_port *ap = link->ap;
709 void __iomem *port = ap->ioaddr.cmd_addr;
710 struct sil24_port_priv *pp = ap->private_data;
711 int did_port_rst = 0;
717 /* Sometimes, DEV_RST is not enough to recover the controller.
718 * This happens often after PM DMA CS errata.
720 if (pp->do_port_rst) {
721 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
722 "state, performing PORT_RST\n");
724 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
726 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
727 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
730 /* restore port configuration */
731 sil24_config_port(ap);
732 sil24_config_pmp(ap, ap->nr_pmp_links);
738 /* sil24 does the right thing(tm) without any protection */
742 if (ata_link_online(link))
745 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
746 tmp = ata_wait_register(port + PORT_CTRL_STAT,
747 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
750 /* SStatus oscillates between zero and valid status after
751 * DEV_RST, debounce it.
753 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
755 reason = "PHY debouncing failed";
759 if (tmp & PORT_CS_DEV_RST) {
760 if (ata_link_offline(link))
762 reason = "link not ready";
766 /* Sil24 doesn't store signature FIS after hardreset, so we
767 * can't wait for BSY to clear. Some devices take a long time
768 * to get ready and those devices will choke if we don't wait
769 * for BSY clearance here. Tell libata to perform follow-up
780 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
784 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
785 struct sil24_sge *sge)
787 struct scatterlist *sg;
788 struct sil24_sge *last_sge = NULL;
791 for_each_sg(qc->sg, sg, qc->n_elem, si) {
792 sge->addr = cpu_to_le64(sg_dma_address(sg));
793 sge->cnt = cpu_to_le32(sg_dma_len(sg));
800 last_sge->flags = cpu_to_le32(SGE_TRM);
803 static int sil24_qc_defer(struct ata_queued_cmd *qc)
805 struct ata_link *link = qc->dev->link;
806 struct ata_port *ap = link->ap;
807 u8 prot = qc->tf.protocol;
810 * There is a bug in the chip:
811 * Port LRAM Causes the PRB/SGT Data to be Corrupted
812 * If the host issues a read request for LRAM and SActive registers
813 * while active commands are available in the port, PRB/SGT data in
814 * the LRAM can become corrupted. This issue applies only when
815 * reading from, but not writing to, the LRAM.
817 * Therefore, reading LRAM when there is no particular error [and
818 * other commands may be outstanding] is prohibited.
820 * To avoid this bug there are two situations where a command must run
821 * exclusive of any other commands on the port:
823 * - ATAPI commands which check the sense data
824 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
828 int is_excl = (ata_is_atapi(prot) ||
829 (qc->flags & ATA_QCFLAG_RESULT_TF));
831 if (unlikely(ap->excl_link)) {
832 if (link == ap->excl_link) {
833 if (ap->nr_active_links)
834 return ATA_DEFER_PORT;
835 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
837 return ATA_DEFER_PORT;
838 } else if (unlikely(is_excl)) {
839 ap->excl_link = link;
840 if (ap->nr_active_links)
841 return ATA_DEFER_PORT;
842 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
845 return ata_std_qc_defer(qc);
848 static void sil24_qc_prep(struct ata_queued_cmd *qc)
850 struct ata_port *ap = qc->ap;
851 struct sil24_port_priv *pp = ap->private_data;
852 union sil24_cmd_block *cb;
853 struct sil24_prb *prb;
854 struct sil24_sge *sge;
857 cb = &pp->cmd_block[sil24_tag(qc->tag)];
859 if (!ata_is_atapi(qc->tf.protocol)) {
863 prb = &cb->atapi.prb;
865 memset(cb->atapi.cdb, 0, 32);
866 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
868 if (ata_is_data(qc->tf.protocol)) {
869 if (qc->tf.flags & ATA_TFLAG_WRITE)
870 ctrl = PRB_CTRL_PACKET_WRITE;
872 ctrl = PRB_CTRL_PACKET_READ;
876 prb->ctrl = cpu_to_le16(ctrl);
877 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
879 if (qc->flags & ATA_QCFLAG_DMAMAP)
880 sil24_fill_sg(qc, sge);
883 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
885 struct ata_port *ap = qc->ap;
886 struct sil24_port_priv *pp = ap->private_data;
887 void __iomem *port = ap->ioaddr.cmd_addr;
888 unsigned int tag = sil24_tag(qc->tag);
890 void __iomem *activate;
892 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
893 activate = port + PORT_CMD_ACTIVATE + tag * 8;
895 writel((u32)paddr, activate);
896 writel((u64)paddr >> 32, activate + 4);
901 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
903 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
907 static void sil24_pmp_attach(struct ata_port *ap)
909 sil24_config_pmp(ap, 1);
913 static void sil24_pmp_detach(struct ata_port *ap)
916 sil24_config_pmp(ap, 0);
919 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
920 unsigned long deadline)
922 return sil24_do_softreset(link, class, link->pmp, deadline);
925 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
926 unsigned long deadline)
930 rc = sil24_init_port(link->ap);
932 ata_link_printk(link, KERN_ERR,
933 "hardreset failed (port not ready)\n");
937 return sata_std_hardreset(link, class, deadline);
940 static void sil24_freeze(struct ata_port *ap)
942 void __iomem *port = ap->ioaddr.cmd_addr;
944 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
945 * PORT_IRQ_ENABLE instead.
947 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
950 static void sil24_thaw(struct ata_port *ap)
952 void __iomem *port = ap->ioaddr.cmd_addr;
956 tmp = readl(port + PORT_IRQ_STAT);
957 writel(tmp, port + PORT_IRQ_STAT);
959 /* turn IRQ back on */
960 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
963 static void sil24_error_intr(struct ata_port *ap)
965 void __iomem *port = ap->ioaddr.cmd_addr;
966 struct sil24_port_priv *pp = ap->private_data;
967 struct ata_queued_cmd *qc = NULL;
968 struct ata_link *link;
969 struct ata_eh_info *ehi;
970 int abort = 0, freeze = 0;
973 /* on error, we need to clear IRQ explicitly */
974 irq_stat = readl(port + PORT_IRQ_STAT);
975 writel(irq_stat, port + PORT_IRQ_STAT);
977 /* first, analyze and record host port events */
979 ehi = &link->eh_info;
980 ata_ehi_clear_desc(ehi);
982 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
984 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
985 ata_ehi_push_desc(ehi, "SDB notify");
986 sata_async_notification(ap);
989 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
990 ata_ehi_hotplugged(ehi);
991 ata_ehi_push_desc(ehi, "%s",
992 irq_stat & PORT_IRQ_PHYRDY_CHG ?
993 "PHY RDY changed" : "device exchanged");
997 if (irq_stat & PORT_IRQ_UNK_FIS) {
998 ehi->err_mask |= AC_ERR_HSM;
999 ehi->action |= ATA_EH_RESET;
1000 ata_ehi_push_desc(ehi, "unknown FIS");
1004 /* deal with command error */
1005 if (irq_stat & PORT_IRQ_ERROR) {
1006 struct sil24_cerr_info *ci = NULL;
1007 unsigned int err_mask = 0, action = 0;
1013 /* DMA Context Switch Failure in Port Multiplier Mode
1014 * errata. If we have active commands to 3 or more
1015 * devices, any error condition on active devices can
1016 * corrupt DMA context switching.
1018 if (ap->nr_active_links >= 3) {
1019 ehi->err_mask |= AC_ERR_OTHER;
1020 ehi->action |= ATA_EH_RESET;
1021 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1022 pp->do_port_rst = 1;
1026 /* find out the offending link and qc */
1027 if (ap->nr_pmp_links) {
1028 context = readl(port + PORT_CONTEXT);
1029 pmp = (context >> 5) & 0xf;
1031 if (pmp < ap->nr_pmp_links) {
1032 link = &ap->pmp_link[pmp];
1033 ehi = &link->eh_info;
1034 qc = ata_qc_from_tag(ap, link->active_tag);
1036 ata_ehi_clear_desc(ehi);
1037 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1040 err_mask |= AC_ERR_HSM;
1041 action |= ATA_EH_RESET;
1045 qc = ata_qc_from_tag(ap, link->active_tag);
1047 /* analyze CMD_ERR */
1048 cerr = readl(port + PORT_CMD_ERR);
1049 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1050 ci = &sil24_cerr_db[cerr];
1052 if (ci && ci->desc) {
1053 err_mask |= ci->err_mask;
1054 action |= ci->action;
1055 if (action & ATA_EH_RESET)
1057 ata_ehi_push_desc(ehi, "%s", ci->desc);
1059 err_mask |= AC_ERR_OTHER;
1060 action |= ATA_EH_RESET;
1062 ata_ehi_push_desc(ehi, "unknown command error %d",
1066 /* record error info */
1068 qc->err_mask |= err_mask;
1070 ehi->err_mask |= err_mask;
1072 ehi->action |= action;
1074 /* if PMP, resume */
1075 if (ap->nr_pmp_links)
1076 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1079 /* freeze or abort */
1081 ata_port_freeze(ap);
1084 ata_link_abort(qc->dev->link);
1090 static inline void sil24_host_intr(struct ata_port *ap)
1092 void __iomem *port = ap->ioaddr.cmd_addr;
1093 u32 slot_stat, qc_active;
1096 /* If PCIX_IRQ_WOC, there's an inherent race window between
1097 * clearing IRQ pending status and reading PORT_SLOT_STAT
1098 * which may cause spurious interrupts afterwards. This is
1099 * unavoidable and much better than losing interrupts which
1100 * happens if IRQ pending is cleared after reading
1103 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1104 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1106 slot_stat = readl(port + PORT_SLOT_STAT);
1108 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1109 sil24_error_intr(ap);
1113 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1114 rc = ata_qc_complete_multiple(ap, qc_active);
1118 struct ata_eh_info *ehi = &ap->link.eh_info;
1119 ehi->err_mask |= AC_ERR_HSM;
1120 ehi->action |= ATA_EH_RESET;
1121 ata_port_freeze(ap);
1125 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1126 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1127 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1128 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1129 slot_stat, ap->link.active_tag, ap->link.sactive);
1132 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1134 struct ata_host *host = dev_instance;
1135 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1136 unsigned handled = 0;
1140 status = readl(host_base + HOST_IRQ_STAT);
1142 if (status == 0xffffffff) {
1143 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1144 "PCI fault or device removal?\n");
1148 if (!(status & IRQ_STAT_4PORTS))
1151 spin_lock(&host->lock);
1153 for (i = 0; i < host->n_ports; i++)
1154 if (status & (1 << i)) {
1155 struct ata_port *ap = host->ports[i];
1156 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1157 sil24_host_intr(ap);
1160 printk(KERN_ERR DRV_NAME
1161 ": interrupt from disabled port %d\n", i);
1164 spin_unlock(&host->lock);
1166 return IRQ_RETVAL(handled);
1169 static void sil24_error_handler(struct ata_port *ap)
1171 struct sil24_port_priv *pp = ap->private_data;
1173 if (sil24_init_port(ap))
1174 ata_eh_freeze_port(ap);
1176 sata_pmp_error_handler(ap);
1178 pp->do_port_rst = 0;
1181 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1183 struct ata_port *ap = qc->ap;
1185 /* make DMA engine forget about the failed command */
1186 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1187 ata_eh_freeze_port(ap);
1190 static int sil24_port_start(struct ata_port *ap)
1192 struct device *dev = ap->host->dev;
1193 struct sil24_port_priv *pp;
1194 union sil24_cmd_block *cb;
1195 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1198 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1202 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1205 memset(cb, 0, cb_size);
1208 pp->cmd_block_dma = cb_dma;
1210 ap->private_data = pp;
1215 static void sil24_init_controller(struct ata_host *host)
1217 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1222 writel(0, host_base + HOST_FLASH_CMD);
1224 /* clear global reset & mask interrupts during initialization */
1225 writel(0, host_base + HOST_CTRL);
1228 for (i = 0; i < host->n_ports; i++) {
1229 struct ata_port *ap = host->ports[i];
1230 void __iomem *port = ap->ioaddr.cmd_addr;
1232 /* Initial PHY setting */
1233 writel(0x20c, port + PORT_PHY_CFG);
1235 /* Clear port RST */
1236 tmp = readl(port + PORT_CTRL_STAT);
1237 if (tmp & PORT_CS_PORT_RST) {
1238 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1239 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1241 PORT_CS_PORT_RST, 10, 100);
1242 if (tmp & PORT_CS_PORT_RST)
1243 dev_printk(KERN_ERR, host->dev,
1244 "failed to clear port RST\n");
1247 /* configure port */
1248 sil24_config_port(ap);
1251 /* Turn on interrupts */
1252 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1255 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1257 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1258 static int printed_version;
1259 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1260 const struct ata_port_info *ppi[] = { &pi, NULL };
1261 void __iomem * const *iomap;
1262 struct ata_host *host;
1266 /* cause link error if sil24_cmd_block is sized wrongly */
1267 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1268 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1270 if (!printed_version++)
1271 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1273 /* acquire resources */
1274 rc = pcim_enable_device(pdev);
1278 rc = pcim_iomap_regions(pdev,
1279 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1283 iomap = pcim_iomap_table(pdev);
1285 /* apply workaround for completion IRQ loss on PCI-X errata */
1286 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1287 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1288 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1289 dev_printk(KERN_INFO, &pdev->dev,
1290 "Applying completion IRQ loss on PCI-X "
1293 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1296 /* allocate and fill host */
1297 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1298 SIL24_FLAG2NPORTS(ppi[0]->flags));
1301 host->iomap = iomap;
1303 for (i = 0; i < host->n_ports; i++) {
1304 struct ata_port *ap = host->ports[i];
1305 size_t offset = ap->port_no * PORT_REGS_SIZE;
1306 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1308 host->ports[i]->ioaddr.cmd_addr = port;
1309 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1311 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1312 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1315 /* configure and activate the device */
1316 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1317 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1319 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1321 dev_printk(KERN_ERR, &pdev->dev,
1322 "64-bit DMA enable failed\n");
1327 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1329 dev_printk(KERN_ERR, &pdev->dev,
1330 "32-bit DMA enable failed\n");
1333 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1335 dev_printk(KERN_ERR, &pdev->dev,
1336 "32-bit consistent DMA enable failed\n");
1341 sil24_init_controller(host);
1343 pci_set_master(pdev);
1344 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1349 static int sil24_pci_device_resume(struct pci_dev *pdev)
1351 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1352 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1355 rc = ata_pci_device_do_resume(pdev);
1359 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1360 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1362 sil24_init_controller(host);
1364 ata_host_resume(host);
1369 static int sil24_port_resume(struct ata_port *ap)
1371 sil24_config_pmp(ap, ap->nr_pmp_links);
1376 static int __init sil24_init(void)
1378 return pci_register_driver(&sil24_pci_driver);
1381 static void __exit sil24_exit(void)
1383 pci_unregister_driver(&sil24_pci_driver);
1386 MODULE_AUTHOR("Tejun Heo");
1387 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1388 MODULE_LICENSE("GPL");
1389 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1391 module_init(sil24_init);
1392 module_exit(sil24_exit);