1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
5 * Author: Tang Yuantian <b29983@freescale.com>
13 #include <asm/byteorder.h>
20 #include <linux/delay.h>
22 #if CONFIG_IS_ENABLED(BLK)
25 #include <dm/device-internal.h>
30 #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
32 /* just compatible ahci_ops */
36 int (*scan)(struct udevice *dev);
39 static struct sata_info sata_info;
41 static struct pci_device_id supported[] = {
42 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
43 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
44 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
48 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
50 printf("Status FIS dump:\n");
51 printf("fis_type: %02x\n", s->fis_type);
52 printf("pm_port_i: %02x\n", s->pm_port_i);
53 printf("status: %02x\n", s->status);
54 printf("error: %02x\n", s->error);
55 printf("lba_low: %02x\n", s->lba_low);
56 printf("lba_mid: %02x\n", s->lba_mid);
57 printf("lba_high: %02x\n", s->lba_high);
58 printf("device: %02x\n", s->device);
59 printf("lba_low_exp: %02x\n", s->lba_low_exp);
60 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
61 printf("lba_high_exp: %02x\n", s->lba_high_exp);
62 printf("res1: %02x\n", s->res1);
63 printf("sector_count: %02x\n", s->sector_count);
64 printf("sector_count_exp: %02x\n", s->sector_count_exp);
67 static const char *sata_spd_string(unsigned int speed)
69 static const char * const spd_str[] = {
78 return spd_str[speed - 1];
81 static u32 ata_wait_register(void *reg, u32 mask,
82 u32 val, int timeout_msec)
87 while ((tmp & mask) == val && timeout_msec > 0) {
96 static void sil_config_port(void *port)
98 /* configure IRQ WoC */
99 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
101 /* zero error counters. */
102 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
103 writew(0x8000, port + PORT_CRC_ERR_THRESH);
104 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
105 writew(0x0000, port + PORT_DECODE_ERR_CNT);
106 writew(0x0000, port + PORT_CRC_ERR_CNT);
107 writew(0x0000, port + PORT_HSHK_ERR_CNT);
109 /* always use 64bit activation */
110 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
112 /* clear port multiplier enable and resume bits */
113 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
116 static int sil_init_port(void *port)
120 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
121 ata_wait_register(port + PORT_CTRL_STAT,
122 PORT_CS_INIT, PORT_CS_INIT, 100);
123 tmp = ata_wait_register(port + PORT_CTRL_STAT,
124 PORT_CS_RDY, 0, 100);
126 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
132 static void sil_read_fis(struct sil_sata *sata, int tag,
133 struct sata_fis_d2h *fis)
135 void *port = sata->port;
140 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
141 src = (u32 *)&prb->fis;
143 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
144 *dst++ = readl(src++);
147 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
150 void *port = sata->port;
151 u64 paddr = virt_to_bus(sata->devno, pcmd);
152 u32 irq_mask, irq_stat;
155 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
157 /* better to add momery barrior here */
158 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
159 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
161 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
162 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
166 writel(irq_mask, port + PORT_IRQ_STAT);
167 irq_stat >>= PORT_IRQ_RAW_SHIFT;
169 if (irq_stat & PORT_IRQ_COMPLETE)
172 /* force port into known state */
174 if (irq_stat & PORT_IRQ_ERROR)
183 static int sil_cmd_set_feature(struct sil_sata *sata)
185 struct sil_cmd_block cmdb, *pcmd = &cmdb;
186 struct sata_fis_d2h fis;
190 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
191 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
192 pcmd->prb.fis.pm_port_c = (1 << 7);
193 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
194 pcmd->prb.fis.features = SETFEATURES_XFER;
196 /* First check the device capablity */
197 udma_cap = (u8)(sata->udma & 0xff);
198 debug("udma_cap %02x\n", udma_cap);
200 if (udma_cap == ATA_UDMA6)
201 pcmd->prb.fis.sector_count = XFER_UDMA_6;
202 if (udma_cap == ATA_UDMA5)
203 pcmd->prb.fis.sector_count = XFER_UDMA_5;
204 if (udma_cap == ATA_UDMA4)
205 pcmd->prb.fis.sector_count = XFER_UDMA_4;
206 if (udma_cap == ATA_UDMA3)
207 pcmd->prb.fis.sector_count = XFER_UDMA_3;
209 ret = sil_exec_cmd(sata, pcmd, 0);
211 sil_read_fis(sata, 0, &fis);
212 printf("Err: exe cmd(0x%x).\n",
213 readl(sata->port + PORT_SERROR));
214 sil_sata_dump_fis(&fis);
221 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
223 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
225 if (ata_id_has_flush(id))
227 if (ata_id_has_flush_ext(id))
231 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
234 /* Check if support LBA48 */
235 if (ata_id_has_lba48(id)) {
237 debug("Device supports LBA48\n");
239 debug("Device supports LBA28\n");
243 sil_sata_init_wcache(sata, id);
244 sil_cmd_set_feature(sata);
247 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
249 struct sil_cmd_block cmdb, *pcmd = &cmdb;
250 struct sata_fis_d2h fis;
253 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
254 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
255 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
256 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
257 pcmd->prb.fis.pm_port_c = (1 << 7);
258 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
259 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
260 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
261 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
263 ret = sil_exec_cmd(sata, pcmd, 0);
265 sil_read_fis(sata, 0, &fis);
266 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
267 sil_sata_dump_fis(&fis);
270 ata_swap_buf_le16(id, ATA_ID_WORDS);
275 static int sil_cmd_soft_reset(struct sil_sata *sata)
277 struct sil_cmd_block cmdb, *pcmd = &cmdb;
278 struct sata_fis_d2h fis;
279 void *port = sata->port;
282 /* put the port into known state */
283 if (sil_init_port(port)) {
284 printf("SRST: port %d not ready\n", sata->id);
288 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
290 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
291 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
292 pcmd->prb.fis.pm_port_c = 0xf;
294 ret = sil_exec_cmd(sata, &cmdb, 0);
296 sil_read_fis(sata, 0, &fis);
297 printf("SRST cmd error.\n");
298 sil_sata_dump_fis(&fis);
305 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
306 u8 *buffer, int is_write)
308 struct sil_cmd_block cmdb, *pcmd = &cmdb;
309 struct sata_fis_d2h fis;
314 memset(pcmd, 0, sizeof(struct sil_cmd_block));
315 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
316 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
317 pcmd->prb.fis.pm_port_c = (1 << 7);
319 pcmd->prb.fis.command = ATA_CMD_WRITE;
320 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
322 pcmd->prb.fis.command = ATA_CMD_READ;
323 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
326 pcmd->prb.fis.device = ATA_LBA;
327 pcmd->prb.fis.device |= (block >> 24) & 0xf;
328 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
329 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
330 pcmd->prb.fis.lba_low = block & 0xff;
331 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
333 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
334 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
335 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
337 ret = sil_exec_cmd(sata, pcmd, 0);
339 sil_read_fis(sata, 0, &fis);
340 printf("Err: rw cmd(0x%08x).\n",
341 readl(sata->port + PORT_SERROR));
342 sil_sata_dump_fis(&fis);
349 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
350 ulong blkcnt, u8 *buffer, int is_write)
352 struct sil_cmd_block cmdb, *pcmd = &cmdb;
353 struct sata_fis_d2h fis;
358 memset(pcmd, 0, sizeof(struct sil_cmd_block));
359 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
360 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
361 pcmd->prb.fis.pm_port_c = (1 << 7);
363 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
364 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
366 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
367 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
370 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
371 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
372 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
373 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
374 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
375 pcmd->prb.fis.lba_low = block & 0xff;
376 pcmd->prb.fis.device = ATA_LBA;
377 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
378 pcmd->prb.fis.sector_count = blkcnt & 0xff;
380 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
381 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
382 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
384 ret = sil_exec_cmd(sata, pcmd, 0);
386 sil_read_fis(sata, 0, &fis);
387 printf("Err: rw ext cmd(0x%08x).\n",
388 readl(sata->port + PORT_SERROR));
389 sil_sata_dump_fis(&fis);
396 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
397 lbaint_t blkcnt, const void *buffer,
400 ulong start, blks, max_blks;
407 max_blks = ATA_MAX_SECTORS;
409 if (blks > max_blks) {
410 sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
413 addr += ATA_SECT_SIZE * max_blks;
415 sil_sata_rw_cmd(sata, start, blks, addr, is_write);
418 addr += ATA_SECT_SIZE * blks;
425 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
426 lbaint_t blkcnt, const void *buffer,
429 ulong start, blks, max_blks;
436 max_blks = ATA_MAX_SECTORS_LBA48;
438 if (blks > max_blks) {
439 sil_sata_rw_cmd_ext(sata, start, max_blks,
443 addr += ATA_SECT_SIZE * max_blks;
445 sil_sata_rw_cmd_ext(sata, start, blks,
449 addr += ATA_SECT_SIZE * blks;
456 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
458 struct sil_cmd_block cmdb, *pcmd = &cmdb;
460 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
461 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
462 pcmd->prb.fis.pm_port_c = (1 << 7);
463 pcmd->prb.fis.command = ATA_CMD_FLUSH;
465 sil_exec_cmd(sata, pcmd, 0);
468 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
470 struct sil_cmd_block cmdb, *pcmd = &cmdb;
472 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
473 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
474 pcmd->prb.fis.pm_port_c = (1 << 7);
475 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
477 sil_exec_cmd(sata, pcmd, 0);
481 * SATA interface between low level driver and command layer
483 #if !CONFIG_IS_ENABLED(BLK)
484 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
486 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
488 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
491 struct sil_sata_priv *priv = dev_get_plat(dev);
492 int port_number = priv->port_num;
493 struct sil_sata *sata = priv->sil_sata_desc[port_number];
498 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
500 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
506 * SATA interface between low level driver and command layer
508 #if !CONFIG_IS_ENABLED(BLK)
509 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
511 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
513 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
516 struct sil_sata_priv *priv = dev_get_plat(dev);
517 int port_number = priv->port_num;
518 struct sil_sata *sata = priv->sil_sata_desc[port_number];
523 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
524 if (sata->wcache && sata->flush_ext)
525 sil_sata_cmd_flush_cache_ext(sata);
527 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
528 if (sata->wcache && sata->flush)
529 sil_sata_cmd_flush_cache(sata);
535 #if !CONFIG_IS_ENABLED(BLK)
536 static int sil_init_sata(int dev)
539 static int sil_init_sata(struct udevice *uc_dev, int dev)
541 struct sil_sata_priv *priv = dev_get_plat(uc_dev);
543 struct sil_sata *sata;
548 printf("SATA#%d:\n", dev);
550 port = (void *)sata_info.iobase[1] +
551 PORT_REGS_SIZE * (dev - sata_info.portbase);
553 /* Initial PHY setting */
554 writel(0x20c, port + PORT_PHY_CFG);
557 tmp = readl(port + PORT_CTRL_STAT);
558 if (tmp & PORT_CS_PORT_RST) {
559 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
560 tmp = ata_wait_register(port + PORT_CTRL_STAT,
561 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
562 if (tmp & PORT_CS_PORT_RST)
563 printf("Err: Failed to clear port RST\n");
566 /* Check if device is present */
567 for (cnt = 0; cnt < 100; cnt++) {
568 tmp = readl(port + PORT_SSTATUS);
569 if ((tmp & 0xF) == 0x3)
574 tmp = readl(port + PORT_SSTATUS);
575 if ((tmp & 0xf) != 0x3) {
576 printf(" (No RDY)\n");
580 /* Wait for port ready */
581 tmp = ata_wait_register(port + PORT_CTRL_STAT,
582 PORT_CS_RDY, PORT_CS_RDY, 100);
583 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
584 printf("%d port not ready.\n", dev);
589 sil_config_port(port);
592 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
593 readl(port + PORT_CTRL_STAT);
594 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
595 PORT_CS_DEV_RST, 100);
596 if (tmp & PORT_CS_DEV_RST) {
597 printf("%d port reset failed.\n", dev);
601 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
603 printf("%d no memory.\n", dev);
606 memset((void *)sata, 0, sizeof(struct sil_sata));
608 /* Save the private struct to block device struct */
609 #if !CONFIG_IS_ENABLED(BLK)
610 sata_dev_desc[dev].priv = (void *)sata;
611 sata->devno = sata_info.devno;
613 priv->sil_sata_desc[dev] = sata;
614 priv->port_num = dev;
615 sata->devno = uc_dev->parent;
619 sprintf(sata->name, "SATA#%d", dev);
620 sil_cmd_soft_reset(sata);
621 tmp = readl(port + PORT_SSTATUS);
622 tmp = (tmp >> 4) & 0xf;
623 printf(" (%s)\n", sata_spd_string(tmp));
628 #if !CONFIG_IS_ENABLED(BLK)
630 * SATA interface between low level driver and command layer
632 int init_sata(int dev)
634 static int init_done, idx;
638 if (init_done == 1 && dev < sata_info.maxport)
643 /* Find PCI device(s) */
644 devno = pci_find_devices(supported, idx++);
648 pci_read_config_word(devno, PCI_DEVICE_ID, &word);
650 /* get the port count */
653 sata_info.portbase = 0;
654 sata_info.maxport = sata_info.portbase + word;
655 sata_info.devno = devno;
657 /* Read out all BARs */
658 sata_info.iobase[0] = (ulong)pci_map_bar(devno,
659 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
660 sata_info.iobase[1] = (ulong)pci_map_bar(devno,
661 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
663 /* mask out the unused bits */
664 sata_info.iobase[0] &= 0xffffff80;
665 sata_info.iobase[1] &= 0xfffffc00;
667 /* Enable Bus Mastering and memory region */
668 pci_write_config_word(devno, PCI_COMMAND,
669 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
671 /* Check if mem accesses and Bus Mastering are enabled. */
672 pci_read_config_word(devno, PCI_COMMAND, &word);
673 if (!(word & PCI_COMMAND_MEMORY) ||
674 (!(word & PCI_COMMAND_MASTER))) {
675 printf("Error: Can not enable MEM access or Bus Mastering.\n");
676 debug("PCI command: %04x\n", word);
681 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
682 /* clear global reset & mask interrupts during initialization */
683 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
686 return sil_init_sata(dev);
689 int reset_sata(int dev)
695 * SATA interface between low level driver and command layer
697 int scan_sata(int dev)
699 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
701 static int scan_sata(struct udevice *blk_dev, int dev)
703 struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
704 struct sil_sata_priv *priv = dev_get_plat(blk_dev);
705 struct sil_sata *sata = priv->sil_sata_desc[dev];
707 unsigned char serial[ATA_ID_SERNO_LEN + 1];
708 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
709 unsigned char product[ATA_ID_PROD_LEN + 1];
712 id = (u16 *)malloc(ATA_ID_WORDS * 2);
714 printf("Id malloc failed\n");
717 sil_cmd_identify_device(sata, id);
719 sil_sata_set_feature_by_id(sata, id);
722 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
724 /* Firmware version */
725 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
728 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
730 #if !CONFIG_IS_ENABLED(BLK)
731 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
732 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
733 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
735 sata_dev_desc[dev].lba = ata_id_n_sectors(id);
737 sata_dev_desc[dev].lba48 = sata->lba48;
740 memcpy(desc->product, serial, sizeof(serial));
741 memcpy(desc->revision, firmware, sizeof(firmware));
742 memcpy(desc->vendor, product, sizeof(product));
743 desc->lba = ata_id_n_sectors(id);
745 desc->lba48 = sata->lba48;
757 #if CONFIG_IS_ENABLED(BLK)
758 static const struct blk_ops sata_sil_blk_ops = {
763 U_BOOT_DRIVER(sata_sil_driver) = {
764 .name = "sata_sil_blk",
766 .ops = &sata_sil_blk_ops,
767 .plat_auto = sizeof(struct sil_sata_priv),
770 static int sil_unbind_device(struct udevice *dev)
774 ret = device_remove(dev, DM_REMOVE_NORMAL);
778 ret = device_unbind(dev);
785 static int sil_pci_probe(struct udevice *dev)
797 /* Get PCI device number */
798 devno = dm_pci_get_bdf(dev);
802 dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
804 /* get the port count */
807 sata_info.portbase = 0;
808 sata_info.maxport = sata_info.portbase + word;
809 sata_info.devno = devno;
811 /* Read out all BARs */
812 sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
813 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
814 sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
815 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
817 /* mask out the unused bits */
818 sata_info.iobase[0] &= 0xffffff80;
819 sata_info.iobase[1] &= 0xfffffc00;
821 /* Enable Bus Mastering and memory region */
822 dm_pci_write_config16(dev, PCI_COMMAND,
823 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
825 /* Check if mem accesses and Bus Mastering are enabled. */
826 dm_pci_read_config16(dev, PCI_COMMAND, &word);
827 if (!(word & PCI_COMMAND_MEMORY) ||
828 (!(word & PCI_COMMAND_MASTER))) {
829 printf("Error: Can not enable MEM access or Bus Mastering.\n");
830 debug("PCI command: %04x\n", word);
835 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
836 /* clear global reset & mask interrupts during initialization */
837 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
839 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
840 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
841 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
842 IF_TYPE_SATA, -1, 512, 0, &blk);
844 debug("Can't create device\n");
848 ret = sil_init_sata(blk, i);
850 ret = sil_unbind_device(blk);
858 ret = scan_sata(blk, i);
860 ret = sil_unbind_device(blk);
869 if (failed_number == sata_info.maxport)
875 static int sil_pci_remove(struct udevice *dev)
878 struct sil_sata *sata;
879 struct sil_sata_priv *priv;
881 priv = dev_get_priv(dev);
883 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
884 sata = priv->sil_sata_desc[i];
892 static int sata_sil_scan(struct udevice *dev)
894 /* Nothing to do here */
899 struct sil_ops sata_sil_ops = {
900 .scan = sata_sil_scan,
903 static const struct udevice_id sil_pci_ids[] = {
904 { .compatible = "sil-pci-sample" },
908 U_BOOT_DRIVER(sil_ahci_pci) = {
909 .name = "sil_ahci_pci",
911 .of_match = sil_pci_ids,
912 .ops = &sata_sil_ops,
913 .probe = sil_pci_probe,
914 .remove = sil_pci_remove,
915 .priv_auto = sizeof(struct sil_sata_priv),
918 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);