1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Excito Elektronik i Skåne AB, 2010.
4 * Author: Tor Krill <tor@excito.com>
6 * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
10 * This driver supports the SATA controller of some Mavell SoC's.
11 * Here a (most likely incomplete) list of the supported SoC's:
16 * This driver implementation is an alternative to the already available
17 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
18 * But this driver only supports PIO mode and as this new driver also
19 * supports transfer via DMA, its much faster.
21 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
22 * by this driver. As they have an AHCI compatible SATA controller
28 * Better error recovery
29 * No support for using PRDs (Thus max 64KB transfers)
31 * No port multiplier support
37 #include <dm/device-internal.h>
43 #include <linux/errno.h>
45 #include <linux/mbus.h>
47 #if defined(CONFIG_KIRKWOOD)
48 #include <asm/arch/kirkwood.h>
49 #define SATAHC_BASE KW_SATA_BASE
51 #include <asm/arch/soc.h>
52 #define SATAHC_BASE MVEBU_AXP_SATA_BASE
55 #define SATA0_BASE (SATAHC_BASE + 0x2000)
56 #define SATA1_BASE (SATAHC_BASE + 0x4000)
59 #define EDMA_CFG 0x000
60 #define EDMA_CFG_NCQ (1 << 5)
61 #define EDMA_CFG_EQUE (1 << 9)
62 #define EDMA_TIMER 0x004
63 #define EDMA_IECR 0x008
64 #define EDMA_IEMR 0x00c
65 #define EDMA_RQBA_HI 0x010
66 #define EDMA_RQIPR 0x014
67 #define EDMA_RQIPR_IPMASK (0x1f << 5)
68 #define EDMA_RQIPR_IPSHIFT 5
69 #define EDMA_RQOPR 0x018
70 #define EDMA_RQOPR_OPMASK (0x1f << 5)
71 #define EDMA_RQOPR_OPSHIFT 5
72 #define EDMA_RSBA_HI 0x01c
73 #define EDMA_RSIPR 0x020
74 #define EDMA_RSIPR_IPMASK (0x1f << 3)
75 #define EDMA_RSIPR_IPSHIFT 3
76 #define EDMA_RSOPR 0x024
77 #define EDMA_RSOPR_OPMASK (0x1f << 3)
78 #define EDMA_RSOPR_OPSHIFT 3
79 #define EDMA_CMD 0x028
80 #define EDMA_CMD_ENEDMA (0x01 << 0)
81 #define EDMA_CMD_DISEDMA (0x01 << 1)
82 #define EDMA_CMD_ATARST (0x01 << 2)
83 #define EDMA_CMD_FREEZE (0x01 << 4)
84 #define EDMA_TEST_CTL 0x02c
85 #define EDMA_STATUS 0x030
86 #define EDMA_IORTO 0x034
87 #define EDMA_CDTR 0x040
88 #define EDMA_HLTCND 0x060
89 #define EDMA_NTSR 0x094
91 /* Basic DMA registers */
92 #define BDMA_CMD 0x224
93 #define BDMA_STATUS 0x228
94 #define BDMA_DTLB 0x22c
95 #define BDMA_DTHB 0x230
96 #define BDMA_DRL 0x234
97 #define BDMA_DRH 0x238
99 /* SATA Interface registers */
100 #define SIR_ICFG 0x050
101 #define SIR_CFG_GEN2EN (0x1 << 7)
102 #define SIR_PLL_CFG 0x054
103 #define SIR_SSTATUS 0x300
104 #define SSTATUS_DET_MASK (0x0f << 0)
105 #define SIR_SERROR 0x304
106 #define SIR_SCONTROL 0x308
107 #define SIR_SCONTROL_DETEN (0x01 << 0)
108 #define SIR_LTMODE 0x30c
109 #define SIR_LTMODE_NELBE (0x01 << 7)
110 #define SIR_PHYMODE3 0x310
111 #define SIR_PHYMODE4 0x314
112 #define SIR_PHYMODE1 0x32c
113 #define SIR_PHYMODE2 0x330
114 #define SIR_BIST_CTRL 0x334
115 #define SIR_BIST_DW1 0x338
116 #define SIR_BIST_DW2 0x33c
117 #define SIR_SERR_IRQ_MASK 0x340
118 #define SIR_SATA_IFCTRL 0x344
119 #define SIR_SATA_TESTCTRL 0x348
120 #define SIR_SATA_IFSTATUS 0x34c
121 #define SIR_VEND_UNIQ 0x35c
122 #define SIR_FIS_CFG 0x360
123 #define SIR_FIS_IRQ_CAUSE 0x364
124 #define SIR_FIS_IRQ_MASK 0x368
125 #define SIR_FIS_DWORD0 0x370
126 #define SIR_FIS_DWORD1 0x374
127 #define SIR_FIS_DWORD2 0x378
128 #define SIR_FIS_DWORD3 0x37c
129 #define SIR_FIS_DWORD4 0x380
130 #define SIR_FIS_DWORD5 0x384
131 #define SIR_FIS_DWORD6 0x388
132 #define SIR_PHYM9_GEN2 0x398
133 #define SIR_PHYM9_GEN1 0x39c
134 #define SIR_PHY_CFG 0x3a0
135 #define SIR_PHYCTL 0x3a4
136 #define SIR_PHYM10 0x3a8
137 #define SIR_PHYM12 0x3b0
139 /* Shadow registers */
140 #define PIO_DATA 0x100
141 #define PIO_ERR_FEATURES 0x104
142 #define PIO_SECTOR_COUNT 0x108
143 #define PIO_LBA_LOW 0x10c
144 #define PIO_LBA_MID 0x110
145 #define PIO_LBA_HI 0x114
146 #define PIO_DEVICE 0x118
147 #define PIO_CMD_STATUS 0x11c
148 #define PIO_STATUS_ERR (0x01 << 0)
149 #define PIO_STATUS_DRQ (0x01 << 3)
150 #define PIO_STATUS_DF (0x01 << 5)
151 #define PIO_STATUS_DRDY (0x01 << 6)
152 #define PIO_STATUS_BSY (0x01 << 7)
153 #define PIO_CTRL_ALTSTAT 0x120
155 /* SATAHC arbiter registers */
156 #define SATAHC_CFG 0x000
157 #define SATAHC_RQOP 0x004
158 #define SATAHC_RQIP 0x008
159 #define SATAHC_ICT 0x00c
160 #define SATAHC_ITT 0x010
161 #define SATAHC_ICR 0x014
162 #define SATAHC_ICR_PORT0 (0x01 << 0)
163 #define SATAHC_ICR_PORT1 (0x01 << 1)
164 #define SATAHC_MIC 0x020
165 #define SATAHC_MIM 0x024
166 #define SATAHC_LED_CFG 0x02c
168 #define REQUEST_QUEUE_SIZE 32
169 #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
172 u32 dtb_low; /* DW0 */
173 u32 dtb_high; /* DW1 */
174 u32 control_flags; /* DW2 */
175 u32 drb_count; /* DW3 */
176 u32 ata_cmd_feat; /* DW4 */
177 u32 ata_addr; /* DW5 */
178 u32 ata_addr_exp; /* DW6 */
179 u32 ata_sect_count; /* DW7 */
182 #define CRQB_ALIGN 0x400
184 #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
185 #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
186 #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
187 #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
188 #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
189 #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
190 #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
191 #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
193 #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
194 #define CRQB_CMDFEAT_CMDSHIFT 16
195 #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
196 #define CRQB_CMDFEAT_FEATSHIFT 24
198 #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
199 #define CRQB_ADDR_LBA_LOWSHIFT 0
200 #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
201 #define CRQB_ADDR_LBA_MIDSHIFT 8
202 #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
203 #define CRQB_ADDR_LBA_HIGHSHIFT 16
204 #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
205 #define CRQB_ADDR_DEVICE_SHIFT 24
207 #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
208 #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
209 #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
210 #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
211 #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
212 #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
213 #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
214 #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
216 #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
217 #define CRQB_SECTCOUNT_COUNT_SHIFT 0
218 #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
219 #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
221 #define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
222 #define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
231 #define EPRD_PHYADDR_MASK 0xfffffffe
232 #define EPRD_BYTECOUNT_MASK 0x0000ffff
233 #define EPRD_EOT (0x01 << 31)
241 #define CRPB_ALIGN 0x100
247 * Since we don't use PRDs yet max transfer size
250 #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
252 /* Keep track if hw is initialized or not */
266 struct crqb *request;
269 struct crpb *response;
272 static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
276 start = get_timer(0);
278 if ((in_le32(addr) & mask) == val)
280 } while (get_timer(start) < timeout_msec);
285 /* Cut from sata_mv in linux kernel */
286 static int mv_stop_edma_engine(struct udevice *dev, int port)
288 struct mv_priv *priv = dev_get_platdata(dev);
291 /* Disable eDMA. The disable bit auto clears. */
292 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
294 /* Wait for the chip to confirm eDMA is off. */
295 for (i = 10000; i > 0; i--) {
296 u32 reg = in_le32(priv->regbase + EDMA_CMD);
297 if (!(reg & EDMA_CMD_ENEDMA)) {
298 debug("EDMA stop on port %d succesful\n", port);
303 debug("EDMA stop on port %d failed\n", port);
307 static int mv_start_edma_engine(struct udevice *dev, int port)
309 struct mv_priv *priv = dev_get_platdata(dev);
312 /* Check preconditions */
313 tmp = in_le32(priv->regbase + SIR_SSTATUS);
314 if ((tmp & SSTATUS_DET_MASK) != 0x03) {
315 printf("Device error on port: %d\n", port);
319 tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
320 if (tmp & (ATA_BUSY | ATA_DRQ)) {
321 printf("Device not ready on port: %d\n", port);
325 /* Clear interrupt cause */
326 out_le32(priv->regbase + EDMA_IECR, 0x0);
328 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
329 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
330 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
332 /* Configure edma operation */
333 tmp = in_le32(priv->regbase + EDMA_CFG);
334 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
335 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
336 out_le32(priv->regbase + EDMA_CFG, tmp);
338 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
340 /* Configure fis, set all to no-wait for now */
341 out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
343 /* Setup request queue */
344 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
345 out_le32(priv->regbase + EDMA_RQIPR, priv->request);
346 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
348 /* Setup response queue */
349 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
350 out_le32(priv->regbase + EDMA_RSOPR, priv->response);
351 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
354 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
359 static int mv_reset_channel(struct udevice *dev, int port)
361 struct mv_priv *priv = dev_get_platdata(dev);
363 /* Make sure edma is stopped */
364 mv_stop_edma_engine(dev, port);
366 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
367 udelay(25); /* allow reset propagation */
368 out_le32(priv->regbase + EDMA_CMD, 0);
374 static void mv_reset_port(struct udevice *dev, int port)
376 struct mv_priv *priv = dev_get_platdata(dev);
378 mv_reset_channel(dev, port);
380 out_le32(priv->regbase + EDMA_CMD, 0x0);
381 out_le32(priv->regbase + EDMA_CFG, 0x101f);
382 out_le32(priv->regbase + EDMA_IECR, 0x0);
383 out_le32(priv->regbase + EDMA_IEMR, 0x0);
384 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
385 out_le32(priv->regbase + EDMA_RQIPR, 0x0);
386 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
387 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
388 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
389 out_le32(priv->regbase + EDMA_RSOPR, 0x0);
390 out_le32(priv->regbase + EDMA_IORTO, 0xfa);
393 static void mv_reset_one_hc(void)
395 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
396 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
397 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
400 static int probe_port(struct udevice *dev, int port)
402 struct mv_priv *priv = dev_get_platdata(dev);
403 int tries, tries2, set15 = 0;
406 debug("Probe port: %d\n", port);
408 for (tries = 0; tries < 2; tries++) {
410 out_le32(priv->regbase + SIR_SERROR, 0x0);
412 /* trigger com-init */
413 tmp = in_le32(priv->regbase + SIR_SCONTROL);
414 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
415 out_le32(priv->regbase + SIR_SCONTROL, tmp);
419 tmp = in_le32(priv->regbase + SIR_SCONTROL);
422 tmp = (tmp & 0x0f0) | 0x300;
423 out_le32(priv->regbase + SIR_SCONTROL, tmp);
425 tmp = in_le32(priv->regbase + SIR_SCONTROL);
426 } while ((tmp & 0xf0f) != 0x300 && tries2--);
430 for (tries2 = 0; tries2 < 200; tries2++) {
431 tmp = in_le32(priv->regbase + SIR_SSTATUS);
432 if ((tmp & SSTATUS_DET_MASK) == 0x03) {
433 debug("Found device on port\n");
439 if ((tmp & SSTATUS_DET_MASK) == 0) {
440 debug("No device attached on port %d\n", port);
446 debug("Try 1.5Gb link\n");
448 out_le32(priv->regbase + SIR_SCONTROL, 0x304);
450 tmp = in_le32(priv->regbase + SIR_ICFG);
451 tmp &= ~SIR_CFG_GEN2EN;
452 out_le32(priv->regbase + SIR_ICFG, tmp);
454 mv_reset_channel(dev, port);
458 debug("Failed to probe port\n");
462 /* Get request queue in pointer */
463 static int get_reqip(struct udevice *dev, int port)
465 struct mv_priv *priv = dev_get_platdata(dev);
468 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
469 tmp = tmp >> EDMA_RQIPR_IPSHIFT;
474 static void set_reqip(struct udevice *dev, int port, int reqin)
476 struct mv_priv *priv = dev_get_platdata(dev);
479 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
480 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
481 out_le32(priv->regbase + EDMA_RQIPR, tmp);
484 /* Get next available slot, ignoring possible overwrite */
485 static int get_next_reqip(struct udevice *dev, int port)
487 int slot = get_reqip(dev, port);
488 slot = (slot + 1) % REQUEST_QUEUE_SIZE;
492 /* Get response queue in pointer */
493 static int get_rspip(struct udevice *dev, int port)
495 struct mv_priv *priv = dev_get_platdata(dev);
498 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
499 tmp = tmp >> EDMA_RSIPR_IPSHIFT;
504 /* Get response queue out pointer */
505 static int get_rspop(struct udevice *dev, int port)
507 struct mv_priv *priv = dev_get_platdata(dev);
510 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
511 tmp = tmp >> EDMA_RSOPR_OPSHIFT;
515 /* Get next response queue pointer */
516 static int get_next_rspop(struct udevice *dev, int port)
518 return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
521 /* Set response queue pointer */
522 static void set_rspop(struct udevice *dev, int port, int reqin)
524 struct mv_priv *priv = dev_get_platdata(dev);
527 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
528 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
530 out_le32(priv->regbase + EDMA_RSOPR, tmp);
533 static int wait_dma_completion(struct udevice *dev, int port, int index,
538 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
539 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
542 printf("Failed to wait for completion on port %d\n", port);
547 static void process_responses(struct udevice *dev, int port)
550 struct mv_priv *priv = dev_get_platdata(dev);
553 u32 outind = get_rspop(dev, port);
556 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
558 tmp &= ~(BIT(0) | BIT(8));
560 tmp &= ~(BIT(1) | BIT(9));
562 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
564 while (get_rspip(dev, port) != outind) {
566 debug("Response index %d flags %08x on port %d\n", outind,
567 priv->response[outind].flags, port);
569 outind = get_next_rspop(dev, port);
570 set_rspop(dev, port, outind);
574 static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
575 struct sata_fis_h2d *cfis,
576 u8 *buffer, u32 len, u32 iswrite)
578 struct mv_priv *priv = dev_get_platdata(dev);
583 if (len >= 64 * 1024) {
584 printf("We only support <64K transfers for now\n");
588 /* Initialize request */
589 slot = get_reqip(dev, port);
590 memset(&priv->request[slot], 0, sizeof(struct crqb));
591 req = &priv->request[slot];
593 req->dtb_low = (u32)buffer;
596 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
597 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
598 req->control_flags |=
599 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
600 & CRQB_CNTRLFLAGS_PMPORTMASK);
602 req->drb_count = len;
604 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
605 CRQB_CMDFEAT_CMDMASK;
606 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
607 CRQB_CMDFEAT_FEATMASK;
609 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
610 CRQB_ADDR_LBA_LOWMASK;
611 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
612 CRQB_ADDR_LBA_MIDMASK;
613 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
614 CRQB_ADDR_LBA_HIGHMASK;
615 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
616 CRQB_ADDR_DEVICE_MASK;
618 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
619 CRQB_ADDR_LBA_LOW_EXP_MASK;
621 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
622 CRQB_ADDR_LBA_MID_EXP_MASK;
624 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
625 CRQB_ADDR_LBA_HIGH_EXP_MASK;
627 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
628 CRQB_ADDR_FEATURE_EXP_MASK;
630 req->ata_sect_count =
631 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
632 CRQB_SECTCOUNT_COUNT_MASK;
633 req->ata_sect_count |=
634 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
635 CRQB_SECTCOUNT_COUNT_EXP_MASK;
638 start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
639 flush_dcache_range(start,
640 start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
642 /* Trigger operation */
643 slot = get_next_reqip(dev, port);
644 set_reqip(dev, port, slot);
646 /* Wait for completion */
647 if (wait_dma_completion(dev, port, slot, 10000)) {
648 printf("ATA operation timed out\n");
652 process_responses(dev, port);
654 /* Invalidate data on read */
656 start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
657 invalidate_dcache_range(start,
658 start + ALIGN(len, ARCH_DMA_MINALIGN));
664 static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
666 u8 *buffer, int is_write)
668 struct sata_fis_h2d cfis;
674 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
676 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
677 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
679 cfis.lba_high_exp = (block >> 40) & 0xff;
680 cfis.lba_mid_exp = (block >> 32) & 0xff;
681 cfis.lba_low_exp = (block >> 24) & 0xff;
682 cfis.lba_high = (block >> 16) & 0xff;
683 cfis.lba_mid = (block >> 8) & 0xff;
684 cfis.lba_low = block & 0xff;
685 cfis.device = ATA_LBA;
686 cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
687 cfis.sector_count = blkcnt & 0xff;
689 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
690 ATA_SECT_SIZE * blkcnt, is_write);
692 return res >= 0 ? blkcnt : res;
695 static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
696 u32 blkcnt, u8 *buffer, int is_write)
698 struct sata_fis_h2d cfis;
704 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
706 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
707 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
708 cfis.device = ATA_LBA;
710 cfis.device |= (block >> 24) & 0xf;
711 cfis.lba_high = (block >> 16) & 0xff;
712 cfis.lba_mid = (block >> 8) & 0xff;
713 cfis.lba_low = block & 0xff;
714 cfis.sector_count = (u8)(blkcnt & 0xff);
716 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
717 ATA_SECT_SIZE * blkcnt, is_write);
719 return res >= 0 ? blkcnt : res;
722 static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
723 lbaint_t blkcnt, void *buffer, int is_write)
725 struct blk_desc *desc = dev_get_uclass_platdata(dev);
726 lbaint_t start, blks;
730 debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
736 max_blks = MV_ATA_MAX_SECTORS;
738 if (blks > max_blks) {
740 mv_sata_rw_cmd_ext(dev, port, start, max_blks,
743 mv_sata_rw_cmd(dev, port, start, max_blks,
748 addr += ATA_SECT_SIZE * max_blks;
751 mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
754 mv_sata_rw_cmd(dev, port, start, blks, addr,
759 addr += ATA_SECT_SIZE * blks;
766 static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
767 struct sata_fis_h2d *cfis, u8 *buffer,
768 u32 len, u32 iswrite)
770 struct mv_priv *priv = dev_get_platdata(dev);
774 debug("%s\n", __func__);
776 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
777 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
778 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
779 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
780 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
781 out_le32(priv->regbase + PIO_DEVICE, cfis->device);
782 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
784 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
785 ATA_BUSY, 0x0, 10000)) {
786 debug("Failed to wait for completion\n");
792 for (i = 0; i < len / 2; i++) {
794 out_le16(priv->regbase + PIO_DATA, *tp++);
796 *tp++ = in_le16(priv->regbase + PIO_DATA);
803 static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
805 struct sata_fis_h2d h2d;
807 memset(&h2d, 0, sizeof(struct sata_fis_h2d));
809 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
810 h2d.command = ATA_CMD_ID_ATA;
812 /* Give device time to get operational */
815 return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
816 ATA_ID_WORDS * 2, READ_CMD);
819 static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
821 struct mv_priv *priv = dev_get_platdata(dev);
823 priv->pio = id[ATA_ID_PIO_MODES];
824 priv->mwdma = id[ATA_ID_MWDMA_MODES];
825 priv->udma = id[ATA_ID_UDMA_MODES];
826 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
830 static void mv_sata_set_features(struct udevice *dev, int port)
832 struct mv_priv *priv = dev_get_platdata(dev);
833 struct sata_fis_h2d cfis;
836 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
838 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
839 cfis.command = ATA_CMD_SET_FEATURES;
840 cfis.features = SETFEATURES_XFER;
842 /* First check the device capablity */
843 udma_cap = (u8) (priv->udma & 0xff);
845 if (udma_cap == ATA_UDMA6)
846 cfis.sector_count = XFER_UDMA_6;
847 if (udma_cap == ATA_UDMA5)
848 cfis.sector_count = XFER_UDMA_5;
849 if (udma_cap == ATA_UDMA4)
850 cfis.sector_count = XFER_UDMA_4;
851 if (udma_cap == ATA_UDMA3)
852 cfis.sector_count = XFER_UDMA_3;
854 mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
858 * Initialize SATA memory windows
860 static void mvsata_ide_conf_mbus_windows(void)
862 const struct mbus_dram_target_info *dram;
865 dram = mvebu_mbus_dram_info();
867 /* Disable windows, Set Size/Base to 0 */
868 for (i = 0; i < 4; i++) {
869 writel(0, MVSATA_WIN_CONTROL(i));
870 writel(0, MVSATA_WIN_BASE(i));
873 for (i = 0; i < dram->num_cs; i++) {
874 const struct mbus_dram_window *cs = dram->cs + i;
875 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
876 (dram->mbus_dram_target_id << 4) | 1,
877 MVSATA_WIN_CONTROL(i));
878 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
882 static int sata_mv_init_sata(struct udevice *dev, int port)
884 struct mv_priv *priv = dev_get_platdata(dev);
886 debug("Initialize sata dev: %d\n", port);
888 if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
889 printf("Invalid sata device %d\n", port);
893 /* Allocate and align request buffer */
894 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
896 if (!priv->crqb_alloc) {
897 printf("Unable to allocate memory for request queue\n");
900 memset(priv->crqb_alloc, 0,
901 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
902 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
905 /* Allocate and align response buffer */
906 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
908 if (!priv->crpb_alloc) {
909 printf("Unable to allocate memory for response queue\n");
912 memset(priv->crpb_alloc, 0,
913 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
914 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
917 sprintf(priv->name, "SATA%d", port);
919 priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
922 debug("Initialize sata hw\n");
925 mvsata_ide_conf_mbus_windows();
928 mv_reset_port(dev, port);
930 if (probe_port(dev, port)) {
939 static int sata_mv_scan_sata(struct udevice *dev, int port)
941 struct blk_desc *desc = dev_get_uclass_platdata(dev);
942 struct mv_priv *priv = dev_get_platdata(dev);
943 unsigned char serial[ATA_ID_SERNO_LEN + 1];
944 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
945 unsigned char product[ATA_ID_PROD_LEN + 1];
952 id = (u16 *)malloc(ATA_ID_WORDS * 2);
954 printf("Failed to malloc id data\n");
958 mv_sata_identify(dev, port, id);
959 ata_swap_buf_le16(id, ATA_ID_WORDS);
965 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
966 memcpy(desc->product, serial, sizeof(serial));
968 /* Firmware version */
969 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
970 memcpy(desc->revision, firmware, sizeof(firmware));
973 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
974 memcpy(desc->vendor, product, sizeof(product));
977 n_sectors = ata_id_n_sectors(id);
978 desc->lba = n_sectors;
980 /* Check if support LBA48 */
981 if (ata_id_has_lba48(id)) {
983 debug("Device support LBA48\n");
986 /* Get the NCQ queue depth from device */
987 priv->queue_depth = ata_id_queue_depth(id);
989 /* Get the xfer mode from device */
990 mv_sata_xfer_mode(dev, port, id);
992 /* Set the xfer mode to highest speed */
993 mv_sata_set_features(dev, port);
996 mv_start_edma_engine(dev, port);
1001 static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
1002 lbaint_t blkcnt, void *buffer)
1004 struct mv_priv *priv = dev_get_platdata(blk);
1006 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1010 static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
1011 lbaint_t blkcnt, const void *buffer)
1013 struct mv_priv *priv = dev_get_platdata(blk);
1015 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1016 (void *)buffer, WRITE_CMD);
1019 static const struct blk_ops sata_mv_blk_ops = {
1020 .read = sata_mv_read,
1021 .write = sata_mv_write,
1024 U_BOOT_DRIVER(sata_mv_driver) = {
1025 .name = "sata_mv_blk",
1027 .ops = &sata_mv_blk_ops,
1028 .platdata_auto_alloc_size = sizeof(struct mv_priv),
1031 static int sata_mv_probe(struct udevice *dev)
1033 const void *blob = gd->fdt_blob;
1034 int node = dev_of_offset(dev);
1035 struct mv_priv *priv;
1036 struct udevice *blk;
1041 /* Get number of ports of this SATA controller */
1042 nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
1043 CONFIG_SYS_SATA_MAX_DEVICE);
1045 for (i = 0; i < nr_ports; i++) {
1046 ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
1047 IF_TYPE_SATA, -1, 512, 0, &blk);
1049 debug("Can't create device\n");
1053 priv = dev_get_platdata(blk);
1056 /* Init SATA port */
1057 ret = sata_mv_init_sata(blk, i);
1059 debug("%s: Failed to init bus\n", __func__);
1063 /* Scan SATA port */
1064 ret = sata_mv_scan_sata(blk, i);
1066 debug("%s: Failed to scan bus\n", __func__);
1074 static int sata_mv_scan(struct udevice *dev)
1076 /* Nothing to do here */
1081 static const struct udevice_id sata_mv_ids[] = {
1082 { .compatible = "marvell,armada-370-sata" },
1086 struct ahci_ops sata_mv_ahci_ops = {
1087 .scan = sata_mv_scan,
1090 U_BOOT_DRIVER(sata_mv_ahci) = {
1091 .name = "sata_mv_ahci",
1093 .of_match = sata_mv_ids,
1094 .ops = &sata_mv_ahci_ops,
1095 .probe = sata_mv_probe,