1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 - 2016 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
9 #include <generic-phy.h>
14 #include <dm/device_compat.h>
15 #include <linux/ioport.h>
17 /* Vendor Specific Register Offsets */
18 #define AHCI_VEND_PCFG 0xA4
19 #define AHCI_VEND_PPCFG 0xA8
20 #define AHCI_VEND_PP2C 0xAC
21 #define AHCI_VEND_PP3C 0xB0
22 #define AHCI_VEND_PP4C 0xB4
23 #define AHCI_VEND_PP5C 0xB8
24 #define AHCI_VEND_AXICC 0xBc
25 #define AHCI_VEND_PAXIC 0xC0
26 #define AHCI_VEND_PTC 0xC8
28 /* Vendor Specific Register bit definitions */
29 #define PAXIC_ADBW_BW64 0x1
30 #define PAXIC_MAWIDD (1 << 8)
31 #define PAXIC_MARIDD (1 << 16)
32 #define PAXIC_OTL (0x4 << 20)
34 #define PCFG_TPSS_VAL (0x32 << 16)
35 #define PCFG_TPRS_VAL (0x2 << 12)
36 #define PCFG_PAD_VAL 0x2
38 #define PPCFG_TTA 0x1FFFE
39 #define PPCFG_PSSO_EN (1 << 28)
40 #define PPCFG_PSS_EN (1 << 29)
41 #define PPCFG_ESDF_EN (1 << 31)
43 #define PP2C_CIBGMN 0x0F
44 #define PP2C_CIBGMX (0x25 << 8)
45 #define PP2C_CIBGN (0x18 << 16)
46 #define PP2C_CINMP (0x29 << 24)
48 #define PP3C_CWBGMN 0x04
49 #define PP3C_CWBGMX (0x0B << 8)
50 #define PP3C_CWBGN (0x08 << 16)
51 #define PP3C_CWNMP (0x0F << 24)
54 #define PP4C_BNM (0x08 << 8)
55 #define PP4C_SFD (0x4a << 16)
56 #define PP4C_PTST (0x06 << 24)
58 #define PP5C_RIT 0x60216
59 #define PP5C_RCT (0x7f0 << 20)
61 #define PTC_RX_WM_VAL 0x40
62 #define PTC_RSVD (1 << 27)
64 #define PORT0_BASE 0x100
65 #define PORT1_BASE 0x180
67 /* Port Control Register Bit Definitions */
68 #define PORT_SCTL_SPD_GEN3 (0x3 << 4)
69 #define PORT_SCTL_SPD_GEN2 (0x2 << 4)
70 #define PORT_SCTL_SPD_GEN1 (0x1 << 4)
71 #define PORT_SCTL_IPM (0x3 << 8)
73 #define PORT_BASE 0x100
74 #define PORT_OFFSET 0x80
76 #define DRV_NAME "ahci-ceva"
77 #define CEVA_FLAG_BROKEN_GEN2 1
79 /* flag bit definition */
80 #define FLAG_COHERENT 1
82 /* register config value */
83 #define CEVA_PHY1_CFG 0xa003fffe
84 #define CEVA_PHY2_CFG 0x28184d1f
85 #define CEVA_PHY3_CFG 0x0e081509
86 #define CEVA_TRANS_CFG 0x08000029
87 #define CEVA_AXICC_CFG 0x3fffffff
90 #define LS1021_AHCI_VEND_AXICC 0xC0
91 #define LS1021_CEVA_PHY2_CFG 0x28183414
92 #define LS1021_CEVA_PHY3_CFG 0x0e080e06
93 #define LS1021_CEVA_PHY4_CFG 0x064a080b
94 #define LS1021_CEVA_PHY5_CFG 0x2aa86470
97 #define ECC_DIS_VAL_CH1 0x00020000
98 #define ECC_DIS_VAL_CH2 0x80000000
99 #define ECC_DIS_VAL_CH3 0x40000000
112 struct ceva_sata_priv {
119 static int ceva_init_sata(struct ceva_sata_priv *priv)
121 ulong ecc_addr = priv->ecc_base;
122 ulong base = priv->base;
127 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
128 writel(tmp, base + AHCI_VEND_PAXIC);
129 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
130 writel(tmp, base + AHCI_VEND_PCFG);
131 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
132 writel(tmp, base + AHCI_VEND_PPCFG);
133 tmp = PTC_RX_WM_VAL | PTC_RSVD;
134 writel(tmp, base + AHCI_VEND_PTC);
140 writel(ECC_DIS_VAL_CH1, ecc_addr);
141 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
142 writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
143 writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
144 writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
145 writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
146 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
154 writel(ECC_DIS_VAL_CH2, ecc_addr);
157 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
158 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
165 writel(ECC_DIS_VAL_CH3, ecc_addr);
166 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
167 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
171 if (priv->flag & FLAG_COHERENT)
172 writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
177 static int sata_ceva_bind(struct udevice *dev)
179 struct udevice *scsi_dev;
181 return ahci_bind_scsi(dev, &scsi_dev);
184 static int sata_ceva_probe(struct udevice *dev)
186 struct ceva_sata_priv *priv = dev_get_priv(dev);
189 struct reset_ctl_bulk resets;
191 ret = generic_phy_get_by_index(dev, 0, &phy);
193 dev_dbg(dev, "Perform PHY initialization\n");
194 ret = generic_phy_init(&phy);
197 } else if (ret != -ENOENT) {
198 dev_dbg(dev, "could not get phy (err %d)\n", ret);
202 /* reset is optional */
203 ret = reset_get_bulk(dev, &resets);
204 if (ret && ret != -ENOTSUPP && ret != -ENOENT) {
205 dev_dbg(dev, "Getting reset fails (err %d)\n", ret);
209 /* Just trigger reset when reset is specified */
211 dev_dbg(dev, "Perform IP reset\n");
212 ret = reset_deassert_bulk(&resets);
214 dev_dbg(dev, "Reset fails (err %d)\n", ret);
215 reset_release_bulk(&resets);
221 dev_dbg(dev, "Perform PHY power on\n");
222 ret = generic_phy_power_on(&phy);
224 dev_dbg(dev, "PHY power on failed (err %d)\n", ret);
229 ceva_init_sata(priv);
231 return ahci_probe_scsi(dev, priv->base);
234 static const struct udevice_id sata_ceva_ids[] = {
235 { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
236 { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
237 { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
238 { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
239 { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
240 { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
241 { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
242 { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
246 static int sata_ceva_of_to_plat(struct udevice *dev)
248 struct ceva_sata_priv *priv = dev_get_priv(dev);
249 struct resource res_regs;
252 if (dev_read_bool(dev, "dma-coherent"))
253 priv->flag |= FLAG_COHERENT;
255 priv->base = dev_read_addr(dev);
256 if (priv->base == FDT_ADDR_T_NONE)
259 ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
263 priv->ecc_base = res_regs.start;
265 priv->soc = dev_get_driver_data(dev);
267 debug("ccsr-sata-base %lx\t ecc-base %lx\n",
274 U_BOOT_DRIVER(ceva_host_blk) = {
277 .of_match = sata_ceva_ids,
278 .bind = sata_ceva_bind,
280 .priv_auto = sizeof(struct ceva_sata_priv),
281 .probe = sata_ceva_probe,
282 .of_to_plat = sata_ceva_of_to_plat,