1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libata-sff.c - helper library for PCI IDE BMDMA
5 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2006 Jeff Garzik
8 * libata documentation is available via 'make {ps|pdf}docs',
9 * as Documentation/driver-api/libata.rst
11 * Hardware documentation available from http://www.t13.org/ and
12 * http://www.sata-io.org/
15 #include <linux/kernel.h>
16 #include <linux/gfp.h>
17 #include <linux/pci.h>
18 #include <linux/module.h>
19 #include <linux/libata.h>
20 #include <linux/highmem.h>
21 #include <trace/events/libata.h>
24 static struct workqueue_struct *ata_sff_wq;
26 const struct ata_port_operations ata_sff_port_ops = {
27 .inherits = &ata_base_port_ops,
29 .qc_prep = ata_noop_qc_prep,
30 .qc_issue = ata_sff_qc_issue,
31 .qc_fill_rtf = ata_sff_qc_fill_rtf,
33 .freeze = ata_sff_freeze,
35 .prereset = ata_sff_prereset,
36 .softreset = ata_sff_softreset,
37 .hardreset = sata_sff_hardreset,
38 .postreset = ata_sff_postreset,
39 .error_handler = ata_sff_error_handler,
41 .sff_dev_select = ata_sff_dev_select,
42 .sff_check_status = ata_sff_check_status,
43 .sff_tf_load = ata_sff_tf_load,
44 .sff_tf_read = ata_sff_tf_read,
45 .sff_exec_command = ata_sff_exec_command,
46 .sff_data_xfer = ata_sff_data_xfer,
47 .sff_drain_fifo = ata_sff_drain_fifo,
49 .lost_interrupt = ata_sff_lost_interrupt,
51 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
54 * ata_sff_check_status - Read device status reg & clear interrupt
55 * @ap: port where the device is
57 * Reads ATA taskfile status register for currently-selected device
58 * and return its value. This also clears pending interrupts
62 * Inherited from caller.
64 u8 ata_sff_check_status(struct ata_port *ap)
66 return ioread8(ap->ioaddr.status_addr);
68 EXPORT_SYMBOL_GPL(ata_sff_check_status);
71 * ata_sff_altstatus - Read device alternate status reg
72 * @ap: port where the device is
74 * Reads ATA taskfile alternate status register for
75 * currently-selected device and return its value.
77 * Note: may NOT be used as the check_altstatus() entry in
78 * ata_port_operations.
81 * Inherited from caller.
83 static u8 ata_sff_altstatus(struct ata_port *ap)
85 if (ap->ops->sff_check_altstatus)
86 return ap->ops->sff_check_altstatus(ap);
88 return ioread8(ap->ioaddr.altstatus_addr);
92 * ata_sff_irq_status - Check if the device is busy
93 * @ap: port where the device is
95 * Determine if the port is currently busy. Uses altstatus
96 * if available in order to avoid clearing shared IRQ status
97 * when finding an IRQ source. Non ctl capable devices don't
98 * share interrupt lines fortunately for us.
101 * Inherited from caller.
103 static u8 ata_sff_irq_status(struct ata_port *ap)
107 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
108 status = ata_sff_altstatus(ap);
109 /* Not us: We are busy */
110 if (status & ATA_BUSY)
113 /* Clear INTRQ latch */
114 status = ap->ops->sff_check_status(ap);
119 * ata_sff_sync - Flush writes
120 * @ap: Port to wait for.
123 * If we have an mmio device with no ctl and no altstatus
124 * method this will fail. No such devices are known to exist.
127 * Inherited from caller.
130 static void ata_sff_sync(struct ata_port *ap)
132 if (ap->ops->sff_check_altstatus)
133 ap->ops->sff_check_altstatus(ap);
134 else if (ap->ioaddr.altstatus_addr)
135 ioread8(ap->ioaddr.altstatus_addr);
139 * ata_sff_pause - Flush writes and wait 400nS
140 * @ap: Port to pause for.
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
147 * Inherited from caller.
150 void ata_sff_pause(struct ata_port *ap)
155 EXPORT_SYMBOL_GPL(ata_sff_pause);
158 * ata_sff_dma_pause - Pause before commencing DMA
159 * @ap: Port to pause for.
161 * Perform I/O fencing and ensure sufficient cycle delays occur
162 * for the HDMA1:0 transition
165 void ata_sff_dma_pause(struct ata_port *ap)
167 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
168 /* An altstatus read will cause the needed delay without
169 messing up the IRQ status */
170 ata_sff_altstatus(ap);
173 /* There are no DMA controllers without ctl. BUG here to ensure
174 we never violate the HDMA1:0 transition timing and risk
178 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
181 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
182 * @ap: port containing status register to be polled
183 * @tmout_pat: impatience timeout in msecs
184 * @tmout: overall timeout in msecs
186 * Sleep until ATA Status register bit BSY clears,
187 * or a timeout occurs.
190 * Kernel thread context (may sleep).
193 * 0 on success, -errno otherwise.
195 int ata_sff_busy_sleep(struct ata_port *ap,
196 unsigned long tmout_pat, unsigned long tmout)
198 unsigned long timer_start, timeout;
201 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
202 timer_start = jiffies;
203 timeout = ata_deadline(timer_start, tmout_pat);
204 while (status != 0xff && (status & ATA_BUSY) &&
205 time_before(jiffies, timeout)) {
207 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
210 if (status != 0xff && (status & ATA_BUSY))
212 "port is slow to respond, please be patient (Status 0x%x)\n",
215 timeout = ata_deadline(timer_start, tmout);
216 while (status != 0xff && (status & ATA_BUSY) &&
217 time_before(jiffies, timeout)) {
219 status = ap->ops->sff_check_status(ap);
225 if (status & ATA_BUSY) {
227 "port failed to respond (%lu secs, Status 0x%x)\n",
228 DIV_ROUND_UP(tmout, 1000), status);
234 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
236 static int ata_sff_check_ready(struct ata_link *link)
238 u8 status = link->ap->ops->sff_check_status(link->ap);
240 return ata_check_ready(status);
244 * ata_sff_wait_ready - sleep until BSY clears, or timeout
245 * @link: SFF link to wait ready status for
246 * @deadline: deadline jiffies for the operation
248 * Sleep until ATA Status register bit BSY clears, or timeout
252 * Kernel thread context (may sleep).
255 * 0 on success, -errno otherwise.
257 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
259 return ata_wait_ready(link, deadline, ata_sff_check_ready);
261 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
264 * ata_sff_set_devctl - Write device control reg
265 * @ap: port where the device is
266 * @ctl: value to write
268 * Writes ATA taskfile device control register.
270 * Note: may NOT be used as the sff_set_devctl() entry in
271 * ata_port_operations.
274 * Inherited from caller.
276 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
278 if (ap->ops->sff_set_devctl)
279 ap->ops->sff_set_devctl(ap, ctl);
281 iowrite8(ctl, ap->ioaddr.ctl_addr);
285 * ata_sff_dev_select - Select device 0/1 on ATA bus
286 * @ap: ATA channel to manipulate
287 * @device: ATA device (numbered from zero) to select
289 * Use the method defined in the ATA specification to
290 * make either device 0, or device 1, active on the
291 * ATA channel. Works with both PIO and MMIO.
293 * May be used as the dev_select() entry in ata_port_operations.
298 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
303 tmp = ATA_DEVICE_OBS;
305 tmp = ATA_DEVICE_OBS | ATA_DEV1;
307 iowrite8(tmp, ap->ioaddr.device_addr);
308 ata_sff_pause(ap); /* needed; also flushes, for mmio */
310 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
313 * ata_dev_select - Select device 0/1 on ATA bus
314 * @ap: ATA channel to manipulate
315 * @device: ATA device (numbered from zero) to select
316 * @wait: non-zero to wait for Status register BSY bit to clear
317 * @can_sleep: non-zero if context allows sleeping
319 * Use the method defined in the ATA specification to
320 * make either device 0, or device 1, active on the
323 * This is a high-level version of ata_sff_dev_select(), which
324 * additionally provides the services of inserting the proper
325 * pauses and status polling, where needed.
330 static void ata_dev_select(struct ata_port *ap, unsigned int device,
331 unsigned int wait, unsigned int can_sleep)
336 ap->ops->sff_dev_select(ap, device);
339 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
346 * ata_sff_irq_on - Enable interrupts on a port.
347 * @ap: Port on which interrupts are enabled.
349 * Enable interrupts on a legacy IDE device using MMIO or PIO,
350 * wait for idle, clear any pending interrupts.
352 * Note: may NOT be used as the sff_irq_on() entry in
353 * ata_port_operations.
356 * Inherited from caller.
358 void ata_sff_irq_on(struct ata_port *ap)
360 struct ata_ioports *ioaddr = &ap->ioaddr;
362 if (ap->ops->sff_irq_on) {
363 ap->ops->sff_irq_on(ap);
367 ap->ctl &= ~ATA_NIEN;
368 ap->last_ctl = ap->ctl;
370 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
371 ata_sff_set_devctl(ap, ap->ctl);
374 if (ap->ops->sff_irq_clear)
375 ap->ops->sff_irq_clear(ap);
377 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
380 * ata_sff_tf_load - send taskfile registers to host controller
381 * @ap: Port to which output is sent
382 * @tf: ATA taskfile register set
384 * Outputs ATA taskfile to standard ATA host controller.
387 * Inherited from caller.
389 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
391 struct ata_ioports *ioaddr = &ap->ioaddr;
392 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
394 if (tf->ctl != ap->last_ctl) {
395 if (ioaddr->ctl_addr)
396 iowrite8(tf->ctl, ioaddr->ctl_addr);
397 ap->last_ctl = tf->ctl;
401 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
402 WARN_ON_ONCE(!ioaddr->ctl_addr);
403 iowrite8(tf->hob_feature, ioaddr->feature_addr);
404 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
405 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
406 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
407 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
411 iowrite8(tf->feature, ioaddr->feature_addr);
412 iowrite8(tf->nsect, ioaddr->nsect_addr);
413 iowrite8(tf->lbal, ioaddr->lbal_addr);
414 iowrite8(tf->lbam, ioaddr->lbam_addr);
415 iowrite8(tf->lbah, ioaddr->lbah_addr);
418 if (tf->flags & ATA_TFLAG_DEVICE)
419 iowrite8(tf->device, ioaddr->device_addr);
423 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
426 * ata_sff_tf_read - input device's ATA taskfile shadow registers
427 * @ap: Port from which input is read
428 * @tf: ATA taskfile register set for storing input
430 * Reads ATA taskfile registers for currently-selected device
431 * into @tf. Assumes the device has a fully SFF compliant task file
432 * layout and behaviour. If you device does not (eg has a different
433 * status method) then you will need to provide a replacement tf_read
436 * Inherited from caller.
438 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
440 struct ata_ioports *ioaddr = &ap->ioaddr;
442 tf->command = ata_sff_check_status(ap);
443 tf->feature = ioread8(ioaddr->error_addr);
444 tf->nsect = ioread8(ioaddr->nsect_addr);
445 tf->lbal = ioread8(ioaddr->lbal_addr);
446 tf->lbam = ioread8(ioaddr->lbam_addr);
447 tf->lbah = ioread8(ioaddr->lbah_addr);
448 tf->device = ioread8(ioaddr->device_addr);
450 if (tf->flags & ATA_TFLAG_LBA48) {
451 if (likely(ioaddr->ctl_addr)) {
452 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
453 tf->hob_feature = ioread8(ioaddr->error_addr);
454 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
455 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
456 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
457 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
458 iowrite8(tf->ctl, ioaddr->ctl_addr);
459 ap->last_ctl = tf->ctl;
464 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
467 * ata_sff_exec_command - issue ATA command to host controller
468 * @ap: port to which command is being issued
469 * @tf: ATA taskfile register set
471 * Issues ATA command, with proper synchronization with interrupt
472 * handler / other threads.
475 * spin_lock_irqsave(host lock)
477 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
479 iowrite8(tf->command, ap->ioaddr.command_addr);
482 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
485 * ata_tf_to_host - issue ATA taskfile to host controller
486 * @ap: port to which command is being issued
487 * @tf: ATA taskfile register set
488 * @tag: tag of the associated command
490 * Issues ATA taskfile register set to ATA host controller,
491 * with proper synchronization with interrupt handler and
495 * spin_lock_irqsave(host lock)
497 static inline void ata_tf_to_host(struct ata_port *ap,
498 const struct ata_taskfile *tf,
501 trace_ata_tf_load(ap, tf);
502 ap->ops->sff_tf_load(ap, tf);
503 trace_ata_exec_command(ap, tf, tag);
504 ap->ops->sff_exec_command(ap, tf);
508 * ata_sff_data_xfer - Transfer data by PIO
509 * @qc: queued command
511 * @buflen: buffer length
514 * Transfer data from/to the device data register by PIO.
517 * Inherited from caller.
522 unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
523 unsigned int buflen, int rw)
525 struct ata_port *ap = qc->dev->link->ap;
526 void __iomem *data_addr = ap->ioaddr.data_addr;
527 unsigned int words = buflen >> 1;
529 /* Transfer multiple of 2 bytes */
531 ioread16_rep(data_addr, buf, words);
533 iowrite16_rep(data_addr, buf, words);
535 /* Transfer trailing byte, if any. */
536 if (unlikely(buflen & 0x01)) {
537 unsigned char pad[2] = { };
539 /* Point buf to the tail of buffer */
543 * Use io*16_rep() accessors here as well to avoid pointlessly
544 * swapping bytes to and from on the big endian machines...
547 ioread16_rep(data_addr, pad, 1);
551 iowrite16_rep(data_addr, pad, 1);
558 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
561 * ata_sff_data_xfer32 - Transfer data by PIO
562 * @qc: queued command
564 * @buflen: buffer length
567 * Transfer data from/to the device data register by PIO using 32bit
571 * Inherited from caller.
577 unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
578 unsigned int buflen, int rw)
580 struct ata_device *dev = qc->dev;
581 struct ata_port *ap = dev->link->ap;
582 void __iomem *data_addr = ap->ioaddr.data_addr;
583 unsigned int words = buflen >> 2;
584 int slop = buflen & 3;
586 if (!(ap->pflags & ATA_PFLAG_PIO32))
587 return ata_sff_data_xfer(qc, buf, buflen, rw);
589 /* Transfer multiple of 4 bytes */
591 ioread32_rep(data_addr, buf, words);
593 iowrite32_rep(data_addr, buf, words);
595 /* Transfer trailing bytes, if any */
596 if (unlikely(slop)) {
597 unsigned char pad[4] = { };
599 /* Point buf to the tail of buffer */
600 buf += buflen - slop;
603 * Use io*_rep() accessors here as well to avoid pointlessly
604 * swapping bytes to and from on the big endian machines...
608 ioread16_rep(data_addr, pad, 1);
610 ioread32_rep(data_addr, pad, 1);
611 memcpy(buf, pad, slop);
613 memcpy(pad, buf, slop);
615 iowrite16_rep(data_addr, pad, 1);
617 iowrite32_rep(data_addr, pad, 1);
620 return (buflen + 1) & ~1;
622 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
624 static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
625 unsigned int offset, size_t xfer_size)
627 bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
630 buf = kmap_atomic(page);
631 qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
634 if (!do_write && !PageSlab(page))
635 flush_dcache_page(page);
639 * ata_pio_sector - Transfer a sector of data.
640 * @qc: Command on going
642 * Transfer qc->sect_size bytes of data from/to the ATA device.
645 * Inherited from caller.
647 static void ata_pio_sector(struct ata_queued_cmd *qc)
649 struct ata_port *ap = qc->ap;
654 qc->curbytes = qc->nbytes;
657 if (qc->curbytes == qc->nbytes - qc->sect_size)
658 ap->hsm_task_state = HSM_ST_LAST;
660 page = sg_page(qc->cursg);
661 offset = qc->cursg->offset + qc->cursg_ofs;
663 /* get the current page and offset */
664 page = nth_page(page, (offset >> PAGE_SHIFT));
667 trace_ata_sff_pio_transfer_data(qc, offset, qc->sect_size);
670 * Split the transfer when it splits a page boundary. Note that the
671 * split still has to be dword aligned like all ATA data transfers.
673 WARN_ON_ONCE(offset % 4);
674 if (offset + qc->sect_size > PAGE_SIZE) {
675 unsigned int split_len = PAGE_SIZE - offset;
677 ata_pio_xfer(qc, page, offset, split_len);
678 ata_pio_xfer(qc, nth_page(page, 1), 0,
679 qc->sect_size - split_len);
681 ata_pio_xfer(qc, page, offset, qc->sect_size);
684 qc->curbytes += qc->sect_size;
685 qc->cursg_ofs += qc->sect_size;
687 if (qc->cursg_ofs == qc->cursg->length) {
688 qc->cursg = sg_next(qc->cursg);
690 ap->hsm_task_state = HSM_ST_LAST;
696 * ata_pio_sectors - Transfer one or many sectors.
697 * @qc: Command on going
699 * Transfer one or many sectors of data from/to the
700 * ATA device for the DRQ request.
703 * Inherited from caller.
705 static void ata_pio_sectors(struct ata_queued_cmd *qc)
707 if (is_multi_taskfile(&qc->tf)) {
708 /* READ/WRITE MULTIPLE */
711 WARN_ON_ONCE(qc->dev->multi_count == 0);
713 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
714 qc->dev->multi_count);
720 ata_sff_sync(qc->ap); /* flush */
724 * atapi_send_cdb - Write CDB bytes to hardware
725 * @ap: Port to which ATAPI device is attached.
726 * @qc: Taskfile currently active
728 * When device has indicated its readiness to accept
729 * a CDB, this function is called. Send the CDB.
734 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
737 trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len);
738 WARN_ON_ONCE(qc->dev->cdb_len < 12);
740 ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
742 /* FIXME: If the CDB is for DMA do we need to do the transition delay
743 or is bmdma_start guaranteed to do it ? */
744 switch (qc->tf.protocol) {
746 ap->hsm_task_state = HSM_ST;
748 case ATAPI_PROT_NODATA:
749 ap->hsm_task_state = HSM_ST_LAST;
751 #ifdef CONFIG_ATA_BMDMA
753 ap->hsm_task_state = HSM_ST_LAST;
755 trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
756 ap->ops->bmdma_start(qc);
758 #endif /* CONFIG_ATA_BMDMA */
765 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
766 * @qc: Command on going
767 * @bytes: number of bytes
769 * Transfer Transfer data from/to the ATAPI device.
772 * Inherited from caller.
775 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
777 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
778 struct ata_port *ap = qc->ap;
779 struct ata_device *dev = qc->dev;
780 struct ata_eh_info *ehi = &dev->link->eh_info;
781 struct scatterlist *sg;
784 unsigned int offset, count, consumed;
789 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
790 "buf=%u cur=%u bytes=%u",
791 qc->nbytes, qc->curbytes, bytes);
796 offset = sg->offset + qc->cursg_ofs;
798 /* get the current page and offset */
799 page = nth_page(page, (offset >> PAGE_SHIFT));
802 /* don't overrun current sg */
803 count = min(sg->length - qc->cursg_ofs, bytes);
805 /* don't cross page boundaries */
806 count = min(count, (unsigned int)PAGE_SIZE - offset);
808 trace_atapi_pio_transfer_data(qc, offset, count);
810 /* do the actual data transfer */
811 buf = kmap_atomic(page);
812 consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
815 bytes -= min(bytes, consumed);
816 qc->curbytes += count;
817 qc->cursg_ofs += count;
819 if (qc->cursg_ofs == sg->length) {
820 qc->cursg = sg_next(qc->cursg);
825 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
826 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
827 * check correctly as it doesn't know if it is the last request being
828 * made. Somebody should implement a proper sanity check.
836 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
837 * @qc: Command on going
839 * Transfer Transfer data from/to the ATAPI device.
842 * Inherited from caller.
844 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
846 struct ata_port *ap = qc->ap;
847 struct ata_device *dev = qc->dev;
848 struct ata_eh_info *ehi = &dev->link->eh_info;
849 unsigned int ireason, bc_lo, bc_hi, bytes;
850 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
852 /* Abuse qc->result_tf for temp storage of intermediate TF
853 * here to save some kernel stack usage.
854 * For normal completion, qc->result_tf is not relevant. For
855 * error, qc->result_tf is later overwritten by ata_qc_complete().
856 * So, the correctness of qc->result_tf is not affected.
858 ap->ops->sff_tf_read(ap, &qc->result_tf);
859 ireason = qc->result_tf.nsect;
860 bc_lo = qc->result_tf.lbam;
861 bc_hi = qc->result_tf.lbah;
862 bytes = (bc_hi << 8) | bc_lo;
864 /* shall be cleared to zero, indicating xfer of data */
865 if (unlikely(ireason & ATAPI_COD))
868 /* make sure transfer direction matches expected */
869 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
870 if (unlikely(do_write != i_write))
873 if (unlikely(!bytes))
876 if (unlikely(__atapi_pio_bytes(qc, bytes)))
878 ata_sff_sync(ap); /* flush */
883 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
886 qc->err_mask |= AC_ERR_HSM;
887 ap->hsm_task_state = HSM_ST_ERR;
891 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
892 * @ap: the target ata_port
896 * 1 if ok in workqueue, 0 otherwise.
898 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
899 struct ata_queued_cmd *qc)
901 if (qc->tf.flags & ATA_TFLAG_POLLING)
904 if (ap->hsm_task_state == HSM_ST_FIRST) {
905 if (qc->tf.protocol == ATA_PROT_PIO &&
906 (qc->tf.flags & ATA_TFLAG_WRITE))
909 if (ata_is_atapi(qc->tf.protocol) &&
910 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
918 * ata_hsm_qc_complete - finish a qc running on standard HSM
919 * @qc: Command to complete
920 * @in_wq: 1 if called from workqueue, 0 otherwise
922 * Finish @qc which is running on standard HSM.
925 * If @in_wq is zero, spin_lock_irqsave(host lock).
926 * Otherwise, none on entry and grabs host lock.
928 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
930 struct ata_port *ap = qc->ap;
932 if (ap->ops->error_handler) {
934 /* EH might have kicked in while host lock is
937 qc = ata_qc_from_tag(ap, qc->tag);
939 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
946 if (likely(!(qc->err_mask & AC_ERR_HSM)))
961 * ata_sff_hsm_move - move the HSM to the next state.
962 * @ap: the target ata_port
964 * @status: current device status
965 * @in_wq: 1 if called from workqueue, 0 otherwise
968 * 1 when poll next status needed, 0 otherwise.
970 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
971 u8 status, int in_wq)
973 struct ata_link *link = qc->dev->link;
974 struct ata_eh_info *ehi = &link->eh_info;
977 lockdep_assert_held(ap->lock);
979 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
981 /* Make sure ata_sff_qc_issue() does not throw things
982 * like DMA polling into the workqueue. Notice that
983 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
985 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
988 trace_ata_sff_hsm_state(qc, status);
990 switch (ap->hsm_task_state) {
992 /* Send first data block or PACKET CDB */
994 /* If polling, we will stay in the work queue after
995 * sending the data. Otherwise, interrupt handler
996 * takes over after sending the data.
998 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1000 /* check device status */
1001 if (unlikely((status & ATA_DRQ) == 0)) {
1002 /* handle BSY=0, DRQ=0 as error */
1003 if (likely(status & (ATA_ERR | ATA_DF)))
1004 /* device stops HSM for abort/error */
1005 qc->err_mask |= AC_ERR_DEV;
1007 /* HSM violation. Let EH handle this */
1008 ata_ehi_push_desc(ehi,
1009 "ST_FIRST: !(DRQ|ERR|DF)");
1010 qc->err_mask |= AC_ERR_HSM;
1013 ap->hsm_task_state = HSM_ST_ERR;
1017 /* Device should not ask for data transfer (DRQ=1)
1018 * when it finds something wrong.
1019 * We ignore DRQ here and stop the HSM by
1020 * changing hsm_task_state to HSM_ST_ERR and
1021 * let the EH abort the command or reset the device.
1023 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1024 /* Some ATAPI tape drives forget to clear the ERR bit
1025 * when doing the next command (mostly request sense).
1026 * We ignore ERR here to workaround and proceed sending
1029 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1030 ata_ehi_push_desc(ehi, "ST_FIRST: "
1031 "DRQ=1 with device error, "
1032 "dev_stat 0x%X", status);
1033 qc->err_mask |= AC_ERR_HSM;
1034 ap->hsm_task_state = HSM_ST_ERR;
1039 if (qc->tf.protocol == ATA_PROT_PIO) {
1040 /* PIO data out protocol.
1041 * send first data block.
1044 /* ata_pio_sectors() might change the state
1045 * to HSM_ST_LAST. so, the state is changed here
1046 * before ata_pio_sectors().
1048 ap->hsm_task_state = HSM_ST;
1049 ata_pio_sectors(qc);
1052 atapi_send_cdb(ap, qc);
1054 /* if polling, ata_sff_pio_task() handles the rest.
1055 * otherwise, interrupt handler takes over from here.
1060 /* complete command or read/write the data register */
1061 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1062 /* ATAPI PIO protocol */
1063 if ((status & ATA_DRQ) == 0) {
1064 /* No more data to transfer or device error.
1065 * Device error will be tagged in HSM_ST_LAST.
1067 ap->hsm_task_state = HSM_ST_LAST;
1071 /* Device should not ask for data transfer (DRQ=1)
1072 * when it finds something wrong.
1073 * We ignore DRQ here and stop the HSM by
1074 * changing hsm_task_state to HSM_ST_ERR and
1075 * let the EH abort the command or reset the device.
1077 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1078 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1079 "DRQ=1 with device error, "
1080 "dev_stat 0x%X", status);
1081 qc->err_mask |= AC_ERR_HSM;
1082 ap->hsm_task_state = HSM_ST_ERR;
1086 atapi_pio_bytes(qc);
1088 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1089 /* bad ireason reported by device */
1093 /* ATA PIO protocol */
1094 if (unlikely((status & ATA_DRQ) == 0)) {
1095 /* handle BSY=0, DRQ=0 as error */
1096 if (likely(status & (ATA_ERR | ATA_DF))) {
1097 /* device stops HSM for abort/error */
1098 qc->err_mask |= AC_ERR_DEV;
1100 /* If diagnostic failed and this is
1101 * IDENTIFY, it's likely a phantom
1102 * device. Mark hint.
1104 if (qc->dev->horkage &
1105 ATA_HORKAGE_DIAGNOSTIC)
1109 /* HSM violation. Let EH handle this.
1110 * Phantom devices also trigger this
1111 * condition. Mark hint.
1113 ata_ehi_push_desc(ehi, "ST-ATA: "
1114 "DRQ=0 without device error, "
1115 "dev_stat 0x%X", status);
1116 qc->err_mask |= AC_ERR_HSM |
1120 ap->hsm_task_state = HSM_ST_ERR;
1124 /* For PIO reads, some devices may ask for
1125 * data transfer (DRQ=1) alone with ERR=1.
1126 * We respect DRQ here and transfer one
1127 * block of junk data before changing the
1128 * hsm_task_state to HSM_ST_ERR.
1130 * For PIO writes, ERR=1 DRQ=1 doesn't make
1131 * sense since the data block has been
1132 * transferred to the device.
1134 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1135 /* data might be corrputed */
1136 qc->err_mask |= AC_ERR_DEV;
1138 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1139 ata_pio_sectors(qc);
1140 status = ata_wait_idle(ap);
1143 if (status & (ATA_BUSY | ATA_DRQ)) {
1144 ata_ehi_push_desc(ehi, "ST-ATA: "
1145 "BUSY|DRQ persists on ERR|DF, "
1146 "dev_stat 0x%X", status);
1147 qc->err_mask |= AC_ERR_HSM;
1150 /* There are oddball controllers with
1151 * status register stuck at 0x7f and
1152 * lbal/m/h at zero which makes it
1153 * pass all other presence detection
1154 * mechanisms we have. Set NODEV_HINT
1155 * for it. Kernel bz#7241.
1158 qc->err_mask |= AC_ERR_NODEV_HINT;
1160 /* ata_pio_sectors() might change the
1161 * state to HSM_ST_LAST. so, the state
1162 * is changed after ata_pio_sectors().
1164 ap->hsm_task_state = HSM_ST_ERR;
1168 ata_pio_sectors(qc);
1170 if (ap->hsm_task_state == HSM_ST_LAST &&
1171 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1173 status = ata_wait_idle(ap);
1182 if (unlikely(!ata_ok(status))) {
1183 qc->err_mask |= __ac_err_mask(status);
1184 ap->hsm_task_state = HSM_ST_ERR;
1188 /* no more data to transfer */
1189 trace_ata_sff_hsm_command_complete(qc, status);
1191 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1193 ap->hsm_task_state = HSM_ST_IDLE;
1195 /* complete taskfile transaction */
1196 ata_hsm_qc_complete(qc, in_wq);
1202 ap->hsm_task_state = HSM_ST_IDLE;
1204 /* complete taskfile transaction */
1205 ata_hsm_qc_complete(qc, in_wq);
1211 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1212 ap->print_id, ap->hsm_task_state);
1217 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1219 void ata_sff_queue_work(struct work_struct *work)
1221 queue_work(ata_sff_wq, work);
1223 EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1225 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1227 queue_delayed_work(ata_sff_wq, dwork, delay);
1229 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1231 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1233 struct ata_port *ap = link->ap;
1235 WARN_ON((ap->sff_pio_task_link != NULL) &&
1236 (ap->sff_pio_task_link != link));
1237 ap->sff_pio_task_link = link;
1239 /* may fail if ata_sff_flush_pio_task() in progress */
1240 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1242 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1244 void ata_sff_flush_pio_task(struct ata_port *ap)
1246 trace_ata_sff_flush_pio_task(ap);
1248 cancel_delayed_work_sync(&ap->sff_pio_task);
1251 * We wanna reset the HSM state to IDLE. If we do so without
1252 * grabbing the port lock, critical sections protected by it which
1253 * expect the HSM state to stay stable may get surprised. For
1254 * example, we may set IDLE in between the time
1255 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1256 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1258 spin_lock_irq(ap->lock);
1259 ap->hsm_task_state = HSM_ST_IDLE;
1260 spin_unlock_irq(ap->lock);
1262 ap->sff_pio_task_link = NULL;
1265 static void ata_sff_pio_task(struct work_struct *work)
1267 struct ata_port *ap =
1268 container_of(work, struct ata_port, sff_pio_task.work);
1269 struct ata_link *link = ap->sff_pio_task_link;
1270 struct ata_queued_cmd *qc;
1274 spin_lock_irq(ap->lock);
1276 BUG_ON(ap->sff_pio_task_link == NULL);
1277 /* qc can be NULL if timeout occurred */
1278 qc = ata_qc_from_tag(ap, link->active_tag);
1280 ap->sff_pio_task_link = NULL;
1285 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1288 * This is purely heuristic. This is a fast path.
1289 * Sometimes when we enter, BSY will be cleared in
1290 * a chk-status or two. If not, the drive is probably seeking
1291 * or something. Snooze for a couple msecs, then
1292 * chk-status again. If still busy, queue delayed work.
1294 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1295 if (status & ATA_BUSY) {
1296 spin_unlock_irq(ap->lock);
1298 spin_lock_irq(ap->lock);
1300 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1301 if (status & ATA_BUSY) {
1302 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1308 * hsm_move() may trigger another command to be processed.
1309 * clean the link beforehand.
1311 ap->sff_pio_task_link = NULL;
1313 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1315 /* another command or interrupt handler
1316 * may be running at this point.
1321 spin_unlock_irq(ap->lock);
1325 * ata_sff_qc_issue - issue taskfile to a SFF controller
1326 * @qc: command to issue to device
1328 * This function issues a PIO or NODATA command to a SFF
1332 * spin_lock_irqsave(host lock)
1335 * Zero on success, AC_ERR_* mask on failure
1337 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1339 struct ata_port *ap = qc->ap;
1340 struct ata_link *link = qc->dev->link;
1342 /* Use polling pio if the LLD doesn't handle
1343 * interrupt driven pio and atapi CDB interrupt.
1345 if (ap->flags & ATA_FLAG_PIO_POLLING)
1346 qc->tf.flags |= ATA_TFLAG_POLLING;
1348 /* select the device */
1349 ata_dev_select(ap, qc->dev->devno, 1, 0);
1351 /* start the command */
1352 switch (qc->tf.protocol) {
1353 case ATA_PROT_NODATA:
1354 if (qc->tf.flags & ATA_TFLAG_POLLING)
1355 ata_qc_set_polling(qc);
1357 ata_tf_to_host(ap, &qc->tf, qc->tag);
1358 ap->hsm_task_state = HSM_ST_LAST;
1360 if (qc->tf.flags & ATA_TFLAG_POLLING)
1361 ata_sff_queue_pio_task(link, 0);
1366 if (qc->tf.flags & ATA_TFLAG_POLLING)
1367 ata_qc_set_polling(qc);
1369 ata_tf_to_host(ap, &qc->tf, qc->tag);
1371 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1372 /* PIO data out protocol */
1373 ap->hsm_task_state = HSM_ST_FIRST;
1374 ata_sff_queue_pio_task(link, 0);
1376 /* always send first data block using the
1377 * ata_sff_pio_task() codepath.
1380 /* PIO data in protocol */
1381 ap->hsm_task_state = HSM_ST;
1383 if (qc->tf.flags & ATA_TFLAG_POLLING)
1384 ata_sff_queue_pio_task(link, 0);
1386 /* if polling, ata_sff_pio_task() handles the
1387 * rest. otherwise, interrupt handler takes
1394 case ATAPI_PROT_PIO:
1395 case ATAPI_PROT_NODATA:
1396 if (qc->tf.flags & ATA_TFLAG_POLLING)
1397 ata_qc_set_polling(qc);
1399 ata_tf_to_host(ap, &qc->tf, qc->tag);
1401 ap->hsm_task_state = HSM_ST_FIRST;
1403 /* send cdb by polling if no cdb interrupt */
1404 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1405 (qc->tf.flags & ATA_TFLAG_POLLING))
1406 ata_sff_queue_pio_task(link, 0);
1410 return AC_ERR_SYSTEM;
1415 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1418 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1419 * @qc: qc to fill result TF for
1421 * @qc is finished and result TF needs to be filled. Fill it
1422 * using ->sff_tf_read.
1425 * spin_lock_irqsave(host lock)
1428 * true indicating that result TF is successfully filled.
1430 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1432 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1435 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1437 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1439 ap->stats.idle_irq++;
1442 if ((ap->stats.idle_irq % 1000) == 0) {
1443 ap->ops->sff_check_status(ap);
1444 if (ap->ops->sff_irq_clear)
1445 ap->ops->sff_irq_clear(ap);
1446 ata_port_warn(ap, "irq trap\n");
1450 return 0; /* irq not handled */
1453 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1454 struct ata_queued_cmd *qc,
1459 trace_ata_sff_port_intr(qc, hsmv_on_idle);
1461 /* Check whether we are expecting interrupt in this state */
1462 switch (ap->hsm_task_state) {
1464 /* Some pre-ATAPI-4 devices assert INTRQ
1465 * at this state when ready to receive CDB.
1468 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1469 * The flag was turned on only for atapi devices. No
1470 * need to check ata_is_atapi(qc->tf.protocol) again.
1472 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1473 return ata_sff_idle_irq(ap);
1476 return ata_sff_idle_irq(ap);
1481 /* check main status, clearing INTRQ if needed */
1482 status = ata_sff_irq_status(ap);
1483 if (status & ATA_BUSY) {
1485 /* BMDMA engine is already stopped, we're screwed */
1486 qc->err_mask |= AC_ERR_HSM;
1487 ap->hsm_task_state = HSM_ST_ERR;
1489 return ata_sff_idle_irq(ap);
1492 /* clear irq events */
1493 if (ap->ops->sff_irq_clear)
1494 ap->ops->sff_irq_clear(ap);
1496 ata_sff_hsm_move(ap, qc, status, 0);
1498 return 1; /* irq handled */
1502 * ata_sff_port_intr - Handle SFF port interrupt
1503 * @ap: Port on which interrupt arrived (possibly...)
1504 * @qc: Taskfile currently active in engine
1506 * Handle port interrupt for given queued command.
1509 * spin_lock_irqsave(host lock)
1512 * One if interrupt was handled, zero if not (shared irq).
1514 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1516 return __ata_sff_port_intr(ap, qc, false);
1518 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1520 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1521 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1523 struct ata_host *host = dev_instance;
1524 bool retried = false;
1526 unsigned int handled, idle, polling;
1527 unsigned long flags;
1529 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1530 spin_lock_irqsave(&host->lock, flags);
1533 handled = idle = polling = 0;
1534 for (i = 0; i < host->n_ports; i++) {
1535 struct ata_port *ap = host->ports[i];
1536 struct ata_queued_cmd *qc;
1538 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1540 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1541 handled |= port_intr(ap, qc);
1549 * If no port was expecting IRQ but the controller is actually
1550 * asserting IRQ line, nobody cared will ensue. Check IRQ
1551 * pending status if available and clear spurious IRQ.
1553 if (!handled && !retried) {
1556 for (i = 0; i < host->n_ports; i++) {
1557 struct ata_port *ap = host->ports[i];
1559 if (polling & (1 << i))
1562 if (!ap->ops->sff_irq_check ||
1563 !ap->ops->sff_irq_check(ap))
1566 if (idle & (1 << i)) {
1567 ap->ops->sff_check_status(ap);
1568 if (ap->ops->sff_irq_clear)
1569 ap->ops->sff_irq_clear(ap);
1571 /* clear INTRQ and check if BUSY cleared */
1572 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1575 * With command in flight, we can't do
1576 * sff_irq_clear() w/o racing with completion.
1587 spin_unlock_irqrestore(&host->lock, flags);
1589 return IRQ_RETVAL(handled);
1593 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1594 * @irq: irq line (unused)
1595 * @dev_instance: pointer to our ata_host information structure
1597 * Default interrupt handler for PCI IDE devices. Calls
1598 * ata_sff_port_intr() for each port that is not disabled.
1601 * Obtains host lock during operation.
1604 * IRQ_NONE or IRQ_HANDLED.
1606 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1608 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1610 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1613 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1614 * @ap: port that appears to have timed out
1616 * Called from the libata error handlers when the core code suspects
1617 * an interrupt has been lost. If it has complete anything we can and
1618 * then return. Interface must support altstatus for this faster
1619 * recovery to occur.
1622 * Caller holds host lock
1625 void ata_sff_lost_interrupt(struct ata_port *ap)
1628 struct ata_queued_cmd *qc;
1630 /* Only one outstanding command per SFF channel */
1631 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1632 /* We cannot lose an interrupt on a non-existent or polled command */
1633 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1635 /* See if the controller thinks it is still busy - if so the command
1636 isn't a lost IRQ but is still in progress */
1637 status = ata_sff_altstatus(ap);
1638 if (status & ATA_BUSY)
1641 /* There was a command running, we are no longer busy and we have
1643 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1645 /* Run the host interrupt logic as if the interrupt had not been
1647 ata_sff_port_intr(ap, qc);
1649 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1652 * ata_sff_freeze - Freeze SFF controller port
1653 * @ap: port to freeze
1655 * Freeze SFF controller port.
1658 * Inherited from caller.
1660 void ata_sff_freeze(struct ata_port *ap)
1662 ap->ctl |= ATA_NIEN;
1663 ap->last_ctl = ap->ctl;
1665 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1666 ata_sff_set_devctl(ap, ap->ctl);
1668 /* Under certain circumstances, some controllers raise IRQ on
1669 * ATA_NIEN manipulation. Also, many controllers fail to mask
1670 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1672 ap->ops->sff_check_status(ap);
1674 if (ap->ops->sff_irq_clear)
1675 ap->ops->sff_irq_clear(ap);
1677 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1680 * ata_sff_thaw - Thaw SFF controller port
1683 * Thaw SFF controller port.
1686 * Inherited from caller.
1688 void ata_sff_thaw(struct ata_port *ap)
1690 /* clear & re-enable interrupts */
1691 ap->ops->sff_check_status(ap);
1692 if (ap->ops->sff_irq_clear)
1693 ap->ops->sff_irq_clear(ap);
1696 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1699 * ata_sff_prereset - prepare SFF link for reset
1700 * @link: SFF link to be reset
1701 * @deadline: deadline jiffies for the operation
1703 * SFF link @link is about to be reset. Initialize it. It first
1704 * calls ata_std_prereset() and wait for !BSY if the port is
1708 * Kernel thread context (may sleep)
1711 * 0 on success, -errno otherwise.
1713 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1715 struct ata_eh_context *ehc = &link->eh_context;
1718 rc = ata_std_prereset(link, deadline);
1722 /* if we're about to do hardreset, nothing more to do */
1723 if (ehc->i.action & ATA_EH_HARDRESET)
1726 /* wait for !BSY if we don't know that no device is attached */
1727 if (!ata_link_offline(link)) {
1728 rc = ata_sff_wait_ready(link, deadline);
1729 if (rc && rc != -ENODEV) {
1731 "device not ready (errno=%d), forcing hardreset\n",
1733 ehc->i.action |= ATA_EH_HARDRESET;
1739 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1742 * ata_devchk - PATA device presence detection
1743 * @ap: ATA channel to examine
1744 * @device: Device to examine (starting at zero)
1746 * This technique was originally described in
1747 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1748 * later found its way into the ATA/ATAPI spec.
1750 * Write a pattern to the ATA shadow registers,
1751 * and if a device is present, it will respond by
1752 * correctly storing and echoing back the
1753 * ATA shadow register contents.
1758 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1760 struct ata_ioports *ioaddr = &ap->ioaddr;
1763 ap->ops->sff_dev_select(ap, device);
1765 iowrite8(0x55, ioaddr->nsect_addr);
1766 iowrite8(0xaa, ioaddr->lbal_addr);
1768 iowrite8(0xaa, ioaddr->nsect_addr);
1769 iowrite8(0x55, ioaddr->lbal_addr);
1771 iowrite8(0x55, ioaddr->nsect_addr);
1772 iowrite8(0xaa, ioaddr->lbal_addr);
1774 nsect = ioread8(ioaddr->nsect_addr);
1775 lbal = ioread8(ioaddr->lbal_addr);
1777 if ((nsect == 0x55) && (lbal == 0xaa))
1778 return 1; /* we found a device */
1780 return 0; /* nothing found */
1784 * ata_sff_dev_classify - Parse returned ATA device signature
1785 * @dev: ATA device to classify (starting at zero)
1786 * @present: device seems present
1787 * @r_err: Value of error register on completion
1789 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1790 * an ATA/ATAPI-defined set of values is placed in the ATA
1791 * shadow registers, indicating the results of device detection
1794 * Select the ATA device, and read the values from the ATA shadow
1795 * registers. Then parse according to the Error register value,
1796 * and the spec-defined values examined by ata_dev_classify().
1802 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1804 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1807 struct ata_port *ap = dev->link->ap;
1808 struct ata_taskfile tf;
1812 ap->ops->sff_dev_select(ap, dev->devno);
1814 memset(&tf, 0, sizeof(tf));
1816 ap->ops->sff_tf_read(ap, &tf);
1821 /* see if device passed diags: continue and warn later */
1823 /* diagnostic fail : do nothing _YET_ */
1824 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1827 else if ((dev->devno == 0) && (err == 0x81))
1830 return ATA_DEV_NONE;
1832 /* determine if device is ATA or ATAPI */
1833 class = ata_port_classify(ap, &tf);
1835 if (class == ATA_DEV_UNKNOWN) {
1836 /* If the device failed diagnostic, it's likely to
1837 * have reported incorrect device signature too.
1838 * Assume ATA device if the device seems present but
1839 * device signature is invalid with diagnostic
1842 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1843 class = ATA_DEV_ATA;
1845 class = ATA_DEV_NONE;
1846 } else if ((class == ATA_DEV_ATA) &&
1847 (ap->ops->sff_check_status(ap) == 0))
1848 class = ATA_DEV_NONE;
1852 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1855 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1856 * @link: SFF link which is just reset
1857 * @devmask: mask of present devices
1858 * @deadline: deadline jiffies for the operation
1860 * Wait devices attached to SFF @link to become ready after
1861 * reset. It contains preceding 150ms wait to avoid accessing TF
1862 * status register too early.
1865 * Kernel thread context (may sleep).
1868 * 0 on success, -ENODEV if some or all of devices in @devmask
1869 * don't seem to exist. -errno on other errors.
1871 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1872 unsigned long deadline)
1874 struct ata_port *ap = link->ap;
1875 struct ata_ioports *ioaddr = &ap->ioaddr;
1876 unsigned int dev0 = devmask & (1 << 0);
1877 unsigned int dev1 = devmask & (1 << 1);
1880 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1882 /* always check readiness of the master device */
1883 rc = ata_sff_wait_ready(link, deadline);
1884 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1885 * and TF status is 0xff, bail out on it too.
1890 /* if device 1 was found in ata_devchk, wait for register
1891 * access briefly, then wait for BSY to clear.
1896 ap->ops->sff_dev_select(ap, 1);
1898 /* Wait for register access. Some ATAPI devices fail
1899 * to set nsect/lbal after reset, so don't waste too
1900 * much time on it. We're gonna wait for !BSY anyway.
1902 for (i = 0; i < 2; i++) {
1905 nsect = ioread8(ioaddr->nsect_addr);
1906 lbal = ioread8(ioaddr->lbal_addr);
1907 if ((nsect == 1) && (lbal == 1))
1909 ata_msleep(ap, 50); /* give drive a breather */
1912 rc = ata_sff_wait_ready(link, deadline);
1920 /* is all this really necessary? */
1921 ap->ops->sff_dev_select(ap, 0);
1923 ap->ops->sff_dev_select(ap, 1);
1925 ap->ops->sff_dev_select(ap, 0);
1929 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1931 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1932 unsigned long deadline)
1934 struct ata_ioports *ioaddr = &ap->ioaddr;
1936 if (ap->ioaddr.ctl_addr) {
1937 /* software reset. causes dev0 to be selected */
1938 iowrite8(ap->ctl, ioaddr->ctl_addr);
1939 udelay(20); /* FIXME: flush */
1940 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1941 udelay(20); /* FIXME: flush */
1942 iowrite8(ap->ctl, ioaddr->ctl_addr);
1943 ap->last_ctl = ap->ctl;
1946 /* wait the port to become ready */
1947 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1951 * ata_sff_softreset - reset host port via ATA SRST
1952 * @link: ATA link to reset
1953 * @classes: resulting classes of attached devices
1954 * @deadline: deadline jiffies for the operation
1956 * Reset host port using ATA SRST.
1959 * Kernel thread context (may sleep)
1962 * 0 on success, -errno otherwise.
1964 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1965 unsigned long deadline)
1967 struct ata_port *ap = link->ap;
1968 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1969 unsigned int devmask = 0;
1973 /* determine if device 0/1 are present */
1974 if (ata_devchk(ap, 0))
1975 devmask |= (1 << 0);
1976 if (slave_possible && ata_devchk(ap, 1))
1977 devmask |= (1 << 1);
1979 /* select device 0 again */
1980 ap->ops->sff_dev_select(ap, 0);
1982 /* issue bus reset */
1983 rc = ata_bus_softreset(ap, devmask, deadline);
1984 /* if link is occupied, -ENODEV too is an error */
1985 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1986 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
1990 /* determine by signature whether we have ATA or ATAPI devices */
1991 classes[0] = ata_sff_dev_classify(&link->device[0],
1992 devmask & (1 << 0), &err);
1993 if (slave_possible && err != 0x81)
1994 classes[1] = ata_sff_dev_classify(&link->device[1],
1995 devmask & (1 << 1), &err);
1999 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2002 * sata_sff_hardreset - reset host port via SATA phy reset
2003 * @link: link to reset
2004 * @class: resulting class of attached device
2005 * @deadline: deadline jiffies for the operation
2007 * SATA phy-reset host port using DET bits of SControl register,
2008 * wait for !BSY and classify the attached device.
2011 * Kernel thread context (may sleep)
2014 * 0 on success, -errno otherwise.
2016 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2017 unsigned long deadline)
2019 struct ata_eh_context *ehc = &link->eh_context;
2020 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2024 rc = sata_link_hardreset(link, timing, deadline, &online,
2025 ata_sff_check_ready);
2027 *class = ata_sff_dev_classify(link->device, 1, NULL);
2031 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2034 * ata_sff_postreset - SFF postreset callback
2035 * @link: the target SFF ata_link
2036 * @classes: classes of attached devices
2038 * This function is invoked after a successful reset. It first
2039 * calls ata_std_postreset() and performs SFF specific postreset
2043 * Kernel thread context (may sleep)
2045 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2047 struct ata_port *ap = link->ap;
2049 ata_std_postreset(link, classes);
2051 /* is double-select really necessary? */
2052 if (classes[0] != ATA_DEV_NONE)
2053 ap->ops->sff_dev_select(ap, 1);
2054 if (classes[1] != ATA_DEV_NONE)
2055 ap->ops->sff_dev_select(ap, 0);
2057 /* bail out if no device is present */
2058 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE)
2061 /* set up device control */
2062 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2063 ata_sff_set_devctl(ap, ap->ctl);
2064 ap->last_ctl = ap->ctl;
2067 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2070 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2073 * Drain the FIFO and device of any stuck data following a command
2074 * failing to complete. In some cases this is necessary before a
2075 * reset will recover the device.
2079 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2082 struct ata_port *ap;
2084 /* We only need to flush incoming data when a command was running */
2085 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2089 /* Drain up to 64K of data before we give up this recovery method */
2090 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2091 && count < 65536; count += 2)
2092 ioread16(ap->ioaddr.data_addr);
2095 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2098 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2101 * ata_sff_error_handler - Stock error handler for SFF controller
2102 * @ap: port to handle error for
2104 * Stock error handler for SFF controller. It can handle both
2105 * PATA and SATA controllers. Many controllers should be able to
2106 * use this EH as-is or with some added handling before and
2110 * Kernel thread context (may sleep)
2112 void ata_sff_error_handler(struct ata_port *ap)
2114 ata_reset_fn_t softreset = ap->ops->softreset;
2115 ata_reset_fn_t hardreset = ap->ops->hardreset;
2116 struct ata_queued_cmd *qc;
2117 unsigned long flags;
2119 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2120 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2123 spin_lock_irqsave(ap->lock, flags);
2126 * We *MUST* do FIFO draining before we issue a reset as
2127 * several devices helpfully clear their internal state and
2128 * will lock solid if we touch the data port post reset. Pass
2129 * qc in case anyone wants to do different PIO/DMA recovery or
2130 * has per command fixups
2132 if (ap->ops->sff_drain_fifo)
2133 ap->ops->sff_drain_fifo(qc);
2135 spin_unlock_irqrestore(ap->lock, flags);
2137 /* ignore built-in hardresets if SCR access is not available */
2138 if ((hardreset == sata_std_hardreset ||
2139 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2142 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2143 ap->ops->postreset);
2145 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2148 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2149 * @ioaddr: IO address structure to be initialized
2151 * Utility function which initializes data_addr, error_addr,
2152 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2153 * device_addr, status_addr, and command_addr to standard offsets
2154 * relative to cmd_addr.
2156 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2158 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2160 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2161 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2162 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2163 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2164 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2165 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2166 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2167 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2168 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2169 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2171 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2175 static int ata_resources_present(struct pci_dev *pdev, int port)
2179 /* Check the PCI resources for this channel are enabled */
2181 for (i = 0; i < 2; i++) {
2182 if (pci_resource_start(pdev, port + i) == 0 ||
2183 pci_resource_len(pdev, port + i) == 0)
2190 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2191 * @host: target ATA host
2193 * Acquire native PCI ATA resources for @host and initialize the
2194 * first two ports of @host accordingly. Ports marked dummy are
2195 * skipped and allocation failure makes the port dummy.
2197 * Note that native PCI resources are valid even for legacy hosts
2198 * as we fix up pdev resources array early in boot, so this
2199 * function can be used for both native and legacy SFF hosts.
2202 * Inherited from calling layer (may sleep).
2205 * 0 if at least one port is initialized, -ENODEV if no port is
2208 int ata_pci_sff_init_host(struct ata_host *host)
2210 struct device *gdev = host->dev;
2211 struct pci_dev *pdev = to_pci_dev(gdev);
2212 unsigned int mask = 0;
2215 /* request, iomap BARs and init port addresses accordingly */
2216 for (i = 0; i < 2; i++) {
2217 struct ata_port *ap = host->ports[i];
2219 void __iomem * const *iomap;
2221 if (ata_port_is_dummy(ap))
2224 /* Discard disabled ports. Some controllers show
2225 * their unused channels this way. Disabled ports are
2228 if (!ata_resources_present(pdev, i)) {
2229 ap->ops = &ata_dummy_port_ops;
2233 rc = pcim_iomap_regions(pdev, 0x3 << base,
2234 dev_driver_string(gdev));
2237 "failed to request/iomap BARs for port %d (errno=%d)\n",
2240 pcim_pin_device(pdev);
2241 ap->ops = &ata_dummy_port_ops;
2244 host->iomap = iomap = pcim_iomap_table(pdev);
2246 ap->ioaddr.cmd_addr = iomap[base];
2247 ap->ioaddr.altstatus_addr =
2248 ap->ioaddr.ctl_addr = (void __iomem *)
2249 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2250 ata_sff_std_ports(&ap->ioaddr);
2252 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2253 (unsigned long long)pci_resource_start(pdev, base),
2254 (unsigned long long)pci_resource_start(pdev, base + 1));
2260 dev_err(gdev, "no available native port\n");
2266 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2269 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2270 * @pdev: target PCI device
2271 * @ppi: array of port_info, must be enough for two ports
2272 * @r_host: out argument for the initialized ATA host
2274 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2275 * all PCI resources and initialize it accordingly in one go.
2278 * Inherited from calling layer (may sleep).
2281 * 0 on success, -errno otherwise.
2283 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2284 const struct ata_port_info * const *ppi,
2285 struct ata_host **r_host)
2287 struct ata_host *host;
2290 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2293 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2295 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2300 rc = ata_pci_sff_init_host(host);
2304 devres_remove_group(&pdev->dev, NULL);
2309 devres_release_group(&pdev->dev, NULL);
2312 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2315 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2316 * @host: target SFF ATA host
2317 * @irq_handler: irq_handler used when requesting IRQ(s)
2318 * @sht: scsi_host_template to use when registering the host
2320 * This is the counterpart of ata_host_activate() for SFF ATA
2321 * hosts. This separate helper is necessary because SFF hosts
2322 * use two separate interrupts in legacy mode.
2325 * Inherited from calling layer (may sleep).
2328 * 0 on success, -errno otherwise.
2330 int ata_pci_sff_activate_host(struct ata_host *host,
2331 irq_handler_t irq_handler,
2332 struct scsi_host_template *sht)
2334 struct device *dev = host->dev;
2335 struct pci_dev *pdev = to_pci_dev(dev);
2336 const char *drv_name = dev_driver_string(host->dev);
2337 int legacy_mode = 0, rc;
2339 rc = ata_host_start(host);
2343 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2347 * ATA spec says we should use legacy mode when one
2348 * port is in legacy mode, but disabled ports on some
2349 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2350 * on which the secondary port is not wired, so
2351 * ignore ports that are marked as 'dummy' during
2354 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2355 if (!ata_port_is_dummy(host->ports[0]))
2357 if (!ata_port_is_dummy(host->ports[1]))
2359 if ((tmp8 & mask) != mask)
2363 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2366 if (!legacy_mode && pdev->irq) {
2369 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2370 IRQF_SHARED, drv_name, host);
2374 for (i = 0; i < 2; i++) {
2375 if (ata_port_is_dummy(host->ports[i]))
2377 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2379 } else if (legacy_mode) {
2380 if (!ata_port_is_dummy(host->ports[0])) {
2381 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2382 irq_handler, IRQF_SHARED,
2387 ata_port_desc(host->ports[0], "irq %d",
2388 ATA_PRIMARY_IRQ(pdev));
2391 if (!ata_port_is_dummy(host->ports[1])) {
2392 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2393 irq_handler, IRQF_SHARED,
2398 ata_port_desc(host->ports[1], "irq %d",
2399 ATA_SECONDARY_IRQ(pdev));
2403 rc = ata_host_register(host, sht);
2406 devres_remove_group(dev, NULL);
2408 devres_release_group(dev, NULL);
2412 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2414 static const struct ata_port_info *ata_sff_find_valid_pi(
2415 const struct ata_port_info * const *ppi)
2419 /* look up the first valid port_info */
2420 for (i = 0; i < 2 && ppi[i]; i++)
2421 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2427 static int ata_pci_init_one(struct pci_dev *pdev,
2428 const struct ata_port_info * const *ppi,
2429 struct scsi_host_template *sht, void *host_priv,
2430 int hflags, bool bmdma)
2432 struct device *dev = &pdev->dev;
2433 const struct ata_port_info *pi;
2434 struct ata_host *host = NULL;
2437 pi = ata_sff_find_valid_pi(ppi);
2439 dev_err(&pdev->dev, "no valid port_info specified\n");
2443 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2446 rc = pcim_enable_device(pdev);
2450 #ifdef CONFIG_ATA_BMDMA
2452 /* prepare and activate BMDMA host */
2453 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2456 /* prepare and activate SFF host */
2457 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2460 host->private_data = host_priv;
2461 host->flags |= hflags;
2463 #ifdef CONFIG_ATA_BMDMA
2465 pci_set_master(pdev);
2466 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2469 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2472 devres_remove_group(&pdev->dev, NULL);
2474 devres_release_group(&pdev->dev, NULL);
2480 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2481 * @pdev: Controller to be initialized
2482 * @ppi: array of port_info, must be enough for two ports
2483 * @sht: scsi_host_template to use when registering the host
2484 * @host_priv: host private_data
2485 * @hflag: host flags
2487 * This is a helper function which can be called from a driver's
2488 * xxx_init_one() probe function if the hardware uses traditional
2489 * IDE taskfile registers and is PIO only.
2492 * Nobody makes a single channel controller that appears solely as
2493 * the secondary legacy port on PCI.
2496 * Inherited from PCI layer (may sleep).
2499 * Zero on success, negative on errno-based value on error.
2501 int ata_pci_sff_init_one(struct pci_dev *pdev,
2502 const struct ata_port_info * const *ppi,
2503 struct scsi_host_template *sht, void *host_priv, int hflag)
2505 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2507 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2509 #endif /* CONFIG_PCI */
2515 #ifdef CONFIG_ATA_BMDMA
2517 const struct ata_port_operations ata_bmdma_port_ops = {
2518 .inherits = &ata_sff_port_ops,
2520 .error_handler = ata_bmdma_error_handler,
2521 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2523 .qc_prep = ata_bmdma_qc_prep,
2524 .qc_issue = ata_bmdma_qc_issue,
2526 .sff_irq_clear = ata_bmdma_irq_clear,
2527 .bmdma_setup = ata_bmdma_setup,
2528 .bmdma_start = ata_bmdma_start,
2529 .bmdma_stop = ata_bmdma_stop,
2530 .bmdma_status = ata_bmdma_status,
2532 .port_start = ata_bmdma_port_start,
2534 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2536 const struct ata_port_operations ata_bmdma32_port_ops = {
2537 .inherits = &ata_bmdma_port_ops,
2539 .sff_data_xfer = ata_sff_data_xfer32,
2540 .port_start = ata_bmdma_port_start32,
2542 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2545 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2546 * @qc: Metadata associated with taskfile to be transferred
2548 * Fill PCI IDE PRD (scatter-gather) table with segments
2549 * associated with the current disk command.
2552 * spin_lock_irqsave(host lock)
2555 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2557 struct ata_port *ap = qc->ap;
2558 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2559 struct scatterlist *sg;
2560 unsigned int si, pi;
2563 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2567 /* determine if physical DMA addr spans 64K boundary.
2568 * Note h/w doesn't support 64-bit, so we unconditionally
2569 * truncate dma_addr_t to u32.
2571 addr = (u32) sg_dma_address(sg);
2572 sg_len = sg_dma_len(sg);
2575 offset = addr & 0xffff;
2577 if ((offset + sg_len) > 0x10000)
2578 len = 0x10000 - offset;
2580 prd[pi].addr = cpu_to_le32(addr);
2581 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2589 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2593 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2594 * @qc: Metadata associated with taskfile to be transferred
2596 * Fill PCI IDE PRD (scatter-gather) table with segments
2597 * associated with the current disk command. Perform the fill
2598 * so that we avoid writing any length 64K records for
2599 * controllers that don't follow the spec.
2602 * spin_lock_irqsave(host lock)
2605 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2607 struct ata_port *ap = qc->ap;
2608 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2609 struct scatterlist *sg;
2610 unsigned int si, pi;
2613 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2615 u32 sg_len, len, blen;
2617 /* determine if physical DMA addr spans 64K boundary.
2618 * Note h/w doesn't support 64-bit, so we unconditionally
2619 * truncate dma_addr_t to u32.
2621 addr = (u32) sg_dma_address(sg);
2622 sg_len = sg_dma_len(sg);
2625 offset = addr & 0xffff;
2627 if ((offset + sg_len) > 0x10000)
2628 len = 0x10000 - offset;
2630 blen = len & 0xffff;
2631 prd[pi].addr = cpu_to_le32(addr);
2633 /* Some PATA chipsets like the CS5530 can't
2634 cope with 0x0000 meaning 64K as the spec
2636 prd[pi].flags_len = cpu_to_le32(0x8000);
2638 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2640 prd[pi].flags_len = cpu_to_le32(blen);
2648 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2652 * ata_bmdma_qc_prep - Prepare taskfile for submission
2653 * @qc: Metadata associated with taskfile to be prepared
2655 * Prepare ATA taskfile for submission.
2658 * spin_lock_irqsave(host lock)
2660 enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2662 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2665 ata_bmdma_fill_sg(qc);
2669 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2672 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2673 * @qc: Metadata associated with taskfile to be prepared
2675 * Prepare ATA taskfile for submission.
2678 * spin_lock_irqsave(host lock)
2680 enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2682 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2685 ata_bmdma_fill_sg_dumb(qc);
2689 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2692 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2693 * @qc: command to issue to device
2695 * This function issues a PIO, NODATA or DMA command to a
2696 * SFF/BMDMA controller. PIO and NODATA are handled by
2697 * ata_sff_qc_issue().
2700 * spin_lock_irqsave(host lock)
2703 * Zero on success, AC_ERR_* mask on failure
2705 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2707 struct ata_port *ap = qc->ap;
2708 struct ata_link *link = qc->dev->link;
2710 /* defer PIO handling to sff_qc_issue */
2711 if (!ata_is_dma(qc->tf.protocol))
2712 return ata_sff_qc_issue(qc);
2714 /* select the device */
2715 ata_dev_select(ap, qc->dev->devno, 1, 0);
2717 /* start the command */
2718 switch (qc->tf.protocol) {
2720 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2722 trace_ata_tf_load(ap, &qc->tf);
2723 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2724 trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2725 ap->ops->bmdma_setup(qc); /* set up bmdma */
2726 trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
2727 ap->ops->bmdma_start(qc); /* initiate bmdma */
2728 ap->hsm_task_state = HSM_ST_LAST;
2731 case ATAPI_PROT_DMA:
2732 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2734 trace_ata_tf_load(ap, &qc->tf);
2735 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2736 trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2737 ap->ops->bmdma_setup(qc); /* set up bmdma */
2738 ap->hsm_task_state = HSM_ST_FIRST;
2740 /* send cdb by polling if no cdb interrupt */
2741 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2742 ata_sff_queue_pio_task(link, 0);
2747 return AC_ERR_SYSTEM;
2752 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2755 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2756 * @ap: Port on which interrupt arrived (possibly...)
2757 * @qc: Taskfile currently active in engine
2759 * Handle port interrupt for given queued command.
2762 * spin_lock_irqsave(host lock)
2765 * One if interrupt was handled, zero if not (shared irq).
2767 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2769 struct ata_eh_info *ehi = &ap->link.eh_info;
2771 bool bmdma_stopped = false;
2772 unsigned int handled;
2774 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2775 /* check status of DMA engine */
2776 host_stat = ap->ops->bmdma_status(ap);
2777 trace_ata_bmdma_status(ap, host_stat);
2779 /* if it's not our irq... */
2780 if (!(host_stat & ATA_DMA_INTR))
2781 return ata_sff_idle_irq(ap);
2783 /* before we do anything else, clear DMA-Start bit */
2784 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2785 ap->ops->bmdma_stop(qc);
2786 bmdma_stopped = true;
2788 if (unlikely(host_stat & ATA_DMA_ERR)) {
2789 /* error when transferring data to/from memory */
2790 qc->err_mask |= AC_ERR_HOST_BUS;
2791 ap->hsm_task_state = HSM_ST_ERR;
2795 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2797 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2798 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2802 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2805 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2806 * @irq: irq line (unused)
2807 * @dev_instance: pointer to our ata_host information structure
2809 * Default interrupt handler for PCI IDE devices. Calls
2810 * ata_bmdma_port_intr() for each port that is not disabled.
2813 * Obtains host lock during operation.
2816 * IRQ_NONE or IRQ_HANDLED.
2818 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2820 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2822 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2825 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2826 * @ap: port to handle error for
2828 * Stock error handler for BMDMA controller. It can handle both
2829 * PATA and SATA controllers. Most BMDMA controllers should be
2830 * able to use this EH as-is or with some added handling before
2834 * Kernel thread context (may sleep)
2836 void ata_bmdma_error_handler(struct ata_port *ap)
2838 struct ata_queued_cmd *qc;
2839 unsigned long flags;
2842 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2843 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2846 /* reset PIO HSM and stop DMA engine */
2847 spin_lock_irqsave(ap->lock, flags);
2849 if (qc && ata_is_dma(qc->tf.protocol)) {
2852 host_stat = ap->ops->bmdma_status(ap);
2853 trace_ata_bmdma_status(ap, host_stat);
2855 /* BMDMA controllers indicate host bus error by
2856 * setting DMA_ERR bit and timing out. As it wasn't
2857 * really a timeout event, adjust error mask and
2858 * cancel frozen state.
2860 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2861 qc->err_mask = AC_ERR_HOST_BUS;
2865 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2866 ap->ops->bmdma_stop(qc);
2868 /* if we're gonna thaw, make sure IRQ is clear */
2870 ap->ops->sff_check_status(ap);
2871 if (ap->ops->sff_irq_clear)
2872 ap->ops->sff_irq_clear(ap);
2876 spin_unlock_irqrestore(ap->lock, flags);
2879 ata_eh_thaw_port(ap);
2881 ata_sff_error_handler(ap);
2883 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2886 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2887 * @qc: internal command to clean up
2890 * Kernel thread context (may sleep)
2892 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2894 struct ata_port *ap = qc->ap;
2895 unsigned long flags;
2897 if (ata_is_dma(qc->tf.protocol)) {
2898 spin_lock_irqsave(ap->lock, flags);
2899 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2900 ap->ops->bmdma_stop(qc);
2901 spin_unlock_irqrestore(ap->lock, flags);
2904 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2907 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2908 * @ap: Port associated with this ATA transaction.
2910 * Clear interrupt and error flags in DMA status register.
2912 * May be used as the irq_clear() entry in ata_port_operations.
2915 * spin_lock_irqsave(host lock)
2917 void ata_bmdma_irq_clear(struct ata_port *ap)
2919 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2924 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2926 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2929 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2930 * @qc: Info associated with this ATA transaction.
2933 * spin_lock_irqsave(host lock)
2935 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2937 struct ata_port *ap = qc->ap;
2938 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2941 /* load PRD table addr. */
2942 mb(); /* make sure PRD table writes are visible to controller */
2943 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2945 /* specify data direction, triple-check start bit is clear */
2946 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2947 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2949 dmactl |= ATA_DMA_WR;
2950 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2952 /* issue r/w command */
2953 ap->ops->sff_exec_command(ap, &qc->tf);
2955 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2958 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2959 * @qc: Info associated with this ATA transaction.
2962 * spin_lock_irqsave(host lock)
2964 void ata_bmdma_start(struct ata_queued_cmd *qc)
2966 struct ata_port *ap = qc->ap;
2969 /* start host DMA transaction */
2970 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2971 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2973 /* Strictly, one may wish to issue an ioread8() here, to
2974 * flush the mmio write. However, control also passes
2975 * to the hardware at this point, and it will interrupt
2976 * us when we are to resume control. So, in effect,
2977 * we don't care when the mmio write flushes.
2978 * Further, a read of the DMA status register _immediately_
2979 * following the write may not be what certain flaky hardware
2980 * is expected, so I think it is best to not add a readb()
2981 * without first all the MMIO ATA cards/mobos.
2982 * Or maybe I'm just being paranoid.
2984 * FIXME: The posting of this write means I/O starts are
2985 * unnecessarily delayed for MMIO
2988 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2991 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2992 * @qc: Command we are ending DMA for
2994 * Clears the ATA_DMA_START flag in the dma control register
2996 * May be used as the bmdma_stop() entry in ata_port_operations.
2999 * spin_lock_irqsave(host lock)
3001 void ata_bmdma_stop(struct ata_queued_cmd *qc)
3003 struct ata_port *ap = qc->ap;
3004 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3006 /* clear start/stop bit */
3007 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3008 mmio + ATA_DMA_CMD);
3010 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3011 ata_sff_dma_pause(ap);
3013 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3016 * ata_bmdma_status - Read PCI IDE BMDMA status
3017 * @ap: Port associated with this ATA transaction.
3019 * Read and return BMDMA status register.
3021 * May be used as the bmdma_status() entry in ata_port_operations.
3024 * spin_lock_irqsave(host lock)
3026 u8 ata_bmdma_status(struct ata_port *ap)
3028 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3030 EXPORT_SYMBOL_GPL(ata_bmdma_status);
3034 * ata_bmdma_port_start - Set port up for bmdma.
3035 * @ap: Port to initialize
3037 * Called just after data structures for each port are
3038 * initialized. Allocates space for PRD table.
3040 * May be used as the port_start() entry in ata_port_operations.
3043 * Inherited from caller.
3045 int ata_bmdma_port_start(struct ata_port *ap)
3047 if (ap->mwdma_mask || ap->udma_mask) {
3049 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3050 &ap->bmdma_prd_dma, GFP_KERNEL);
3057 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3060 * ata_bmdma_port_start32 - Set port up for dma.
3061 * @ap: Port to initialize
3063 * Called just after data structures for each port are
3064 * initialized. Enables 32bit PIO and allocates space for PRD
3067 * May be used as the port_start() entry in ata_port_operations for
3068 * devices that are capable of 32bit PIO.
3071 * Inherited from caller.
3073 int ata_bmdma_port_start32(struct ata_port *ap)
3075 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3076 return ata_bmdma_port_start(ap);
3078 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3083 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3086 * Some PCI ATA devices report simplex mode but in fact can be told to
3087 * enter non simplex mode. This implements the necessary logic to
3088 * perform the task on such devices. Calling it on other devices will
3089 * have -undefined- behaviour.
3091 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3093 unsigned long bmdma = pci_resource_start(pdev, 4);
3099 simplex = inb(bmdma + 0x02);
3100 outb(simplex & 0x60, bmdma + 0x02);
3101 simplex = inb(bmdma + 0x02);
3106 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3108 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3112 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3114 for (i = 0; i < 2; i++) {
3115 host->ports[i]->mwdma_mask = 0;
3116 host->ports[i]->udma_mask = 0;
3121 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3122 * @host: target ATA host
3124 * Acquire PCI BMDMA resources and initialize @host accordingly.
3127 * Inherited from calling layer (may sleep).
3129 void ata_pci_bmdma_init(struct ata_host *host)
3131 struct device *gdev = host->dev;
3132 struct pci_dev *pdev = to_pci_dev(gdev);
3135 /* No BAR4 allocation: No DMA */
3136 if (pci_resource_start(pdev, 4) == 0) {
3137 ata_bmdma_nodma(host, "BAR4 is zero");
3142 * Some controllers require BMDMA region to be initialized
3143 * even if DMA is not in use to clear IRQ status via
3144 * ->sff_irq_clear method. Try to initialize bmdma_addr
3145 * regardless of dma masks.
3147 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
3149 ata_bmdma_nodma(host, "failed to set dma mask");
3151 /* request and iomap DMA region */
3152 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3154 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3157 host->iomap = pcim_iomap_table(pdev);
3159 for (i = 0; i < 2; i++) {
3160 struct ata_port *ap = host->ports[i];
3161 void __iomem *bmdma = host->iomap[4] + 8 * i;
3163 if (ata_port_is_dummy(ap))
3166 ap->ioaddr.bmdma_addr = bmdma;
3167 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3168 (ioread8(bmdma + 2) & 0x80))
3169 host->flags |= ATA_HOST_SIMPLEX;
3171 ata_port_desc(ap, "bmdma 0x%llx",
3172 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3175 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3178 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3179 * @pdev: target PCI device
3180 * @ppi: array of port_info, must be enough for two ports
3181 * @r_host: out argument for the initialized ATA host
3183 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3184 * resources and initialize it accordingly in one go.
3187 * Inherited from calling layer (may sleep).
3190 * 0 on success, -errno otherwise.
3192 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3193 const struct ata_port_info * const * ppi,
3194 struct ata_host **r_host)
3198 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3202 ata_pci_bmdma_init(*r_host);
3205 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3208 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3209 * @pdev: Controller to be initialized
3210 * @ppi: array of port_info, must be enough for two ports
3211 * @sht: scsi_host_template to use when registering the host
3212 * @host_priv: host private_data
3213 * @hflags: host flags
3215 * This function is similar to ata_pci_sff_init_one() but also
3216 * takes care of BMDMA initialization.
3219 * Inherited from PCI layer (may sleep).
3222 * Zero on success, negative on errno-based value on error.
3224 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3225 const struct ata_port_info * const * ppi,
3226 struct scsi_host_template *sht, void *host_priv,
3229 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3231 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3233 #endif /* CONFIG_PCI */
3234 #endif /* CONFIG_ATA_BMDMA */
3237 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3238 * @ap: Port to initialize
3240 * Called on port allocation to initialize SFF/BMDMA specific
3246 void ata_sff_port_init(struct ata_port *ap)
3248 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3249 ap->ctl = ATA_DEVCTL_OBS;
3250 ap->last_ctl = 0xFF;
3253 int __init ata_sff_init(void)
3255 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3262 void ata_sff_exit(void)
3264 destroy_workqueue(ata_sff_wq);