1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libahci.c - Common AHCI SATA low-level routines
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/bitops.h>
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/module.h>
23 #include <linux/nospec.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/device.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/pci.h>
36 static int ahci_skip_host_reset;
38 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask);
60 static int ahci_port_start(struct ata_port *ap);
61 static void ahci_port_stop(struct ata_port *ap);
62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
64 static void ahci_freeze(struct ata_port *ap);
65 static void ahci_thaw(struct ata_port *ap);
66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
67 static void ahci_enable_fbs(struct ata_port *ap);
68 static void ahci_disable_fbs(struct ata_port *ap);
69 static void ahci_pmp_attach(struct ata_port *ap);
70 static void ahci_pmp_detach(struct ata_port *ap);
71 static int ahci_softreset(struct ata_link *link, unsigned int *class,
72 unsigned long deadline);
73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
74 unsigned long deadline);
75 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
76 unsigned long deadline);
77 static void ahci_postreset(struct ata_link *link, unsigned int *class);
78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
79 static void ahci_dev_config(struct ata_device *dev);
81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
84 static ssize_t ahci_activity_store(struct ata_device *dev,
85 enum sw_activity val);
86 static void ahci_init_sw_activity(struct ata_link *link);
88 static ssize_t ahci_show_host_caps(struct device *dev,
89 struct device_attribute *attr, char *buf);
90 static ssize_t ahci_show_host_cap2(struct device *dev,
91 struct device_attribute *attr, char *buf);
92 static ssize_t ahci_show_host_version(struct device *dev,
93 struct device_attribute *attr, char *buf);
94 static ssize_t ahci_show_port_cmd(struct device *dev,
95 struct device_attribute *attr, char *buf);
96 static ssize_t ahci_read_em_buffer(struct device *dev,
97 struct device_attribute *attr, char *buf);
98 static ssize_t ahci_store_em_buffer(struct device *dev,
99 struct device_attribute *attr,
100 const char *buf, size_t size);
101 static ssize_t ahci_show_em_supported(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
110 ahci_read_em_buffer, ahci_store_em_buffer);
111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
113 static struct attribute *ahci_shost_attrs[] = {
114 &dev_attr_link_power_management_policy.attr,
115 &dev_attr_em_message_type.attr,
116 &dev_attr_em_message.attr,
117 &dev_attr_ahci_host_caps.attr,
118 &dev_attr_ahci_host_cap2.attr,
119 &dev_attr_ahci_host_version.attr,
120 &dev_attr_ahci_port_cmd.attr,
121 &dev_attr_em_buffer.attr,
122 &dev_attr_em_message_supported.attr,
126 static const struct attribute_group ahci_shost_attr_group = {
127 .attrs = ahci_shost_attrs
130 const struct attribute_group *ahci_shost_groups[] = {
131 &ahci_shost_attr_group,
134 EXPORT_SYMBOL_GPL(ahci_shost_groups);
136 static struct attribute *ahci_sdev_attrs[] = {
137 &dev_attr_sw_activity.attr,
138 &dev_attr_unload_heads.attr,
139 &dev_attr_ncq_prio_supported.attr,
140 &dev_attr_ncq_prio_enable.attr,
144 static const struct attribute_group ahci_sdev_attr_group = {
145 .attrs = ahci_sdev_attrs
148 const struct attribute_group *ahci_sdev_groups[] = {
149 &ahci_sdev_attr_group,
152 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
154 struct ata_port_operations ahci_ops = {
155 .inherits = &sata_pmp_port_ops,
157 .qc_defer = ahci_pmp_qc_defer,
158 .qc_prep = ahci_qc_prep,
159 .qc_issue = ahci_qc_issue,
160 .qc_fill_rtf = ahci_qc_fill_rtf,
161 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf,
163 .freeze = ahci_freeze,
165 .softreset = ahci_softreset,
166 .hardreset = ahci_hardreset,
167 .postreset = ahci_postreset,
168 .pmp_softreset = ahci_softreset,
169 .error_handler = ahci_error_handler,
170 .post_internal_cmd = ahci_post_internal_cmd,
171 .dev_config = ahci_dev_config,
173 .scr_read = ahci_scr_read,
174 .scr_write = ahci_scr_write,
175 .pmp_attach = ahci_pmp_attach,
176 .pmp_detach = ahci_pmp_detach,
178 .set_lpm = ahci_set_lpm,
179 .em_show = ahci_led_show,
180 .em_store = ahci_led_store,
181 .sw_activity_show = ahci_activity_show,
182 .sw_activity_store = ahci_activity_store,
183 .transmit_led_message = ahci_transmit_led_message,
185 .port_suspend = ahci_port_suspend,
186 .port_resume = ahci_port_resume,
188 .port_start = ahci_port_start,
189 .port_stop = ahci_port_stop,
191 EXPORT_SYMBOL_GPL(ahci_ops);
193 struct ata_port_operations ahci_pmp_retry_srst_ops = {
194 .inherits = &ahci_ops,
195 .softreset = ahci_pmp_retry_softreset,
197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
199 static bool ahci_em_messages __read_mostly = true;
200 module_param(ahci_em_messages, bool, 0444);
201 /* add other LED protocol types when they become supported */
202 MODULE_PARM_DESC(ahci_em_messages,
203 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
205 /* device sleep idle timeout in ms */
206 static int devslp_idle_timeout __read_mostly = 1000;
207 module_param(devslp_idle_timeout, int, 0644);
208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
210 static void ahci_enable_ahci(void __iomem *mmio)
215 /* turn on AHCI_EN */
216 tmp = readl(mmio + HOST_CTL);
217 if (tmp & HOST_AHCI_EN)
220 /* Some controllers need AHCI_EN to be written multiple times.
221 * Try a few times before giving up.
223 for (i = 0; i < 5; i++) {
225 writel(tmp, mmio + HOST_CTL);
226 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
227 if (tmp & HOST_AHCI_EN)
236 * ahci_rpm_get_port - Make sure the port is powered on
237 * @ap: Port to power on
239 * Whenever there is need to access the AHCI host registers outside of
240 * normal execution paths, call this function to make sure the host is
241 * actually powered on.
243 static int ahci_rpm_get_port(struct ata_port *ap)
245 return pm_runtime_get_sync(ap->dev);
249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
250 * @ap: Port to power down
252 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
253 * if it has no more active users.
255 static void ahci_rpm_put_port(struct ata_port *ap)
257 pm_runtime_put(ap->dev);
260 static ssize_t ahci_show_host_caps(struct device *dev,
261 struct device_attribute *attr, char *buf)
263 struct Scsi_Host *shost = class_to_shost(dev);
264 struct ata_port *ap = ata_shost_to_port(shost);
265 struct ahci_host_priv *hpriv = ap->host->private_data;
267 return sprintf(buf, "%x\n", hpriv->cap);
270 static ssize_t ahci_show_host_cap2(struct device *dev,
271 struct device_attribute *attr, char *buf)
273 struct Scsi_Host *shost = class_to_shost(dev);
274 struct ata_port *ap = ata_shost_to_port(shost);
275 struct ahci_host_priv *hpriv = ap->host->private_data;
277 return sprintf(buf, "%x\n", hpriv->cap2);
280 static ssize_t ahci_show_host_version(struct device *dev,
281 struct device_attribute *attr, char *buf)
283 struct Scsi_Host *shost = class_to_shost(dev);
284 struct ata_port *ap = ata_shost_to_port(shost);
285 struct ahci_host_priv *hpriv = ap->host->private_data;
287 return sprintf(buf, "%x\n", hpriv->version);
290 static ssize_t ahci_show_port_cmd(struct device *dev,
291 struct device_attribute *attr, char *buf)
293 struct Scsi_Host *shost = class_to_shost(dev);
294 struct ata_port *ap = ata_shost_to_port(shost);
295 void __iomem *port_mmio = ahci_port_base(ap);
298 ahci_rpm_get_port(ap);
299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
300 ahci_rpm_put_port(ap);
305 static ssize_t ahci_read_em_buffer(struct device *dev,
306 struct device_attribute *attr, char *buf)
308 struct Scsi_Host *shost = class_to_shost(dev);
309 struct ata_port *ap = ata_shost_to_port(shost);
310 struct ahci_host_priv *hpriv = ap->host->private_data;
311 void __iomem *mmio = hpriv->mmio;
312 void __iomem *em_mmio = mmio + hpriv->em_loc;
318 ahci_rpm_get_port(ap);
319 spin_lock_irqsave(ap->lock, flags);
321 em_ctl = readl(mmio + HOST_EM_CTL);
322 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
323 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
329 if (!(em_ctl & EM_CTL_MR)) {
330 spin_unlock_irqrestore(ap->lock, flags);
331 ahci_rpm_put_port(ap);
335 if (!(em_ctl & EM_CTL_SMB))
336 em_mmio += hpriv->em_buf_sz;
338 count = hpriv->em_buf_sz;
340 /* the count should not be larger than PAGE_SIZE */
341 if (count > PAGE_SIZE) {
342 if (printk_ratelimit())
344 "EM read buffer size too large: "
345 "buffer size %u, page size %lu\n",
346 hpriv->em_buf_sz, PAGE_SIZE);
350 for (i = 0; i < count; i += 4) {
351 msg = readl(em_mmio + i);
353 buf[i + 1] = (msg >> 8) & 0xff;
354 buf[i + 2] = (msg >> 16) & 0xff;
355 buf[i + 3] = (msg >> 24) & 0xff;
358 spin_unlock_irqrestore(ap->lock, flags);
359 ahci_rpm_put_port(ap);
364 static ssize_t ahci_store_em_buffer(struct device *dev,
365 struct device_attribute *attr,
366 const char *buf, size_t size)
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 void __iomem *em_mmio = mmio + hpriv->em_loc;
373 const unsigned char *msg_buf = buf;
378 /* check size validity */
379 if (!(ap->flags & ATA_FLAG_EM) ||
380 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
381 size % 4 || size > hpriv->em_buf_sz)
384 ahci_rpm_get_port(ap);
385 spin_lock_irqsave(ap->lock, flags);
387 em_ctl = readl(mmio + HOST_EM_CTL);
388 if (em_ctl & EM_CTL_TM) {
389 spin_unlock_irqrestore(ap->lock, flags);
390 ahci_rpm_put_port(ap);
394 for (i = 0; i < size; i += 4) {
395 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
396 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
397 writel(msg, em_mmio + i);
400 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
402 spin_unlock_irqrestore(ap->lock, flags);
403 ahci_rpm_put_port(ap);
408 static ssize_t ahci_show_em_supported(struct device *dev,
409 struct device_attribute *attr, char *buf)
411 struct Scsi_Host *shost = class_to_shost(dev);
412 struct ata_port *ap = ata_shost_to_port(shost);
413 struct ahci_host_priv *hpriv = ap->host->private_data;
414 void __iomem *mmio = hpriv->mmio;
417 ahci_rpm_get_port(ap);
418 em_ctl = readl(mmio + HOST_EM_CTL);
419 ahci_rpm_put_port(ap);
421 return sprintf(buf, "%s%s%s%s\n",
422 em_ctl & EM_CTL_LED ? "led " : "",
423 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
424 em_ctl & EM_CTL_SES ? "ses-2 " : "",
425 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
429 * ahci_save_initial_config - Save and fixup initial config values
430 * @dev: target AHCI device
431 * @hpriv: host private area to store config values
433 * Some registers containing configuration info might be setup by
434 * BIOS and might be cleared on reset. This function saves the
435 * initial values of those registers into @hpriv such that they
436 * can be restored after controller reset.
438 * If inconsistent, config values are fixed up by this function.
440 * If it is not set already this function sets hpriv->start_engine to
446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
448 void __iomem *mmio = hpriv->mmio;
449 void __iomem *port_mmio;
450 unsigned long port_map;
454 /* make sure AHCI mode is enabled before accessing CAP */
455 ahci_enable_ahci(mmio);
458 * Values prefixed with saved_ are written back to the HBA and ports
459 * registers after reset. Values without are used for driver operation.
463 * Override HW-init HBA capability fields with the platform-specific
464 * values. The rest of the HBA capabilities are defined as Read-only
465 * and can't be modified in CSR anyway.
467 cap = readl(mmio + HOST_CAP);
468 if (hpriv->saved_cap)
469 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
470 hpriv->saved_cap = cap;
472 /* CAP2 register is only defined for AHCI 1.2 and later */
473 vers = readl(mmio + HOST_VERSION);
474 if ((vers >> 16) > 1 ||
475 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
476 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
478 hpriv->saved_cap2 = cap2 = 0;
480 /* some chips have errata preventing 64bit use */
481 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
482 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
486 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
487 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
488 cap &= ~HOST_CAP_NCQ;
491 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
492 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
496 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
497 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
498 cap &= ~HOST_CAP_PMP;
501 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
503 "controller can't do SNTF, turning off CAP_SNTF\n");
504 cap &= ~HOST_CAP_SNTF;
507 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
509 "controller can't do DEVSLP, turning off\n");
510 cap2 &= ~HOST_CAP2_SDS;
511 cap2 &= ~HOST_CAP2_SADM;
514 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
515 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
519 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
520 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
521 cap &= ~HOST_CAP_FBS;
524 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
525 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
526 cap |= HOST_CAP_ALPM;
529 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
530 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
531 cap &= ~HOST_CAP_SXS;
534 /* Override the HBA ports mapping if the platform needs it */
535 port_map = readl(mmio + HOST_PORTS_IMPL);
536 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
537 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
538 port_map, hpriv->saved_port_map);
539 port_map = hpriv->saved_port_map;
541 hpriv->saved_port_map = port_map;
544 if (hpriv->mask_port_map) {
545 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
547 port_map & hpriv->mask_port_map);
548 port_map &= hpriv->mask_port_map;
551 /* cross check port_map and cap.n_ports */
555 for (i = 0; i < AHCI_MAX_PORTS; i++)
556 if (port_map & (1 << i))
559 /* If PI has more ports than n_ports, whine, clear
560 * port_map and let it be generated from n_ports.
562 if (map_ports > ahci_nr_ports(cap)) {
564 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
565 port_map, ahci_nr_ports(cap));
570 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
571 if (!port_map && vers < 0x10300) {
572 port_map = (1 << ahci_nr_ports(cap)) - 1;
573 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
575 /* write the fixed up value to the PI register */
576 hpriv->saved_port_map = port_map;
580 * Preserve the ports capabilities defined by the platform. Note there
581 * is no need in storing the rest of the P#.CMD fields since they are
584 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
585 if (hpriv->saved_port_cap[i])
588 port_mmio = __ahci_port_base(hpriv, i);
589 hpriv->saved_port_cap[i] =
590 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
593 /* record values to use during operation */
596 hpriv->version = vers;
597 hpriv->port_map = port_map;
599 if (!hpriv->start_engine)
600 hpriv->start_engine = ahci_start_engine;
602 if (!hpriv->stop_engine)
603 hpriv->stop_engine = ahci_stop_engine;
605 if (!hpriv->irq_handler)
606 hpriv->irq_handler = ahci_single_level_irq_intr;
608 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
611 * ahci_restore_initial_config - Restore initial config
612 * @host: target ATA host
614 * Restore initial config stored by ahci_save_initial_config().
619 static void ahci_restore_initial_config(struct ata_host *host)
621 struct ahci_host_priv *hpriv = host->private_data;
622 unsigned long port_map = hpriv->port_map;
623 void __iomem *mmio = hpriv->mmio;
624 void __iomem *port_mmio;
627 writel(hpriv->saved_cap, mmio + HOST_CAP);
628 if (hpriv->saved_cap2)
629 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
630 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
631 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
633 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
634 port_mmio = __ahci_port_base(hpriv, i);
635 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
639 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
641 static const int offset[] = {
642 [SCR_STATUS] = PORT_SCR_STAT,
643 [SCR_CONTROL] = PORT_SCR_CTL,
644 [SCR_ERROR] = PORT_SCR_ERR,
645 [SCR_ACTIVE] = PORT_SCR_ACT,
646 [SCR_NOTIFICATION] = PORT_SCR_NTF,
648 struct ahci_host_priv *hpriv = ap->host->private_data;
650 if (sc_reg < ARRAY_SIZE(offset) &&
651 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
652 return offset[sc_reg];
656 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
658 void __iomem *port_mmio = ahci_port_base(link->ap);
659 int offset = ahci_scr_offset(link->ap, sc_reg);
662 *val = readl(port_mmio + offset);
668 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
670 void __iomem *port_mmio = ahci_port_base(link->ap);
671 int offset = ahci_scr_offset(link->ap, sc_reg);
674 writel(val, port_mmio + offset);
680 void ahci_start_engine(struct ata_port *ap)
682 void __iomem *port_mmio = ahci_port_base(ap);
686 tmp = readl(port_mmio + PORT_CMD);
687 tmp |= PORT_CMD_START;
688 writel(tmp, port_mmio + PORT_CMD);
689 readl(port_mmio + PORT_CMD); /* flush */
691 EXPORT_SYMBOL_GPL(ahci_start_engine);
693 int ahci_stop_engine(struct ata_port *ap)
695 void __iomem *port_mmio = ahci_port_base(ap);
696 struct ahci_host_priv *hpriv = ap->host->private_data;
700 * On some controllers, stopping a port's DMA engine while the port
701 * is in ALPM state (partial or slumber) results in failures on
702 * subsequent DMA engine starts. For those controllers, put the
703 * port back in active state before stopping its DMA engine.
705 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
706 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
707 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
708 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
712 tmp = readl(port_mmio + PORT_CMD);
714 /* check if the HBA is idle */
715 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
719 * Don't try to issue commands but return with ENODEV if the
720 * AHCI controller not available anymore (e.g. due to PCIe hot
721 * unplugging). Otherwise a 500ms delay for each port is added.
723 if (tmp == 0xffffffff) {
724 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
728 /* setting HBA to idle */
729 tmp &= ~PORT_CMD_START;
730 writel(tmp, port_mmio + PORT_CMD);
732 /* wait for engine to stop. This could be as long as 500 msec */
733 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
734 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
735 if (tmp & PORT_CMD_LIST_ON)
740 EXPORT_SYMBOL_GPL(ahci_stop_engine);
742 void ahci_start_fis_rx(struct ata_port *ap)
744 void __iomem *port_mmio = ahci_port_base(ap);
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 struct ahci_port_priv *pp = ap->private_data;
749 /* set FIS registers */
750 if (hpriv->cap & HOST_CAP_64)
751 writel((pp->cmd_slot_dma >> 16) >> 16,
752 port_mmio + PORT_LST_ADDR_HI);
753 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
755 if (hpriv->cap & HOST_CAP_64)
756 writel((pp->rx_fis_dma >> 16) >> 16,
757 port_mmio + PORT_FIS_ADDR_HI);
758 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
760 /* enable FIS reception */
761 tmp = readl(port_mmio + PORT_CMD);
762 tmp |= PORT_CMD_FIS_RX;
763 writel(tmp, port_mmio + PORT_CMD);
766 readl(port_mmio + PORT_CMD);
768 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
770 static int ahci_stop_fis_rx(struct ata_port *ap)
772 void __iomem *port_mmio = ahci_port_base(ap);
775 /* disable FIS reception */
776 tmp = readl(port_mmio + PORT_CMD);
777 tmp &= ~PORT_CMD_FIS_RX;
778 writel(tmp, port_mmio + PORT_CMD);
780 /* wait for completion, spec says 500ms, give it 1000 */
781 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
782 PORT_CMD_FIS_ON, 10, 1000);
783 if (tmp & PORT_CMD_FIS_ON)
789 static void ahci_power_up(struct ata_port *ap)
791 struct ahci_host_priv *hpriv = ap->host->private_data;
792 void __iomem *port_mmio = ahci_port_base(ap);
795 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
798 if (hpriv->cap & HOST_CAP_SSS) {
799 cmd |= PORT_CMD_SPIN_UP;
800 writel(cmd, port_mmio + PORT_CMD);
804 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
807 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
810 struct ata_port *ap = link->ap;
811 struct ahci_host_priv *hpriv = ap->host->private_data;
812 struct ahci_port_priv *pp = ap->private_data;
813 void __iomem *port_mmio = ahci_port_base(ap);
815 if (policy != ATA_LPM_MAX_POWER) {
816 /* wakeup flag only applies to the max power policy */
817 hints &= ~ATA_LPM_WAKE_ONLY;
820 * Disable interrupts on Phy Ready. This keeps us from
821 * getting woken up due to spurious phy ready
824 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
825 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
827 sata_link_scr_lpm(link, policy, false);
830 if (hpriv->cap & HOST_CAP_ALPM) {
831 u32 cmd = readl(port_mmio + PORT_CMD);
833 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
834 if (!(hints & ATA_LPM_WAKE_ONLY))
835 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
836 cmd |= PORT_CMD_ICC_ACTIVE;
838 writel(cmd, port_mmio + PORT_CMD);
839 readl(port_mmio + PORT_CMD);
841 /* wait 10ms to be sure we've come out of LPM state */
844 if (hints & ATA_LPM_WAKE_ONLY)
847 cmd |= PORT_CMD_ALPE;
848 if (policy == ATA_LPM_MIN_POWER)
850 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
851 cmd &= ~PORT_CMD_ASP;
853 /* write out new cmd value */
854 writel(cmd, port_mmio + PORT_CMD);
858 /* set aggressive device sleep */
859 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
860 (hpriv->cap2 & HOST_CAP2_SADM) &&
861 (link->device->flags & ATA_DFLAG_DEVSLP)) {
862 if (policy == ATA_LPM_MIN_POWER ||
863 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
864 ahci_set_aggressive_devslp(ap, true);
866 ahci_set_aggressive_devslp(ap, false);
869 if (policy == ATA_LPM_MAX_POWER) {
870 sata_link_scr_lpm(link, policy, false);
872 /* turn PHYRDY IRQ back on */
873 pp->intr_mask |= PORT_IRQ_PHYRDY;
874 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
881 static void ahci_power_down(struct ata_port *ap)
883 struct ahci_host_priv *hpriv = ap->host->private_data;
884 void __iomem *port_mmio = ahci_port_base(ap);
887 if (!(hpriv->cap & HOST_CAP_SSS))
890 /* put device into listen mode, first set PxSCTL.DET to 0 */
891 scontrol = readl(port_mmio + PORT_SCR_CTL);
893 writel(scontrol, port_mmio + PORT_SCR_CTL);
895 /* then set PxCMD.SUD to 0 */
896 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
897 cmd &= ~PORT_CMD_SPIN_UP;
898 writel(cmd, port_mmio + PORT_CMD);
902 static void ahci_start_port(struct ata_port *ap)
904 struct ahci_host_priv *hpriv = ap->host->private_data;
905 struct ahci_port_priv *pp = ap->private_data;
906 struct ata_link *link;
907 struct ahci_em_priv *emp;
911 /* enable FIS reception */
912 ahci_start_fis_rx(ap);
915 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
916 hpriv->start_engine(ap);
919 if (ap->flags & ATA_FLAG_EM) {
920 ata_for_each_link(link, ap, EDGE) {
921 emp = &pp->em_priv[link->pmp];
923 /* EM Transmit bit maybe busy during init */
924 for (i = 0; i < EM_MAX_RETRY; i++) {
925 rc = ap->ops->transmit_led_message(ap,
929 * If busy, give a breather but do not
930 * release EH ownership by using msleep()
931 * instead of ata_msleep(). EM Transmit
932 * bit is busy for the whole host and
933 * releasing ownership will cause other
934 * ports to fail the same way.
944 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
945 ata_for_each_link(link, ap, EDGE)
946 ahci_init_sw_activity(link);
950 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
953 struct ahci_host_priv *hpriv = ap->host->private_data;
956 rc = hpriv->stop_engine(ap);
958 *emsg = "failed to stop engine";
962 /* disable FIS reception */
963 rc = ahci_stop_fis_rx(ap);
965 *emsg = "failed stop FIS RX";
972 int ahci_reset_controller(struct ata_host *host)
974 struct ahci_host_priv *hpriv = host->private_data;
975 void __iomem *mmio = hpriv->mmio;
978 /* we must be in AHCI mode, before using anything
979 * AHCI-specific, such as HOST_RESET.
981 ahci_enable_ahci(mmio);
983 /* global controller reset */
984 if (!ahci_skip_host_reset) {
985 tmp = readl(mmio + HOST_CTL);
986 if ((tmp & HOST_RESET) == 0) {
987 writel(tmp | HOST_RESET, mmio + HOST_CTL);
988 readl(mmio + HOST_CTL); /* flush */
992 * to perform host reset, OS should set HOST_RESET
993 * and poll until this bit is read to be "0".
994 * reset must complete within 1 second, or
995 * the hardware should be considered fried.
997 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
998 HOST_RESET, 10, 1000);
1000 if (tmp & HOST_RESET) {
1001 dev_err(host->dev, "controller reset failed (0x%x)\n",
1006 /* turn on AHCI mode */
1007 ahci_enable_ahci(mmio);
1009 /* Some registers might be cleared on reset. Restore
1012 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
1013 ahci_restore_initial_config(host);
1015 dev_info(host->dev, "skipping global host reset\n");
1019 EXPORT_SYMBOL_GPL(ahci_reset_controller);
1021 static void ahci_sw_activity(struct ata_link *link)
1023 struct ata_port *ap = link->ap;
1024 struct ahci_port_priv *pp = ap->private_data;
1025 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1027 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1031 if (!timer_pending(&emp->timer))
1032 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1035 static void ahci_sw_activity_blink(struct timer_list *t)
1037 struct ahci_em_priv *emp = from_timer(emp, t, timer);
1038 struct ata_link *link = emp->link;
1039 struct ata_port *ap = link->ap;
1041 unsigned long led_message = emp->led_state;
1042 u32 activity_led_state;
1043 unsigned long flags;
1045 led_message &= EM_MSG_LED_VALUE;
1046 led_message |= ap->port_no | (link->pmp << 8);
1048 /* check to see if we've had activity. If so,
1049 * toggle state of LED and reset timer. If not,
1050 * turn LED to desired idle state.
1052 spin_lock_irqsave(ap->lock, flags);
1053 if (emp->saved_activity != emp->activity) {
1054 emp->saved_activity = emp->activity;
1055 /* get the current LED state */
1056 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1058 if (activity_led_state)
1059 activity_led_state = 0;
1061 activity_led_state = 1;
1063 /* clear old state */
1064 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1067 led_message |= (activity_led_state << 16);
1068 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1070 /* switch to idle */
1071 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1072 if (emp->blink_policy == BLINK_OFF)
1073 led_message |= (1 << 16);
1075 spin_unlock_irqrestore(ap->lock, flags);
1076 ap->ops->transmit_led_message(ap, led_message, 4);
1079 static void ahci_init_sw_activity(struct ata_link *link)
1081 struct ata_port *ap = link->ap;
1082 struct ahci_port_priv *pp = ap->private_data;
1083 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1085 /* init activity stats, setup timer */
1086 emp->saved_activity = emp->activity = 0;
1088 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1090 /* check our blink policy and set flag for link if it's enabled */
1091 if (emp->blink_policy)
1092 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1095 int ahci_reset_em(struct ata_host *host)
1097 struct ahci_host_priv *hpriv = host->private_data;
1098 void __iomem *mmio = hpriv->mmio;
1101 em_ctl = readl(mmio + HOST_EM_CTL);
1102 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1105 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1108 EXPORT_SYMBOL_GPL(ahci_reset_em);
1110 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1113 struct ahci_host_priv *hpriv = ap->host->private_data;
1114 struct ahci_port_priv *pp = ap->private_data;
1115 void __iomem *mmio = hpriv->mmio;
1117 u32 message[] = {0, 0};
1118 unsigned long flags;
1120 struct ahci_em_priv *emp;
1122 /* get the slot number from the message */
1123 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1124 if (pmp < EM_MAX_SLOTS)
1125 emp = &pp->em_priv[pmp];
1129 ahci_rpm_get_port(ap);
1130 spin_lock_irqsave(ap->lock, flags);
1133 * if we are still busy transmitting a previous message,
1136 em_ctl = readl(mmio + HOST_EM_CTL);
1137 if (em_ctl & EM_CTL_TM) {
1138 spin_unlock_irqrestore(ap->lock, flags);
1139 ahci_rpm_put_port(ap);
1143 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1145 * create message header - this is all zero except for
1146 * the message size, which is 4 bytes.
1148 message[0] |= (4 << 8);
1150 /* ignore 0:4 of byte zero, fill in port info yourself */
1151 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1153 /* write message to EM_LOC */
1154 writel(message[0], mmio + hpriv->em_loc);
1155 writel(message[1], mmio + hpriv->em_loc+4);
1158 * tell hardware to transmit the message
1160 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1163 /* save off new led state for port/slot */
1164 emp->led_state = state;
1166 spin_unlock_irqrestore(ap->lock, flags);
1167 ahci_rpm_put_port(ap);
1172 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1174 struct ahci_port_priv *pp = ap->private_data;
1175 struct ata_link *link;
1176 struct ahci_em_priv *emp;
1179 ata_for_each_link(link, ap, EDGE) {
1180 emp = &pp->em_priv[link->pmp];
1181 rc += sprintf(buf, "%lx\n", emp->led_state);
1186 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1191 struct ahci_port_priv *pp = ap->private_data;
1192 struct ahci_em_priv *emp;
1194 if (kstrtouint(buf, 0, &state) < 0)
1197 /* get the slot number from the message */
1198 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1199 if (pmp < EM_MAX_SLOTS) {
1200 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1201 emp = &pp->em_priv[pmp];
1206 /* mask off the activity bits if we are in sw_activity
1207 * mode, user should turn off sw_activity before setting
1208 * activity led through em_message
1210 if (emp->blink_policy)
1211 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1213 return ap->ops->transmit_led_message(ap, state, size);
1216 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1218 struct ata_link *link = dev->link;
1219 struct ata_port *ap = link->ap;
1220 struct ahci_port_priv *pp = ap->private_data;
1221 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1222 u32 port_led_state = emp->led_state;
1224 /* save the desired Activity LED behavior */
1227 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1229 /* set the LED to OFF */
1230 port_led_state &= EM_MSG_LED_VALUE_OFF;
1231 port_led_state |= (ap->port_no | (link->pmp << 8));
1232 ap->ops->transmit_led_message(ap, port_led_state, 4);
1234 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1235 if (val == BLINK_OFF) {
1236 /* set LED to ON for idle */
1237 port_led_state &= EM_MSG_LED_VALUE_OFF;
1238 port_led_state |= (ap->port_no | (link->pmp << 8));
1239 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1240 ap->ops->transmit_led_message(ap, port_led_state, 4);
1243 emp->blink_policy = val;
1247 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1249 struct ata_link *link = dev->link;
1250 struct ata_port *ap = link->ap;
1251 struct ahci_port_priv *pp = ap->private_data;
1252 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1254 /* display the saved value of activity behavior for this
1257 return sprintf(buf, "%d\n", emp->blink_policy);
1260 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1261 int port_no, void __iomem *mmio,
1262 void __iomem *port_mmio)
1264 struct ahci_host_priv *hpriv = ap->host->private_data;
1265 const char *emsg = NULL;
1269 /* make sure port is not active */
1270 rc = ahci_deinit_port(ap, &emsg);
1272 dev_warn(dev, "%s (%d)\n", emsg, rc);
1275 tmp = readl(port_mmio + PORT_SCR_ERR);
1276 dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
1277 writel(tmp, port_mmio + PORT_SCR_ERR);
1279 /* clear port IRQ */
1280 tmp = readl(port_mmio + PORT_IRQ_STAT);
1281 dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1283 writel(tmp, port_mmio + PORT_IRQ_STAT);
1285 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1287 /* mark esata ports */
1288 tmp = readl(port_mmio + PORT_CMD);
1289 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1290 ap->pflags |= ATA_PFLAG_EXTERNAL;
1293 void ahci_init_controller(struct ata_host *host)
1295 struct ahci_host_priv *hpriv = host->private_data;
1296 void __iomem *mmio = hpriv->mmio;
1298 void __iomem *port_mmio;
1301 for (i = 0; i < host->n_ports; i++) {
1302 struct ata_port *ap = host->ports[i];
1304 port_mmio = ahci_port_base(ap);
1305 if (ata_port_is_dummy(ap))
1308 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1311 tmp = readl(mmio + HOST_CTL);
1312 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1313 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1314 tmp = readl(mmio + HOST_CTL);
1315 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1317 EXPORT_SYMBOL_GPL(ahci_init_controller);
1319 static void ahci_dev_config(struct ata_device *dev)
1321 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1323 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1324 dev->max_sectors = 255;
1326 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1330 unsigned int ahci_dev_classify(struct ata_port *ap)
1332 void __iomem *port_mmio = ahci_port_base(ap);
1333 struct ata_taskfile tf;
1336 tmp = readl(port_mmio + PORT_SIG);
1337 tf.lbah = (tmp >> 24) & 0xff;
1338 tf.lbam = (tmp >> 16) & 0xff;
1339 tf.lbal = (tmp >> 8) & 0xff;
1340 tf.nsect = (tmp) & 0xff;
1342 return ata_port_classify(ap, &tf);
1344 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1346 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1349 dma_addr_t cmd_tbl_dma;
1351 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1353 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1354 pp->cmd_slot[tag].status = 0;
1355 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1356 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1358 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1360 int ahci_kick_engine(struct ata_port *ap)
1362 void __iomem *port_mmio = ahci_port_base(ap);
1363 struct ahci_host_priv *hpriv = ap->host->private_data;
1364 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1369 rc = hpriv->stop_engine(ap);
1374 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1376 busy = status & (ATA_BUSY | ATA_DRQ);
1377 if (!busy && !sata_pmp_attached(ap)) {
1382 if (!(hpriv->cap & HOST_CAP_CLO)) {
1388 tmp = readl(port_mmio + PORT_CMD);
1389 tmp |= PORT_CMD_CLO;
1390 writel(tmp, port_mmio + PORT_CMD);
1393 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1394 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1395 if (tmp & PORT_CMD_CLO)
1398 /* restart engine */
1400 hpriv->start_engine(ap);
1403 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1405 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1406 struct ata_taskfile *tf, int is_cmd, u16 flags,
1407 unsigned long timeout_msec)
1409 const u32 cmd_fis_len = 5; /* five dwords */
1410 struct ahci_port_priv *pp = ap->private_data;
1411 void __iomem *port_mmio = ahci_port_base(ap);
1412 u8 *fis = pp->cmd_tbl;
1415 /* prep the command */
1416 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1417 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1419 /* set port value for softreset of Port Multiplier */
1420 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1421 tmp = readl(port_mmio + PORT_FBS);
1422 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1423 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1424 writel(tmp, port_mmio + PORT_FBS);
1425 pp->fbs_last_dev = pmp;
1429 writel(1, port_mmio + PORT_CMD_ISSUE);
1432 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1433 0x1, 0x1, 1, timeout_msec);
1435 ahci_kick_engine(ap);
1439 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1444 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1445 int pmp, unsigned long deadline,
1446 int (*check_ready)(struct ata_link *link))
1448 struct ata_port *ap = link->ap;
1449 struct ahci_host_priv *hpriv = ap->host->private_data;
1450 struct ahci_port_priv *pp = ap->private_data;
1451 const char *reason = NULL;
1452 unsigned long now, msecs;
1453 struct ata_taskfile tf;
1454 bool fbs_disabled = false;
1457 /* prepare for SRST (AHCI-1.1 10.4.1) */
1458 rc = ahci_kick_engine(ap);
1459 if (rc && rc != -EOPNOTSUPP)
1460 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1463 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1464 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1465 * that is attached to port multiplier.
1467 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1468 ahci_disable_fbs(ap);
1469 fbs_disabled = true;
1472 ata_tf_init(link->device, &tf);
1474 /* issue the first H2D Register FIS */
1477 if (time_after(deadline, now))
1478 msecs = jiffies_to_msecs(deadline - now);
1481 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1482 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1484 reason = "1st FIS failed";
1488 /* spec says at least 5us, but be generous and sleep for 1ms */
1491 /* issue the second H2D Register FIS */
1492 tf.ctl &= ~ATA_SRST;
1493 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1495 /* wait for link to become ready */
1496 rc = ata_wait_after_reset(link, deadline, check_ready);
1497 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1499 * Workaround for cases where link online status can't
1500 * be trusted. Treat device readiness timeout as link
1503 ata_link_info(link, "device not ready, treating as offline\n");
1504 *class = ATA_DEV_NONE;
1506 /* link occupied, -ENODEV too is an error */
1507 reason = "device not ready";
1510 *class = ahci_dev_classify(ap);
1512 /* re-enable FBS if disabled before */
1514 ahci_enable_fbs(ap);
1519 ata_link_err(link, "softreset failed (%s)\n", reason);
1523 int ahci_check_ready(struct ata_link *link)
1525 void __iomem *port_mmio = ahci_port_base(link->ap);
1526 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1528 return ata_check_ready(status);
1530 EXPORT_SYMBOL_GPL(ahci_check_ready);
1532 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1533 unsigned long deadline)
1535 int pmp = sata_srst_pmp(link);
1537 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1539 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1541 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1543 void __iomem *port_mmio = ahci_port_base(link->ap);
1544 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1545 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1548 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1549 * which can save timeout delay.
1551 if (irq_status & PORT_IRQ_BAD_PMP)
1554 return ata_check_ready(status);
1557 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1558 unsigned long deadline)
1560 struct ata_port *ap = link->ap;
1561 void __iomem *port_mmio = ahci_port_base(ap);
1562 int pmp = sata_srst_pmp(link);
1566 rc = ahci_do_softreset(link, class, pmp, deadline,
1567 ahci_bad_pmp_check_ready);
1570 * Soft reset fails with IPMS set when PMP is enabled but
1571 * SATA HDD/ODD is connected to SATA port, do soft reset
1575 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1576 if (irq_sts & PORT_IRQ_BAD_PMP) {
1578 "applying PMP SRST workaround "
1580 rc = ahci_do_softreset(link, class, 0, deadline,
1588 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1589 unsigned long deadline, bool *online)
1591 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1592 struct ata_port *ap = link->ap;
1593 struct ahci_port_priv *pp = ap->private_data;
1594 struct ahci_host_priv *hpriv = ap->host->private_data;
1595 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1596 struct ata_taskfile tf;
1599 hpriv->stop_engine(ap);
1601 /* clear D2H reception area to properly wait for D2H FIS */
1602 ata_tf_init(link->device, &tf);
1603 tf.status = ATA_BUSY;
1604 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1606 rc = sata_link_hardreset(link, timing, deadline, online,
1609 hpriv->start_engine(ap);
1612 *class = ahci_dev_classify(ap);
1616 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1618 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1619 unsigned long deadline)
1623 return ahci_do_hardreset(link, class, deadline, &online);
1626 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1628 struct ata_port *ap = link->ap;
1629 void __iomem *port_mmio = ahci_port_base(ap);
1632 ata_std_postreset(link, class);
1634 /* Make sure port's ATAPI bit is set appropriately */
1635 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1636 if (*class == ATA_DEV_ATAPI)
1637 new_tmp |= PORT_CMD_ATAPI;
1639 new_tmp &= ~PORT_CMD_ATAPI;
1640 if (new_tmp != tmp) {
1641 writel(new_tmp, port_mmio + PORT_CMD);
1642 readl(port_mmio + PORT_CMD); /* flush */
1646 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1648 struct scatterlist *sg;
1649 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1653 * Next, the S/G list.
1655 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1656 dma_addr_t addr = sg_dma_address(sg);
1657 u32 sg_len = sg_dma_len(sg);
1659 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1660 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1661 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1667 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1669 struct ata_port *ap = qc->ap;
1670 struct ahci_port_priv *pp = ap->private_data;
1672 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1673 return ata_std_qc_defer(qc);
1675 return sata_pmp_qc_defer_cmd_switch(qc);
1678 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1680 struct ata_port *ap = qc->ap;
1681 struct ahci_port_priv *pp = ap->private_data;
1682 int is_atapi = ata_is_atapi(qc->tf.protocol);
1685 const u32 cmd_fis_len = 5; /* five dwords */
1686 unsigned int n_elem;
1689 * Fill in command table information. First, the header,
1690 * a SATA Register - Host to Device command FIS.
1692 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1694 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1696 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1697 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1701 if (qc->flags & ATA_QCFLAG_DMAMAP)
1702 n_elem = ahci_fill_sg(qc, cmd_tbl);
1705 * Fill in command slot information.
1707 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1708 if (qc->tf.flags & ATA_TFLAG_WRITE)
1709 opts |= AHCI_CMD_WRITE;
1711 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1713 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1718 static void ahci_fbs_dec_intr(struct ata_port *ap)
1720 struct ahci_port_priv *pp = ap->private_data;
1721 void __iomem *port_mmio = ahci_port_base(ap);
1722 u32 fbs = readl(port_mmio + PORT_FBS);
1725 BUG_ON(!pp->fbs_enabled);
1727 /* time to wait for DEC is not specified by AHCI spec,
1728 * add a retry loop for safety.
1730 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1731 fbs = readl(port_mmio + PORT_FBS);
1732 while ((fbs & PORT_FBS_DEC) && retries--) {
1734 fbs = readl(port_mmio + PORT_FBS);
1737 if (fbs & PORT_FBS_DEC)
1738 dev_err(ap->host->dev, "failed to clear device error\n");
1741 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1743 struct ahci_host_priv *hpriv = ap->host->private_data;
1744 struct ahci_port_priv *pp = ap->private_data;
1745 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1746 struct ata_link *link = NULL;
1747 struct ata_queued_cmd *active_qc;
1748 struct ata_eh_info *active_ehi;
1749 bool fbs_need_dec = false;
1752 /* determine active link with error */
1753 if (pp->fbs_enabled) {
1754 void __iomem *port_mmio = ahci_port_base(ap);
1755 u32 fbs = readl(port_mmio + PORT_FBS);
1756 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1758 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1759 link = &ap->pmp_link[pmp];
1760 fbs_need_dec = true;
1764 ata_for_each_link(link, ap, EDGE)
1765 if (ata_link_active(link))
1771 active_qc = ata_qc_from_tag(ap, link->active_tag);
1772 active_ehi = &link->eh_info;
1774 /* record irq stat */
1775 ata_ehi_clear_desc(host_ehi);
1776 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1778 /* AHCI needs SError cleared; otherwise, it might lock up */
1779 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1780 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1781 host_ehi->serror |= serror;
1783 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1784 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1785 irq_stat &= ~PORT_IRQ_IF_ERR;
1787 if (irq_stat & PORT_IRQ_TF_ERR) {
1788 /* If qc is active, charge it; otherwise, the active
1789 * link. There's no active qc on NCQ errors. It will
1790 * be determined by EH by reading log page 10h.
1793 active_qc->err_mask |= AC_ERR_DEV;
1795 active_ehi->err_mask |= AC_ERR_DEV;
1797 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1798 host_ehi->serror &= ~SERR_INTERNAL;
1801 if (irq_stat & PORT_IRQ_UNK_FIS) {
1802 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1804 active_ehi->err_mask |= AC_ERR_HSM;
1805 active_ehi->action |= ATA_EH_RESET;
1806 ata_ehi_push_desc(active_ehi,
1807 "unknown FIS %08x %08x %08x %08x" ,
1808 unk[0], unk[1], unk[2], unk[3]);
1811 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1812 active_ehi->err_mask |= AC_ERR_HSM;
1813 active_ehi->action |= ATA_EH_RESET;
1814 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1817 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1818 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1819 host_ehi->action |= ATA_EH_RESET;
1820 ata_ehi_push_desc(host_ehi, "host bus error");
1823 if (irq_stat & PORT_IRQ_IF_ERR) {
1825 active_ehi->err_mask |= AC_ERR_DEV;
1827 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1828 host_ehi->action |= ATA_EH_RESET;
1831 ata_ehi_push_desc(host_ehi, "interface fatal error");
1834 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1835 ata_ehi_hotplugged(host_ehi);
1836 ata_ehi_push_desc(host_ehi, "%s",
1837 irq_stat & PORT_IRQ_CONNECT ?
1838 "connection status changed" : "PHY RDY changed");
1841 /* okay, let's hand over to EH */
1843 if (irq_stat & PORT_IRQ_FREEZE)
1844 ata_port_freeze(ap);
1845 else if (fbs_need_dec) {
1846 ata_link_abort(link);
1847 ahci_fbs_dec_intr(ap);
1852 static void ahci_handle_port_interrupt(struct ata_port *ap,
1853 void __iomem *port_mmio, u32 status)
1855 struct ata_eh_info *ehi = &ap->link.eh_info;
1856 struct ahci_port_priv *pp = ap->private_data;
1857 struct ahci_host_priv *hpriv = ap->host->private_data;
1858 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1862 /* ignore BAD_PMP while resetting */
1863 if (unlikely(resetting))
1864 status &= ~PORT_IRQ_BAD_PMP;
1866 if (sata_lpm_ignore_phy_events(&ap->link)) {
1867 status &= ~PORT_IRQ_PHYRDY;
1868 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1871 if (unlikely(status & PORT_IRQ_ERROR)) {
1872 ahci_error_intr(ap, status);
1876 if (status & PORT_IRQ_SDB_FIS) {
1877 /* If SNotification is available, leave notification
1878 * handling to sata_async_notification(). If not,
1879 * emulate it by snooping SDB FIS RX area.
1881 * Snooping FIS RX area is probably cheaper than
1882 * poking SNotification but some constrollers which
1883 * implement SNotification, ICH9 for example, don't
1884 * store AN SDB FIS into receive area.
1886 if (hpriv->cap & HOST_CAP_SNTF)
1887 sata_async_notification(ap);
1889 /* If the 'N' bit in word 0 of the FIS is set,
1890 * we just received asynchronous notification.
1891 * Tell libata about it.
1893 * Lack of SNotification should not appear in
1894 * ahci 1.2, so the workaround is unnecessary
1895 * when FBS is enabled.
1897 if (pp->fbs_enabled)
1900 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1901 u32 f0 = le32_to_cpu(f[0]);
1903 sata_async_notification(ap);
1908 /* pp->active_link is not reliable once FBS is enabled, both
1909 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1910 * NCQ and non-NCQ commands may be in flight at the same time.
1912 if (pp->fbs_enabled) {
1913 if (ap->qc_active) {
1914 qc_active = readl(port_mmio + PORT_SCR_ACT);
1915 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1918 /* pp->active_link is valid iff any command is in flight */
1919 if (ap->qc_active && pp->active_link->sactive)
1920 qc_active = readl(port_mmio + PORT_SCR_ACT);
1922 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1926 rc = ata_qc_complete_multiple(ap, qc_active);
1928 /* while resetting, invalid completions are expected */
1929 if (unlikely(rc < 0 && !resetting)) {
1930 ehi->err_mask |= AC_ERR_HSM;
1931 ehi->action |= ATA_EH_RESET;
1932 ata_port_freeze(ap);
1936 static void ahci_port_intr(struct ata_port *ap)
1938 void __iomem *port_mmio = ahci_port_base(ap);
1941 status = readl(port_mmio + PORT_IRQ_STAT);
1942 writel(status, port_mmio + PORT_IRQ_STAT);
1944 ahci_handle_port_interrupt(ap, port_mmio, status);
1947 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1949 struct ata_port *ap = dev_instance;
1950 void __iomem *port_mmio = ahci_port_base(ap);
1953 status = readl(port_mmio + PORT_IRQ_STAT);
1954 writel(status, port_mmio + PORT_IRQ_STAT);
1956 spin_lock(ap->lock);
1957 ahci_handle_port_interrupt(ap, port_mmio, status);
1958 spin_unlock(ap->lock);
1963 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1965 unsigned int i, handled = 0;
1967 for (i = 0; i < host->n_ports; i++) {
1968 struct ata_port *ap;
1970 if (!(irq_masked & (1 << i)))
1973 ap = host->ports[i];
1977 if (ata_ratelimit())
1979 "interrupt on disabled port %u\n", i);
1987 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1989 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1991 struct ata_host *host = dev_instance;
1992 struct ahci_host_priv *hpriv;
1993 unsigned int rc = 0;
1995 u32 irq_stat, irq_masked;
1997 hpriv = host->private_data;
2000 /* sigh. 0xffffffff is a valid return from h/w */
2001 irq_stat = readl(mmio + HOST_IRQ_STAT);
2005 irq_masked = irq_stat & hpriv->port_map;
2007 spin_lock(&host->lock);
2009 rc = ahci_handle_port_intr(host, irq_masked);
2011 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2012 * it should be cleared after all the port events are cleared;
2013 * otherwise, it will raise a spurious interrupt after each
2014 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2017 * Also, use the unmasked value to clear interrupt as spurious
2018 * pending event on a dummy port might cause screaming IRQ.
2020 writel(irq_stat, mmio + HOST_IRQ_STAT);
2022 spin_unlock(&host->lock);
2024 return IRQ_RETVAL(rc);
2027 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2029 struct ata_port *ap = qc->ap;
2030 void __iomem *port_mmio = ahci_port_base(ap);
2031 struct ahci_port_priv *pp = ap->private_data;
2033 /* Keep track of the currently active link. It will be used
2034 * in completion path to determine whether NCQ phase is in
2037 pp->active_link = qc->dev->link;
2039 if (ata_is_ncq(qc->tf.protocol))
2040 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2042 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2043 u32 fbs = readl(port_mmio + PORT_FBS);
2044 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2045 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2046 writel(fbs, port_mmio + PORT_FBS);
2047 pp->fbs_last_dev = qc->dev->link->pmp;
2050 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2052 ahci_sw_activity(qc->dev->link);
2056 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2058 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2060 struct ahci_port_priv *pp = qc->ap->private_data;
2061 u8 *rx_fis = pp->rx_fis;
2064 * rtf may already be filled (e.g. for successful NCQ commands).
2065 * If that is the case, we have nothing to do.
2067 if (qc->flags & ATA_QCFLAG_RTF_FILLED)
2070 if (pp->fbs_enabled)
2071 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2074 * After a successful execution of an ATA PIO data-in command,
2075 * the device doesn't send D2H Reg FIS to update the TF and
2076 * the host should take TF and E_Status from the preceding PIO
2079 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2080 !(qc->flags & ATA_QCFLAG_EH)) {
2081 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2082 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
2083 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2088 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register
2089 * FIS area of the Received FIS Structure (which contains a copy of the
2090 * last D2H FIS received) will contain an outdated status code.
2091 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
2092 * instead. However, the SDB FIS does not contain the LBA, so we can't
2093 * use the ata_tf_from_fis() helper.
2095 if (ata_is_ncq(qc->tf.protocol)) {
2096 const u8 *fis = rx_fis + RX_FIS_SDB;
2099 * Successful NCQ commands have been filled already.
2100 * A failed NCQ command will read the status here.
2101 * (Note that a failed NCQ command will get a more specific
2102 * error when reading the NCQ Command Error log.)
2104 qc->result_tf.status = fis[2];
2105 qc->result_tf.error = fis[3];
2106 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2110 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2111 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2114 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask)
2116 struct ahci_port_priv *pp = ap->private_data;
2119 /* No outstanding commands. */
2124 * FBS not enabled, so read status and error once, since they are shared
2127 if (!pp->fbs_enabled) {
2130 /* No outstanding NCQ commands. */
2131 if (!pp->active_link->sactive)
2134 fis = pp->rx_fis + RX_FIS_SDB;
2139 struct ata_queued_cmd *qc;
2140 unsigned int tag = __ffs64(done_mask);
2142 qc = ata_qc_from_tag(ap, tag);
2143 if (qc && ata_is_ncq(qc->tf.protocol)) {
2144 qc->result_tf.status = status;
2145 qc->result_tf.error = error;
2146 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2148 done_mask &= ~(1ULL << tag);
2155 * FBS enabled, so read the status and error for each QC, since the QCs
2156 * can belong to different PMP links. (Each PMP link has its own FIS
2160 struct ata_queued_cmd *qc;
2161 unsigned int tag = __ffs64(done_mask);
2163 qc = ata_qc_from_tag(ap, tag);
2164 if (qc && ata_is_ncq(qc->tf.protocol)) {
2166 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2168 qc->result_tf.status = fis[2];
2169 qc->result_tf.error = fis[3];
2170 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2172 done_mask &= ~(1ULL << tag);
2176 static void ahci_freeze(struct ata_port *ap)
2178 void __iomem *port_mmio = ahci_port_base(ap);
2181 writel(0, port_mmio + PORT_IRQ_MASK);
2184 static void ahci_thaw(struct ata_port *ap)
2186 struct ahci_host_priv *hpriv = ap->host->private_data;
2187 void __iomem *mmio = hpriv->mmio;
2188 void __iomem *port_mmio = ahci_port_base(ap);
2190 struct ahci_port_priv *pp = ap->private_data;
2193 tmp = readl(port_mmio + PORT_IRQ_STAT);
2194 writel(tmp, port_mmio + PORT_IRQ_STAT);
2195 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2197 /* turn IRQ back on */
2198 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2201 void ahci_error_handler(struct ata_port *ap)
2203 struct ahci_host_priv *hpriv = ap->host->private_data;
2205 if (!ata_port_is_frozen(ap)) {
2206 /* restart engine */
2207 hpriv->stop_engine(ap);
2208 hpriv->start_engine(ap);
2211 sata_pmp_error_handler(ap);
2213 if (!ata_dev_enabled(ap->link.device))
2214 hpriv->stop_engine(ap);
2216 EXPORT_SYMBOL_GPL(ahci_error_handler);
2218 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2220 struct ata_port *ap = qc->ap;
2222 /* make DMA engine forget about the failed command */
2223 if (qc->flags & ATA_QCFLAG_EH)
2224 ahci_kick_engine(ap);
2227 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2229 struct ahci_host_priv *hpriv = ap->host->private_data;
2230 void __iomem *port_mmio = ahci_port_base(ap);
2231 struct ata_device *dev = ap->link.device;
2232 u32 devslp, dm, dito, mdat, deto, dito_conf;
2234 unsigned int err_mask;
2236 devslp = readl(port_mmio + PORT_DEVSLP);
2237 if (!(devslp & PORT_DEVSLP_DSP)) {
2238 dev_info(ap->host->dev, "port does not support device sleep\n");
2242 /* disable device sleep */
2244 if (devslp & PORT_DEVSLP_ADSE) {
2245 writel(devslp & ~PORT_DEVSLP_ADSE,
2246 port_mmio + PORT_DEVSLP);
2247 err_mask = ata_dev_set_feature(dev,
2248 SETFEATURES_SATA_DISABLE,
2250 if (err_mask && err_mask != AC_ERR_DEV)
2251 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2256 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2257 dito = devslp_idle_timeout / (dm + 1);
2261 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2263 /* device sleep was already enabled and same dito */
2264 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2267 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2268 rc = hpriv->stop_engine(ap);
2272 /* Use the nominal value 10 ms if the read MDAT is zero,
2273 * the nominal value of DETO is 20 ms.
2275 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2276 ATA_LOG_DEVSLP_VALID_MASK) {
2277 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2278 ATA_LOG_DEVSLP_MDAT_MASK;
2281 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2289 /* Make dito, mdat, deto bits to 0s */
2290 devslp &= ~GENMASK_ULL(24, 2);
2291 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2292 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2293 (deto << PORT_DEVSLP_DETO_OFFSET) |
2295 writel(devslp, port_mmio + PORT_DEVSLP);
2297 hpriv->start_engine(ap);
2299 /* enable device sleep feature for the drive */
2300 err_mask = ata_dev_set_feature(dev,
2301 SETFEATURES_SATA_ENABLE,
2303 if (err_mask && err_mask != AC_ERR_DEV)
2304 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2307 static void ahci_enable_fbs(struct ata_port *ap)
2309 struct ahci_host_priv *hpriv = ap->host->private_data;
2310 struct ahci_port_priv *pp = ap->private_data;
2311 void __iomem *port_mmio = ahci_port_base(ap);
2315 if (!pp->fbs_supported)
2318 fbs = readl(port_mmio + PORT_FBS);
2319 if (fbs & PORT_FBS_EN) {
2320 pp->fbs_enabled = true;
2321 pp->fbs_last_dev = -1; /* initialization */
2325 rc = hpriv->stop_engine(ap);
2329 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2330 fbs = readl(port_mmio + PORT_FBS);
2331 if (fbs & PORT_FBS_EN) {
2332 dev_info(ap->host->dev, "FBS is enabled\n");
2333 pp->fbs_enabled = true;
2334 pp->fbs_last_dev = -1; /* initialization */
2336 dev_err(ap->host->dev, "Failed to enable FBS\n");
2338 hpriv->start_engine(ap);
2341 static void ahci_disable_fbs(struct ata_port *ap)
2343 struct ahci_host_priv *hpriv = ap->host->private_data;
2344 struct ahci_port_priv *pp = ap->private_data;
2345 void __iomem *port_mmio = ahci_port_base(ap);
2349 if (!pp->fbs_supported)
2352 fbs = readl(port_mmio + PORT_FBS);
2353 if ((fbs & PORT_FBS_EN) == 0) {
2354 pp->fbs_enabled = false;
2358 rc = hpriv->stop_engine(ap);
2362 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2363 fbs = readl(port_mmio + PORT_FBS);
2364 if (fbs & PORT_FBS_EN)
2365 dev_err(ap->host->dev, "Failed to disable FBS\n");
2367 dev_info(ap->host->dev, "FBS is disabled\n");
2368 pp->fbs_enabled = false;
2371 hpriv->start_engine(ap);
2374 static void ahci_pmp_attach(struct ata_port *ap)
2376 void __iomem *port_mmio = ahci_port_base(ap);
2377 struct ahci_port_priv *pp = ap->private_data;
2380 cmd = readl(port_mmio + PORT_CMD);
2381 cmd |= PORT_CMD_PMP;
2382 writel(cmd, port_mmio + PORT_CMD);
2384 ahci_enable_fbs(ap);
2386 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2389 * We must not change the port interrupt mask register if the
2390 * port is marked frozen, the value in pp->intr_mask will be
2391 * restored later when the port is thawed.
2393 * Note that during initialization, the port is marked as
2394 * frozen since the irq handler is not yet registered.
2396 if (!ata_port_is_frozen(ap))
2397 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2400 static void ahci_pmp_detach(struct ata_port *ap)
2402 void __iomem *port_mmio = ahci_port_base(ap);
2403 struct ahci_port_priv *pp = ap->private_data;
2406 ahci_disable_fbs(ap);
2408 cmd = readl(port_mmio + PORT_CMD);
2409 cmd &= ~PORT_CMD_PMP;
2410 writel(cmd, port_mmio + PORT_CMD);
2412 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2414 /* see comment above in ahci_pmp_attach() */
2415 if (!ata_port_is_frozen(ap))
2416 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2419 int ahci_port_resume(struct ata_port *ap)
2421 ahci_rpm_get_port(ap);
2424 ahci_start_port(ap);
2426 if (sata_pmp_attached(ap))
2427 ahci_pmp_attach(ap);
2429 ahci_pmp_detach(ap);
2433 EXPORT_SYMBOL_GPL(ahci_port_resume);
2436 static void ahci_handle_s2idle(struct ata_port *ap)
2438 void __iomem *port_mmio = ahci_port_base(ap);
2441 if (pm_suspend_via_firmware())
2443 devslp = readl(port_mmio + PORT_DEVSLP);
2444 if ((devslp & PORT_DEVSLP_ADSE))
2445 ata_msleep(ap, devslp_idle_timeout);
2448 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2450 const char *emsg = NULL;
2453 rc = ahci_deinit_port(ap, &emsg);
2455 ahci_power_down(ap);
2457 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2458 ata_port_freeze(ap);
2461 if (acpi_storage_d3(ap->host->dev))
2462 ahci_handle_s2idle(ap);
2464 ahci_rpm_put_port(ap);
2469 static int ahci_port_start(struct ata_port *ap)
2471 struct ahci_host_priv *hpriv = ap->host->private_data;
2472 struct device *dev = ap->host->dev;
2473 struct ahci_port_priv *pp;
2476 size_t dma_sz, rx_fis_sz;
2478 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2482 if (ap->host->n_ports > 1) {
2483 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2484 if (!pp->irq_desc) {
2485 devm_kfree(dev, pp);
2488 snprintf(pp->irq_desc, 8,
2489 "%s%d", dev_driver_string(dev), ap->port_no);
2492 /* check FBS capability */
2493 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2494 void __iomem *port_mmio = ahci_port_base(ap);
2495 u32 cmd = readl(port_mmio + PORT_CMD);
2496 if (cmd & PORT_CMD_FBSCP)
2497 pp->fbs_supported = true;
2498 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2499 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2501 pp->fbs_supported = true;
2503 dev_warn(dev, "port %d is not capable of FBS\n",
2507 if (pp->fbs_supported) {
2508 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2509 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2511 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2512 rx_fis_sz = AHCI_RX_FIS_SZ;
2515 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2520 * First item in chunk of DMA memory: 32-slot command table,
2521 * 32 bytes each in size
2524 pp->cmd_slot_dma = mem_dma;
2526 mem += AHCI_CMD_SLOT_SZ;
2527 mem_dma += AHCI_CMD_SLOT_SZ;
2530 * Second item: Received-FIS area
2533 pp->rx_fis_dma = mem_dma;
2536 mem_dma += rx_fis_sz;
2539 * Third item: data area for storing a single command
2540 * and its scatter-gather table
2543 pp->cmd_tbl_dma = mem_dma;
2546 * Save off initial list of interrupts to be enabled.
2547 * This could be changed later
2549 pp->intr_mask = DEF_PORT_IRQ;
2552 * Switch to per-port locking in case each port has its own MSI vector.
2554 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2555 spin_lock_init(&pp->lock);
2556 ap->lock = &pp->lock;
2559 ap->private_data = pp;
2561 /* engage engines, captain */
2562 return ahci_port_resume(ap);
2565 static void ahci_port_stop(struct ata_port *ap)
2567 const char *emsg = NULL;
2568 struct ahci_host_priv *hpriv = ap->host->private_data;
2569 void __iomem *host_mmio = hpriv->mmio;
2572 /* de-initialize port */
2573 rc = ahci_deinit_port(ap, &emsg);
2575 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2578 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2581 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2583 ahci_rpm_put_port(ap);
2586 void ahci_print_info(struct ata_host *host, const char *scc_s)
2588 struct ahci_host_priv *hpriv = host->private_data;
2589 u32 vers, cap, cap2, impl, speed;
2590 const char *speed_s;
2592 vers = hpriv->version;
2595 impl = hpriv->port_map;
2597 speed = (cap >> 20) & 0xf;
2600 else if (speed == 2)
2602 else if (speed == 3)
2608 "AHCI %02x%02x.%02x%02x "
2609 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2612 (vers >> 24) & 0xff,
2613 (vers >> 16) & 0xff,
2617 ((cap >> 8) & 0x1f) + 1,
2631 cap & HOST_CAP_64 ? "64bit " : "",
2632 cap & HOST_CAP_NCQ ? "ncq " : "",
2633 cap & HOST_CAP_SNTF ? "sntf " : "",
2634 cap & HOST_CAP_MPS ? "ilck " : "",
2635 cap & HOST_CAP_SSS ? "stag " : "",
2636 cap & HOST_CAP_ALPM ? "pm " : "",
2637 cap & HOST_CAP_LED ? "led " : "",
2638 cap & HOST_CAP_CLO ? "clo " : "",
2639 cap & HOST_CAP_ONLY ? "only " : "",
2640 cap & HOST_CAP_PMP ? "pmp " : "",
2641 cap & HOST_CAP_FBS ? "fbs " : "",
2642 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2643 cap & HOST_CAP_SSC ? "slum " : "",
2644 cap & HOST_CAP_PART ? "part " : "",
2645 cap & HOST_CAP_CCC ? "ccc " : "",
2646 cap & HOST_CAP_EMS ? "ems " : "",
2647 cap & HOST_CAP_SXS ? "sxs " : "",
2648 cap2 & HOST_CAP2_DESO ? "deso " : "",
2649 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2650 cap2 & HOST_CAP2_SDS ? "sds " : "",
2651 cap2 & HOST_CAP2_APST ? "apst " : "",
2652 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2653 cap2 & HOST_CAP2_BOH ? "boh " : ""
2656 EXPORT_SYMBOL_GPL(ahci_print_info);
2658 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2659 struct ata_port_info *pi)
2662 void __iomem *mmio = hpriv->mmio;
2663 u32 em_loc = readl(mmio + HOST_EM_LOC);
2664 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2666 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2669 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2673 hpriv->em_loc = ((em_loc >> 16) * 4);
2674 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2675 hpriv->em_msg_type = messages;
2676 pi->flags |= ATA_FLAG_EM;
2677 if (!(em_ctl & EM_CTL_ALHD))
2678 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2681 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2683 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2684 struct scsi_host_template *sht)
2686 struct ahci_host_priv *hpriv = host->private_data;
2689 rc = ata_host_start(host);
2693 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2694 * allocated. That is one MSI per port, starting from @irq.
2696 for (i = 0; i < host->n_ports; i++) {
2697 struct ahci_port_priv *pp = host->ports[i]->private_data;
2698 int irq = hpriv->get_irq_vector(host, i);
2700 /* Do not receive interrupts sent by dummy ports */
2706 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2707 0, pp->irq_desc, host->ports[i]);
2711 ata_port_desc(host->ports[i], "irq %d", irq);
2714 return ata_host_register(host, sht);
2718 * ahci_host_activate - start AHCI host, request IRQs and register it
2719 * @host: target ATA host
2720 * @sht: scsi_host_template to use when registering the host
2723 * Inherited from calling layer (may sleep).
2726 * 0 on success, -errno otherwise.
2728 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2730 struct ahci_host_priv *hpriv = host->private_data;
2731 int irq = hpriv->irq;
2734 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2735 if (hpriv->irq_handler &&
2736 hpriv->irq_handler != ahci_single_level_irq_intr)
2738 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2739 if (!hpriv->get_irq_vector) {
2741 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2745 rc = ahci_host_activate_multi_irqs(host, sht);
2747 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2754 EXPORT_SYMBOL_GPL(ahci_host_activate);
2756 MODULE_AUTHOR("Jeff Garzik");
2757 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2758 MODULE_LICENSE("GPL");