2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
50 static int ahci_skip_host_reset;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_error_handler(struct ata_port *ap);
93 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
94 static void ahci_dev_config(struct ata_device *dev);
96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99 static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101 static void ahci_init_sw_activity(struct ata_link *link);
103 static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_read_em_buffer(struct device *dev,
112 struct device_attribute *attr, char *buf);
113 static ssize_t ahci_store_em_buffer(struct device *dev,
114 struct device_attribute *attr,
115 const char *buf, size_t size);
116 static ssize_t ahci_show_em_supported(struct device *dev,
117 struct device_attribute *attr, char *buf);
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
136 &dev_attr_em_message_supported,
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
156 .freeze = ahci_freeze,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 .transmit_led_message = ahci_transmit_led_message,
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
184 EXPORT_SYMBOL_GPL(ahci_ops);
186 struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192 static bool ahci_em_messages __read_mostly = true;
193 EXPORT_SYMBOL_GPL(ahci_em_messages);
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204 static void ahci_enable_ahci(void __iomem *mmio)
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
217 for (i = 0; i < 5; i++) {
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
229 static ssize_t ahci_show_host_caps(struct device *dev,
230 struct device_attribute *attr, char *buf)
232 struct Scsi_Host *shost = class_to_shost(dev);
233 struct ata_port *ap = ata_shost_to_port(shost);
234 struct ahci_host_priv *hpriv = ap->host->private_data;
236 return sprintf(buf, "%x\n", hpriv->cap);
239 static ssize_t ahci_show_host_cap2(struct device *dev,
240 struct device_attribute *attr, char *buf)
242 struct Scsi_Host *shost = class_to_shost(dev);
243 struct ata_port *ap = ata_shost_to_port(shost);
244 struct ahci_host_priv *hpriv = ap->host->private_data;
246 return sprintf(buf, "%x\n", hpriv->cap2);
249 static ssize_t ahci_show_host_version(struct device *dev,
250 struct device_attribute *attr, char *buf)
252 struct Scsi_Host *shost = class_to_shost(dev);
253 struct ata_port *ap = ata_shost_to_port(shost);
254 struct ahci_host_priv *hpriv = ap->host->private_data;
255 void __iomem *mmio = hpriv->mmio;
257 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
260 static ssize_t ahci_show_port_cmd(struct device *dev,
261 struct device_attribute *attr, char *buf)
263 struct Scsi_Host *shost = class_to_shost(dev);
264 struct ata_port *ap = ata_shost_to_port(shost);
265 void __iomem *port_mmio = ahci_port_base(ap);
267 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
270 static ssize_t ahci_read_em_buffer(struct device *dev,
271 struct device_attribute *attr, char *buf)
273 struct Scsi_Host *shost = class_to_shost(dev);
274 struct ata_port *ap = ata_shost_to_port(shost);
275 struct ahci_host_priv *hpriv = ap->host->private_data;
276 void __iomem *mmio = hpriv->mmio;
277 void __iomem *em_mmio = mmio + hpriv->em_loc;
283 spin_lock_irqsave(ap->lock, flags);
285 em_ctl = readl(mmio + HOST_EM_CTL);
286 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
287 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
288 spin_unlock_irqrestore(ap->lock, flags);
292 if (!(em_ctl & EM_CTL_MR)) {
293 spin_unlock_irqrestore(ap->lock, flags);
297 if (!(em_ctl & EM_CTL_SMB))
298 em_mmio += hpriv->em_buf_sz;
300 count = hpriv->em_buf_sz;
302 /* the count should not be larger than PAGE_SIZE */
303 if (count > PAGE_SIZE) {
304 if (printk_ratelimit())
306 "EM read buffer size too large: "
307 "buffer size %u, page size %lu\n",
308 hpriv->em_buf_sz, PAGE_SIZE);
312 for (i = 0; i < count; i += 4) {
313 msg = readl(em_mmio + i);
315 buf[i + 1] = (msg >> 8) & 0xff;
316 buf[i + 2] = (msg >> 16) & 0xff;
317 buf[i + 3] = (msg >> 24) & 0xff;
320 spin_unlock_irqrestore(ap->lock, flags);
325 static ssize_t ahci_store_em_buffer(struct device *dev,
326 struct device_attribute *attr,
327 const char *buf, size_t size)
329 struct Scsi_Host *shost = class_to_shost(dev);
330 struct ata_port *ap = ata_shost_to_port(shost);
331 struct ahci_host_priv *hpriv = ap->host->private_data;
332 void __iomem *mmio = hpriv->mmio;
333 void __iomem *em_mmio = mmio + hpriv->em_loc;
334 const unsigned char *msg_buf = buf;
339 /* check size validity */
340 if (!(ap->flags & ATA_FLAG_EM) ||
341 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
342 size % 4 || size > hpriv->em_buf_sz)
345 spin_lock_irqsave(ap->lock, flags);
347 em_ctl = readl(mmio + HOST_EM_CTL);
348 if (em_ctl & EM_CTL_TM) {
349 spin_unlock_irqrestore(ap->lock, flags);
353 for (i = 0; i < size; i += 4) {
354 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
355 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
356 writel(msg, em_mmio + i);
359 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
361 spin_unlock_irqrestore(ap->lock, flags);
366 static ssize_t ahci_show_em_supported(struct device *dev,
367 struct device_attribute *attr, char *buf)
369 struct Scsi_Host *shost = class_to_shost(dev);
370 struct ata_port *ap = ata_shost_to_port(shost);
371 struct ahci_host_priv *hpriv = ap->host->private_data;
372 void __iomem *mmio = hpriv->mmio;
375 em_ctl = readl(mmio + HOST_EM_CTL);
377 return sprintf(buf, "%s%s%s%s\n",
378 em_ctl & EM_CTL_LED ? "led " : "",
379 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
380 em_ctl & EM_CTL_SES ? "ses-2 " : "",
381 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
385 * ahci_save_initial_config - Save and fixup initial config values
386 * @dev: target AHCI device
387 * @hpriv: host private area to store config values
388 * @force_port_map: force port map to a specified value
389 * @mask_port_map: mask out particular bits from port map
391 * Some registers containing configuration info might be setup by
392 * BIOS and might be cleared on reset. This function saves the
393 * initial values of those registers into @hpriv such that they
394 * can be restored after controller reset.
396 * If inconsistent, config values are fixed up by this function.
401 void ahci_save_initial_config(struct device *dev,
402 struct ahci_host_priv *hpriv,
403 unsigned int force_port_map,
404 unsigned int mask_port_map)
406 void __iomem *mmio = hpriv->mmio;
407 u32 cap, cap2, vers, port_map;
410 /* make sure AHCI mode is enabled before accessing CAP */
411 ahci_enable_ahci(mmio);
413 /* Values prefixed with saved_ are written back to host after
414 * reset. Values without are used for driver operation.
416 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
417 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
419 /* CAP2 register is only defined for AHCI 1.2 and later */
420 vers = readl(mmio + HOST_VERSION);
421 if ((vers >> 16) > 1 ||
422 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
423 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
425 hpriv->saved_cap2 = cap2 = 0;
427 /* some chips have errata preventing 64bit use */
428 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
429 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
433 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
434 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
435 cap &= ~HOST_CAP_NCQ;
438 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
439 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
443 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
444 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
445 cap &= ~HOST_CAP_PMP;
448 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
450 "controller can't do SNTF, turning off CAP_SNTF\n");
451 cap &= ~HOST_CAP_SNTF;
454 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
455 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
459 if (force_port_map && port_map != force_port_map) {
460 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
461 port_map, force_port_map);
462 port_map = force_port_map;
466 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
468 port_map & mask_port_map);
469 port_map &= mask_port_map;
472 /* cross check port_map and cap.n_ports */
476 for (i = 0; i < AHCI_MAX_PORTS; i++)
477 if (port_map & (1 << i))
480 /* If PI has more ports than n_ports, whine, clear
481 * port_map and let it be generated from n_ports.
483 if (map_ports > ahci_nr_ports(cap)) {
485 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
486 port_map, ahci_nr_ports(cap));
491 /* fabricate port_map from cap.nr_ports */
493 port_map = (1 << ahci_nr_ports(cap)) - 1;
494 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
496 /* write the fixed up value to the PI register */
497 hpriv->saved_port_map = port_map;
500 /* record values to use during operation */
503 hpriv->port_map = port_map;
505 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
508 * ahci_restore_initial_config - Restore initial config
509 * @host: target ATA host
511 * Restore initial config stored by ahci_save_initial_config().
516 static void ahci_restore_initial_config(struct ata_host *host)
518 struct ahci_host_priv *hpriv = host->private_data;
519 void __iomem *mmio = hpriv->mmio;
521 writel(hpriv->saved_cap, mmio + HOST_CAP);
522 if (hpriv->saved_cap2)
523 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
524 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
525 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
528 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
530 static const int offset[] = {
531 [SCR_STATUS] = PORT_SCR_STAT,
532 [SCR_CONTROL] = PORT_SCR_CTL,
533 [SCR_ERROR] = PORT_SCR_ERR,
534 [SCR_ACTIVE] = PORT_SCR_ACT,
535 [SCR_NOTIFICATION] = PORT_SCR_NTF,
537 struct ahci_host_priv *hpriv = ap->host->private_data;
539 if (sc_reg < ARRAY_SIZE(offset) &&
540 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
541 return offset[sc_reg];
545 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
547 void __iomem *port_mmio = ahci_port_base(link->ap);
548 int offset = ahci_scr_offset(link->ap, sc_reg);
551 *val = readl(port_mmio + offset);
557 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
559 void __iomem *port_mmio = ahci_port_base(link->ap);
560 int offset = ahci_scr_offset(link->ap, sc_reg);
563 writel(val, port_mmio + offset);
569 void ahci_start_engine(struct ata_port *ap)
571 void __iomem *port_mmio = ahci_port_base(ap);
575 tmp = readl(port_mmio + PORT_CMD);
576 tmp |= PORT_CMD_START;
577 writel(tmp, port_mmio + PORT_CMD);
578 readl(port_mmio + PORT_CMD); /* flush */
580 EXPORT_SYMBOL_GPL(ahci_start_engine);
582 int ahci_stop_engine(struct ata_port *ap)
584 void __iomem *port_mmio = ahci_port_base(ap);
587 tmp = readl(port_mmio + PORT_CMD);
589 /* check if the HBA is idle */
590 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
593 /* setting HBA to idle */
594 tmp &= ~PORT_CMD_START;
595 writel(tmp, port_mmio + PORT_CMD);
597 /* wait for engine to stop. This could be as long as 500 msec */
598 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
599 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
600 if (tmp & PORT_CMD_LIST_ON)
605 EXPORT_SYMBOL_GPL(ahci_stop_engine);
607 static void ahci_start_fis_rx(struct ata_port *ap)
609 void __iomem *port_mmio = ahci_port_base(ap);
610 struct ahci_host_priv *hpriv = ap->host->private_data;
611 struct ahci_port_priv *pp = ap->private_data;
614 /* set FIS registers */
615 if (hpriv->cap & HOST_CAP_64)
616 writel((pp->cmd_slot_dma >> 16) >> 16,
617 port_mmio + PORT_LST_ADDR_HI);
618 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
620 if (hpriv->cap & HOST_CAP_64)
621 writel((pp->rx_fis_dma >> 16) >> 16,
622 port_mmio + PORT_FIS_ADDR_HI);
623 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
625 /* enable FIS reception */
626 tmp = readl(port_mmio + PORT_CMD);
627 tmp |= PORT_CMD_FIS_RX;
628 writel(tmp, port_mmio + PORT_CMD);
631 readl(port_mmio + PORT_CMD);
634 static int ahci_stop_fis_rx(struct ata_port *ap)
636 void __iomem *port_mmio = ahci_port_base(ap);
639 /* disable FIS reception */
640 tmp = readl(port_mmio + PORT_CMD);
641 tmp &= ~PORT_CMD_FIS_RX;
642 writel(tmp, port_mmio + PORT_CMD);
644 /* wait for completion, spec says 500ms, give it 1000 */
645 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
646 PORT_CMD_FIS_ON, 10, 1000);
647 if (tmp & PORT_CMD_FIS_ON)
653 static void ahci_power_up(struct ata_port *ap)
655 struct ahci_host_priv *hpriv = ap->host->private_data;
656 void __iomem *port_mmio = ahci_port_base(ap);
659 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
662 if (hpriv->cap & HOST_CAP_SSS) {
663 cmd |= PORT_CMD_SPIN_UP;
664 writel(cmd, port_mmio + PORT_CMD);
668 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
671 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
674 struct ata_port *ap = link->ap;
675 struct ahci_host_priv *hpriv = ap->host->private_data;
676 struct ahci_port_priv *pp = ap->private_data;
677 void __iomem *port_mmio = ahci_port_base(ap);
679 if (policy != ATA_LPM_MAX_POWER) {
681 * Disable interrupts on Phy Ready. This keeps us from
682 * getting woken up due to spurious phy ready
685 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
686 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
688 sata_link_scr_lpm(link, policy, false);
691 if (hpriv->cap & HOST_CAP_ALPM) {
692 u32 cmd = readl(port_mmio + PORT_CMD);
694 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
695 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
696 cmd |= PORT_CMD_ICC_ACTIVE;
698 writel(cmd, port_mmio + PORT_CMD);
699 readl(port_mmio + PORT_CMD);
701 /* wait 10ms to be sure we've come out of LPM state */
704 cmd |= PORT_CMD_ALPE;
705 if (policy == ATA_LPM_MIN_POWER)
708 /* write out new cmd value */
709 writel(cmd, port_mmio + PORT_CMD);
713 /* set aggressive device sleep */
714 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
715 (hpriv->cap2 & HOST_CAP2_SADM) &&
716 (link->device->flags & ATA_DFLAG_DEVSLP)) {
717 if (policy == ATA_LPM_MIN_POWER)
718 ahci_set_aggressive_devslp(ap, true);
720 ahci_set_aggressive_devslp(ap, false);
723 if (policy == ATA_LPM_MAX_POWER) {
724 sata_link_scr_lpm(link, policy, false);
726 /* turn PHYRDY IRQ back on */
727 pp->intr_mask |= PORT_IRQ_PHYRDY;
728 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
735 static void ahci_power_down(struct ata_port *ap)
737 struct ahci_host_priv *hpriv = ap->host->private_data;
738 void __iomem *port_mmio = ahci_port_base(ap);
741 if (!(hpriv->cap & HOST_CAP_SSS))
744 /* put device into listen mode, first set PxSCTL.DET to 0 */
745 scontrol = readl(port_mmio + PORT_SCR_CTL);
747 writel(scontrol, port_mmio + PORT_SCR_CTL);
749 /* then set PxCMD.SUD to 0 */
750 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
751 cmd &= ~PORT_CMD_SPIN_UP;
752 writel(cmd, port_mmio + PORT_CMD);
756 static void ahci_start_port(struct ata_port *ap)
758 struct ahci_host_priv *hpriv = ap->host->private_data;
759 struct ahci_port_priv *pp = ap->private_data;
760 struct ata_link *link;
761 struct ahci_em_priv *emp;
765 /* enable FIS reception */
766 ahci_start_fis_rx(ap);
769 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
770 ahci_start_engine(ap);
773 if (ap->flags & ATA_FLAG_EM) {
774 ata_for_each_link(link, ap, EDGE) {
775 emp = &pp->em_priv[link->pmp];
777 /* EM Transmit bit maybe busy during init */
778 for (i = 0; i < EM_MAX_RETRY; i++) {
779 rc = ap->ops->transmit_led_message(ap,
790 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
791 ata_for_each_link(link, ap, EDGE)
792 ahci_init_sw_activity(link);
796 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
801 rc = ahci_stop_engine(ap);
803 *emsg = "failed to stop engine";
807 /* disable FIS reception */
808 rc = ahci_stop_fis_rx(ap);
810 *emsg = "failed stop FIS RX";
817 int ahci_reset_controller(struct ata_host *host)
819 struct ahci_host_priv *hpriv = host->private_data;
820 void __iomem *mmio = hpriv->mmio;
823 /* we must be in AHCI mode, before using anything
824 * AHCI-specific, such as HOST_RESET.
826 ahci_enable_ahci(mmio);
828 /* global controller reset */
829 if (!ahci_skip_host_reset) {
830 tmp = readl(mmio + HOST_CTL);
831 if ((tmp & HOST_RESET) == 0) {
832 writel(tmp | HOST_RESET, mmio + HOST_CTL);
833 readl(mmio + HOST_CTL); /* flush */
837 * to perform host reset, OS should set HOST_RESET
838 * and poll until this bit is read to be "0".
839 * reset must complete within 1 second, or
840 * the hardware should be considered fried.
842 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
843 HOST_RESET, 10, 1000);
845 if (tmp & HOST_RESET) {
846 dev_err(host->dev, "controller reset failed (0x%x)\n",
851 /* turn on AHCI mode */
852 ahci_enable_ahci(mmio);
854 /* Some registers might be cleared on reset. Restore
857 ahci_restore_initial_config(host);
859 dev_info(host->dev, "skipping global host reset\n");
863 EXPORT_SYMBOL_GPL(ahci_reset_controller);
865 static void ahci_sw_activity(struct ata_link *link)
867 struct ata_port *ap = link->ap;
868 struct ahci_port_priv *pp = ap->private_data;
869 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
871 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
875 if (!timer_pending(&emp->timer))
876 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
879 static void ahci_sw_activity_blink(unsigned long arg)
881 struct ata_link *link = (struct ata_link *)arg;
882 struct ata_port *ap = link->ap;
883 struct ahci_port_priv *pp = ap->private_data;
884 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
885 unsigned long led_message = emp->led_state;
886 u32 activity_led_state;
889 led_message &= EM_MSG_LED_VALUE;
890 led_message |= ap->port_no | (link->pmp << 8);
892 /* check to see if we've had activity. If so,
893 * toggle state of LED and reset timer. If not,
894 * turn LED to desired idle state.
896 spin_lock_irqsave(ap->lock, flags);
897 if (emp->saved_activity != emp->activity) {
898 emp->saved_activity = emp->activity;
899 /* get the current LED state */
900 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
902 if (activity_led_state)
903 activity_led_state = 0;
905 activity_led_state = 1;
907 /* clear old state */
908 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
911 led_message |= (activity_led_state << 16);
912 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
915 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
916 if (emp->blink_policy == BLINK_OFF)
917 led_message |= (1 << 16);
919 spin_unlock_irqrestore(ap->lock, flags);
920 ap->ops->transmit_led_message(ap, led_message, 4);
923 static void ahci_init_sw_activity(struct ata_link *link)
925 struct ata_port *ap = link->ap;
926 struct ahci_port_priv *pp = ap->private_data;
927 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
929 /* init activity stats, setup timer */
930 emp->saved_activity = emp->activity = 0;
931 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
933 /* check our blink policy and set flag for link if it's enabled */
934 if (emp->blink_policy)
935 link->flags |= ATA_LFLAG_SW_ACTIVITY;
938 int ahci_reset_em(struct ata_host *host)
940 struct ahci_host_priv *hpriv = host->private_data;
941 void __iomem *mmio = hpriv->mmio;
944 em_ctl = readl(mmio + HOST_EM_CTL);
945 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
948 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
951 EXPORT_SYMBOL_GPL(ahci_reset_em);
953 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
956 struct ahci_host_priv *hpriv = ap->host->private_data;
957 struct ahci_port_priv *pp = ap->private_data;
958 void __iomem *mmio = hpriv->mmio;
960 u32 message[] = {0, 0};
963 struct ahci_em_priv *emp;
965 /* get the slot number from the message */
966 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
967 if (pmp < EM_MAX_SLOTS)
968 emp = &pp->em_priv[pmp];
972 spin_lock_irqsave(ap->lock, flags);
975 * if we are still busy transmitting a previous message,
978 em_ctl = readl(mmio + HOST_EM_CTL);
979 if (em_ctl & EM_CTL_TM) {
980 spin_unlock_irqrestore(ap->lock, flags);
984 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
986 * create message header - this is all zero except for
987 * the message size, which is 4 bytes.
989 message[0] |= (4 << 8);
991 /* ignore 0:4 of byte zero, fill in port info yourself */
992 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
994 /* write message to EM_LOC */
995 writel(message[0], mmio + hpriv->em_loc);
996 writel(message[1], mmio + hpriv->em_loc+4);
999 * tell hardware to transmit the message
1001 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1004 /* save off new led state for port/slot */
1005 emp->led_state = state;
1007 spin_unlock_irqrestore(ap->lock, flags);
1011 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1013 struct ahci_port_priv *pp = ap->private_data;
1014 struct ata_link *link;
1015 struct ahci_em_priv *emp;
1018 ata_for_each_link(link, ap, EDGE) {
1019 emp = &pp->em_priv[link->pmp];
1020 rc += sprintf(buf, "%lx\n", emp->led_state);
1025 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1030 struct ahci_port_priv *pp = ap->private_data;
1031 struct ahci_em_priv *emp;
1033 state = simple_strtoul(buf, NULL, 0);
1035 /* get the slot number from the message */
1036 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1037 if (pmp < EM_MAX_SLOTS)
1038 emp = &pp->em_priv[pmp];
1042 /* mask off the activity bits if we are in sw_activity
1043 * mode, user should turn off sw_activity before setting
1044 * activity led through em_message
1046 if (emp->blink_policy)
1047 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1049 return ap->ops->transmit_led_message(ap, state, size);
1052 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1054 struct ata_link *link = dev->link;
1055 struct ata_port *ap = link->ap;
1056 struct ahci_port_priv *pp = ap->private_data;
1057 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1058 u32 port_led_state = emp->led_state;
1060 /* save the desired Activity LED behavior */
1063 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1065 /* set the LED to OFF */
1066 port_led_state &= EM_MSG_LED_VALUE_OFF;
1067 port_led_state |= (ap->port_no | (link->pmp << 8));
1068 ap->ops->transmit_led_message(ap, port_led_state, 4);
1070 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1071 if (val == BLINK_OFF) {
1072 /* set LED to ON for idle */
1073 port_led_state &= EM_MSG_LED_VALUE_OFF;
1074 port_led_state |= (ap->port_no | (link->pmp << 8));
1075 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1076 ap->ops->transmit_led_message(ap, port_led_state, 4);
1079 emp->blink_policy = val;
1083 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1085 struct ata_link *link = dev->link;
1086 struct ata_port *ap = link->ap;
1087 struct ahci_port_priv *pp = ap->private_data;
1088 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1090 /* display the saved value of activity behavior for this
1093 return sprintf(buf, "%d\n", emp->blink_policy);
1096 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1097 int port_no, void __iomem *mmio,
1098 void __iomem *port_mmio)
1100 const char *emsg = NULL;
1104 /* make sure port is not active */
1105 rc = ahci_deinit_port(ap, &emsg);
1107 dev_warn(dev, "%s (%d)\n", emsg, rc);
1110 tmp = readl(port_mmio + PORT_SCR_ERR);
1111 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1112 writel(tmp, port_mmio + PORT_SCR_ERR);
1114 /* clear port IRQ */
1115 tmp = readl(port_mmio + PORT_IRQ_STAT);
1116 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1118 writel(tmp, port_mmio + PORT_IRQ_STAT);
1120 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1123 void ahci_init_controller(struct ata_host *host)
1125 struct ahci_host_priv *hpriv = host->private_data;
1126 void __iomem *mmio = hpriv->mmio;
1128 void __iomem *port_mmio;
1131 for (i = 0; i < host->n_ports; i++) {
1132 struct ata_port *ap = host->ports[i];
1134 port_mmio = ahci_port_base(ap);
1135 if (ata_port_is_dummy(ap))
1138 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1141 tmp = readl(mmio + HOST_CTL);
1142 VPRINTK("HOST_CTL 0x%x\n", tmp);
1143 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1144 tmp = readl(mmio + HOST_CTL);
1145 VPRINTK("HOST_CTL 0x%x\n", tmp);
1147 EXPORT_SYMBOL_GPL(ahci_init_controller);
1149 static void ahci_dev_config(struct ata_device *dev)
1151 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1153 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1154 dev->max_sectors = 255;
1156 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1160 unsigned int ahci_dev_classify(struct ata_port *ap)
1162 void __iomem *port_mmio = ahci_port_base(ap);
1163 struct ata_taskfile tf;
1166 tmp = readl(port_mmio + PORT_SIG);
1167 tf.lbah = (tmp >> 24) & 0xff;
1168 tf.lbam = (tmp >> 16) & 0xff;
1169 tf.lbal = (tmp >> 8) & 0xff;
1170 tf.nsect = (tmp) & 0xff;
1172 return ata_dev_classify(&tf);
1174 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1176 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1179 dma_addr_t cmd_tbl_dma;
1181 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1183 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1184 pp->cmd_slot[tag].status = 0;
1185 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1186 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1188 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1190 int ahci_kick_engine(struct ata_port *ap)
1192 void __iomem *port_mmio = ahci_port_base(ap);
1193 struct ahci_host_priv *hpriv = ap->host->private_data;
1194 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1199 rc = ahci_stop_engine(ap);
1204 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1206 busy = status & (ATA_BUSY | ATA_DRQ);
1207 if (!busy && !sata_pmp_attached(ap)) {
1212 if (!(hpriv->cap & HOST_CAP_CLO)) {
1218 tmp = readl(port_mmio + PORT_CMD);
1219 tmp |= PORT_CMD_CLO;
1220 writel(tmp, port_mmio + PORT_CMD);
1223 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1224 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1225 if (tmp & PORT_CMD_CLO)
1228 /* restart engine */
1230 ahci_start_engine(ap);
1233 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1235 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1236 struct ata_taskfile *tf, int is_cmd, u16 flags,
1237 unsigned long timeout_msec)
1239 const u32 cmd_fis_len = 5; /* five dwords */
1240 struct ahci_port_priv *pp = ap->private_data;
1241 void __iomem *port_mmio = ahci_port_base(ap);
1242 u8 *fis = pp->cmd_tbl;
1245 /* prep the command */
1246 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1247 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1250 writel(1, port_mmio + PORT_CMD_ISSUE);
1253 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1254 0x1, 0x1, 1, timeout_msec);
1256 ahci_kick_engine(ap);
1260 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1265 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1266 int pmp, unsigned long deadline,
1267 int (*check_ready)(struct ata_link *link))
1269 struct ata_port *ap = link->ap;
1270 struct ahci_host_priv *hpriv = ap->host->private_data;
1271 const char *reason = NULL;
1272 unsigned long now, msecs;
1273 struct ata_taskfile tf;
1278 /* prepare for SRST (AHCI-1.1 10.4.1) */
1279 rc = ahci_kick_engine(ap);
1280 if (rc && rc != -EOPNOTSUPP)
1281 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1283 ata_tf_init(link->device, &tf);
1285 /* issue the first D2H Register FIS */
1288 if (time_after(deadline, now))
1289 msecs = jiffies_to_msecs(deadline - now);
1292 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1293 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1295 reason = "1st FIS failed";
1299 /* spec says at least 5us, but be generous and sleep for 1ms */
1302 /* issue the second D2H Register FIS */
1303 tf.ctl &= ~ATA_SRST;
1304 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1306 /* wait for link to become ready */
1307 rc = ata_wait_after_reset(link, deadline, check_ready);
1308 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1310 * Workaround for cases where link online status can't
1311 * be trusted. Treat device readiness timeout as link
1314 ata_link_info(link, "device not ready, treating as offline\n");
1315 *class = ATA_DEV_NONE;
1317 /* link occupied, -ENODEV too is an error */
1318 reason = "device not ready";
1321 *class = ahci_dev_classify(ap);
1323 DPRINTK("EXIT, class=%u\n", *class);
1327 ata_link_err(link, "softreset failed (%s)\n", reason);
1331 int ahci_check_ready(struct ata_link *link)
1333 void __iomem *port_mmio = ahci_port_base(link->ap);
1334 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1336 return ata_check_ready(status);
1338 EXPORT_SYMBOL_GPL(ahci_check_ready);
1340 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1341 unsigned long deadline)
1343 int pmp = sata_srst_pmp(link);
1347 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1349 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1351 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1353 void __iomem *port_mmio = ahci_port_base(link->ap);
1354 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1355 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1358 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1359 * which can save timeout delay.
1361 if (irq_status & PORT_IRQ_BAD_PMP)
1364 return ata_check_ready(status);
1367 int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1368 unsigned long deadline)
1370 struct ata_port *ap = link->ap;
1371 void __iomem *port_mmio = ahci_port_base(ap);
1372 int pmp = sata_srst_pmp(link);
1378 rc = ahci_do_softreset(link, class, pmp, deadline,
1379 ahci_bad_pmp_check_ready);
1382 * Soft reset fails with IPMS set when PMP is enabled but
1383 * SATA HDD/ODD is connected to SATA port, do soft reset
1387 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1388 if (irq_sts & PORT_IRQ_BAD_PMP) {
1390 "applying PMP SRST workaround "
1392 rc = ahci_do_softreset(link, class, 0, deadline,
1400 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1401 unsigned long deadline)
1403 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1404 struct ata_port *ap = link->ap;
1405 struct ahci_port_priv *pp = ap->private_data;
1406 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1407 struct ata_taskfile tf;
1413 ahci_stop_engine(ap);
1415 /* clear D2H reception area to properly wait for D2H FIS */
1416 ata_tf_init(link->device, &tf);
1417 tf.command = ATA_BUSY;
1418 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1420 rc = sata_link_hardreset(link, timing, deadline, &online,
1423 ahci_start_engine(ap);
1426 *class = ahci_dev_classify(ap);
1428 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1432 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1434 struct ata_port *ap = link->ap;
1435 void __iomem *port_mmio = ahci_port_base(ap);
1438 ata_std_postreset(link, class);
1440 /* Make sure port's ATAPI bit is set appropriately */
1441 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1442 if (*class == ATA_DEV_ATAPI)
1443 new_tmp |= PORT_CMD_ATAPI;
1445 new_tmp &= ~PORT_CMD_ATAPI;
1446 if (new_tmp != tmp) {
1447 writel(new_tmp, port_mmio + PORT_CMD);
1448 readl(port_mmio + PORT_CMD); /* flush */
1452 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1454 struct scatterlist *sg;
1455 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1461 * Next, the S/G list.
1463 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1464 dma_addr_t addr = sg_dma_address(sg);
1465 u32 sg_len = sg_dma_len(sg);
1467 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1468 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1469 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1475 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1477 struct ata_port *ap = qc->ap;
1478 struct ahci_port_priv *pp = ap->private_data;
1480 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1481 return ata_std_qc_defer(qc);
1483 return sata_pmp_qc_defer_cmd_switch(qc);
1486 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1488 struct ata_port *ap = qc->ap;
1489 struct ahci_port_priv *pp = ap->private_data;
1490 int is_atapi = ata_is_atapi(qc->tf.protocol);
1493 const u32 cmd_fis_len = 5; /* five dwords */
1494 unsigned int n_elem;
1497 * Fill in command table information. First, the header,
1498 * a SATA Register - Host to Device command FIS.
1500 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1502 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1504 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1505 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1509 if (qc->flags & ATA_QCFLAG_DMAMAP)
1510 n_elem = ahci_fill_sg(qc, cmd_tbl);
1513 * Fill in command slot information.
1515 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1516 if (qc->tf.flags & ATA_TFLAG_WRITE)
1517 opts |= AHCI_CMD_WRITE;
1519 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1521 ahci_fill_cmd_slot(pp, qc->tag, opts);
1524 static void ahci_fbs_dec_intr(struct ata_port *ap)
1526 struct ahci_port_priv *pp = ap->private_data;
1527 void __iomem *port_mmio = ahci_port_base(ap);
1528 u32 fbs = readl(port_mmio + PORT_FBS);
1532 BUG_ON(!pp->fbs_enabled);
1534 /* time to wait for DEC is not specified by AHCI spec,
1535 * add a retry loop for safety.
1537 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1538 fbs = readl(port_mmio + PORT_FBS);
1539 while ((fbs & PORT_FBS_DEC) && retries--) {
1541 fbs = readl(port_mmio + PORT_FBS);
1544 if (fbs & PORT_FBS_DEC)
1545 dev_err(ap->host->dev, "failed to clear device error\n");
1548 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1550 struct ahci_host_priv *hpriv = ap->host->private_data;
1551 struct ahci_port_priv *pp = ap->private_data;
1552 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1553 struct ata_link *link = NULL;
1554 struct ata_queued_cmd *active_qc;
1555 struct ata_eh_info *active_ehi;
1556 bool fbs_need_dec = false;
1559 /* determine active link with error */
1560 if (pp->fbs_enabled) {
1561 void __iomem *port_mmio = ahci_port_base(ap);
1562 u32 fbs = readl(port_mmio + PORT_FBS);
1563 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1565 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1566 link = &ap->pmp_link[pmp];
1567 fbs_need_dec = true;
1571 ata_for_each_link(link, ap, EDGE)
1572 if (ata_link_active(link))
1578 active_qc = ata_qc_from_tag(ap, link->active_tag);
1579 active_ehi = &link->eh_info;
1581 /* record irq stat */
1582 ata_ehi_clear_desc(host_ehi);
1583 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1585 /* AHCI needs SError cleared; otherwise, it might lock up */
1586 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1587 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1588 host_ehi->serror |= serror;
1590 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1591 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1592 irq_stat &= ~PORT_IRQ_IF_ERR;
1594 if (irq_stat & PORT_IRQ_TF_ERR) {
1595 /* If qc is active, charge it; otherwise, the active
1596 * link. There's no active qc on NCQ errors. It will
1597 * be determined by EH by reading log page 10h.
1600 active_qc->err_mask |= AC_ERR_DEV;
1602 active_ehi->err_mask |= AC_ERR_DEV;
1604 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1605 host_ehi->serror &= ~SERR_INTERNAL;
1608 if (irq_stat & PORT_IRQ_UNK_FIS) {
1609 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1611 active_ehi->err_mask |= AC_ERR_HSM;
1612 active_ehi->action |= ATA_EH_RESET;
1613 ata_ehi_push_desc(active_ehi,
1614 "unknown FIS %08x %08x %08x %08x" ,
1615 unk[0], unk[1], unk[2], unk[3]);
1618 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1619 active_ehi->err_mask |= AC_ERR_HSM;
1620 active_ehi->action |= ATA_EH_RESET;
1621 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1624 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1625 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1626 host_ehi->action |= ATA_EH_RESET;
1627 ata_ehi_push_desc(host_ehi, "host bus error");
1630 if (irq_stat & PORT_IRQ_IF_ERR) {
1632 active_ehi->err_mask |= AC_ERR_DEV;
1634 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1635 host_ehi->action |= ATA_EH_RESET;
1638 ata_ehi_push_desc(host_ehi, "interface fatal error");
1641 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1642 ata_ehi_hotplugged(host_ehi);
1643 ata_ehi_push_desc(host_ehi, "%s",
1644 irq_stat & PORT_IRQ_CONNECT ?
1645 "connection status changed" : "PHY RDY changed");
1648 /* okay, let's hand over to EH */
1650 if (irq_stat & PORT_IRQ_FREEZE)
1651 ata_port_freeze(ap);
1652 else if (fbs_need_dec) {
1653 ata_link_abort(link);
1654 ahci_fbs_dec_intr(ap);
1659 static void ahci_handle_port_interrupt(struct ata_port *ap,
1660 void __iomem *port_mmio, u32 status)
1662 struct ata_eh_info *ehi = &ap->link.eh_info;
1663 struct ahci_port_priv *pp = ap->private_data;
1664 struct ahci_host_priv *hpriv = ap->host->private_data;
1665 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1669 /* ignore BAD_PMP while resetting */
1670 if (unlikely(resetting))
1671 status &= ~PORT_IRQ_BAD_PMP;
1673 /* if LPM is enabled, PHYRDY doesn't mean anything */
1674 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
1675 status &= ~PORT_IRQ_PHYRDY;
1676 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1679 if (unlikely(status & PORT_IRQ_ERROR)) {
1680 ahci_error_intr(ap, status);
1684 if (status & PORT_IRQ_SDB_FIS) {
1685 /* If SNotification is available, leave notification
1686 * handling to sata_async_notification(). If not,
1687 * emulate it by snooping SDB FIS RX area.
1689 * Snooping FIS RX area is probably cheaper than
1690 * poking SNotification but some constrollers which
1691 * implement SNotification, ICH9 for example, don't
1692 * store AN SDB FIS into receive area.
1694 if (hpriv->cap & HOST_CAP_SNTF)
1695 sata_async_notification(ap);
1697 /* If the 'N' bit in word 0 of the FIS is set,
1698 * we just received asynchronous notification.
1699 * Tell libata about it.
1701 * Lack of SNotification should not appear in
1702 * ahci 1.2, so the workaround is unnecessary
1703 * when FBS is enabled.
1705 if (pp->fbs_enabled)
1708 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1709 u32 f0 = le32_to_cpu(f[0]);
1711 sata_async_notification(ap);
1716 /* pp->active_link is not reliable once FBS is enabled, both
1717 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1718 * NCQ and non-NCQ commands may be in flight at the same time.
1720 if (pp->fbs_enabled) {
1721 if (ap->qc_active) {
1722 qc_active = readl(port_mmio + PORT_SCR_ACT);
1723 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1726 /* pp->active_link is valid iff any command is in flight */
1727 if (ap->qc_active && pp->active_link->sactive)
1728 qc_active = readl(port_mmio + PORT_SCR_ACT);
1730 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1734 rc = ata_qc_complete_multiple(ap, qc_active);
1736 /* while resetting, invalid completions are expected */
1737 if (unlikely(rc < 0 && !resetting)) {
1738 ehi->err_mask |= AC_ERR_HSM;
1739 ehi->action |= ATA_EH_RESET;
1740 ata_port_freeze(ap);
1744 void ahci_port_intr(struct ata_port *ap)
1746 void __iomem *port_mmio = ahci_port_base(ap);
1749 status = readl(port_mmio + PORT_IRQ_STAT);
1750 writel(status, port_mmio + PORT_IRQ_STAT);
1752 ahci_handle_port_interrupt(ap, port_mmio, status);
1755 irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1757 struct ata_port *ap = dev_instance;
1758 struct ahci_port_priv *pp = ap->private_data;
1759 void __iomem *port_mmio = ahci_port_base(ap);
1760 unsigned long flags;
1763 spin_lock_irqsave(&ap->host->lock, flags);
1764 status = pp->intr_status;
1766 pp->intr_status = 0;
1767 spin_unlock_irqrestore(&ap->host->lock, flags);
1769 spin_lock_bh(ap->lock);
1770 ahci_handle_port_interrupt(ap, port_mmio, status);
1771 spin_unlock_bh(ap->lock);
1775 EXPORT_SYMBOL_GPL(ahci_thread_fn);
1777 void ahci_hw_port_interrupt(struct ata_port *ap)
1779 void __iomem *port_mmio = ahci_port_base(ap);
1780 struct ahci_port_priv *pp = ap->private_data;
1783 status = readl(port_mmio + PORT_IRQ_STAT);
1784 writel(status, port_mmio + PORT_IRQ_STAT);
1786 pp->intr_status |= status;
1789 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1791 struct ata_port *ap_this = dev_instance;
1792 struct ahci_port_priv *pp = ap_this->private_data;
1793 struct ata_host *host = ap_this->host;
1794 struct ahci_host_priv *hpriv = host->private_data;
1795 void __iomem *mmio = hpriv->mmio;
1797 u32 irq_stat, irq_masked;
1801 spin_lock(&host->lock);
1803 irq_stat = readl(mmio + HOST_IRQ_STAT);
1806 u32 status = pp->intr_status;
1808 spin_unlock(&host->lock);
1812 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1815 irq_masked = irq_stat & hpriv->port_map;
1817 for (i = 0; i < host->n_ports; i++) {
1818 struct ata_port *ap;
1820 if (!(irq_masked & (1 << i)))
1823 ap = host->ports[i];
1825 ahci_hw_port_interrupt(ap);
1826 VPRINTK("port %u\n", i);
1828 VPRINTK("port %u (no irq)\n", i);
1829 if (ata_ratelimit())
1831 "interrupt on disabled port %u\n", i);
1835 writel(irq_stat, mmio + HOST_IRQ_STAT);
1837 spin_unlock(&host->lock);
1841 return IRQ_WAKE_THREAD;
1843 EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1845 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1847 struct ata_host *host = dev_instance;
1848 struct ahci_host_priv *hpriv;
1849 unsigned int i, handled = 0;
1851 u32 irq_stat, irq_masked;
1855 hpriv = host->private_data;
1858 /* sigh. 0xffffffff is a valid return from h/w */
1859 irq_stat = readl(mmio + HOST_IRQ_STAT);
1863 irq_masked = irq_stat & hpriv->port_map;
1865 spin_lock(&host->lock);
1867 for (i = 0; i < host->n_ports; i++) {
1868 struct ata_port *ap;
1870 if (!(irq_masked & (1 << i)))
1873 ap = host->ports[i];
1876 VPRINTK("port %u\n", i);
1878 VPRINTK("port %u (no irq)\n", i);
1879 if (ata_ratelimit())
1881 "interrupt on disabled port %u\n", i);
1887 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1888 * it should be cleared after all the port events are cleared;
1889 * otherwise, it will raise a spurious interrupt after each
1890 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1893 * Also, use the unmasked value to clear interrupt as spurious
1894 * pending event on a dummy port might cause screaming IRQ.
1896 writel(irq_stat, mmio + HOST_IRQ_STAT);
1898 spin_unlock(&host->lock);
1902 return IRQ_RETVAL(handled);
1904 EXPORT_SYMBOL_GPL(ahci_interrupt);
1906 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1908 struct ata_port *ap = qc->ap;
1909 void __iomem *port_mmio = ahci_port_base(ap);
1910 struct ahci_port_priv *pp = ap->private_data;
1912 /* Keep track of the currently active link. It will be used
1913 * in completion path to determine whether NCQ phase is in
1916 pp->active_link = qc->dev->link;
1918 if (qc->tf.protocol == ATA_PROT_NCQ)
1919 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1921 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1922 u32 fbs = readl(port_mmio + PORT_FBS);
1923 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1924 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1925 writel(fbs, port_mmio + PORT_FBS);
1926 pp->fbs_last_dev = qc->dev->link->pmp;
1929 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1931 ahci_sw_activity(qc->dev->link);
1936 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1938 struct ahci_port_priv *pp = qc->ap->private_data;
1939 u8 *rx_fis = pp->rx_fis;
1941 if (pp->fbs_enabled)
1942 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1945 * After a successful execution of an ATA PIO data-in command,
1946 * the device doesn't send D2H Reg FIS to update the TF and
1947 * the host should take TF and E_Status from the preceding PIO
1950 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1951 !(qc->flags & ATA_QCFLAG_FAILED)) {
1952 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1953 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1955 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1960 static void ahci_freeze(struct ata_port *ap)
1962 void __iomem *port_mmio = ahci_port_base(ap);
1965 writel(0, port_mmio + PORT_IRQ_MASK);
1968 static void ahci_thaw(struct ata_port *ap)
1970 struct ahci_host_priv *hpriv = ap->host->private_data;
1971 void __iomem *mmio = hpriv->mmio;
1972 void __iomem *port_mmio = ahci_port_base(ap);
1974 struct ahci_port_priv *pp = ap->private_data;
1977 tmp = readl(port_mmio + PORT_IRQ_STAT);
1978 writel(tmp, port_mmio + PORT_IRQ_STAT);
1979 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1981 /* turn IRQ back on */
1982 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1985 static void ahci_error_handler(struct ata_port *ap)
1987 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1988 /* restart engine */
1989 ahci_stop_engine(ap);
1990 ahci_start_engine(ap);
1993 sata_pmp_error_handler(ap);
1995 if (!ata_dev_enabled(ap->link.device))
1996 ahci_stop_engine(ap);
1999 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2001 struct ata_port *ap = qc->ap;
2003 /* make DMA engine forget about the failed command */
2004 if (qc->flags & ATA_QCFLAG_FAILED)
2005 ahci_kick_engine(ap);
2008 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2010 void __iomem *port_mmio = ahci_port_base(ap);
2011 struct ata_device *dev = ap->link.device;
2012 u32 devslp, dm, dito, mdat, deto;
2014 unsigned int err_mask;
2016 devslp = readl(port_mmio + PORT_DEVSLP);
2017 if (!(devslp & PORT_DEVSLP_DSP)) {
2018 dev_err(ap->host->dev, "port does not support device sleep\n");
2022 /* disable device sleep */
2024 if (devslp & PORT_DEVSLP_ADSE) {
2025 writel(devslp & ~PORT_DEVSLP_ADSE,
2026 port_mmio + PORT_DEVSLP);
2027 err_mask = ata_dev_set_feature(dev,
2028 SETFEATURES_SATA_DISABLE,
2030 if (err_mask && err_mask != AC_ERR_DEV)
2031 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2036 /* device sleep was already enabled */
2037 if (devslp & PORT_DEVSLP_ADSE)
2040 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2041 rc = ahci_stop_engine(ap);
2045 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2046 dito = devslp_idle_timeout / (dm + 1);
2050 /* Use the nominal value 10 ms if the read MDAT is zero,
2051 * the nominal value of DETO is 20 ms.
2053 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2054 ATA_LOG_DEVSLP_VALID_MASK) {
2055 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2056 ATA_LOG_DEVSLP_MDAT_MASK;
2059 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2067 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2068 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2069 (deto << PORT_DEVSLP_DETO_OFFSET) |
2071 writel(devslp, port_mmio + PORT_DEVSLP);
2073 ahci_start_engine(ap);
2075 /* enable device sleep feature for the drive */
2076 err_mask = ata_dev_set_feature(dev,
2077 SETFEATURES_SATA_ENABLE,
2079 if (err_mask && err_mask != AC_ERR_DEV)
2080 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2083 static void ahci_enable_fbs(struct ata_port *ap)
2085 struct ahci_port_priv *pp = ap->private_data;
2086 void __iomem *port_mmio = ahci_port_base(ap);
2090 if (!pp->fbs_supported)
2093 fbs = readl(port_mmio + PORT_FBS);
2094 if (fbs & PORT_FBS_EN) {
2095 pp->fbs_enabled = true;
2096 pp->fbs_last_dev = -1; /* initialization */
2100 rc = ahci_stop_engine(ap);
2104 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2105 fbs = readl(port_mmio + PORT_FBS);
2106 if (fbs & PORT_FBS_EN) {
2107 dev_info(ap->host->dev, "FBS is enabled\n");
2108 pp->fbs_enabled = true;
2109 pp->fbs_last_dev = -1; /* initialization */
2111 dev_err(ap->host->dev, "Failed to enable FBS\n");
2113 ahci_start_engine(ap);
2116 static void ahci_disable_fbs(struct ata_port *ap)
2118 struct ahci_port_priv *pp = ap->private_data;
2119 void __iomem *port_mmio = ahci_port_base(ap);
2123 if (!pp->fbs_supported)
2126 fbs = readl(port_mmio + PORT_FBS);
2127 if ((fbs & PORT_FBS_EN) == 0) {
2128 pp->fbs_enabled = false;
2132 rc = ahci_stop_engine(ap);
2136 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2137 fbs = readl(port_mmio + PORT_FBS);
2138 if (fbs & PORT_FBS_EN)
2139 dev_err(ap->host->dev, "Failed to disable FBS\n");
2141 dev_info(ap->host->dev, "FBS is disabled\n");
2142 pp->fbs_enabled = false;
2145 ahci_start_engine(ap);
2148 static void ahci_pmp_attach(struct ata_port *ap)
2150 void __iomem *port_mmio = ahci_port_base(ap);
2151 struct ahci_port_priv *pp = ap->private_data;
2154 cmd = readl(port_mmio + PORT_CMD);
2155 cmd |= PORT_CMD_PMP;
2156 writel(cmd, port_mmio + PORT_CMD);
2158 ahci_enable_fbs(ap);
2160 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2163 * We must not change the port interrupt mask register if the
2164 * port is marked frozen, the value in pp->intr_mask will be
2165 * restored later when the port is thawed.
2167 * Note that during initialization, the port is marked as
2168 * frozen since the irq handler is not yet registered.
2170 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2171 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2174 static void ahci_pmp_detach(struct ata_port *ap)
2176 void __iomem *port_mmio = ahci_port_base(ap);
2177 struct ahci_port_priv *pp = ap->private_data;
2180 ahci_disable_fbs(ap);
2182 cmd = readl(port_mmio + PORT_CMD);
2183 cmd &= ~PORT_CMD_PMP;
2184 writel(cmd, port_mmio + PORT_CMD);
2186 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2188 /* see comment above in ahci_pmp_attach() */
2189 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2190 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2193 int ahci_port_resume(struct ata_port *ap)
2196 ahci_start_port(ap);
2198 if (sata_pmp_attached(ap))
2199 ahci_pmp_attach(ap);
2201 ahci_pmp_detach(ap);
2205 EXPORT_SYMBOL_GPL(ahci_port_resume);
2208 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2210 const char *emsg = NULL;
2213 rc = ahci_deinit_port(ap, &emsg);
2215 ahci_power_down(ap);
2217 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2218 ata_port_freeze(ap);
2225 static int ahci_port_start(struct ata_port *ap)
2227 struct ahci_host_priv *hpriv = ap->host->private_data;
2228 struct device *dev = ap->host->dev;
2229 struct ahci_port_priv *pp;
2232 size_t dma_sz, rx_fis_sz;
2234 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2238 if (ap->host->n_ports > 1) {
2239 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2240 if (!pp->irq_desc) {
2241 devm_kfree(dev, pp);
2244 snprintf(pp->irq_desc, 8,
2245 "%s%d", dev_driver_string(dev), ap->port_no);
2248 /* check FBS capability */
2249 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2250 void __iomem *port_mmio = ahci_port_base(ap);
2251 u32 cmd = readl(port_mmio + PORT_CMD);
2252 if (cmd & PORT_CMD_FBSCP)
2253 pp->fbs_supported = true;
2254 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2255 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2257 pp->fbs_supported = true;
2259 dev_warn(dev, "port %d is not capable of FBS\n",
2263 if (pp->fbs_supported) {
2264 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2265 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2267 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2268 rx_fis_sz = AHCI_RX_FIS_SZ;
2271 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2274 memset(mem, 0, dma_sz);
2277 * First item in chunk of DMA memory: 32-slot command table,
2278 * 32 bytes each in size
2281 pp->cmd_slot_dma = mem_dma;
2283 mem += AHCI_CMD_SLOT_SZ;
2284 mem_dma += AHCI_CMD_SLOT_SZ;
2287 * Second item: Received-FIS area
2290 pp->rx_fis_dma = mem_dma;
2293 mem_dma += rx_fis_sz;
2296 * Third item: data area for storing a single command
2297 * and its scatter-gather table
2300 pp->cmd_tbl_dma = mem_dma;
2303 * Save off initial list of interrupts to be enabled.
2304 * This could be changed later
2306 pp->intr_mask = DEF_PORT_IRQ;
2309 * Switch to per-port locking in case each port has its own MSI vector.
2311 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2312 spin_lock_init(&pp->lock);
2313 ap->lock = &pp->lock;
2316 ap->private_data = pp;
2318 /* engage engines, captain */
2319 return ahci_port_resume(ap);
2322 static void ahci_port_stop(struct ata_port *ap)
2324 const char *emsg = NULL;
2327 /* de-initialize port */
2328 rc = ahci_deinit_port(ap, &emsg);
2330 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2333 void ahci_print_info(struct ata_host *host, const char *scc_s)
2335 struct ahci_host_priv *hpriv = host->private_data;
2336 void __iomem *mmio = hpriv->mmio;
2337 u32 vers, cap, cap2, impl, speed;
2338 const char *speed_s;
2340 vers = readl(mmio + HOST_VERSION);
2343 impl = hpriv->port_map;
2345 speed = (cap >> 20) & 0xf;
2348 else if (speed == 2)
2350 else if (speed == 3)
2356 "AHCI %02x%02x.%02x%02x "
2357 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2360 (vers >> 24) & 0xff,
2361 (vers >> 16) & 0xff,
2365 ((cap >> 8) & 0x1f) + 1,
2379 cap & HOST_CAP_64 ? "64bit " : "",
2380 cap & HOST_CAP_NCQ ? "ncq " : "",
2381 cap & HOST_CAP_SNTF ? "sntf " : "",
2382 cap & HOST_CAP_MPS ? "ilck " : "",
2383 cap & HOST_CAP_SSS ? "stag " : "",
2384 cap & HOST_CAP_ALPM ? "pm " : "",
2385 cap & HOST_CAP_LED ? "led " : "",
2386 cap & HOST_CAP_CLO ? "clo " : "",
2387 cap & HOST_CAP_ONLY ? "only " : "",
2388 cap & HOST_CAP_PMP ? "pmp " : "",
2389 cap & HOST_CAP_FBS ? "fbs " : "",
2390 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2391 cap & HOST_CAP_SSC ? "slum " : "",
2392 cap & HOST_CAP_PART ? "part " : "",
2393 cap & HOST_CAP_CCC ? "ccc " : "",
2394 cap & HOST_CAP_EMS ? "ems " : "",
2395 cap & HOST_CAP_SXS ? "sxs " : "",
2396 cap2 & HOST_CAP2_DESO ? "deso " : "",
2397 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2398 cap2 & HOST_CAP2_SDS ? "sds " : "",
2399 cap2 & HOST_CAP2_APST ? "apst " : "",
2400 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2401 cap2 & HOST_CAP2_BOH ? "boh " : ""
2404 EXPORT_SYMBOL_GPL(ahci_print_info);
2406 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2407 struct ata_port_info *pi)
2410 void __iomem *mmio = hpriv->mmio;
2411 u32 em_loc = readl(mmio + HOST_EM_LOC);
2412 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2414 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2417 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2421 hpriv->em_loc = ((em_loc >> 16) * 4);
2422 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2423 hpriv->em_msg_type = messages;
2424 pi->flags |= ATA_FLAG_EM;
2425 if (!(em_ctl & EM_CTL_ALHD))
2426 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2429 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2431 MODULE_AUTHOR("Jeff Garzik");
2432 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2433 MODULE_LICENSE("GPL");