1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Terry Lv <r65388@freescale.com>
11 #include <dwc_ahsata.h>
17 #include <asm/cache.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/sata.h>
22 #include <linux/bitops.h>
23 #include <linux/ctype.h>
24 #include <linux/errno.h>
25 #include "dwc_ahsata_priv.h"
27 struct sata_port_regs {
51 struct sata_host_regs {
80 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
81 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
83 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
85 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
87 return base + 0x100 + (port * 0x80);
90 static int waiting_for_cmd_completed(u8 *offset,
98 ((status = readl(offset)) & sign) && i < timeout_msec;
102 return (i < timeout_msec) ? 0 : -1;
105 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
107 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
109 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
110 writel(0x02060b14, &host_mmio->oobr);
115 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
117 u32 tmp, cap_save, num_ports;
118 int i, j, timeout = 1000;
119 struct sata_port_regs *port_mmio = NULL;
120 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
121 int clk = mxc_get_clock(MXC_SATA_CLK);
123 cap_save = readl(&host_mmio->cap);
124 cap_save |= SATA_HOST_CAP_SSS;
126 /* global controller reset */
127 tmp = readl(&host_mmio->ghc);
128 if ((tmp & SATA_HOST_GHC_HR) == 0)
129 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
131 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
135 debug("controller reset failed (0x%x)\n", tmp);
140 writel(clk / 1000, &host_mmio->timer1ms);
142 ahci_setup_oobr(uc_priv, 0);
144 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
145 writel(cap_save, &host_mmio->cap);
146 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
147 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
150 * Determine which Ports are implemented by the DWC_ahsata,
151 * by reading the PI register. This bit map value aids the
152 * software to determine how many Ports are available and
153 * which Port registers need to be initialized.
155 uc_priv->cap = readl(&host_mmio->cap);
156 uc_priv->port_map = readl(&host_mmio->pi);
158 /* Determine how many command slots the HBA supports */
159 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
161 debug("cap 0x%x port_map 0x%x n_ports %d\n",
162 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
164 for (i = 0; i < uc_priv->n_ports; i++) {
165 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
166 port_mmio = uc_priv->port[i].port_mmio;
168 /* Ensure that the DWC_ahsata is in idle state */
169 tmp = readl(&port_mmio->cmd);
172 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
173 * are all cleared, the Port is in an idle state.
175 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
176 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
179 * System software places a Port into the idle state by
180 * clearing P#CMD.ST and waiting for P#CMD.CR to return
183 tmp &= ~SATA_PORT_CMD_ST;
184 writel_with_flush(tmp, &port_mmio->cmd);
187 * spec says 500 msecs for each bit, so
188 * this is slightly incorrect.
193 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
198 debug("port reset failed (0x%x)\n", tmp);
204 tmp = readl(&port_mmio->cmd);
205 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
207 /* Wait for spin-up to finish */
209 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
213 debug("Spin-Up can't finish!\n");
217 for (j = 0; j < 100; ++j) {
219 tmp = readl(&port_mmio->ssts);
220 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
221 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
225 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
227 while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
231 debug("Can't find DIAG_X set!\n");
236 * For each implemented Port, clear the P#SERR
237 * register, by writing ones to each implemented\
240 tmp = readl(&port_mmio->serr);
241 debug("P#SERR 0x%x\n",
243 writel(tmp, &port_mmio->serr);
245 /* Ack any pending irq events for this port */
246 tmp = readl(&host_mmio->is);
247 debug("IS 0x%x\n", tmp);
249 writel(tmp, &host_mmio->is);
251 writel(1 << i, &host_mmio->is);
253 /* set irq mask (enables interrupts) */
254 writel(DEF_PORT_IRQ, &port_mmio->ie);
256 /* register linkup ports */
257 tmp = readl(&port_mmio->ssts);
258 debug("Port %d status: 0x%x\n", i, tmp);
259 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
260 uc_priv->link_port_map |= (0x01 << i);
263 tmp = readl(&host_mmio->ghc);
264 debug("GHC 0x%x\n", tmp);
265 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
266 tmp = readl(&host_mmio->ghc);
267 debug("GHC 0x%x\n", tmp);
272 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
274 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
275 u32 vers, cap, impl, speed;
279 vers = readl(&host_mmio->vs);
281 impl = uc_priv->port_map;
283 speed = (cap & SATA_HOST_CAP_ISS_MASK)
284 >> SATA_HOST_CAP_ISS_OFFSET;
294 printf("AHCI %02x%02x.%02x%02x "
295 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
300 ((cap >> 8) & 0x1f) + 1,
309 cap & (1 << 31) ? "64bit " : "",
310 cap & (1 << 30) ? "ncq " : "",
311 cap & (1 << 28) ? "ilck " : "",
312 cap & (1 << 27) ? "stag " : "",
313 cap & (1 << 26) ? "pm " : "",
314 cap & (1 << 25) ? "led " : "",
315 cap & (1 << 24) ? "clo " : "",
316 cap & (1 << 19) ? "nz " : "",
317 cap & (1 << 18) ? "only " : "",
318 cap & (1 << 17) ? "pmp " : "",
319 cap & (1 << 15) ? "pio " : "",
320 cap & (1 << 14) ? "slum " : "",
321 cap & (1 << 13) ? "part " : "");
324 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
325 unsigned char *buf, int buf_len)
327 struct ahci_ioports *pp = &uc_priv->port[port];
328 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
329 u32 sg_count, max_bytes;
332 max_bytes = MAX_DATA_BYTES_PER_SG;
333 sg_count = ((buf_len - 1) / max_bytes) + 1;
334 if (sg_count > AHCI_MAX_SG) {
335 printf("Error:Too much sg!\n");
339 for (i = 0; i < sg_count; i++) {
341 cpu_to_le32((u32)buf + i * max_bytes);
342 ahci_sg->addr_hi = 0;
343 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
348 buf_len -= max_bytes;
354 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
356 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
357 AHCI_CMD_SLOT_SZ * cmd_slot);
359 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
360 cmd_hdr->opts = cpu_to_le32(opts);
362 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
363 #ifdef CONFIG_PHYS_64BIT
364 pp->cmd_slot->tbl_addr_hi =
365 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
369 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
371 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
372 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
375 struct ahci_ioports *pp = &uc_priv->port[port];
376 struct sata_port_regs *port_mmio = pp->port_mmio;
378 int sg_count = 0, cmd_slot = 0;
380 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
381 if (32 == cmd_slot) {
382 printf("Can't find empty command slot!\n");
386 /* Check xfer length */
387 if (buf_len > MAX_BYTES_PER_TRANS) {
388 printf("Max transfer length is %dB\n\r",
389 MAX_BYTES_PER_TRANS);
393 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
395 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
396 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
399 flush_cache((ulong)buf, buf_len);
401 ahci_fill_cmd_slot(pp, cmd_slot, opts);
403 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
404 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
406 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
408 printf("timeout exit!\n");
411 invalidate_dcache_range((int)(pp->cmd_slot),
412 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
413 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
414 pp->cmd_slot->status);
416 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
421 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
423 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
424 struct sata_fis_h2d *cfis = &h2d;
426 memset(cfis, 0, sizeof(struct sata_fis_h2d));
427 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
428 cfis->pm_port_c = 1 << 7;
429 cfis->command = ATA_CMD_SET_FEATURES;
430 cfis->features = SETFEATURES_XFER;
431 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
433 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
436 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
438 struct ahci_ioports *pp = &uc_priv->port[port];
439 struct sata_port_regs *port_mmio = pp->port_mmio;
442 int timeout = 10000000;
444 debug("Enter start port: %d\n", port);
445 port_status = readl(&port_mmio->ssts);
446 debug("Port %d status: %x\n", port, port_status);
447 if ((port_status & 0xf) != 0x03) {
448 printf("No Link on this port!\n");
452 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
454 printf("No mem for table!\n");
458 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
459 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
462 * First item in chunk of DMA memory: 32-slot command table,
463 * 32 bytes each in size
465 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
466 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
467 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
470 * Second item: Received-FIS area, 256-Byte aligned
473 mem += AHCI_RX_FIS_SZ;
476 * Third item: data area for storing a single command
477 * and its scatter-gather table
480 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
482 mem += AHCI_CMD_TBL_HDR;
484 writel_with_flush(0x00004444, &port_mmio->dmacr);
485 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
486 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
487 writel_with_flush(pp->rx_fis, &port_mmio->fb);
490 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
493 /* Wait device ready */
494 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
495 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
499 debug("Device not ready for BSY, DRQ and"
504 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
505 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
506 PORT_CMD_START, &port_mmio->cmd);
508 debug("Exit start port %d\n", port);
513 static void dwc_ahsata_print_info(struct blk_desc *pdev)
515 printf("SATA Device Info:\n\r");
516 printf("S/N: %s\n\rProduct model number: %s\n\r"
517 "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
518 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
521 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
523 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
524 struct sata_fis_h2d *cfis = &h2d;
525 u8 port = uc_priv->hard_port_no;
527 memset(cfis, 0, sizeof(struct sata_fis_h2d));
529 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
530 cfis->pm_port_c = 0x80; /* is command */
531 cfis->command = ATA_CMD_ID_ATA;
533 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
535 ata_swap_buf_le16(id, ATA_ID_WORDS);
538 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
540 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
541 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
542 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
545 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
546 u32 blkcnt, u8 *buffer, int is_write)
548 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
549 struct sata_fis_h2d *cfis = &h2d;
550 u8 port = uc_priv->hard_port_no;
555 memset(cfis, 0, sizeof(struct sata_fis_h2d));
557 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
558 cfis->pm_port_c = 0x80; /* is command */
559 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
560 cfis->device = ATA_LBA;
562 cfis->device |= (block >> 24) & 0xf;
563 cfis->lba_high = (block >> 16) & 0xff;
564 cfis->lba_mid = (block >> 8) & 0xff;
565 cfis->lba_low = block & 0xff;
566 cfis->sector_count = (u8)(blkcnt & 0xff);
568 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
569 ATA_SECT_SIZE * blkcnt, is_write) > 0)
575 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
577 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
578 struct sata_fis_h2d *cfis = &h2d;
579 u8 port = uc_priv->hard_port_no;
581 memset(cfis, 0, sizeof(struct sata_fis_h2d));
583 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
584 cfis->pm_port_c = 0x80; /* is command */
585 cfis->command = ATA_CMD_FLUSH;
587 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
590 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
591 lbaint_t blkcnt, u8 *buffer, int is_write)
593 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
594 struct sata_fis_h2d *cfis = &h2d;
595 u8 port = uc_priv->hard_port_no;
600 memset(cfis, 0, sizeof(struct sata_fis_h2d));
602 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
603 cfis->pm_port_c = 0x80; /* is command */
605 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
608 cfis->lba_high_exp = (block >> 40) & 0xff;
609 cfis->lba_mid_exp = (block >> 32) & 0xff;
610 cfis->lba_low_exp = (block >> 24) & 0xff;
611 cfis->lba_high = (block >> 16) & 0xff;
612 cfis->lba_mid = (block >> 8) & 0xff;
613 cfis->lba_low = block & 0xff;
614 cfis->device = ATA_LBA;
615 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
616 cfis->sector_count = blkcnt & 0xff;
618 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
619 ATA_SECT_SIZE * blkcnt, is_write) > 0)
625 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
627 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
628 struct sata_fis_h2d *cfis = &h2d;
629 u8 port = uc_priv->hard_port_no;
631 memset(cfis, 0, sizeof(struct sata_fis_h2d));
633 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
634 cfis->pm_port_c = 0x80; /* is command */
635 cfis->command = ATA_CMD_FLUSH_EXT;
637 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
640 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
642 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
643 uc_priv->flags |= SATA_FLAG_WCACHE;
644 if (ata_id_has_flush(id))
645 uc_priv->flags |= SATA_FLAG_FLUSH;
646 if (ata_id_has_flush_ext(id))
647 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
650 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
651 lbaint_t blkcnt, const void *buffer,
662 max_blks = ATA_MAX_SECTORS_LBA48;
665 if (blks > max_blks) {
666 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
672 addr += ATA_SECT_SIZE * max_blks;
674 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
679 addr += ATA_SECT_SIZE * blks;
686 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
687 lbaint_t blkcnt, const void *buffer,
698 max_blks = ATA_MAX_SECTORS;
700 if (blks > max_blks) {
701 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
707 addr += ATA_SECT_SIZE * max_blks;
709 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
714 addr += ATA_SECT_SIZE * blks;
721 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
726 linkmap = uc_priv->link_port_map;
729 printf("No port device detected!\n");
733 for (i = 0; i < uc_priv->n_ports; i++) {
734 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
735 if (ahci_port_start(uc_priv, (u8)i)) {
736 printf("Can not start port %d\n", i);
739 uc_priv->hard_port_no = i;
747 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
748 struct blk_desc *pdev)
750 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
751 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
752 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
753 u8 port = uc_priv->hard_port_no;
754 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
756 /* Identify device to get information */
757 dwc_ahsata_identify(uc_priv, id);
760 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
761 memcpy(pdev->product, serial, sizeof(serial));
763 /* Firmware version */
764 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
765 memcpy(pdev->revision, firmware, sizeof(firmware));
768 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
769 memcpy(pdev->vendor, product, sizeof(product));
772 pdev->lba = ata_id_n_sectors(id);
774 pdev->type = DEV_TYPE_HARDDISK;
775 pdev->blksz = ATA_SECT_SIZE;
778 /* Check if support LBA48 */
779 if (ata_id_has_lba48(id)) {
781 debug("Device support LBA48\n\r");
784 /* Get the NCQ queue depth from device */
785 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
786 uc_priv->flags |= ata_id_queue_depth(id);
788 /* Get the xfer mode from device */
789 dwc_ahsata_xfer_mode(uc_priv, id);
791 /* Get the write cache status from device */
792 dwc_ahsata_init_wcache(uc_priv, id);
794 /* Set the xfer mode to highest speed */
795 ahci_set_feature(uc_priv, port);
797 dwc_ahsata_print_info(pdev);
803 * SATA interface between low level driver and command layer
805 static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
806 struct blk_desc *desc, ulong blknr,
807 lbaint_t blkcnt, void *buffer)
812 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
815 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
821 static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
822 struct blk_desc *desc, ulong blknr,
823 lbaint_t blkcnt, const void *buffer)
826 u32 flags = uc_priv->flags;
829 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
831 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
832 dwc_ahsata_flush_cache_ext(uc_priv);
834 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
836 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
837 dwc_ahsata_flush_cache(uc_priv);
843 #if !CONFIG_IS_ENABLED(AHCI)
844 static int ahci_init_one(int pdev)
847 struct ahci_uc_priv *uc_priv = NULL;
849 uc_priv = malloc(sizeof(struct ahci_uc_priv));
853 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
856 uc_priv->host_flags = ATA_FLAG_SATA
862 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
864 /* initialize adapter */
865 rc = ahci_host_init(uc_priv);
869 ahci_print_info(uc_priv);
871 /* Save the uc_private struct to block device struct */
872 sata_dev_desc[pdev].priv = uc_priv;
882 int init_sata(int dev)
884 struct ahci_uc_priv *uc_priv = NULL;
886 #if defined(CONFIG_MX6)
887 if (!is_mx6dq() && !is_mx6dqp())
890 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
891 printf("The sata index %d is out of ranges\n\r", dev);
897 uc_priv = sata_dev_desc[dev].priv;
899 return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
902 int reset_sata(int dev)
904 struct ahci_uc_priv *uc_priv;
905 struct sata_host_regs *host_mmio;
907 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
908 printf("The sata index %d is out of ranges\n\r", dev);
912 uc_priv = sata_dev_desc[dev].priv;
914 /* not initialized, so nothing to reset */
917 host_mmio = uc_priv->mmio_base;
918 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
919 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
923 memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
928 int sata_port_status(int dev, int port)
930 struct sata_port_regs *port_mmio;
931 struct ahci_uc_priv *uc_priv = NULL;
933 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
936 if (sata_dev_desc[dev].priv == NULL)
939 uc_priv = sata_dev_desc[dev].priv;
940 port_mmio = uc_priv->port[port].port_mmio;
942 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
946 * SATA interface between low level driver and command layer
948 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
950 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
952 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
956 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
958 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
960 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
964 int scan_sata(int dev)
966 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
967 struct blk_desc *pdev = &sata_dev_desc[dev];
969 return dwc_ahsata_scan_common(uc_priv, pdev);
971 #endif /* CONFIG_IS_ENABLED(AHCI) */
973 #if CONFIG_IS_ENABLED(AHCI)
975 int dwc_ahsata_port_status(struct udevice *dev, int port)
977 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
978 struct sata_port_regs *port_mmio;
980 port_mmio = uc_priv->port[port].port_mmio;
981 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
984 int dwc_ahsata_bus_reset(struct udevice *dev)
986 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
987 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
989 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
990 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
996 int dwc_ahsata_scan(struct udevice *dev)
998 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
999 struct blk_desc *desc;
1000 struct udevice *blk;
1004 * Create only one block device and do detection
1005 * to make sure that there won't be a lot of
1006 * block devices created
1008 device_find_first_child(dev, &blk);
1010 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1011 IF_TYPE_SATA, -1, 512, 0, &blk);
1013 debug("Can't create device\n");
1018 desc = dev_get_uclass_platdata(blk);
1019 ret = dwc_ahsata_scan_common(uc_priv, desc);
1021 debug("%s: Failed to scan bus\n", __func__);
1028 int dwc_ahsata_probe(struct udevice *dev)
1030 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1033 #if defined(CONFIG_MX6)
1036 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1037 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1038 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1040 /* initialize adapter */
1041 ret = ahci_host_init(uc_priv);
1045 ahci_print_info(uc_priv);
1047 return dwc_ahci_start_ports(uc_priv);
1050 static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1051 lbaint_t blkcnt, void *buffer)
1053 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1054 struct udevice *dev = dev_get_parent(blk);
1055 struct ahci_uc_priv *uc_priv;
1057 uc_priv = dev_get_uclass_priv(dev);
1058 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1061 static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1062 lbaint_t blkcnt, const void *buffer)
1064 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1065 struct udevice *dev = dev_get_parent(blk);
1066 struct ahci_uc_priv *uc_priv;
1068 uc_priv = dev_get_uclass_priv(dev);
1069 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1072 static const struct blk_ops dwc_ahsata_blk_ops = {
1073 .read = dwc_ahsata_read,
1074 .write = dwc_ahsata_write,
1077 U_BOOT_DRIVER(dwc_ahsata_blk) = {
1078 .name = "dwc_ahsata_blk",
1080 .ops = &dwc_ahsata_blk_ops,
1083 #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
1084 struct ahci_ops dwc_ahsata_ahci_ops = {
1085 .port_status = dwc_ahsata_port_status,
1086 .reset = dwc_ahsata_bus_reset,
1087 .scan = dwc_ahsata_scan,
1090 static const struct udevice_id dwc_ahsata_ahci_ids[] = {
1091 { .compatible = "fsl,imx6q-ahci" },
1095 U_BOOT_DRIVER(dwc_ahsata_ahci) = {
1096 .name = "dwc_ahsata_ahci",
1098 .of_match = dwc_ahsata_ahci_ids,
1099 .ops = &dwc_ahsata_ahci_ops,
1100 .probe = dwc_ahsata_probe,