1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
7 * with the reference on libata and ahci drvier in kernel
9 * This driver provides a SCSI interface to SATA.
19 #include <asm/processor.h>
20 #include <linux/errno.h>
27 #include <linux/ctype.h>
29 #include <dm/device-internal.h>
32 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
34 #ifndef CONFIG_DM_SCSI
35 struct ahci_uc_priv *probe_ent = NULL;
38 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
41 * Some controllers limit number of blocks they can read/write at once.
42 * Contemporary SSD devices work much faster if the read/write size is aligned
43 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
46 #ifndef MAX_SATA_BLOCKS_READ_WRITE
47 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
50 /* Maximum timeouts for each event */
51 #define WAIT_MS_SPINUP 20000
52 #define WAIT_MS_DATAIO 10000
53 #define WAIT_MS_FLUSH 5000
54 #define WAIT_MS_LINKUP 200
56 #define AHCI_CAP_S64A BIT(31)
58 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
60 return base + 0x100 + (port * 0x80);
63 #define msleep(a) udelay(a * 1000)
65 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
67 const unsigned long start = begin;
68 const unsigned long end = start + len;
70 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
71 flush_dcache_range(start, end);
75 * SATA controller DMAs to physical RAM. Ensure data from the
76 * controller is invalidated from dcache; next access comes from
79 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
81 const unsigned long start = begin;
82 const unsigned long end = start + len;
84 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
85 invalidate_dcache_range(start, end);
89 * Ensure data for SATA controller is flushed out of dcache and
90 * written to physical memory.
92 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
94 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
95 AHCI_PORT_PRIV_DMA_SZ);
98 static int waiting_for_cmd_completed(void __iomem *offset,
105 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
108 return (i < timeout_msec) ? 0 : -1;
111 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
115 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
118 * Bring up SATA link.
119 * SATA link bringup time is usually less than 1 ms; only very
120 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
122 while (j < WAIT_MS_LINKUP) {
123 tmp = readl(port_mmio + PORT_SCR_STAT);
124 tmp &= PORT_SCR_STAT_DET_MASK;
125 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
133 #ifdef CONFIG_SUNXI_AHCI
134 /* The sunxi AHCI controller requires this undocumented setup */
135 static void sunxi_dma_init(void __iomem *port_mmio)
137 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
141 int ahci_reset(void __iomem *base)
144 u32 __iomem *host_ctl_reg = base + HOST_CTL;
145 u32 tmp = readl(host_ctl_reg); /* global controller reset */
147 if ((tmp & HOST_RESET) == 0)
148 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
151 * reset must complete within 1 second, or
152 * the hardware should be considered fried.
156 tmp = readl(host_ctl_reg);
158 } while ((i > 0) && (tmp & HOST_RESET));
161 printf("controller reset failed (0x%x)\n", tmp);
168 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
170 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
171 # ifdef CONFIG_DM_PCI
172 struct udevice *dev = uc_priv->dev;
173 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
175 pci_dev_t pdev = uc_priv->dev;
176 unsigned short vendor;
180 void __iomem *mmio = uc_priv->mmio_base;
181 u32 tmp, cap_save, cmd;
183 void __iomem *port_mmio;
186 debug("ahci_host_init: start\n");
188 cap_save = readl(mmio + HOST_CAP);
189 cap_save &= ((1 << 28) | (1 << 17));
190 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
192 ret = ahci_reset(uc_priv->mmio_base);
196 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
197 writel(cap_save, mmio + HOST_CAP);
198 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
200 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
201 # ifdef CONFIG_DM_PCI
202 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
205 dm_pci_read_config16(dev, 0x92, &tmp16);
206 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
209 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
211 if (vendor == PCI_VENDOR_ID_INTEL) {
213 pci_read_config_word(pdev, 0x92, &tmp16);
215 pci_write_config_word(pdev, 0x92, tmp16);
219 uc_priv->cap = readl(mmio + HOST_CAP);
220 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
221 port_map = uc_priv->port_map;
222 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
224 debug("cap 0x%x port_map 0x%x n_ports %d\n",
225 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
227 #if !defined(CONFIG_DM_SCSI)
228 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
229 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
232 for (i = 0; i < uc_priv->n_ports; i++) {
233 if (!(port_map & (1 << i)))
235 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
236 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
238 /* make sure port is not active */
239 tmp = readl(port_mmio + PORT_CMD);
240 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
241 PORT_CMD_FIS_RX | PORT_CMD_START)) {
242 debug("Port %d is active. Deactivating.\n", i);
243 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
244 PORT_CMD_FIS_RX | PORT_CMD_START);
245 writel_with_flush(tmp, port_mmio + PORT_CMD);
247 /* spec says 500 msecs for each bit, so
248 * this is slightly incorrect.
253 #ifdef CONFIG_SUNXI_AHCI
254 sunxi_dma_init(port_mmio);
257 /* Add the spinup command to whatever mode bits may
258 * already be on in the command register.
260 cmd = readl(port_mmio + PORT_CMD);
261 cmd |= PORT_CMD_SPIN_UP;
262 writel_with_flush(cmd, port_mmio + PORT_CMD);
264 /* Bring up SATA link. */
265 ret = ahci_link_up(uc_priv, i);
267 printf("SATA link %d timeout.\n", i);
270 debug("SATA link ok.\n");
273 /* Clear error status */
274 tmp = readl(port_mmio + PORT_SCR_ERR);
276 writel(tmp, port_mmio + PORT_SCR_ERR);
278 debug("Spinning up device on SATA port %d... ", i);
281 while (j < WAIT_MS_SPINUP) {
282 tmp = readl(port_mmio + PORT_TFDATA);
283 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
286 tmp = readl(port_mmio + PORT_SCR_STAT);
287 tmp &= PORT_SCR_STAT_DET_MASK;
288 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
293 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
294 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
295 debug("SATA link %d down (COMINIT received), retrying...\n", i);
300 printf("Target spinup took %d ms.\n", j);
301 if (j == WAIT_MS_SPINUP)
306 tmp = readl(port_mmio + PORT_SCR_ERR);
307 debug("PORT_SCR_ERR 0x%x\n", tmp);
308 writel(tmp, port_mmio + PORT_SCR_ERR);
310 /* ack any pending irq events for this port */
311 tmp = readl(port_mmio + PORT_IRQ_STAT);
312 debug("PORT_IRQ_STAT 0x%x\n", tmp);
314 writel(tmp, port_mmio + PORT_IRQ_STAT);
316 writel(1 << i, mmio + HOST_IRQ_STAT);
318 /* register linkup ports */
319 tmp = readl(port_mmio + PORT_SCR_STAT);
320 debug("SATA port %d status: 0x%x\n", i, tmp);
321 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
322 uc_priv->link_port_map |= (0x01 << i);
325 tmp = readl(mmio + HOST_CTL);
326 debug("HOST_CTL 0x%x\n", tmp);
327 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
328 tmp = readl(mmio + HOST_CTL);
329 debug("HOST_CTL 0x%x\n", tmp);
330 #if !defined(CONFIG_DM_SCSI)
331 #ifndef CONFIG_SCSI_AHCI_PLAT
332 # ifdef CONFIG_DM_PCI
333 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
334 tmp |= PCI_COMMAND_MASTER;
335 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
337 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
338 tmp |= PCI_COMMAND_MASTER;
339 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
347 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
349 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
350 # if defined(CONFIG_DM_PCI)
351 struct udevice *dev = uc_priv->dev;
353 pci_dev_t pdev = uc_priv->dev;
357 void __iomem *mmio = uc_priv->mmio_base;
358 u32 vers, cap, cap2, impl, speed;
362 vers = readl(mmio + HOST_VERSION);
364 cap2 = readl(mmio + HOST_CAP2);
365 impl = uc_priv->port_map;
367 speed = (cap >> 20) & 0xf;
377 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
380 # ifdef CONFIG_DM_PCI
381 dm_pci_read_config16(dev, 0x0a, &cc);
383 pci_read_config_word(pdev, 0x0a, &cc);
387 else if (cc == 0x0106)
389 else if (cc == 0x0104)
394 printf("AHCI %02x%02x.%02x%02x "
395 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
400 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
406 cap & (1 << 31) ? "64bit " : "",
407 cap & (1 << 30) ? "ncq " : "",
408 cap & (1 << 28) ? "ilck " : "",
409 cap & (1 << 27) ? "stag " : "",
410 cap & (1 << 26) ? "pm " : "",
411 cap & (1 << 25) ? "led " : "",
412 cap & (1 << 24) ? "clo " : "",
413 cap & (1 << 19) ? "nz " : "",
414 cap & (1 << 18) ? "only " : "",
415 cap & (1 << 17) ? "pmp " : "",
416 cap & (1 << 16) ? "fbss " : "",
417 cap & (1 << 15) ? "pio " : "",
418 cap & (1 << 14) ? "slum " : "",
419 cap & (1 << 13) ? "part " : "",
420 cap & (1 << 7) ? "ccc " : "",
421 cap & (1 << 6) ? "ems " : "",
422 cap & (1 << 5) ? "sxs " : "",
423 cap2 & (1 << 2) ? "apst " : "",
424 cap2 & (1 << 1) ? "nvmp " : "",
425 cap2 & (1 << 0) ? "boh " : "");
428 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
429 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
430 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
432 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
435 #if !defined(CONFIG_DM_SCSI)
442 uc_priv->host_flags = ATA_FLAG_SATA
447 uc_priv->pio_mask = 0x1f;
448 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
450 #if !defined(CONFIG_DM_SCSI)
452 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
456 * JMicron-specific fixup:
457 * make sure we're in AHCI mode
459 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
460 if (vendor == 0x197b)
461 dm_pci_write_config8(dev, 0x41, 0xa1);
463 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
467 * JMicron-specific fixup:
468 * make sure we're in AHCI mode
470 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
471 if (vendor == 0x197b)
472 pci_write_config_byte(dev, 0x41, 0xa1);
475 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
476 uc_priv->mmio_base = (void *)plat->base;
479 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
480 /* initialize adapter */
481 rc = ahci_host_init(uc_priv);
485 ahci_print_info(uc_priv);
494 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
496 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
497 unsigned char *buf, int buf_len)
499 struct ahci_ioports *pp = &(uc_priv->port[port]);
500 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
504 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
505 if (sg_count > AHCI_MAX_SG) {
506 printf("Error:Too much sg!\n");
510 for (i = 0; i < sg_count; i++) {
511 /* We assume virt=phys */
512 phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
514 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
515 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
516 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
517 printf("Error: DMA address too high\n");
520 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
521 (buf_len < MAX_DATA_BYTE_COUNT
523 : (MAX_DATA_BYTE_COUNT - 1)));
525 buf_len -= MAX_DATA_BYTE_COUNT;
532 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
534 pp->cmd_slot->opts = cpu_to_le32(opts);
535 pp->cmd_slot->status = 0;
536 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
537 #ifdef CONFIG_PHYS_64BIT
538 pp->cmd_slot->tbl_addr_hi =
539 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
543 static int wait_spinup(void __iomem *port_mmio)
548 start = get_timer(0);
550 tf_data = readl(port_mmio + PORT_TFDATA);
551 if (!(tf_data & ATA_BUSY))
553 } while (get_timer(start) < WAIT_MS_SPINUP);
558 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
560 struct ahci_ioports *pp = &(uc_priv->port[port]);
561 void __iomem *port_mmio = pp->port_mmio;
566 debug("Enter start port: %d\n", port);
567 port_status = readl(port_mmio + PORT_SCR_STAT);
568 debug("Port %d status: %x\n", port, port_status);
569 if ((port_status & 0xf) != 0x03) {
570 printf("No Link on this port!\n");
574 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
577 printf("%s: No mem for table!\n", __func__);
580 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
583 * First item in chunk of DMA memory: 32-slot command table,
584 * 32 bytes each in size
587 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
588 debug("cmd_slot = %p\n", pp->cmd_slot);
589 mem += (AHCI_CMD_SLOT_SZ + 224);
592 * Second item: Received-FIS area
594 pp->rx_fis = virt_to_phys((void *)mem);
595 mem += AHCI_RX_FIS_SZ;
598 * Third item: data area for storing a single command
599 * and its scatter-gather table
601 pp->cmd_tbl = virt_to_phys((void *)mem);
602 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
604 mem += AHCI_CMD_TBL_HDR;
606 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
608 dma_addr = (ulong)pp->cmd_slot;
609 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
610 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
611 dma_addr = (ulong)pp->rx_fis;
612 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
613 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
615 #ifdef CONFIG_SUNXI_AHCI
616 sunxi_dma_init(port_mmio);
619 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
620 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
621 PORT_CMD_START, port_mmio + PORT_CMD);
623 debug("Exit start port %d\n", port);
626 * Make sure interface is not busy based on error and status
627 * information from task file data register before proceeding
629 return wait_spinup(port_mmio);
633 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
634 int fis_len, u8 *buf, int buf_len, u8 is_write)
637 struct ahci_ioports *pp = &(uc_priv->port[port]);
638 void __iomem *port_mmio = pp->port_mmio;
643 debug("Enter %s: for port %d\n", __func__, port);
645 if (port > uc_priv->n_ports) {
646 printf("Invalid port number %d\n", port);
650 port_status = readl(port_mmio + PORT_SCR_STAT);
651 if ((port_status & 0xf) != 0x03) {
652 debug("No Link on port %d!\n", port);
656 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
658 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
659 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
660 ahci_fill_cmd_slot(pp, opts);
662 ahci_dcache_flush_sata_cmd(pp);
663 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
665 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
667 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
668 WAIT_MS_DATAIO, 0x1)) {
669 printf("timeout exit!\n");
673 ahci_dcache_invalidate_range((unsigned long)buf,
674 (unsigned long)buf_len);
675 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
681 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
684 for (i = 0; i < len / 2; i++)
685 target[i] = swab16(src[i]);
686 return (char *)target;
690 * SCSI INQUIRY command operation.
692 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
693 struct scsi_cmd *pccb)
695 static const u8 hdr[] = {
698 0x5, /* claim SPC-3 version compatibility */
704 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
707 /* Clean ccb data buffer */
708 memset(pccb->pdata, 0, pccb->datalen);
710 memcpy(pccb->pdata, hdr, sizeof(hdr));
712 if (pccb->datalen <= 35)
715 memset(fis, 0, sizeof(fis));
716 /* Construct the FIS */
717 fis[0] = 0x27; /* Host to device FIS. */
718 fis[1] = 1 << 7; /* Command FIS. */
719 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
721 /* Read id from sata */
724 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
725 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
726 debug("scsi_ahci: SCSI inquiry command failure.\n");
730 if (!uc_priv->ataid[port]) {
731 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
732 if (!uc_priv->ataid[port]) {
733 printf("%s: No memory for ataid[port]\n", __func__);
738 idbuf = uc_priv->ataid[port];
740 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
741 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
743 memcpy(&pccb->pdata[8], "ATA ", 8);
744 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
745 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
755 * SCSI READ10/WRITE10 command operation.
757 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
758 struct scsi_cmd *pccb, u8 is_write)
763 u8 *user_buffer = pccb->pdata;
764 u32 user_buffer_size = pccb->datalen;
766 /* Retrieve the base LBA number from the ccb structure. */
767 if (pccb->cmd[0] == SCSI_READ16) {
768 memcpy(&lba, pccb->cmd + 2, 8);
769 lba = be64_to_cpu(lba);
772 memcpy(&temp, pccb->cmd + 2, 4);
773 lba = be32_to_cpu(temp);
777 * Retrieve the base LBA number and the block count from
780 * For 10-byte and 16-byte SCSI R/W commands, transfer
781 * length 0 means transfer 0 block of data.
782 * However, for ATA R/W commands, sector count 0 means
783 * 256 or 65536 sectors, not 0 sectors as in SCSI.
785 * WARNING: one or two older ATA drives treat 0 as 0...
787 if (pccb->cmd[0] == SCSI_READ16)
788 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
790 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
792 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
793 is_write ? "write" : "read", blocks, lba);
796 memset(fis, 0, sizeof(fis));
797 fis[0] = 0x27; /* Host to device FIS. */
798 fis[1] = 1 << 7; /* Command FIS. */
799 /* Command byte (read/write). */
800 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
803 u16 now_blocks; /* number of blocks per iteration */
804 u32 transfer_size; /* number of bytes per iteration */
806 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
808 transfer_size = ATA_SECT_SIZE * now_blocks;
809 if (transfer_size > user_buffer_size) {
810 printf("scsi_ahci: Error: buffer too small.\n");
815 * LBA48 SATA command but only use 32bit address range within
816 * that (unless we've enabled 64bit LBA support). The next
817 * smaller command range (28bit) is too small.
819 fis[4] = (lba >> 0) & 0xff;
820 fis[5] = (lba >> 8) & 0xff;
821 fis[6] = (lba >> 16) & 0xff;
822 fis[7] = 1 << 6; /* device reg: set LBA mode */
823 fis[8] = ((lba >> 24) & 0xff);
824 #ifdef CONFIG_SYS_64BIT_LBA
825 if (pccb->cmd[0] == SCSI_READ16) {
826 fis[9] = ((lba >> 32) & 0xff);
827 fis[10] = ((lba >> 40) & 0xff);
831 fis[3] = 0xe0; /* features */
833 /* Block (sector) count */
834 fis[12] = (now_blocks >> 0) & 0xff;
835 fis[13] = (now_blocks >> 8) & 0xff;
837 /* Read/Write from ahci */
838 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
839 sizeof(fis), user_buffer, transfer_size,
841 debug("scsi_ahci: SCSI %s10 command failure.\n",
842 is_write ? "WRITE" : "READ");
846 /* If this transaction is a write, do a following flush.
847 * Writes in u-boot are so rare, and the logic to know when is
848 * the last write and do a flush only there is sufficiently
849 * difficult. Just do a flush after every write. This incurs,
850 * usually, one extra flush when the rare writes do happen.
853 if (-EIO == ata_io_flush(uc_priv, pccb->target))
856 user_buffer += transfer_size;
857 user_buffer_size -= transfer_size;
858 blocks -= now_blocks;
867 * SCSI READ CAPACITY10 command operation.
869 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
870 struct scsi_cmd *pccb)
876 if (!uc_priv->ataid[pccb->target]) {
877 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
879 "\tPlease run SCSI command INQUIRY first!\n");
883 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
884 if (cap64 > 0x100000000ULL)
887 cap = cpu_to_be32(cap64);
888 memcpy(pccb->pdata, &cap, sizeof(cap));
890 block_size = cpu_to_be32((u32)512);
891 memcpy(&pccb->pdata[4], &block_size, 4);
898 * SCSI READ CAPACITY16 command operation.
900 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
901 struct scsi_cmd *pccb)
906 if (!uc_priv->ataid[pccb->target]) {
907 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
909 "\tPlease run SCSI command INQUIRY first!\n");
913 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
914 cap = cpu_to_be64(cap);
915 memcpy(pccb->pdata, &cap, sizeof(cap));
917 block_size = cpu_to_be64((u64)512);
918 memcpy(&pccb->pdata[8], &block_size, 8);
925 * SCSI TEST UNIT READY command operation.
927 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
928 struct scsi_cmd *pccb)
930 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
934 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
936 struct ahci_uc_priv *uc_priv;
937 #ifdef CONFIG_DM_SCSI
938 uc_priv = dev_get_uclass_priv(dev->parent);
944 switch (pccb->cmd[0]) {
947 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
950 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
952 case SCSI_RD_CAPAC10:
953 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
955 case SCSI_RD_CAPAC16:
956 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
959 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
962 ret = ata_scsiop_inquiry(uc_priv, pccb);
965 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
970 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
977 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
982 linkmap = uc_priv->link_port_map;
984 for (i = 0; i < uc_priv->n_ports; i++) {
985 if (((linkmap >> i) & 0x01)) {
986 if (ahci_port_start(uc_priv, (u8) i)) {
987 printf("Can not start port %d\n", i);
996 #ifndef CONFIG_DM_SCSI
997 void scsi_low_level_init(int busdevfunc)
999 struct ahci_uc_priv *uc_priv;
1001 #ifndef CONFIG_SCSI_AHCI_PLAT
1002 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1004 printf("%s: No memory for uc_priv\n", __func__);
1007 uc_priv = probe_ent;
1008 # if defined(CONFIG_DM_PCI)
1009 struct udevice *dev;
1012 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1015 ahci_init_one(uc_priv, dev);
1017 ahci_init_one(uc_priv, busdevfunc);
1020 uc_priv = probe_ent;
1023 ahci_start_ports(uc_priv);
1027 #ifndef CONFIG_SCSI_AHCI_PLAT
1028 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
1029 int ahci_init_one_dm(struct udevice *dev)
1031 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1033 return ahci_init_one(uc_priv, dev);
1038 int ahci_start_ports_dm(struct udevice *dev)
1040 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1042 return ahci_start_ports(uc_priv);
1045 #ifdef CONFIG_SCSI_AHCI_PLAT
1046 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1050 uc_priv->host_flags = ATA_FLAG_SATA
1051 | ATA_FLAG_NO_LEGACY
1054 | ATA_FLAG_NO_ATAPI;
1055 uc_priv->pio_mask = 0x1f;
1056 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1058 uc_priv->mmio_base = base;
1060 /* initialize adapter */
1061 rc = ahci_host_init(uc_priv);
1065 ahci_print_info(uc_priv);
1067 rc = ahci_start_ports(uc_priv);
1073 #ifndef CONFIG_DM_SCSI
1074 int ahci_init(void __iomem *base)
1076 struct ahci_uc_priv *uc_priv;
1078 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1080 printf("%s: No memory for uc_priv\n", __func__);
1084 uc_priv = probe_ent;
1085 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1087 return ahci_init_common(uc_priv, base);
1091 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1093 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1095 return ahci_init_common(uc_priv, base);
1098 void __weak scsi_init(void)
1102 #endif /* CONFIG_SCSI_AHCI_PLAT */
1105 * In the general case of generic rotating media it makes sense to have a
1106 * flush capability. It probably even makes sense in the case of SSDs because
1107 * one cannot always know for sure what kind of internal cache/flush mechanism
1108 * is embodied therein. At first it was planned to invoke this after the last
1109 * write to disk and before rebooting. In practice, knowing, a priori, which
1110 * is the last write is difficult. Because writing to the disk in u-boot is
1111 * very rare, this flush command will be invoked after every block write.
1113 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1116 struct ahci_ioports *pp = &(uc_priv->port[port]);
1117 void __iomem *port_mmio = pp->port_mmio;
1118 u32 cmd_fis_len = 5; /* five dwords */
1120 /* Preset the FIS */
1122 fis[0] = 0x27; /* Host to device FIS. */
1123 fis[1] = 1 << 7; /* Command FIS. */
1124 fis[2] = ATA_CMD_FLUSH_EXT;
1126 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1127 ahci_fill_cmd_slot(pp, cmd_fis_len);
1128 ahci_dcache_flush_sata_cmd(pp);
1129 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1131 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1132 WAIT_MS_FLUSH, 0x1)) {
1133 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1140 static int ahci_scsi_bus_reset(struct udevice *dev)
1142 /* Not implemented */
1147 #ifdef CONFIG_DM_SCSI
1148 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1150 struct udevice *dev;
1153 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1161 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1163 struct ahci_uc_priv *uc_priv;
1164 struct scsi_platdata *uc_plat;
1165 struct udevice *dev;
1168 device_find_first_child(ahci_dev, &dev);
1171 uc_plat = dev_get_uclass_platdata(dev);
1172 uc_plat->base = base;
1173 uc_plat->max_lun = 1;
1174 uc_plat->max_id = 2;
1176 uc_priv = dev_get_uclass_priv(ahci_dev);
1177 ret = ahci_init_one(uc_priv, dev);
1180 ret = ahci_start_ports(uc_priv);
1185 * scsi_scan_dev() scans devices up-to the number of max_id.
1186 * Update max_id if the number of detected ports exceeds max_id.
1187 * This allows SCSI to scan all detected ports.
1189 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1195 #ifdef CONFIG_DM_PCI
1196 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1200 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1203 return ahci_probe_scsi(ahci_dev, base);
1207 struct scsi_ops scsi_ops = {
1208 .exec = ahci_scsi_exec,
1209 .bus_reset = ahci_scsi_bus_reset,
1212 U_BOOT_DRIVER(ahci_scsi) = {
1213 .name = "ahci_scsi",
1218 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1220 return ahci_scsi_exec(dev, pccb);
1223 __weak int scsi_bus_reset(struct udevice *dev)
1225 return ahci_scsi_bus_reset(dev);