1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
7 * with the reference on libata and ahci drvier in kernel
9 * This driver provides a SCSI interface to SATA.
17 #include <asm/processor.h>
18 #include <linux/errno.h>
25 #include <linux/ctype.h>
27 #include <dm/device-internal.h>
30 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
32 #ifndef CONFIG_DM_SCSI
33 struct ahci_uc_priv *probe_ent = NULL;
36 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
39 * Some controllers limit number of blocks they can read/write at once.
40 * Contemporary SSD devices work much faster if the read/write size is aligned
41 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
44 #ifndef MAX_SATA_BLOCKS_READ_WRITE
45 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
48 /* Maximum timeouts for each event */
49 #define WAIT_MS_SPINUP 20000
50 #define WAIT_MS_DATAIO 10000
51 #define WAIT_MS_FLUSH 5000
52 #define WAIT_MS_LINKUP 200
54 #define AHCI_CAP_S64A BIT(31)
56 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
58 return base + 0x100 + (port * 0x80);
61 #define msleep(a) udelay(a * 1000)
63 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
65 const unsigned long start = begin;
66 const unsigned long end = start + len;
68 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
69 flush_dcache_range(start, end);
73 * SATA controller DMAs to physical RAM. Ensure data from the
74 * controller is invalidated from dcache; next access comes from
77 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
79 const unsigned long start = begin;
80 const unsigned long end = start + len;
82 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
83 invalidate_dcache_range(start, end);
87 * Ensure data for SATA controller is flushed out of dcache and
88 * written to physical memory.
90 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
93 AHCI_PORT_PRIV_DMA_SZ);
96 static int waiting_for_cmd_completed(void __iomem *offset,
103 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
106 return (i < timeout_msec) ? 0 : -1;
109 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
113 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
116 * Bring up SATA link.
117 * SATA link bringup time is usually less than 1 ms; only very
118 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 while (j < WAIT_MS_LINKUP) {
121 tmp = readl(port_mmio + PORT_SCR_STAT);
122 tmp &= PORT_SCR_STAT_DET_MASK;
123 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
131 #ifdef CONFIG_SUNXI_AHCI
132 /* The sunxi AHCI controller requires this undocumented setup */
133 static void sunxi_dma_init(void __iomem *port_mmio)
135 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
139 int ahci_reset(void __iomem *base)
142 u32 __iomem *host_ctl_reg = base + HOST_CTL;
143 u32 tmp = readl(host_ctl_reg); /* global controller reset */
145 if ((tmp & HOST_RESET) == 0)
146 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
149 * reset must complete within 1 second, or
150 * the hardware should be considered fried.
154 tmp = readl(host_ctl_reg);
156 } while ((i > 0) && (tmp & HOST_RESET));
159 printf("controller reset failed (0x%x)\n", tmp);
166 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
168 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
169 # ifdef CONFIG_DM_PCI
170 struct udevice *dev = uc_priv->dev;
171 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
173 pci_dev_t pdev = uc_priv->dev;
174 unsigned short vendor;
178 void __iomem *mmio = uc_priv->mmio_base;
179 u32 tmp, cap_save, cmd;
181 void __iomem *port_mmio;
184 debug("ahci_host_init: start\n");
186 cap_save = readl(mmio + HOST_CAP);
187 cap_save &= ((1 << 28) | (1 << 17));
188 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
190 ret = ahci_reset(uc_priv->mmio_base);
194 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
195 writel(cap_save, mmio + HOST_CAP);
196 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
198 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
199 # ifdef CONFIG_DM_PCI
200 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
203 dm_pci_read_config16(dev, 0x92, &tmp16);
204 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
207 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
209 if (vendor == PCI_VENDOR_ID_INTEL) {
211 pci_read_config_word(pdev, 0x92, &tmp16);
213 pci_write_config_word(pdev, 0x92, tmp16);
217 uc_priv->cap = readl(mmio + HOST_CAP);
218 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
219 port_map = uc_priv->port_map;
220 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
222 debug("cap 0x%x port_map 0x%x n_ports %d\n",
223 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
225 #if !defined(CONFIG_DM_SCSI)
226 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
227 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
230 for (i = 0; i < uc_priv->n_ports; i++) {
231 if (!(port_map & (1 << i)))
233 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
234 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
236 /* make sure port is not active */
237 tmp = readl(port_mmio + PORT_CMD);
238 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
239 PORT_CMD_FIS_RX | PORT_CMD_START)) {
240 debug("Port %d is active. Deactivating.\n", i);
241 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
242 PORT_CMD_FIS_RX | PORT_CMD_START);
243 writel_with_flush(tmp, port_mmio + PORT_CMD);
245 /* spec says 500 msecs for each bit, so
246 * this is slightly incorrect.
251 #ifdef CONFIG_SUNXI_AHCI
252 sunxi_dma_init(port_mmio);
255 /* Add the spinup command to whatever mode bits may
256 * already be on in the command register.
258 cmd = readl(port_mmio + PORT_CMD);
259 cmd |= PORT_CMD_SPIN_UP;
260 writel_with_flush(cmd, port_mmio + PORT_CMD);
262 /* Bring up SATA link. */
263 ret = ahci_link_up(uc_priv, i);
265 printf("SATA link %d timeout.\n", i);
268 debug("SATA link ok.\n");
271 /* Clear error status */
272 tmp = readl(port_mmio + PORT_SCR_ERR);
274 writel(tmp, port_mmio + PORT_SCR_ERR);
276 debug("Spinning up device on SATA port %d... ", i);
279 while (j < WAIT_MS_SPINUP) {
280 tmp = readl(port_mmio + PORT_TFDATA);
281 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
284 tmp = readl(port_mmio + PORT_SCR_STAT);
285 tmp &= PORT_SCR_STAT_DET_MASK;
286 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
291 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
292 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
293 debug("SATA link %d down (COMINIT received), retrying...\n", i);
298 printf("Target spinup took %d ms.\n", j);
299 if (j == WAIT_MS_SPINUP)
304 tmp = readl(port_mmio + PORT_SCR_ERR);
305 debug("PORT_SCR_ERR 0x%x\n", tmp);
306 writel(tmp, port_mmio + PORT_SCR_ERR);
308 /* ack any pending irq events for this port */
309 tmp = readl(port_mmio + PORT_IRQ_STAT);
310 debug("PORT_IRQ_STAT 0x%x\n", tmp);
312 writel(tmp, port_mmio + PORT_IRQ_STAT);
314 writel(1 << i, mmio + HOST_IRQ_STAT);
316 /* register linkup ports */
317 tmp = readl(port_mmio + PORT_SCR_STAT);
318 debug("SATA port %d status: 0x%x\n", i, tmp);
319 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
320 uc_priv->link_port_map |= (0x01 << i);
323 tmp = readl(mmio + HOST_CTL);
324 debug("HOST_CTL 0x%x\n", tmp);
325 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
326 tmp = readl(mmio + HOST_CTL);
327 debug("HOST_CTL 0x%x\n", tmp);
328 #if !defined(CONFIG_DM_SCSI)
329 #ifndef CONFIG_SCSI_AHCI_PLAT
330 # ifdef CONFIG_DM_PCI
331 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
332 tmp |= PCI_COMMAND_MASTER;
333 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
335 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
336 tmp |= PCI_COMMAND_MASTER;
337 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
345 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
347 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
348 # if defined(CONFIG_DM_PCI)
349 struct udevice *dev = uc_priv->dev;
351 pci_dev_t pdev = uc_priv->dev;
355 void __iomem *mmio = uc_priv->mmio_base;
356 u32 vers, cap, cap2, impl, speed;
360 vers = readl(mmio + HOST_VERSION);
362 cap2 = readl(mmio + HOST_CAP2);
363 impl = uc_priv->port_map;
365 speed = (cap >> 20) & 0xf;
375 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
378 # ifdef CONFIG_DM_PCI
379 dm_pci_read_config16(dev, 0x0a, &cc);
381 pci_read_config_word(pdev, 0x0a, &cc);
385 else if (cc == 0x0106)
387 else if (cc == 0x0104)
392 printf("AHCI %02x%02x.%02x%02x "
393 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
398 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
404 cap & (1 << 31) ? "64bit " : "",
405 cap & (1 << 30) ? "ncq " : "",
406 cap & (1 << 28) ? "ilck " : "",
407 cap & (1 << 27) ? "stag " : "",
408 cap & (1 << 26) ? "pm " : "",
409 cap & (1 << 25) ? "led " : "",
410 cap & (1 << 24) ? "clo " : "",
411 cap & (1 << 19) ? "nz " : "",
412 cap & (1 << 18) ? "only " : "",
413 cap & (1 << 17) ? "pmp " : "",
414 cap & (1 << 16) ? "fbss " : "",
415 cap & (1 << 15) ? "pio " : "",
416 cap & (1 << 14) ? "slum " : "",
417 cap & (1 << 13) ? "part " : "",
418 cap & (1 << 7) ? "ccc " : "",
419 cap & (1 << 6) ? "ems " : "",
420 cap & (1 << 5) ? "sxs " : "",
421 cap2 & (1 << 2) ? "apst " : "",
422 cap2 & (1 << 1) ? "nvmp " : "",
423 cap2 & (1 << 0) ? "boh " : "");
426 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
427 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
428 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
430 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
433 #if !defined(CONFIG_DM_SCSI)
440 uc_priv->host_flags = ATA_FLAG_SATA
445 uc_priv->pio_mask = 0x1f;
446 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
448 #if !defined(CONFIG_DM_SCSI)
450 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
454 * JMicron-specific fixup:
455 * make sure we're in AHCI mode
457 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
458 if (vendor == 0x197b)
459 dm_pci_write_config8(dev, 0x41, 0xa1);
461 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
465 * JMicron-specific fixup:
466 * make sure we're in AHCI mode
468 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
469 if (vendor == 0x197b)
470 pci_write_config_byte(dev, 0x41, 0xa1);
473 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
474 uc_priv->mmio_base = (void *)plat->base;
477 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
478 /* initialize adapter */
479 rc = ahci_host_init(uc_priv);
483 ahci_print_info(uc_priv);
492 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
494 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
495 unsigned char *buf, int buf_len)
497 struct ahci_ioports *pp = &(uc_priv->port[port]);
498 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
502 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
503 if (sg_count > AHCI_MAX_SG) {
504 printf("Error:Too much sg!\n");
508 for (i = 0; i < sg_count; i++) {
509 /* We assume virt=phys */
510 phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
512 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
513 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
514 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
515 printf("Error: DMA address too high\n");
518 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
519 (buf_len < MAX_DATA_BYTE_COUNT
521 : (MAX_DATA_BYTE_COUNT - 1)));
523 buf_len -= MAX_DATA_BYTE_COUNT;
530 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
532 pp->cmd_slot->opts = cpu_to_le32(opts);
533 pp->cmd_slot->status = 0;
534 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
535 #ifdef CONFIG_PHYS_64BIT
536 pp->cmd_slot->tbl_addr_hi =
537 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
541 static int wait_spinup(void __iomem *port_mmio)
546 start = get_timer(0);
548 tf_data = readl(port_mmio + PORT_TFDATA);
549 if (!(tf_data & ATA_BUSY))
551 } while (get_timer(start) < WAIT_MS_SPINUP);
556 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
558 struct ahci_ioports *pp = &(uc_priv->port[port]);
559 void __iomem *port_mmio = pp->port_mmio;
564 debug("Enter start port: %d\n", port);
565 port_status = readl(port_mmio + PORT_SCR_STAT);
566 debug("Port %d status: %x\n", port, port_status);
567 if ((port_status & 0xf) != 0x03) {
568 printf("No Link on this port!\n");
572 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
575 printf("%s: No mem for table!\n", __func__);
578 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
581 * First item in chunk of DMA memory: 32-slot command table,
582 * 32 bytes each in size
585 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
586 debug("cmd_slot = %p\n", pp->cmd_slot);
587 mem += (AHCI_CMD_SLOT_SZ + 224);
590 * Second item: Received-FIS area
592 pp->rx_fis = virt_to_phys((void *)mem);
593 mem += AHCI_RX_FIS_SZ;
596 * Third item: data area for storing a single command
597 * and its scatter-gather table
599 pp->cmd_tbl = virt_to_phys((void *)mem);
600 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
602 mem += AHCI_CMD_TBL_HDR;
604 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
606 dma_addr = (ulong)pp->cmd_slot;
607 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
608 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
609 dma_addr = (ulong)pp->rx_fis;
610 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
611 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
613 #ifdef CONFIG_SUNXI_AHCI
614 sunxi_dma_init(port_mmio);
617 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
618 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
619 PORT_CMD_START, port_mmio + PORT_CMD);
621 debug("Exit start port %d\n", port);
624 * Make sure interface is not busy based on error and status
625 * information from task file data register before proceeding
627 return wait_spinup(port_mmio);
631 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
632 int fis_len, u8 *buf, int buf_len, u8 is_write)
635 struct ahci_ioports *pp = &(uc_priv->port[port]);
636 void __iomem *port_mmio = pp->port_mmio;
641 debug("Enter %s: for port %d\n", __func__, port);
643 if (port > uc_priv->n_ports) {
644 printf("Invalid port number %d\n", port);
648 port_status = readl(port_mmio + PORT_SCR_STAT);
649 if ((port_status & 0xf) != 0x03) {
650 debug("No Link on port %d!\n", port);
654 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
656 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
657 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
658 ahci_fill_cmd_slot(pp, opts);
660 ahci_dcache_flush_sata_cmd(pp);
661 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
663 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
665 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
666 WAIT_MS_DATAIO, 0x1)) {
667 printf("timeout exit!\n");
671 ahci_dcache_invalidate_range((unsigned long)buf,
672 (unsigned long)buf_len);
673 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
679 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
682 for (i = 0; i < len / 2; i++)
683 target[i] = swab16(src[i]);
684 return (char *)target;
688 * SCSI INQUIRY command operation.
690 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
691 struct scsi_cmd *pccb)
693 static const u8 hdr[] = {
696 0x5, /* claim SPC-3 version compatibility */
702 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
705 /* Clean ccb data buffer */
706 memset(pccb->pdata, 0, pccb->datalen);
708 memcpy(pccb->pdata, hdr, sizeof(hdr));
710 if (pccb->datalen <= 35)
713 memset(fis, 0, sizeof(fis));
714 /* Construct the FIS */
715 fis[0] = 0x27; /* Host to device FIS. */
716 fis[1] = 1 << 7; /* Command FIS. */
717 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
719 /* Read id from sata */
722 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
723 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
724 debug("scsi_ahci: SCSI inquiry command failure.\n");
728 if (!uc_priv->ataid[port]) {
729 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
730 if (!uc_priv->ataid[port]) {
731 printf("%s: No memory for ataid[port]\n", __func__);
736 idbuf = uc_priv->ataid[port];
738 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
739 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
741 memcpy(&pccb->pdata[8], "ATA ", 8);
742 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
743 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
753 * SCSI READ10/WRITE10 command operation.
755 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
756 struct scsi_cmd *pccb, u8 is_write)
761 u8 *user_buffer = pccb->pdata;
762 u32 user_buffer_size = pccb->datalen;
764 /* Retrieve the base LBA number from the ccb structure. */
765 if (pccb->cmd[0] == SCSI_READ16) {
766 memcpy(&lba, pccb->cmd + 2, 8);
767 lba = be64_to_cpu(lba);
770 memcpy(&temp, pccb->cmd + 2, 4);
771 lba = be32_to_cpu(temp);
775 * Retrieve the base LBA number and the block count from
778 * For 10-byte and 16-byte SCSI R/W commands, transfer
779 * length 0 means transfer 0 block of data.
780 * However, for ATA R/W commands, sector count 0 means
781 * 256 or 65536 sectors, not 0 sectors as in SCSI.
783 * WARNING: one or two older ATA drives treat 0 as 0...
785 if (pccb->cmd[0] == SCSI_READ16)
786 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
788 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
790 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
791 is_write ? "write" : "read", blocks, lba);
794 memset(fis, 0, sizeof(fis));
795 fis[0] = 0x27; /* Host to device FIS. */
796 fis[1] = 1 << 7; /* Command FIS. */
797 /* Command byte (read/write). */
798 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
801 u16 now_blocks; /* number of blocks per iteration */
802 u32 transfer_size; /* number of bytes per iteration */
804 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
806 transfer_size = ATA_SECT_SIZE * now_blocks;
807 if (transfer_size > user_buffer_size) {
808 printf("scsi_ahci: Error: buffer too small.\n");
813 * LBA48 SATA command but only use 32bit address range within
814 * that (unless we've enabled 64bit LBA support). The next
815 * smaller command range (28bit) is too small.
817 fis[4] = (lba >> 0) & 0xff;
818 fis[5] = (lba >> 8) & 0xff;
819 fis[6] = (lba >> 16) & 0xff;
820 fis[7] = 1 << 6; /* device reg: set LBA mode */
821 fis[8] = ((lba >> 24) & 0xff);
822 #ifdef CONFIG_SYS_64BIT_LBA
823 if (pccb->cmd[0] == SCSI_READ16) {
824 fis[9] = ((lba >> 32) & 0xff);
825 fis[10] = ((lba >> 40) & 0xff);
829 fis[3] = 0xe0; /* features */
831 /* Block (sector) count */
832 fis[12] = (now_blocks >> 0) & 0xff;
833 fis[13] = (now_blocks >> 8) & 0xff;
835 /* Read/Write from ahci */
836 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
837 sizeof(fis), user_buffer, transfer_size,
839 debug("scsi_ahci: SCSI %s10 command failure.\n",
840 is_write ? "WRITE" : "READ");
844 /* If this transaction is a write, do a following flush.
845 * Writes in u-boot are so rare, and the logic to know when is
846 * the last write and do a flush only there is sufficiently
847 * difficult. Just do a flush after every write. This incurs,
848 * usually, one extra flush when the rare writes do happen.
851 if (-EIO == ata_io_flush(uc_priv, pccb->target))
854 user_buffer += transfer_size;
855 user_buffer_size -= transfer_size;
856 blocks -= now_blocks;
865 * SCSI READ CAPACITY10 command operation.
867 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
868 struct scsi_cmd *pccb)
874 if (!uc_priv->ataid[pccb->target]) {
875 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
877 "\tPlease run SCSI command INQUIRY first!\n");
881 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
882 if (cap64 > 0x100000000ULL)
885 cap = cpu_to_be32(cap64);
886 memcpy(pccb->pdata, &cap, sizeof(cap));
888 block_size = cpu_to_be32((u32)512);
889 memcpy(&pccb->pdata[4], &block_size, 4);
896 * SCSI READ CAPACITY16 command operation.
898 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
899 struct scsi_cmd *pccb)
904 if (!uc_priv->ataid[pccb->target]) {
905 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
907 "\tPlease run SCSI command INQUIRY first!\n");
911 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
912 cap = cpu_to_be64(cap);
913 memcpy(pccb->pdata, &cap, sizeof(cap));
915 block_size = cpu_to_be64((u64)512);
916 memcpy(&pccb->pdata[8], &block_size, 8);
923 * SCSI TEST UNIT READY command operation.
925 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
926 struct scsi_cmd *pccb)
928 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
932 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
934 struct ahci_uc_priv *uc_priv;
935 #ifdef CONFIG_DM_SCSI
936 uc_priv = dev_get_uclass_priv(dev->parent);
942 switch (pccb->cmd[0]) {
945 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
948 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
950 case SCSI_RD_CAPAC10:
951 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
953 case SCSI_RD_CAPAC16:
954 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
957 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
960 ret = ata_scsiop_inquiry(uc_priv, pccb);
963 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
968 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
975 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
980 linkmap = uc_priv->link_port_map;
982 for (i = 0; i < uc_priv->n_ports; i++) {
983 if (((linkmap >> i) & 0x01)) {
984 if (ahci_port_start(uc_priv, (u8) i)) {
985 printf("Can not start port %d\n", i);
994 #ifndef CONFIG_DM_SCSI
995 void scsi_low_level_init(int busdevfunc)
997 struct ahci_uc_priv *uc_priv;
999 #ifndef CONFIG_SCSI_AHCI_PLAT
1000 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1002 printf("%s: No memory for uc_priv\n", __func__);
1005 uc_priv = probe_ent;
1006 # if defined(CONFIG_DM_PCI)
1007 struct udevice *dev;
1010 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1013 ahci_init_one(uc_priv, dev);
1015 ahci_init_one(uc_priv, busdevfunc);
1018 uc_priv = probe_ent;
1021 ahci_start_ports(uc_priv);
1025 #ifndef CONFIG_SCSI_AHCI_PLAT
1026 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
1027 int ahci_init_one_dm(struct udevice *dev)
1029 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1031 return ahci_init_one(uc_priv, dev);
1036 int ahci_start_ports_dm(struct udevice *dev)
1038 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1040 return ahci_start_ports(uc_priv);
1043 #ifdef CONFIG_SCSI_AHCI_PLAT
1044 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1048 uc_priv->host_flags = ATA_FLAG_SATA
1049 | ATA_FLAG_NO_LEGACY
1052 | ATA_FLAG_NO_ATAPI;
1053 uc_priv->pio_mask = 0x1f;
1054 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1056 uc_priv->mmio_base = base;
1058 /* initialize adapter */
1059 rc = ahci_host_init(uc_priv);
1063 ahci_print_info(uc_priv);
1065 rc = ahci_start_ports(uc_priv);
1071 #ifndef CONFIG_DM_SCSI
1072 int ahci_init(void __iomem *base)
1074 struct ahci_uc_priv *uc_priv;
1076 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1078 printf("%s: No memory for uc_priv\n", __func__);
1082 uc_priv = probe_ent;
1083 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1085 return ahci_init_common(uc_priv, base);
1089 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1091 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1093 return ahci_init_common(uc_priv, base);
1096 void __weak scsi_init(void)
1100 #endif /* CONFIG_SCSI_AHCI_PLAT */
1103 * In the general case of generic rotating media it makes sense to have a
1104 * flush capability. It probably even makes sense in the case of SSDs because
1105 * one cannot always know for sure what kind of internal cache/flush mechanism
1106 * is embodied therein. At first it was planned to invoke this after the last
1107 * write to disk and before rebooting. In practice, knowing, a priori, which
1108 * is the last write is difficult. Because writing to the disk in u-boot is
1109 * very rare, this flush command will be invoked after every block write.
1111 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1114 struct ahci_ioports *pp = &(uc_priv->port[port]);
1115 void __iomem *port_mmio = pp->port_mmio;
1116 u32 cmd_fis_len = 5; /* five dwords */
1118 /* Preset the FIS */
1120 fis[0] = 0x27; /* Host to device FIS. */
1121 fis[1] = 1 << 7; /* Command FIS. */
1122 fis[2] = ATA_CMD_FLUSH_EXT;
1124 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1125 ahci_fill_cmd_slot(pp, cmd_fis_len);
1126 ahci_dcache_flush_sata_cmd(pp);
1127 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1129 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1130 WAIT_MS_FLUSH, 0x1)) {
1131 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1138 static int ahci_scsi_bus_reset(struct udevice *dev)
1140 /* Not implemented */
1145 #ifdef CONFIG_DM_SCSI
1146 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1148 struct udevice *dev;
1151 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1159 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1161 struct ahci_uc_priv *uc_priv;
1162 struct scsi_platdata *uc_plat;
1163 struct udevice *dev;
1166 device_find_first_child(ahci_dev, &dev);
1169 uc_plat = dev_get_uclass_platdata(dev);
1170 uc_plat->base = base;
1171 uc_plat->max_lun = 1;
1172 uc_plat->max_id = 2;
1174 uc_priv = dev_get_uclass_priv(ahci_dev);
1175 ret = ahci_init_one(uc_priv, dev);
1178 ret = ahci_start_ports(uc_priv);
1183 * scsi_scan_dev() scans devices up-to the number of max_id.
1184 * Update max_id if the number of detected ports exceeds max_id.
1185 * This allows SCSI to scan all detected ports.
1187 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1193 #ifdef CONFIG_DM_PCI
1194 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1198 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1201 return ahci_probe_scsi(ahci_dev, base);
1205 struct scsi_ops scsi_ops = {
1206 .exec = ahci_scsi_exec,
1207 .bus_reset = ahci_scsi_bus_reset,
1210 U_BOOT_DRIVER(ahci_scsi) = {
1211 .name = "ahci_scsi",
1216 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1218 return ahci_scsi_exec(dev, pccb);
1221 __weak int scsi_bus_reset(struct udevice *dev)
1223 return ahci_scsi_bus_reset(dev);