1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
7 * with the reference on libata and ahci drvier in kernel
9 * This driver provides a SCSI interface to SATA.
16 #include <asm/processor.h>
17 #include <linux/errno.h>
24 #include <linux/ctype.h>
26 #include <dm/device-internal.h>
29 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
31 #ifndef CONFIG_DM_SCSI
32 struct ahci_uc_priv *probe_ent = NULL;
35 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
38 * Some controllers limit number of blocks they can read/write at once.
39 * Contemporary SSD devices work much faster if the read/write size is aligned
40 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
43 #ifndef MAX_SATA_BLOCKS_READ_WRITE
44 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
47 /* Maximum timeouts for each event */
48 #define WAIT_MS_SPINUP 20000
49 #define WAIT_MS_DATAIO 10000
50 #define WAIT_MS_FLUSH 5000
51 #define WAIT_MS_LINKUP 200
53 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
55 return base + 0x100 + (port * 0x80);
58 #define msleep(a) udelay(a * 1000)
60 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
62 const unsigned long start = begin;
63 const unsigned long end = start + len;
65 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
66 flush_dcache_range(start, end);
70 * SATA controller DMAs to physical RAM. Ensure data from the
71 * controller is invalidated from dcache; next access comes from
74 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
76 const unsigned long start = begin;
77 const unsigned long end = start + len;
79 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
80 invalidate_dcache_range(start, end);
84 * Ensure data for SATA controller is flushed out of dcache and
85 * written to physical memory.
87 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
89 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
90 AHCI_PORT_PRIV_DMA_SZ);
93 static int waiting_for_cmd_completed(void __iomem *offset,
100 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
103 return (i < timeout_msec) ? 0 : -1;
106 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
110 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
113 * Bring up SATA link.
114 * SATA link bringup time is usually less than 1 ms; only very
115 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
117 while (j < WAIT_MS_LINKUP) {
118 tmp = readl(port_mmio + PORT_SCR_STAT);
119 tmp &= PORT_SCR_STAT_DET_MASK;
120 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
128 #ifdef CONFIG_SUNXI_AHCI
129 /* The sunxi AHCI controller requires this undocumented setup */
130 static void sunxi_dma_init(void __iomem *port_mmio)
132 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
136 int ahci_reset(void __iomem *base)
139 u32 __iomem *host_ctl_reg = base + HOST_CTL;
140 u32 tmp = readl(host_ctl_reg); /* global controller reset */
142 if ((tmp & HOST_RESET) == 0)
143 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
146 * reset must complete within 1 second, or
147 * the hardware should be considered fried.
151 tmp = readl(host_ctl_reg);
153 } while ((i > 0) && (tmp & HOST_RESET));
156 printf("controller reset failed (0x%x)\n", tmp);
163 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
165 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
166 # ifdef CONFIG_DM_PCI
167 struct udevice *dev = uc_priv->dev;
168 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
170 pci_dev_t pdev = uc_priv->dev;
171 unsigned short vendor;
175 void __iomem *mmio = uc_priv->mmio_base;
176 u32 tmp, cap_save, cmd;
178 void __iomem *port_mmio;
181 debug("ahci_host_init: start\n");
183 cap_save = readl(mmio + HOST_CAP);
184 cap_save &= ((1 << 28) | (1 << 17));
185 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
187 ret = ahci_reset(uc_priv->mmio_base);
191 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
192 writel(cap_save, mmio + HOST_CAP);
193 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
195 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
196 # ifdef CONFIG_DM_PCI
197 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
200 dm_pci_read_config16(dev, 0x92, &tmp16);
201 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
204 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
206 if (vendor == PCI_VENDOR_ID_INTEL) {
208 pci_read_config_word(pdev, 0x92, &tmp16);
210 pci_write_config_word(pdev, 0x92, tmp16);
214 uc_priv->cap = readl(mmio + HOST_CAP);
215 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
216 port_map = uc_priv->port_map;
217 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
219 debug("cap 0x%x port_map 0x%x n_ports %d\n",
220 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
222 #if !defined(CONFIG_DM_SCSI)
223 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
224 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
227 for (i = 0; i < uc_priv->n_ports; i++) {
228 if (!(port_map & (1 << i)))
230 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
231 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
233 /* make sure port is not active */
234 tmp = readl(port_mmio + PORT_CMD);
235 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
236 PORT_CMD_FIS_RX | PORT_CMD_START)) {
237 debug("Port %d is active. Deactivating.\n", i);
238 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
239 PORT_CMD_FIS_RX | PORT_CMD_START);
240 writel_with_flush(tmp, port_mmio + PORT_CMD);
242 /* spec says 500 msecs for each bit, so
243 * this is slightly incorrect.
248 #ifdef CONFIG_SUNXI_AHCI
249 sunxi_dma_init(port_mmio);
252 /* Add the spinup command to whatever mode bits may
253 * already be on in the command register.
255 cmd = readl(port_mmio + PORT_CMD);
256 cmd |= PORT_CMD_SPIN_UP;
257 writel_with_flush(cmd, port_mmio + PORT_CMD);
259 /* Bring up SATA link. */
260 ret = ahci_link_up(uc_priv, i);
262 printf("SATA link %d timeout.\n", i);
265 debug("SATA link ok.\n");
268 /* Clear error status */
269 tmp = readl(port_mmio + PORT_SCR_ERR);
271 writel(tmp, port_mmio + PORT_SCR_ERR);
273 debug("Spinning up device on SATA port %d... ", i);
276 while (j < WAIT_MS_SPINUP) {
277 tmp = readl(port_mmio + PORT_TFDATA);
278 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
281 tmp = readl(port_mmio + PORT_SCR_STAT);
282 tmp &= PORT_SCR_STAT_DET_MASK;
283 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
288 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
289 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
290 debug("SATA link %d down (COMINIT received), retrying...\n", i);
295 printf("Target spinup took %d ms.\n", j);
296 if (j == WAIT_MS_SPINUP)
301 tmp = readl(port_mmio + PORT_SCR_ERR);
302 debug("PORT_SCR_ERR 0x%x\n", tmp);
303 writel(tmp, port_mmio + PORT_SCR_ERR);
305 /* ack any pending irq events for this port */
306 tmp = readl(port_mmio + PORT_IRQ_STAT);
307 debug("PORT_IRQ_STAT 0x%x\n", tmp);
309 writel(tmp, port_mmio + PORT_IRQ_STAT);
311 writel(1 << i, mmio + HOST_IRQ_STAT);
313 /* register linkup ports */
314 tmp = readl(port_mmio + PORT_SCR_STAT);
315 debug("SATA port %d status: 0x%x\n", i, tmp);
316 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
317 uc_priv->link_port_map |= (0x01 << i);
320 tmp = readl(mmio + HOST_CTL);
321 debug("HOST_CTL 0x%x\n", tmp);
322 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
323 tmp = readl(mmio + HOST_CTL);
324 debug("HOST_CTL 0x%x\n", tmp);
325 #if !defined(CONFIG_DM_SCSI)
326 #ifndef CONFIG_SCSI_AHCI_PLAT
327 # ifdef CONFIG_DM_PCI
328 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
329 tmp |= PCI_COMMAND_MASTER;
330 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
332 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
333 tmp |= PCI_COMMAND_MASTER;
334 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
342 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
344 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
345 # if defined(CONFIG_DM_PCI)
346 struct udevice *dev = uc_priv->dev;
348 pci_dev_t pdev = uc_priv->dev;
352 void __iomem *mmio = uc_priv->mmio_base;
353 u32 vers, cap, cap2, impl, speed;
357 vers = readl(mmio + HOST_VERSION);
359 cap2 = readl(mmio + HOST_CAP2);
360 impl = uc_priv->port_map;
362 speed = (cap >> 20) & 0xf;
372 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
375 # ifdef CONFIG_DM_PCI
376 dm_pci_read_config16(dev, 0x0a, &cc);
378 pci_read_config_word(pdev, 0x0a, &cc);
382 else if (cc == 0x0106)
384 else if (cc == 0x0104)
389 printf("AHCI %02x%02x.%02x%02x "
390 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
395 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
401 cap & (1 << 31) ? "64bit " : "",
402 cap & (1 << 30) ? "ncq " : "",
403 cap & (1 << 28) ? "ilck " : "",
404 cap & (1 << 27) ? "stag " : "",
405 cap & (1 << 26) ? "pm " : "",
406 cap & (1 << 25) ? "led " : "",
407 cap & (1 << 24) ? "clo " : "",
408 cap & (1 << 19) ? "nz " : "",
409 cap & (1 << 18) ? "only " : "",
410 cap & (1 << 17) ? "pmp " : "",
411 cap & (1 << 16) ? "fbss " : "",
412 cap & (1 << 15) ? "pio " : "",
413 cap & (1 << 14) ? "slum " : "",
414 cap & (1 << 13) ? "part " : "",
415 cap & (1 << 7) ? "ccc " : "",
416 cap & (1 << 6) ? "ems " : "",
417 cap & (1 << 5) ? "sxs " : "",
418 cap2 & (1 << 2) ? "apst " : "",
419 cap2 & (1 << 1) ? "nvmp " : "",
420 cap2 & (1 << 0) ? "boh " : "");
423 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
424 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
425 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
427 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
430 #if !defined(CONFIG_DM_SCSI)
437 uc_priv->host_flags = ATA_FLAG_SATA
442 uc_priv->pio_mask = 0x1f;
443 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
445 #if !defined(CONFIG_DM_SCSI)
447 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
451 * JMicron-specific fixup:
452 * make sure we're in AHCI mode
454 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
455 if (vendor == 0x197b)
456 dm_pci_write_config8(dev, 0x41, 0xa1);
458 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
462 * JMicron-specific fixup:
463 * make sure we're in AHCI mode
465 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
466 if (vendor == 0x197b)
467 pci_write_config_byte(dev, 0x41, 0xa1);
470 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
471 uc_priv->mmio_base = (void *)plat->base;
474 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
475 /* initialize adapter */
476 rc = ahci_host_init(uc_priv);
480 ahci_print_info(uc_priv);
489 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
491 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
492 unsigned char *buf, int buf_len)
494 struct ahci_ioports *pp = &(uc_priv->port[port]);
495 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
499 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
500 if (sg_count > AHCI_MAX_SG) {
501 printf("Error:Too much sg!\n");
505 for (i = 0; i < sg_count; i++) {
507 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
508 ahci_sg->addr_hi = 0;
509 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
510 (buf_len < MAX_DATA_BYTE_COUNT
512 : (MAX_DATA_BYTE_COUNT - 1)));
514 buf_len -= MAX_DATA_BYTE_COUNT;
521 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
523 pp->cmd_slot->opts = cpu_to_le32(opts);
524 pp->cmd_slot->status = 0;
525 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
526 #ifdef CONFIG_PHYS_64BIT
527 pp->cmd_slot->tbl_addr_hi =
528 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
532 static int wait_spinup(void __iomem *port_mmio)
537 start = get_timer(0);
539 tf_data = readl(port_mmio + PORT_TFDATA);
540 if (!(tf_data & ATA_BUSY))
542 } while (get_timer(start) < WAIT_MS_SPINUP);
547 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
549 struct ahci_ioports *pp = &(uc_priv->port[port]);
550 void __iomem *port_mmio = pp->port_mmio;
555 debug("Enter start port: %d\n", port);
556 port_status = readl(port_mmio + PORT_SCR_STAT);
557 debug("Port %d status: %x\n", port, port_status);
558 if ((port_status & 0xf) != 0x03) {
559 printf("No Link on this port!\n");
563 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
566 printf("%s: No mem for table!\n", __func__);
569 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
572 * First item in chunk of DMA memory: 32-slot command table,
573 * 32 bytes each in size
576 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
577 debug("cmd_slot = %p\n", pp->cmd_slot);
578 mem += (AHCI_CMD_SLOT_SZ + 224);
581 * Second item: Received-FIS area
583 pp->rx_fis = virt_to_phys((void *)mem);
584 mem += AHCI_RX_FIS_SZ;
587 * Third item: data area for storing a single command
588 * and its scatter-gather table
590 pp->cmd_tbl = virt_to_phys((void *)mem);
591 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
593 mem += AHCI_CMD_TBL_HDR;
595 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
597 dma_addr = (ulong)pp->cmd_slot;
598 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
599 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
600 dma_addr = (ulong)pp->rx_fis;
601 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
602 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
604 #ifdef CONFIG_SUNXI_AHCI
605 sunxi_dma_init(port_mmio);
608 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
609 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
610 PORT_CMD_START, port_mmio + PORT_CMD);
612 debug("Exit start port %d\n", port);
615 * Make sure interface is not busy based on error and status
616 * information from task file data register before proceeding
618 return wait_spinup(port_mmio);
622 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
623 int fis_len, u8 *buf, int buf_len, u8 is_write)
626 struct ahci_ioports *pp = &(uc_priv->port[port]);
627 void __iomem *port_mmio = pp->port_mmio;
632 debug("Enter %s: for port %d\n", __func__, port);
634 if (port > uc_priv->n_ports) {
635 printf("Invalid port number %d\n", port);
639 port_status = readl(port_mmio + PORT_SCR_STAT);
640 if ((port_status & 0xf) != 0x03) {
641 debug("No Link on port %d!\n", port);
645 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
647 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
648 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
649 ahci_fill_cmd_slot(pp, opts);
651 ahci_dcache_flush_sata_cmd(pp);
652 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
654 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
656 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
657 WAIT_MS_DATAIO, 0x1)) {
658 printf("timeout exit!\n");
662 ahci_dcache_invalidate_range((unsigned long)buf,
663 (unsigned long)buf_len);
664 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
670 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
673 for (i = 0; i < len / 2; i++)
674 target[i] = swab16(src[i]);
675 return (char *)target;
679 * SCSI INQUIRY command operation.
681 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
682 struct scsi_cmd *pccb)
684 static const u8 hdr[] = {
687 0x5, /* claim SPC-3 version compatibility */
693 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
696 /* Clean ccb data buffer */
697 memset(pccb->pdata, 0, pccb->datalen);
699 memcpy(pccb->pdata, hdr, sizeof(hdr));
701 if (pccb->datalen <= 35)
704 memset(fis, 0, sizeof(fis));
705 /* Construct the FIS */
706 fis[0] = 0x27; /* Host to device FIS. */
707 fis[1] = 1 << 7; /* Command FIS. */
708 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
710 /* Read id from sata */
713 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
714 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
715 debug("scsi_ahci: SCSI inquiry command failure.\n");
719 if (!uc_priv->ataid[port]) {
720 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
721 if (!uc_priv->ataid[port]) {
722 printf("%s: No memory for ataid[port]\n", __func__);
727 idbuf = uc_priv->ataid[port];
729 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
730 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
732 memcpy(&pccb->pdata[8], "ATA ", 8);
733 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
734 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
744 * SCSI READ10/WRITE10 command operation.
746 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
747 struct scsi_cmd *pccb, u8 is_write)
752 u8 *user_buffer = pccb->pdata;
753 u32 user_buffer_size = pccb->datalen;
755 /* Retrieve the base LBA number from the ccb structure. */
756 if (pccb->cmd[0] == SCSI_READ16) {
757 memcpy(&lba, pccb->cmd + 2, 8);
758 lba = be64_to_cpu(lba);
761 memcpy(&temp, pccb->cmd + 2, 4);
762 lba = be32_to_cpu(temp);
766 * Retrieve the base LBA number and the block count from
769 * For 10-byte and 16-byte SCSI R/W commands, transfer
770 * length 0 means transfer 0 block of data.
771 * However, for ATA R/W commands, sector count 0 means
772 * 256 or 65536 sectors, not 0 sectors as in SCSI.
774 * WARNING: one or two older ATA drives treat 0 as 0...
776 if (pccb->cmd[0] == SCSI_READ16)
777 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
779 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
781 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
782 is_write ? "write" : "read", blocks, lba);
785 memset(fis, 0, sizeof(fis));
786 fis[0] = 0x27; /* Host to device FIS. */
787 fis[1] = 1 << 7; /* Command FIS. */
788 /* Command byte (read/write). */
789 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
792 u16 now_blocks; /* number of blocks per iteration */
793 u32 transfer_size; /* number of bytes per iteration */
795 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
797 transfer_size = ATA_SECT_SIZE * now_blocks;
798 if (transfer_size > user_buffer_size) {
799 printf("scsi_ahci: Error: buffer too small.\n");
804 * LBA48 SATA command but only use 32bit address range within
805 * that (unless we've enabled 64bit LBA support). The next
806 * smaller command range (28bit) is too small.
808 fis[4] = (lba >> 0) & 0xff;
809 fis[5] = (lba >> 8) & 0xff;
810 fis[6] = (lba >> 16) & 0xff;
811 fis[7] = 1 << 6; /* device reg: set LBA mode */
812 fis[8] = ((lba >> 24) & 0xff);
813 #ifdef CONFIG_SYS_64BIT_LBA
814 if (pccb->cmd[0] == SCSI_READ16) {
815 fis[9] = ((lba >> 32) & 0xff);
816 fis[10] = ((lba >> 40) & 0xff);
820 fis[3] = 0xe0; /* features */
822 /* Block (sector) count */
823 fis[12] = (now_blocks >> 0) & 0xff;
824 fis[13] = (now_blocks >> 8) & 0xff;
826 /* Read/Write from ahci */
827 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
828 sizeof(fis), user_buffer, transfer_size,
830 debug("scsi_ahci: SCSI %s10 command failure.\n",
831 is_write ? "WRITE" : "READ");
835 /* If this transaction is a write, do a following flush.
836 * Writes in u-boot are so rare, and the logic to know when is
837 * the last write and do a flush only there is sufficiently
838 * difficult. Just do a flush after every write. This incurs,
839 * usually, one extra flush when the rare writes do happen.
842 if (-EIO == ata_io_flush(uc_priv, pccb->target))
845 user_buffer += transfer_size;
846 user_buffer_size -= transfer_size;
847 blocks -= now_blocks;
856 * SCSI READ CAPACITY10 command operation.
858 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
859 struct scsi_cmd *pccb)
865 if (!uc_priv->ataid[pccb->target]) {
866 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
868 "\tPlease run SCSI command INQUIRY first!\n");
872 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
873 if (cap64 > 0x100000000ULL)
876 cap = cpu_to_be32(cap64);
877 memcpy(pccb->pdata, &cap, sizeof(cap));
879 block_size = cpu_to_be32((u32)512);
880 memcpy(&pccb->pdata[4], &block_size, 4);
887 * SCSI READ CAPACITY16 command operation.
889 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
890 struct scsi_cmd *pccb)
895 if (!uc_priv->ataid[pccb->target]) {
896 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
898 "\tPlease run SCSI command INQUIRY first!\n");
902 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
903 cap = cpu_to_be64(cap);
904 memcpy(pccb->pdata, &cap, sizeof(cap));
906 block_size = cpu_to_be64((u64)512);
907 memcpy(&pccb->pdata[8], &block_size, 8);
914 * SCSI TEST UNIT READY command operation.
916 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
917 struct scsi_cmd *pccb)
919 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
923 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
925 struct ahci_uc_priv *uc_priv;
926 #ifdef CONFIG_DM_SCSI
927 uc_priv = dev_get_uclass_priv(dev->parent);
933 switch (pccb->cmd[0]) {
936 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
939 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
941 case SCSI_RD_CAPAC10:
942 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
944 case SCSI_RD_CAPAC16:
945 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
948 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
951 ret = ata_scsiop_inquiry(uc_priv, pccb);
954 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
959 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
966 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
971 linkmap = uc_priv->link_port_map;
973 for (i = 0; i < uc_priv->n_ports; i++) {
974 if (((linkmap >> i) & 0x01)) {
975 if (ahci_port_start(uc_priv, (u8) i)) {
976 printf("Can not start port %d\n", i);
985 #ifndef CONFIG_DM_SCSI
986 void scsi_low_level_init(int busdevfunc)
988 struct ahci_uc_priv *uc_priv;
990 #ifndef CONFIG_SCSI_AHCI_PLAT
991 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
993 printf("%s: No memory for uc_priv\n", __func__);
997 # if defined(CONFIG_DM_PCI)
1001 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1004 ahci_init_one(uc_priv, dev);
1006 ahci_init_one(uc_priv, busdevfunc);
1009 uc_priv = probe_ent;
1012 ahci_start_ports(uc_priv);
1016 #ifndef CONFIG_SCSI_AHCI_PLAT
1017 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
1018 int ahci_init_one_dm(struct udevice *dev)
1020 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1022 return ahci_init_one(uc_priv, dev);
1027 int ahci_start_ports_dm(struct udevice *dev)
1029 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1031 return ahci_start_ports(uc_priv);
1034 #ifdef CONFIG_SCSI_AHCI_PLAT
1035 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1039 uc_priv->host_flags = ATA_FLAG_SATA
1040 | ATA_FLAG_NO_LEGACY
1043 | ATA_FLAG_NO_ATAPI;
1044 uc_priv->pio_mask = 0x1f;
1045 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1047 uc_priv->mmio_base = base;
1049 /* initialize adapter */
1050 rc = ahci_host_init(uc_priv);
1054 ahci_print_info(uc_priv);
1056 rc = ahci_start_ports(uc_priv);
1062 #ifndef CONFIG_DM_SCSI
1063 int ahci_init(void __iomem *base)
1065 struct ahci_uc_priv *uc_priv;
1067 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1069 printf("%s: No memory for uc_priv\n", __func__);
1073 uc_priv = probe_ent;
1074 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1076 return ahci_init_common(uc_priv, base);
1080 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1082 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1084 return ahci_init_common(uc_priv, base);
1087 void __weak scsi_init(void)
1091 #endif /* CONFIG_SCSI_AHCI_PLAT */
1094 * In the general case of generic rotating media it makes sense to have a
1095 * flush capability. It probably even makes sense in the case of SSDs because
1096 * one cannot always know for sure what kind of internal cache/flush mechanism
1097 * is embodied therein. At first it was planned to invoke this after the last
1098 * write to disk and before rebooting. In practice, knowing, a priori, which
1099 * is the last write is difficult. Because writing to the disk in u-boot is
1100 * very rare, this flush command will be invoked after every block write.
1102 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1105 struct ahci_ioports *pp = &(uc_priv->port[port]);
1106 void __iomem *port_mmio = pp->port_mmio;
1107 u32 cmd_fis_len = 5; /* five dwords */
1109 /* Preset the FIS */
1111 fis[0] = 0x27; /* Host to device FIS. */
1112 fis[1] = 1 << 7; /* Command FIS. */
1113 fis[2] = ATA_CMD_FLUSH_EXT;
1115 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1116 ahci_fill_cmd_slot(pp, cmd_fis_len);
1117 ahci_dcache_flush_sata_cmd(pp);
1118 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1120 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1121 WAIT_MS_FLUSH, 0x1)) {
1122 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1129 static int ahci_scsi_bus_reset(struct udevice *dev)
1131 /* Not implemented */
1136 #ifdef CONFIG_DM_SCSI
1137 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1139 struct udevice *dev;
1142 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1150 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1152 struct ahci_uc_priv *uc_priv;
1153 struct scsi_platdata *uc_plat;
1154 struct udevice *dev;
1157 device_find_first_child(ahci_dev, &dev);
1160 uc_plat = dev_get_uclass_platdata(dev);
1161 uc_plat->base = base;
1162 uc_plat->max_lun = 1;
1163 uc_plat->max_id = 2;
1165 uc_priv = dev_get_uclass_priv(ahci_dev);
1166 ret = ahci_init_one(uc_priv, dev);
1169 ret = ahci_start_ports(uc_priv);
1174 * scsi_scan_dev() scans devices up-to the number of max_id.
1175 * Update max_id if the number of detected ports exceeds max_id.
1176 * This allows SCSI to scan all detected ports.
1178 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1184 #ifdef CONFIG_DM_PCI
1185 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1189 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1192 return ahci_probe_scsi(ahci_dev, base);
1196 struct scsi_ops scsi_ops = {
1197 .exec = ahci_scsi_exec,
1198 .bus_reset = ahci_scsi_bus_reset,
1201 U_BOOT_DRIVER(ahci_scsi) = {
1202 .name = "ahci_scsi",
1207 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1209 return ahci_scsi_exec(dev, pccb);
1212 __weak int scsi_bus_reset(struct udevice *dev)
1214 return ahci_scsi_bus_reset(dev);