2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
96 static struct scsi_host_template ahci_sht = {
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
110 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
125 [board_ahci_noncq] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_nosntf] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
139 [board_ahci_yes_fbs] = {
140 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
147 [board_ahci_mcp65] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
150 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
155 [board_ahci_mcp77] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_mcp89] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
177 [board_ahci_sb600] = {
178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_pmp_retry_srst_ops,
186 [board_ahci_sb700] = { /* for SB700 and SB800 */
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_vt8251] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
202 static const struct pci_device_id ahci_pci_tbl[] = {
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
272 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
280 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
288 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
297 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
301 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
306 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
310 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
311 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
312 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
313 /* JMicron 362B and 362C have an AHCI function with IDE class code */
314 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
315 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
318 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
319 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
324 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
328 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
329 /* AMD is using RAID class only for ahci controllers */
330 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
331 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
334 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
335 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
338 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
425 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
426 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
428 /* ST Microelectronics */
429 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
432 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
433 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
435 .class = PCI_CLASS_STORAGE_SATA_AHCI,
436 .class_mask = 0xffffff,
437 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
439 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
440 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
441 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
450 .driver_data = board_ahci_yes_fbs },
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
452 .driver_data = board_ahci_yes_fbs },
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
454 .driver_data = board_ahci_yes_fbs },
455 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
456 .driver_data = board_ahci_yes_fbs },
459 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
462 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
463 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
464 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
465 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
468 * Samsung SSDs found on some macbooks. NCQ times out.
469 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
471 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
474 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
476 /* Generic, PCI class code for AHCI */
477 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
478 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
480 { } /* terminate list */
484 static struct pci_driver ahci_pci_driver = {
486 .id_table = ahci_pci_tbl,
487 .probe = ahci_init_one,
488 .remove = ata_pci_remove_one,
490 .suspend = ahci_pci_device_suspend,
491 .resume = ahci_pci_device_resume,
495 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
496 static int marvell_enable;
498 static int marvell_enable = 1;
500 module_param(marvell_enable, int, 0644);
501 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
504 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
505 struct ahci_host_priv *hpriv)
507 unsigned int force_port_map = 0;
508 unsigned int mask_port_map = 0;
510 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
511 dev_info(&pdev->dev, "JMB361 has only one port\n");
516 * Temporary Marvell 6145 hack: PATA port presence
517 * is asserted through the standard AHCI port
518 * presence register, as bit 4 (counting from 0)
520 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
521 if (pdev->device == 0x6121)
526 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
529 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
533 static int ahci_pci_reset_controller(struct ata_host *host)
535 struct pci_dev *pdev = to_pci_dev(host->dev);
537 ahci_reset_controller(host);
539 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
540 struct ahci_host_priv *hpriv = host->private_data;
544 pci_read_config_word(pdev, 0x92, &tmp16);
545 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
546 tmp16 |= hpriv->port_map;
547 pci_write_config_word(pdev, 0x92, tmp16);
554 static void ahci_pci_init_controller(struct ata_host *host)
556 struct ahci_host_priv *hpriv = host->private_data;
557 struct pci_dev *pdev = to_pci_dev(host->dev);
558 void __iomem *port_mmio;
562 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
563 if (pdev->device == 0x6121)
567 port_mmio = __ahci_port_base(host, mv);
569 writel(0, port_mmio + PORT_IRQ_MASK);
572 tmp = readl(port_mmio + PORT_IRQ_STAT);
573 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
575 writel(tmp, port_mmio + PORT_IRQ_STAT);
578 ahci_init_controller(host);
581 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
582 unsigned long deadline)
584 struct ata_port *ap = link->ap;
590 ahci_stop_engine(ap);
592 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
593 deadline, &online, NULL);
595 ahci_start_engine(ap);
597 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
599 /* vt8251 doesn't clear BSY on signature FIS reception,
600 * request follow-up softreset.
602 return online ? -EAGAIN : rc;
605 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
606 unsigned long deadline)
608 struct ata_port *ap = link->ap;
609 struct ahci_port_priv *pp = ap->private_data;
610 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
611 struct ata_taskfile tf;
615 ahci_stop_engine(ap);
617 /* clear D2H reception area to properly wait for D2H FIS */
618 ata_tf_init(link->device, &tf);
619 tf.command = ATA_BUSY;
620 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
622 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
623 deadline, &online, NULL);
625 ahci_start_engine(ap);
627 /* The pseudo configuration device on SIMG4726 attached to
628 * ASUS P5W-DH Deluxe doesn't send signature FIS after
629 * hardreset if no device is attached to the first downstream
630 * port && the pseudo device locks up on SRST w/ PMP==0. To
631 * work around this, wait for !BSY only briefly. If BSY isn't
632 * cleared, perform CLO and proceed to IDENTIFY (achieved by
633 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
635 * Wait for two seconds. Devices attached to downstream port
636 * which can't process the following IDENTIFY after this will
637 * have to be reset again. For most cases, this should
638 * suffice while making probing snappish enough.
641 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
644 ahci_kick_engine(ap);
650 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
652 struct ata_host *host = pci_get_drvdata(pdev);
653 struct ahci_host_priv *hpriv = host->private_data;
654 void __iomem *mmio = hpriv->mmio;
657 if (mesg.event & PM_EVENT_SUSPEND &&
658 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
660 "BIOS update required for suspend/resume\n");
664 if (mesg.event & PM_EVENT_SLEEP) {
665 /* AHCI spec rev1.1 section 8.3.3:
666 * Software must disable interrupts prior to requesting a
667 * transition of the HBA to D3 state.
669 ctl = readl(mmio + HOST_CTL);
671 writel(ctl, mmio + HOST_CTL);
672 readl(mmio + HOST_CTL); /* flush */
675 return ata_pci_device_suspend(pdev, mesg);
678 static int ahci_pci_device_resume(struct pci_dev *pdev)
680 struct ata_host *host = pci_get_drvdata(pdev);
683 rc = ata_pci_device_do_resume(pdev);
687 /* Apple BIOS helpfully mangles the registers on resume */
688 if (is_mcp89_apple(pdev))
689 ahci_mcp89_apple_enable(pdev);
691 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
692 rc = ahci_pci_reset_controller(host);
696 ahci_pci_init_controller(host);
699 ata_host_resume(host);
705 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
710 * If the device fixup already set the dma_mask to some non-standard
711 * value, don't extend it here. This happens on STA2X11, for example.
713 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
717 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
718 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
720 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
723 "64-bit DMA enable failed\n");
728 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
730 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
733 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
736 "32-bit consistent DMA enable failed\n");
743 static void ahci_pci_print_info(struct ata_host *host)
745 struct pci_dev *pdev = to_pci_dev(host->dev);
749 pci_read_config_word(pdev, 0x0a, &cc);
750 if (cc == PCI_CLASS_STORAGE_IDE)
752 else if (cc == PCI_CLASS_STORAGE_SATA)
754 else if (cc == PCI_CLASS_STORAGE_RAID)
759 ahci_print_info(host, scc_s);
762 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
763 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
764 * support PMP and the 4726 either directly exports the device
765 * attached to the first downstream port or acts as a hardware storage
766 * controller and emulate a single ATA device (can be RAID 0/1 or some
767 * other configuration).
769 * When there's no device attached to the first downstream port of the
770 * 4726, "Config Disk" appears, which is a pseudo ATA device to
771 * configure the 4726. However, ATA emulation of the device is very
772 * lame. It doesn't send signature D2H Reg FIS after the initial
773 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
775 * The following function works around the problem by always using
776 * hardreset on the port and not depending on receiving signature FIS
777 * afterward. If signature FIS isn't received soon, ATA class is
778 * assumed without follow-up softreset.
780 static void ahci_p5wdh_workaround(struct ata_host *host)
782 static struct dmi_system_id sysids[] = {
784 .ident = "P5W DH Deluxe",
786 DMI_MATCH(DMI_SYS_VENDOR,
787 "ASUSTEK COMPUTER INC"),
788 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
793 struct pci_dev *pdev = to_pci_dev(host->dev);
795 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
796 dmi_check_system(sysids)) {
797 struct ata_port *ap = host->ports[1];
800 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
802 ap->ops = &ahci_p5wdh_ops;
803 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
808 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
809 * booting in BIOS compatibility mode. We restore the registers but not ID.
811 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
815 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
817 pci_read_config_dword(pdev, 0xf8, &val);
819 /* the following changes the device ID, but appears not to affect function */
820 /* val = (val & ~0xf0000000) | 0x80000000; */
821 pci_write_config_dword(pdev, 0xf8, val);
823 pci_read_config_dword(pdev, 0x54c, &val);
825 pci_write_config_dword(pdev, 0x54c, val);
827 pci_read_config_dword(pdev, 0x4a4, &val);
830 pci_write_config_dword(pdev, 0x4a4, val);
832 pci_read_config_dword(pdev, 0x54c, &val);
834 pci_write_config_dword(pdev, 0x54c, val);
836 pci_read_config_dword(pdev, 0xf8, &val);
838 pci_write_config_dword(pdev, 0xf8, val);
841 static bool is_mcp89_apple(struct pci_dev *pdev)
843 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
844 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
845 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
846 pdev->subsystem_device == 0xcb89;
849 /* only some SB600 ahci controllers can do 64bit DMA */
850 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
852 static const struct dmi_system_id sysids[] = {
854 * The oldest version known to be broken is 0901 and
855 * working is 1501 which was released on 2007-10-26.
856 * Enable 64bit DMA on 1501 and anything newer.
858 * Please read bko#9412 for more info.
861 .ident = "ASUS M2A-VM",
863 DMI_MATCH(DMI_BOARD_VENDOR,
864 "ASUSTeK Computer INC."),
865 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
867 .driver_data = "20071026", /* yyyymmdd */
870 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
873 * BIOS versions earlier than 1.5 had the Manufacturer DMI
874 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
875 * This spelling mistake was fixed in BIOS version 1.5, so
876 * 1.5 and later have the Manufacturer as
877 * "MICRO-STAR INTERNATIONAL CO.,LTD".
878 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
880 * BIOS versions earlier than 1.9 had a Board Product Name
881 * DMI field of "MS-7376". This was changed to be
882 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
883 * match on DMI_BOARD_NAME of "MS-7376".
886 .ident = "MSI K9A2 Platinum",
888 DMI_MATCH(DMI_BOARD_VENDOR,
890 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
894 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
897 * This board also had the typo mentioned above in the
898 * Manufacturer DMI field (fixed in BIOS version 1.5), so
899 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
902 .ident = "MSI K9AGM2",
904 DMI_MATCH(DMI_BOARD_VENDOR,
906 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
910 * All BIOS versions for the Asus M3A support 64bit DMA.
911 * (all release versions from 0301 to 1206 were tested)
916 DMI_MATCH(DMI_BOARD_VENDOR,
917 "ASUSTeK Computer INC."),
918 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
923 const struct dmi_system_id *match;
924 int year, month, date;
927 match = dmi_first_match(sysids);
928 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
932 if (!match->driver_data)
935 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
936 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
938 if (strcmp(buf, match->driver_data) >= 0)
942 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
948 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
952 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
954 static const struct dmi_system_id broken_systems[] = {
956 .ident = "HP Compaq nx6310",
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
961 /* PCI slot number of the controller */
962 .driver_data = (void *)0x1FUL,
965 .ident = "HP Compaq 6720s",
967 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
968 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
970 /* PCI slot number of the controller */
971 .driver_data = (void *)0x1FUL,
974 { } /* terminate list */
976 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
979 unsigned long slot = (unsigned long)dmi->driver_data;
980 /* apply the quirk only to on-board controllers */
981 return slot == PCI_SLOT(pdev->devfn);
987 static bool ahci_broken_suspend(struct pci_dev *pdev)
989 static const struct dmi_system_id sysids[] = {
991 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
992 * to the harddisk doesn't become online after
993 * resuming from STR. Warn and fail suspend.
995 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
997 * Use dates instead of versions to match as HP is
998 * apparently recycling both product and version
1001 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1006 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1007 DMI_MATCH(DMI_PRODUCT_NAME,
1008 "HP Pavilion dv4 Notebook PC"),
1010 .driver_data = "20090105", /* F.30 */
1015 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1016 DMI_MATCH(DMI_PRODUCT_NAME,
1017 "HP Pavilion dv5 Notebook PC"),
1019 .driver_data = "20090506", /* F.16 */
1024 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1025 DMI_MATCH(DMI_PRODUCT_NAME,
1026 "HP Pavilion dv6 Notebook PC"),
1028 .driver_data = "20090423", /* F.21 */
1033 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1034 DMI_MATCH(DMI_PRODUCT_NAME,
1035 "HP HDX18 Notebook PC"),
1037 .driver_data = "20090430", /* F.23 */
1040 * Acer eMachines G725 has the same problem. BIOS
1041 * V1.03 is known to be broken. V3.04 is known to
1042 * work. Between, there are V1.06, V2.06 and V3.03
1043 * that we don't have much idea about. For now,
1044 * blacklist anything older than V3.04.
1046 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1051 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1054 .driver_data = "20091216", /* V3.04 */
1056 { } /* terminate list */
1058 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1059 int year, month, date;
1062 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1065 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1066 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1068 return strcmp(buf, dmi->driver_data) < 0;
1071 static bool ahci_broken_online(struct pci_dev *pdev)
1073 #define ENCODE_BUSDEVFN(bus, slot, func) \
1074 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1075 static const struct dmi_system_id sysids[] = {
1077 * There are several gigabyte boards which use
1078 * SIMG5723s configured as hardware RAID. Certain
1079 * 5723 firmware revisions shipped there keep the link
1080 * online but fail to answer properly to SRST or
1081 * IDENTIFY when no device is attached downstream
1082 * causing libata to retry quite a few times leading
1083 * to excessive detection delay.
1085 * As these firmwares respond to the second reset try
1086 * with invalid device signature, considering unknown
1087 * sig as offline works around the problem acceptably.
1090 .ident = "EP45-DQ6",
1092 DMI_MATCH(DMI_BOARD_VENDOR,
1093 "Gigabyte Technology Co., Ltd."),
1094 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1096 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1099 .ident = "EP45-DS5",
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "Gigabyte Technology Co., Ltd."),
1103 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1105 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1107 { } /* terminate list */
1109 #undef ENCODE_BUSDEVFN
1110 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1116 val = (unsigned long)dmi->driver_data;
1118 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1121 #ifdef CONFIG_ATA_ACPI
1122 static void ahci_gtf_filter_workaround(struct ata_host *host)
1124 static const struct dmi_system_id sysids[] = {
1126 * Aspire 3810T issues a bunch of SATA enable commands
1127 * via _GTF including an invalid one and one which is
1128 * rejected by the device. Among the successful ones
1129 * is FPDMA non-zero offset enable which when enabled
1130 * only on the drive side leads to NCQ command
1131 * failures. Filter it out.
1134 .ident = "Aspire 3810T",
1136 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1137 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1139 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1143 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1144 unsigned int filter;
1150 filter = (unsigned long)dmi->driver_data;
1151 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1152 filter, dmi->ident);
1154 for (i = 0; i < host->n_ports; i++) {
1155 struct ata_port *ap = host->ports[i];
1156 struct ata_link *link;
1157 struct ata_device *dev;
1159 ata_for_each_link(link, ap, EDGE)
1160 ata_for_each_dev(dev, link, ALL)
1161 dev->gtf_filter |= filter;
1165 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1169 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1170 struct ahci_host_priv *hpriv)
1174 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1177 rc = pci_msi_vec_count(pdev);
1182 * If number of MSIs is less than number of ports then Sharing Last
1183 * Message mode could be enforced. In this case assume that advantage
1184 * of multipe MSIs is negated and use single MSI mode instead.
1190 rc = pci_enable_msi_block(pdev, nvec);
1196 /* fallback to single MSI mode if the controller enforced MRSM mode */
1197 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1198 pci_disable_msi(pdev);
1199 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1206 rc = pci_enable_msi(pdev);
1217 * ahci_host_activate - start AHCI host, request IRQs and register it
1218 * @host: target ATA host
1219 * @irq: base IRQ number to request
1220 * @n_msis: number of MSIs allocated for this host
1221 * @irq_handler: irq_handler used when requesting IRQs
1222 * @irq_flags: irq_flags used when requesting IRQs
1224 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1225 * when multiple MSIs were allocated. That is one MSI per port, starting
1229 * Inherited from calling layer (may sleep).
1232 * 0 on success, -errno otherwise.
1234 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1238 /* Sharing Last Message among several ports is not supported */
1239 if (n_msis < host->n_ports)
1242 rc = ata_host_start(host);
1246 for (i = 0; i < host->n_ports; i++) {
1247 struct ahci_port_priv *pp = host->ports[i]->private_data;
1249 /* Do not receive interrupts sent by dummy ports */
1251 disable_irq(irq + i);
1255 rc = devm_request_threaded_irq(host->dev, irq + i,
1257 ahci_thread_fn, IRQF_SHARED,
1258 pp->irq_desc, host->ports[i]);
1263 for (i = 0; i < host->n_ports; i++)
1264 ata_port_desc(host->ports[i], "irq %d", irq + i);
1266 rc = ata_host_register(host, &ahci_sht);
1268 goto out_free_all_irqs;
1275 for (i--; i >= 0; i--)
1276 devm_free_irq(host->dev, irq + i, host->ports[i]);
1281 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1283 unsigned int board_id = ent->driver_data;
1284 struct ata_port_info pi = ahci_port_info[board_id];
1285 const struct ata_port_info *ppi[] = { &pi, NULL };
1286 struct device *dev = &pdev->dev;
1287 struct ahci_host_priv *hpriv;
1288 struct ata_host *host;
1289 int n_ports, n_msis, i, rc;
1290 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1294 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1296 ata_print_version_once(&pdev->dev, DRV_VERSION);
1298 /* The AHCI driver can only drive the SATA ports, the PATA driver
1299 can drive them all so if both drivers are selected make sure
1300 AHCI stays out of the way */
1301 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1304 /* Apple BIOS on MCP89 prevents us using AHCI */
1305 if (is_mcp89_apple(pdev))
1306 ahci_mcp89_apple_enable(pdev);
1308 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1309 * At the moment, we can only use the AHCI mode. Let the users know
1310 * that for SAS drives they're out of luck.
1312 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1313 dev_info(&pdev->dev,
1314 "PDC42819 can only drive SATA devices with this driver\n");
1316 /* Both Connext and Enmotus devices use non-standard BARs */
1317 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1318 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1319 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1320 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1322 /* acquire resources */
1323 rc = pcim_enable_device(pdev);
1327 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1328 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1331 /* ICH6s share the same PCI ID for both piix and ahci
1332 * modes. Enabling ahci mode while MAP indicates
1333 * combined mode is a bad idea. Yield to ata_piix.
1335 pci_read_config_byte(pdev, ICH_MAP, &map);
1337 dev_info(&pdev->dev,
1338 "controller is in combined mode, can't enable AHCI mode\n");
1343 /* AHCI controllers often implement SFF compatible interface.
1344 * Grab all PCI BARs just in case.
1346 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1348 pcim_pin_device(pdev);
1352 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1355 hpriv->flags |= (unsigned long)pi.private_data;
1357 /* MCP65 revision A1 and A2 can't do MSI */
1358 if (board_id == board_ahci_mcp65 &&
1359 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1360 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1362 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1363 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1364 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1366 /* only some SB600s can do 64bit DMA */
1367 if (ahci_sb600_enable_64bit(pdev))
1368 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1370 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1372 /* save initial config */
1373 ahci_pci_save_initial_config(pdev, hpriv);
1376 if (hpriv->cap & HOST_CAP_NCQ) {
1377 pi.flags |= ATA_FLAG_NCQ;
1379 * Auto-activate optimization is supposed to be
1380 * supported on all AHCI controllers indicating NCQ
1381 * capability, but it seems to be broken on some
1382 * chipsets including NVIDIAs.
1384 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1385 pi.flags |= ATA_FLAG_FPDMA_AA;
1388 * All AHCI controllers should be forward-compatible
1389 * with the new auxiliary field. This code should be
1390 * conditionalized if any buggy AHCI controllers are
1393 pi.flags |= ATA_FLAG_FPDMA_AUX;
1396 if (hpriv->cap & HOST_CAP_PMP)
1397 pi.flags |= ATA_FLAG_PMP;
1399 ahci_set_em_messages(hpriv, &pi);
1401 if (ahci_broken_system_poweroff(pdev)) {
1402 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1403 dev_info(&pdev->dev,
1404 "quirky BIOS, skipping spindown on poweroff\n");
1407 if (ahci_broken_suspend(pdev)) {
1408 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1409 dev_warn(&pdev->dev,
1410 "BIOS update required for suspend/resume\n");
1413 if (ahci_broken_online(pdev)) {
1414 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1415 dev_info(&pdev->dev,
1416 "online status unreliable, applying workaround\n");
1419 /* CAP.NP sometimes indicate the index of the last enabled
1420 * port, at other times, that of the last possible port, so
1421 * determining the maximum port number requires looking at
1422 * both CAP.NP and port_map.
1424 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1426 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1428 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1430 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1433 host->private_data = hpriv;
1435 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1436 host->flags |= ATA_HOST_PARALLEL_SCAN;
1438 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1440 if (pi.flags & ATA_FLAG_EM)
1441 ahci_reset_em(host);
1443 for (i = 0; i < host->n_ports; i++) {
1444 struct ata_port *ap = host->ports[i];
1446 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1447 ata_port_pbar_desc(ap, ahci_pci_bar,
1448 0x100 + ap->port_no * 0x80, "port");
1450 /* set enclosure management message type */
1451 if (ap->flags & ATA_FLAG_EM)
1452 ap->em_message_type = hpriv->em_msg_type;
1455 /* disabled/not-implemented port */
1456 if (!(hpriv->port_map & (1 << i)))
1457 ap->ops = &ata_dummy_port_ops;
1460 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1461 ahci_p5wdh_workaround(host);
1463 /* apply gtf filter quirk */
1464 ahci_gtf_filter_workaround(host);
1466 /* initialize adapter */
1467 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1471 rc = ahci_pci_reset_controller(host);
1475 ahci_pci_init_controller(host);
1476 ahci_pci_print_info(host);
1478 pci_set_master(pdev);
1480 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1481 return ahci_host_activate(host, pdev->irq, n_msis);
1483 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1487 module_pci_driver(ahci_pci_driver);
1489 MODULE_AUTHOR("Jeff Garzik");
1490 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1491 MODULE_LICENSE("GPL");
1492 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1493 MODULE_VERSION(DRV_VERSION);