2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_sb700, /* for SB700 and SB800 */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
89 static bool is_mcp89_apple(struct pci_dev *pdev);
90 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
93 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
94 static int ahci_pci_device_resume(struct pci_dev *pdev);
97 static struct scsi_host_template ahci_sht = {
101 static struct ata_port_operations ahci_vt8251_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_vt8251_hardreset,
106 static struct ata_port_operations ahci_p5wdh_ops = {
107 .inherits = &ahci_ops,
108 .hardreset = ahci_p5wdh_hardreset,
111 static const struct ata_port_info ahci_port_info[] = {
114 .flags = AHCI_FLAG_COMMON,
115 .pio_mask = ATA_PIO4,
116 .udma_mask = ATA_UDMA6,
117 .port_ops = &ahci_ops,
119 [board_ahci_ign_iferr] = {
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nomsi] = {
127 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
133 [board_ahci_noncq] = {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
140 [board_ahci_nosntf] = {
141 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
147 [board_ahci_yes_fbs] = {
148 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
155 [board_ahci_mcp65] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
158 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
163 [board_ahci_mcp77] = {
164 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
170 [board_ahci_mcp89] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
178 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
179 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
180 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
185 [board_ahci_sb600] = {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
187 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
188 AHCI_HFLAG_32BIT_ONLY),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_pmp_retry_srst_ops,
194 [board_ahci_sb700] = { /* for SB700 and SB800 */
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_pmp_retry_srst_ops,
201 [board_ahci_vt8251] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_vt8251_ops,
210 static const struct pci_device_id ahci_pci_tbl[] = {
212 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
213 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
214 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
215 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
216 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
217 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
218 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
222 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
238 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
240 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
247 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
249 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
259 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
265 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
272 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
278 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
280 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
286 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
288 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
296 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
305 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
308 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
309 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
312 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
319 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
324 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
325 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
326 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
327 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
328 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
331 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
332 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
333 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
334 /* JMicron 362B and 362C have an AHCI function with IDE class code */
335 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
336 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
339 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
340 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
341 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
348 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
349 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
350 /* AMD is using RAID class only for ahci controllers */
351 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
352 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
355 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
356 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
359 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
360 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
396 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
432 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
445 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
446 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
447 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
449 /* ST Microelectronics */
450 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
453 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
454 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
455 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
456 .class = PCI_CLASS_STORAGE_SATA_AHCI,
457 .class_mask = 0xffffff,
458 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
459 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
460 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
461 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
462 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
463 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
464 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
465 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
466 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
467 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
468 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
469 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
471 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
472 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
473 .driver_data = board_ahci_yes_fbs },
474 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
475 .driver_data = board_ahci_yes_fbs },
476 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
477 .driver_data = board_ahci_yes_fbs },
478 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
479 .driver_data = board_ahci_yes_fbs },
482 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
483 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
486 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
487 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
488 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
489 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
492 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
493 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
495 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
498 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
500 /* Generic, PCI class code for AHCI */
501 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
502 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
504 { } /* terminate list */
508 static struct pci_driver ahci_pci_driver = {
510 .id_table = ahci_pci_tbl,
511 .probe = ahci_init_one,
512 .remove = ata_pci_remove_one,
514 .suspend = ahci_pci_device_suspend,
515 .resume = ahci_pci_device_resume,
519 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
520 static int marvell_enable;
522 static int marvell_enable = 1;
524 module_param(marvell_enable, int, 0644);
525 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
528 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
529 struct ahci_host_priv *hpriv)
531 unsigned int force_port_map = 0;
532 unsigned int mask_port_map = 0;
534 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
535 dev_info(&pdev->dev, "JMB361 has only one port\n");
540 * Temporary Marvell 6145 hack: PATA port presence
541 * is asserted through the standard AHCI port
542 * presence register, as bit 4 (counting from 0)
544 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
545 if (pdev->device == 0x6121)
550 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
553 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
557 static int ahci_pci_reset_controller(struct ata_host *host)
559 struct pci_dev *pdev = to_pci_dev(host->dev);
561 ahci_reset_controller(host);
563 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
564 struct ahci_host_priv *hpriv = host->private_data;
568 pci_read_config_word(pdev, 0x92, &tmp16);
569 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
570 tmp16 |= hpriv->port_map;
571 pci_write_config_word(pdev, 0x92, tmp16);
578 static void ahci_pci_init_controller(struct ata_host *host)
580 struct ahci_host_priv *hpriv = host->private_data;
581 struct pci_dev *pdev = to_pci_dev(host->dev);
582 void __iomem *port_mmio;
586 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
587 if (pdev->device == 0x6121)
591 port_mmio = __ahci_port_base(host, mv);
593 writel(0, port_mmio + PORT_IRQ_MASK);
596 tmp = readl(port_mmio + PORT_IRQ_STAT);
597 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
599 writel(tmp, port_mmio + PORT_IRQ_STAT);
602 ahci_init_controller(host);
605 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
606 unsigned long deadline)
608 struct ata_port *ap = link->ap;
614 ahci_stop_engine(ap);
616 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
617 deadline, &online, NULL);
619 ahci_start_engine(ap);
621 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
623 /* vt8251 doesn't clear BSY on signature FIS reception,
624 * request follow-up softreset.
626 return online ? -EAGAIN : rc;
629 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
630 unsigned long deadline)
632 struct ata_port *ap = link->ap;
633 struct ahci_port_priv *pp = ap->private_data;
634 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
635 struct ata_taskfile tf;
639 ahci_stop_engine(ap);
641 /* clear D2H reception area to properly wait for D2H FIS */
642 ata_tf_init(link->device, &tf);
643 tf.command = ATA_BUSY;
644 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
646 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
647 deadline, &online, NULL);
649 ahci_start_engine(ap);
651 /* The pseudo configuration device on SIMG4726 attached to
652 * ASUS P5W-DH Deluxe doesn't send signature FIS after
653 * hardreset if no device is attached to the first downstream
654 * port && the pseudo device locks up on SRST w/ PMP==0. To
655 * work around this, wait for !BSY only briefly. If BSY isn't
656 * cleared, perform CLO and proceed to IDENTIFY (achieved by
657 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
659 * Wait for two seconds. Devices attached to downstream port
660 * which can't process the following IDENTIFY after this will
661 * have to be reset again. For most cases, this should
662 * suffice while making probing snappish enough.
665 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
668 ahci_kick_engine(ap);
674 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
676 struct ata_host *host = pci_get_drvdata(pdev);
677 struct ahci_host_priv *hpriv = host->private_data;
678 void __iomem *mmio = hpriv->mmio;
681 if (mesg.event & PM_EVENT_SUSPEND &&
682 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
684 "BIOS update required for suspend/resume\n");
688 if (mesg.event & PM_EVENT_SLEEP) {
689 /* AHCI spec rev1.1 section 8.3.3:
690 * Software must disable interrupts prior to requesting a
691 * transition of the HBA to D3 state.
693 ctl = readl(mmio + HOST_CTL);
695 writel(ctl, mmio + HOST_CTL);
696 readl(mmio + HOST_CTL); /* flush */
699 return ata_pci_device_suspend(pdev, mesg);
702 static int ahci_pci_device_resume(struct pci_dev *pdev)
704 struct ata_host *host = pci_get_drvdata(pdev);
707 rc = ata_pci_device_do_resume(pdev);
711 /* Apple BIOS helpfully mangles the registers on resume */
712 if (is_mcp89_apple(pdev))
713 ahci_mcp89_apple_enable(pdev);
715 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
716 rc = ahci_pci_reset_controller(host);
720 ahci_pci_init_controller(host);
723 ata_host_resume(host);
729 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
734 * If the device fixup already set the dma_mask to some non-standard
735 * value, don't extend it here. This happens on STA2X11, for example.
737 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
741 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
742 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
744 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
747 "64-bit DMA enable failed\n");
752 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
754 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
757 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
760 "32-bit consistent DMA enable failed\n");
767 static void ahci_pci_print_info(struct ata_host *host)
769 struct pci_dev *pdev = to_pci_dev(host->dev);
773 pci_read_config_word(pdev, 0x0a, &cc);
774 if (cc == PCI_CLASS_STORAGE_IDE)
776 else if (cc == PCI_CLASS_STORAGE_SATA)
778 else if (cc == PCI_CLASS_STORAGE_RAID)
783 ahci_print_info(host, scc_s);
786 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
787 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
788 * support PMP and the 4726 either directly exports the device
789 * attached to the first downstream port or acts as a hardware storage
790 * controller and emulate a single ATA device (can be RAID 0/1 or some
791 * other configuration).
793 * When there's no device attached to the first downstream port of the
794 * 4726, "Config Disk" appears, which is a pseudo ATA device to
795 * configure the 4726. However, ATA emulation of the device is very
796 * lame. It doesn't send signature D2H Reg FIS after the initial
797 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
799 * The following function works around the problem by always using
800 * hardreset on the port and not depending on receiving signature FIS
801 * afterward. If signature FIS isn't received soon, ATA class is
802 * assumed without follow-up softreset.
804 static void ahci_p5wdh_workaround(struct ata_host *host)
806 static struct dmi_system_id sysids[] = {
808 .ident = "P5W DH Deluxe",
810 DMI_MATCH(DMI_SYS_VENDOR,
811 "ASUSTEK COMPUTER INC"),
812 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
817 struct pci_dev *pdev = to_pci_dev(host->dev);
819 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
820 dmi_check_system(sysids)) {
821 struct ata_port *ap = host->ports[1];
824 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
826 ap->ops = &ahci_p5wdh_ops;
827 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
832 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
833 * booting in BIOS compatibility mode. We restore the registers but not ID.
835 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
839 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
841 pci_read_config_dword(pdev, 0xf8, &val);
843 /* the following changes the device ID, but appears not to affect function */
844 /* val = (val & ~0xf0000000) | 0x80000000; */
845 pci_write_config_dword(pdev, 0xf8, val);
847 pci_read_config_dword(pdev, 0x54c, &val);
849 pci_write_config_dword(pdev, 0x54c, val);
851 pci_read_config_dword(pdev, 0x4a4, &val);
854 pci_write_config_dword(pdev, 0x4a4, val);
856 pci_read_config_dword(pdev, 0x54c, &val);
858 pci_write_config_dword(pdev, 0x54c, val);
860 pci_read_config_dword(pdev, 0xf8, &val);
862 pci_write_config_dword(pdev, 0xf8, val);
865 static bool is_mcp89_apple(struct pci_dev *pdev)
867 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
868 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
869 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
870 pdev->subsystem_device == 0xcb89;
873 /* only some SB600 ahci controllers can do 64bit DMA */
874 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
876 static const struct dmi_system_id sysids[] = {
878 * The oldest version known to be broken is 0901 and
879 * working is 1501 which was released on 2007-10-26.
880 * Enable 64bit DMA on 1501 and anything newer.
882 * Please read bko#9412 for more info.
885 .ident = "ASUS M2A-VM",
887 DMI_MATCH(DMI_BOARD_VENDOR,
888 "ASUSTeK Computer INC."),
889 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
891 .driver_data = "20071026", /* yyyymmdd */
894 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
897 * BIOS versions earlier than 1.5 had the Manufacturer DMI
898 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
899 * This spelling mistake was fixed in BIOS version 1.5, so
900 * 1.5 and later have the Manufacturer as
901 * "MICRO-STAR INTERNATIONAL CO.,LTD".
902 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
904 * BIOS versions earlier than 1.9 had a Board Product Name
905 * DMI field of "MS-7376". This was changed to be
906 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
907 * match on DMI_BOARD_NAME of "MS-7376".
910 .ident = "MSI K9A2 Platinum",
912 DMI_MATCH(DMI_BOARD_VENDOR,
914 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
918 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
921 * This board also had the typo mentioned above in the
922 * Manufacturer DMI field (fixed in BIOS version 1.5), so
923 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
926 .ident = "MSI K9AGM2",
928 DMI_MATCH(DMI_BOARD_VENDOR,
930 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
934 * All BIOS versions for the Asus M3A support 64bit DMA.
935 * (all release versions from 0301 to 1206 were tested)
940 DMI_MATCH(DMI_BOARD_VENDOR,
941 "ASUSTeK Computer INC."),
942 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
947 const struct dmi_system_id *match;
948 int year, month, date;
951 match = dmi_first_match(sysids);
952 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
956 if (!match->driver_data)
959 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
960 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
962 if (strcmp(buf, match->driver_data) >= 0)
966 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
972 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
976 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
978 static const struct dmi_system_id broken_systems[] = {
980 .ident = "HP Compaq nx6310",
982 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
985 /* PCI slot number of the controller */
986 .driver_data = (void *)0x1FUL,
989 .ident = "HP Compaq 6720s",
991 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
994 /* PCI slot number of the controller */
995 .driver_data = (void *)0x1FUL,
998 { } /* terminate list */
1000 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1003 unsigned long slot = (unsigned long)dmi->driver_data;
1004 /* apply the quirk only to on-board controllers */
1005 return slot == PCI_SLOT(pdev->devfn);
1011 static bool ahci_broken_suspend(struct pci_dev *pdev)
1013 static const struct dmi_system_id sysids[] = {
1015 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1016 * to the harddisk doesn't become online after
1017 * resuming from STR. Warn and fail suspend.
1019 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1021 * Use dates instead of versions to match as HP is
1022 * apparently recycling both product and version
1025 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1030 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031 DMI_MATCH(DMI_PRODUCT_NAME,
1032 "HP Pavilion dv4 Notebook PC"),
1034 .driver_data = "20090105", /* F.30 */
1039 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1040 DMI_MATCH(DMI_PRODUCT_NAME,
1041 "HP Pavilion dv5 Notebook PC"),
1043 .driver_data = "20090506", /* F.16 */
1048 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1049 DMI_MATCH(DMI_PRODUCT_NAME,
1050 "HP Pavilion dv6 Notebook PC"),
1052 .driver_data = "20090423", /* F.21 */
1057 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1058 DMI_MATCH(DMI_PRODUCT_NAME,
1059 "HP HDX18 Notebook PC"),
1061 .driver_data = "20090430", /* F.23 */
1064 * Acer eMachines G725 has the same problem. BIOS
1065 * V1.03 is known to be broken. V3.04 is known to
1066 * work. Between, there are V1.06, V2.06 and V3.03
1067 * that we don't have much idea about. For now,
1068 * blacklist anything older than V3.04.
1070 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1075 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1076 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1078 .driver_data = "20091216", /* V3.04 */
1080 { } /* terminate list */
1082 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1083 int year, month, date;
1086 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1089 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1090 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1092 return strcmp(buf, dmi->driver_data) < 0;
1095 static bool ahci_broken_online(struct pci_dev *pdev)
1097 #define ENCODE_BUSDEVFN(bus, slot, func) \
1098 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1099 static const struct dmi_system_id sysids[] = {
1101 * There are several gigabyte boards which use
1102 * SIMG5723s configured as hardware RAID. Certain
1103 * 5723 firmware revisions shipped there keep the link
1104 * online but fail to answer properly to SRST or
1105 * IDENTIFY when no device is attached downstream
1106 * causing libata to retry quite a few times leading
1107 * to excessive detection delay.
1109 * As these firmwares respond to the second reset try
1110 * with invalid device signature, considering unknown
1111 * sig as offline works around the problem acceptably.
1114 .ident = "EP45-DQ6",
1116 DMI_MATCH(DMI_BOARD_VENDOR,
1117 "Gigabyte Technology Co., Ltd."),
1118 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1120 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1123 .ident = "EP45-DS5",
1125 DMI_MATCH(DMI_BOARD_VENDOR,
1126 "Gigabyte Technology Co., Ltd."),
1127 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1129 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1131 { } /* terminate list */
1133 #undef ENCODE_BUSDEVFN
1134 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1140 val = (unsigned long)dmi->driver_data;
1142 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1145 #ifdef CONFIG_ATA_ACPI
1146 static void ahci_gtf_filter_workaround(struct ata_host *host)
1148 static const struct dmi_system_id sysids[] = {
1150 * Aspire 3810T issues a bunch of SATA enable commands
1151 * via _GTF including an invalid one and one which is
1152 * rejected by the device. Among the successful ones
1153 * is FPDMA non-zero offset enable which when enabled
1154 * only on the drive side leads to NCQ command
1155 * failures. Filter it out.
1158 .ident = "Aspire 3810T",
1160 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1161 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1163 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1167 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1168 unsigned int filter;
1174 filter = (unsigned long)dmi->driver_data;
1175 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1176 filter, dmi->ident);
1178 for (i = 0; i < host->n_ports; i++) {
1179 struct ata_port *ap = host->ports[i];
1180 struct ata_link *link;
1181 struct ata_device *dev;
1183 ata_for_each_link(link, ap, EDGE)
1184 ata_for_each_dev(dev, link, ALL)
1185 dev->gtf_filter |= filter;
1189 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1193 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1194 struct ahci_host_priv *hpriv)
1198 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1201 rc = pci_msi_vec_count(pdev);
1206 * If number of MSIs is less than number of ports then Sharing Last
1207 * Message mode could be enforced. In this case assume that advantage
1208 * of multipe MSIs is negated and use single MSI mode instead.
1214 rc = pci_enable_msi_block(pdev, nvec);
1220 /* fallback to single MSI mode if the controller enforced MRSM mode */
1221 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1222 pci_disable_msi(pdev);
1223 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1230 rc = pci_enable_msi(pdev);
1241 * ahci_host_activate - start AHCI host, request IRQs and register it
1242 * @host: target ATA host
1243 * @irq: base IRQ number to request
1244 * @n_msis: number of MSIs allocated for this host
1245 * @irq_handler: irq_handler used when requesting IRQs
1246 * @irq_flags: irq_flags used when requesting IRQs
1248 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1249 * when multiple MSIs were allocated. That is one MSI per port, starting
1253 * Inherited from calling layer (may sleep).
1256 * 0 on success, -errno otherwise.
1258 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1262 /* Sharing Last Message among several ports is not supported */
1263 if (n_msis < host->n_ports)
1266 rc = ata_host_start(host);
1270 for (i = 0; i < host->n_ports; i++) {
1271 struct ahci_port_priv *pp = host->ports[i]->private_data;
1273 /* Do not receive interrupts sent by dummy ports */
1275 disable_irq(irq + i);
1279 rc = devm_request_threaded_irq(host->dev, irq + i,
1281 ahci_thread_fn, IRQF_SHARED,
1282 pp->irq_desc, host->ports[i]);
1287 for (i = 0; i < host->n_ports; i++)
1288 ata_port_desc(host->ports[i], "irq %d", irq + i);
1290 rc = ata_host_register(host, &ahci_sht);
1292 goto out_free_all_irqs;
1299 for (i--; i >= 0; i--)
1300 devm_free_irq(host->dev, irq + i, host->ports[i]);
1305 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1307 unsigned int board_id = ent->driver_data;
1308 struct ata_port_info pi = ahci_port_info[board_id];
1309 const struct ata_port_info *ppi[] = { &pi, NULL };
1310 struct device *dev = &pdev->dev;
1311 struct ahci_host_priv *hpriv;
1312 struct ata_host *host;
1313 int n_ports, n_msis, i, rc;
1314 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1318 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1320 ata_print_version_once(&pdev->dev, DRV_VERSION);
1322 /* The AHCI driver can only drive the SATA ports, the PATA driver
1323 can drive them all so if both drivers are selected make sure
1324 AHCI stays out of the way */
1325 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1328 /* Apple BIOS on MCP89 prevents us using AHCI */
1329 if (is_mcp89_apple(pdev))
1330 ahci_mcp89_apple_enable(pdev);
1332 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1333 * At the moment, we can only use the AHCI mode. Let the users know
1334 * that for SAS drives they're out of luck.
1336 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1337 dev_info(&pdev->dev,
1338 "PDC42819 can only drive SATA devices with this driver\n");
1340 /* Both Connext and Enmotus devices use non-standard BARs */
1341 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1342 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1343 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1344 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1346 /* acquire resources */
1347 rc = pcim_enable_device(pdev);
1351 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1352 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1355 /* ICH6s share the same PCI ID for both piix and ahci
1356 * modes. Enabling ahci mode while MAP indicates
1357 * combined mode is a bad idea. Yield to ata_piix.
1359 pci_read_config_byte(pdev, ICH_MAP, &map);
1361 dev_info(&pdev->dev,
1362 "controller is in combined mode, can't enable AHCI mode\n");
1367 /* AHCI controllers often implement SFF compatible interface.
1368 * Grab all PCI BARs just in case.
1370 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1372 pcim_pin_device(pdev);
1376 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1379 hpriv->flags |= (unsigned long)pi.private_data;
1381 /* MCP65 revision A1 and A2 can't do MSI */
1382 if (board_id == board_ahci_mcp65 &&
1383 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1384 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1386 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1387 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1388 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1390 /* only some SB600s can do 64bit DMA */
1391 if (ahci_sb600_enable_64bit(pdev))
1392 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1394 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1396 /* save initial config */
1397 ahci_pci_save_initial_config(pdev, hpriv);
1400 if (hpriv->cap & HOST_CAP_NCQ) {
1401 pi.flags |= ATA_FLAG_NCQ;
1403 * Auto-activate optimization is supposed to be
1404 * supported on all AHCI controllers indicating NCQ
1405 * capability, but it seems to be broken on some
1406 * chipsets including NVIDIAs.
1408 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1409 pi.flags |= ATA_FLAG_FPDMA_AA;
1412 * All AHCI controllers should be forward-compatible
1413 * with the new auxiliary field. This code should be
1414 * conditionalized if any buggy AHCI controllers are
1417 pi.flags |= ATA_FLAG_FPDMA_AUX;
1420 if (hpriv->cap & HOST_CAP_PMP)
1421 pi.flags |= ATA_FLAG_PMP;
1423 ahci_set_em_messages(hpriv, &pi);
1425 if (ahci_broken_system_poweroff(pdev)) {
1426 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1427 dev_info(&pdev->dev,
1428 "quirky BIOS, skipping spindown on poweroff\n");
1431 if (ahci_broken_suspend(pdev)) {
1432 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1433 dev_warn(&pdev->dev,
1434 "BIOS update required for suspend/resume\n");
1437 if (ahci_broken_online(pdev)) {
1438 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1439 dev_info(&pdev->dev,
1440 "online status unreliable, applying workaround\n");
1443 /* CAP.NP sometimes indicate the index of the last enabled
1444 * port, at other times, that of the last possible port, so
1445 * determining the maximum port number requires looking at
1446 * both CAP.NP and port_map.
1448 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1450 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1452 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1454 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1457 host->private_data = hpriv;
1459 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1460 host->flags |= ATA_HOST_PARALLEL_SCAN;
1462 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1464 if (pi.flags & ATA_FLAG_EM)
1465 ahci_reset_em(host);
1467 for (i = 0; i < host->n_ports; i++) {
1468 struct ata_port *ap = host->ports[i];
1470 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1471 ata_port_pbar_desc(ap, ahci_pci_bar,
1472 0x100 + ap->port_no * 0x80, "port");
1474 /* set enclosure management message type */
1475 if (ap->flags & ATA_FLAG_EM)
1476 ap->em_message_type = hpriv->em_msg_type;
1479 /* disabled/not-implemented port */
1480 if (!(hpriv->port_map & (1 << i)))
1481 ap->ops = &ata_dummy_port_ops;
1484 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1485 ahci_p5wdh_workaround(host);
1487 /* apply gtf filter quirk */
1488 ahci_gtf_filter_workaround(host);
1490 /* initialize adapter */
1491 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1495 rc = ahci_pci_reset_controller(host);
1499 ahci_pci_init_controller(host);
1500 ahci_pci_print_info(host);
1502 pci_set_master(pdev);
1504 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1505 return ahci_host_activate(host, pdev->irq, n_msis);
1507 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1511 module_pci_driver(ahci_pci_driver);
1513 MODULE_AUTHOR("Jeff Garzik");
1514 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1515 MODULE_LICENSE("GPL");
1516 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1517 MODULE_VERSION(DRV_VERSION);