2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
96 static struct scsi_host_template ahci_sht = {
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
110 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
125 [board_ahci_noncq] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_nosntf] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
139 [board_ahci_yes_fbs] = {
140 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
147 [board_ahci_mcp65] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
150 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
155 [board_ahci_mcp77] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_mcp89] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
177 [board_ahci_sb600] = {
178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_pmp_retry_srst_ops,
186 [board_ahci_sb700] = { /* for SB700 and SB800 */
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_vt8251] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
202 static const struct pci_device_id ahci_pci_tbl[] = {
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
272 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
280 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
288 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
297 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
301 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
306 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
309 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
310 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
311 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
315 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
316 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
317 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
318 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
319 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
320 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
321 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
323 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
324 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
325 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
326 /* JMicron 362B and 362C have an AHCI function with IDE class code */
327 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
328 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
331 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
332 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
333 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
334 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
335 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
336 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
337 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
340 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
341 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
342 /* AMD is using RAID class only for ahci controllers */
343 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
344 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
347 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
348 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
351 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
353 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
354 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
355 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
356 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
357 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
358 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
366 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
367 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
393 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
394 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
395 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
396 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
405 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
406 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
407 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
417 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
418 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
419 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
420 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
428 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
429 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
430 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
431 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
432 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
438 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
439 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
441 /* ST Microelectronics */
442 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
445 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
446 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
448 .class = PCI_CLASS_STORAGE_SATA_AHCI,
449 .class_mask = 0xffffff,
450 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
452 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
453 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
454 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
455 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
457 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
459 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
461 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
462 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
463 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
464 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
465 .driver_data = board_ahci_yes_fbs },
466 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
467 .driver_data = board_ahci_yes_fbs },
468 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
469 .driver_data = board_ahci_yes_fbs },
470 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
471 .driver_data = board_ahci_yes_fbs },
474 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
475 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
478 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
479 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
480 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
481 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
484 * Samsung SSDs found on some macbooks. NCQ times out.
485 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
487 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
490 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
492 /* Generic, PCI class code for AHCI */
493 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
496 { } /* terminate list */
500 static struct pci_driver ahci_pci_driver = {
502 .id_table = ahci_pci_tbl,
503 .probe = ahci_init_one,
504 .remove = ata_pci_remove_one,
506 .suspend = ahci_pci_device_suspend,
507 .resume = ahci_pci_device_resume,
511 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
512 static int marvell_enable;
514 static int marvell_enable = 1;
516 module_param(marvell_enable, int, 0644);
517 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
520 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
521 struct ahci_host_priv *hpriv)
523 unsigned int force_port_map = 0;
524 unsigned int mask_port_map = 0;
526 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
527 dev_info(&pdev->dev, "JMB361 has only one port\n");
532 * Temporary Marvell 6145 hack: PATA port presence
533 * is asserted through the standard AHCI port
534 * presence register, as bit 4 (counting from 0)
536 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
537 if (pdev->device == 0x6121)
542 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
545 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
549 static int ahci_pci_reset_controller(struct ata_host *host)
551 struct pci_dev *pdev = to_pci_dev(host->dev);
553 ahci_reset_controller(host);
555 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
556 struct ahci_host_priv *hpriv = host->private_data;
560 pci_read_config_word(pdev, 0x92, &tmp16);
561 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
562 tmp16 |= hpriv->port_map;
563 pci_write_config_word(pdev, 0x92, tmp16);
570 static void ahci_pci_init_controller(struct ata_host *host)
572 struct ahci_host_priv *hpriv = host->private_data;
573 struct pci_dev *pdev = to_pci_dev(host->dev);
574 void __iomem *port_mmio;
578 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
579 if (pdev->device == 0x6121)
583 port_mmio = __ahci_port_base(host, mv);
585 writel(0, port_mmio + PORT_IRQ_MASK);
588 tmp = readl(port_mmio + PORT_IRQ_STAT);
589 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
591 writel(tmp, port_mmio + PORT_IRQ_STAT);
594 ahci_init_controller(host);
597 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
598 unsigned long deadline)
600 struct ata_port *ap = link->ap;
606 ahci_stop_engine(ap);
608 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
609 deadline, &online, NULL);
611 ahci_start_engine(ap);
613 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
615 /* vt8251 doesn't clear BSY on signature FIS reception,
616 * request follow-up softreset.
618 return online ? -EAGAIN : rc;
621 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
622 unsigned long deadline)
624 struct ata_port *ap = link->ap;
625 struct ahci_port_priv *pp = ap->private_data;
626 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
627 struct ata_taskfile tf;
631 ahci_stop_engine(ap);
633 /* clear D2H reception area to properly wait for D2H FIS */
634 ata_tf_init(link->device, &tf);
635 tf.command = ATA_BUSY;
636 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
638 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
639 deadline, &online, NULL);
641 ahci_start_engine(ap);
643 /* The pseudo configuration device on SIMG4726 attached to
644 * ASUS P5W-DH Deluxe doesn't send signature FIS after
645 * hardreset if no device is attached to the first downstream
646 * port && the pseudo device locks up on SRST w/ PMP==0. To
647 * work around this, wait for !BSY only briefly. If BSY isn't
648 * cleared, perform CLO and proceed to IDENTIFY (achieved by
649 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
651 * Wait for two seconds. Devices attached to downstream port
652 * which can't process the following IDENTIFY after this will
653 * have to be reset again. For most cases, this should
654 * suffice while making probing snappish enough.
657 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
660 ahci_kick_engine(ap);
666 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
668 struct ata_host *host = pci_get_drvdata(pdev);
669 struct ahci_host_priv *hpriv = host->private_data;
670 void __iomem *mmio = hpriv->mmio;
673 if (mesg.event & PM_EVENT_SUSPEND &&
674 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
676 "BIOS update required for suspend/resume\n");
680 if (mesg.event & PM_EVENT_SLEEP) {
681 /* AHCI spec rev1.1 section 8.3.3:
682 * Software must disable interrupts prior to requesting a
683 * transition of the HBA to D3 state.
685 ctl = readl(mmio + HOST_CTL);
687 writel(ctl, mmio + HOST_CTL);
688 readl(mmio + HOST_CTL); /* flush */
691 return ata_pci_device_suspend(pdev, mesg);
694 static int ahci_pci_device_resume(struct pci_dev *pdev)
696 struct ata_host *host = pci_get_drvdata(pdev);
699 rc = ata_pci_device_do_resume(pdev);
703 /* Apple BIOS helpfully mangles the registers on resume */
704 if (is_mcp89_apple(pdev))
705 ahci_mcp89_apple_enable(pdev);
707 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
708 rc = ahci_pci_reset_controller(host);
712 ahci_pci_init_controller(host);
715 ata_host_resume(host);
721 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
726 * If the device fixup already set the dma_mask to some non-standard
727 * value, don't extend it here. This happens on STA2X11, for example.
729 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
733 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
734 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
736 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
739 "64-bit DMA enable failed\n");
744 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
746 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
749 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
752 "32-bit consistent DMA enable failed\n");
759 static void ahci_pci_print_info(struct ata_host *host)
761 struct pci_dev *pdev = to_pci_dev(host->dev);
765 pci_read_config_word(pdev, 0x0a, &cc);
766 if (cc == PCI_CLASS_STORAGE_IDE)
768 else if (cc == PCI_CLASS_STORAGE_SATA)
770 else if (cc == PCI_CLASS_STORAGE_RAID)
775 ahci_print_info(host, scc_s);
778 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
779 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
780 * support PMP and the 4726 either directly exports the device
781 * attached to the first downstream port or acts as a hardware storage
782 * controller and emulate a single ATA device (can be RAID 0/1 or some
783 * other configuration).
785 * When there's no device attached to the first downstream port of the
786 * 4726, "Config Disk" appears, which is a pseudo ATA device to
787 * configure the 4726. However, ATA emulation of the device is very
788 * lame. It doesn't send signature D2H Reg FIS after the initial
789 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
791 * The following function works around the problem by always using
792 * hardreset on the port and not depending on receiving signature FIS
793 * afterward. If signature FIS isn't received soon, ATA class is
794 * assumed without follow-up softreset.
796 static void ahci_p5wdh_workaround(struct ata_host *host)
798 static struct dmi_system_id sysids[] = {
800 .ident = "P5W DH Deluxe",
802 DMI_MATCH(DMI_SYS_VENDOR,
803 "ASUSTEK COMPUTER INC"),
804 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
809 struct pci_dev *pdev = to_pci_dev(host->dev);
811 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
812 dmi_check_system(sysids)) {
813 struct ata_port *ap = host->ports[1];
816 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
818 ap->ops = &ahci_p5wdh_ops;
819 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
824 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
825 * booting in BIOS compatibility mode. We restore the registers but not ID.
827 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
831 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
833 pci_read_config_dword(pdev, 0xf8, &val);
835 /* the following changes the device ID, but appears not to affect function */
836 /* val = (val & ~0xf0000000) | 0x80000000; */
837 pci_write_config_dword(pdev, 0xf8, val);
839 pci_read_config_dword(pdev, 0x54c, &val);
841 pci_write_config_dword(pdev, 0x54c, val);
843 pci_read_config_dword(pdev, 0x4a4, &val);
846 pci_write_config_dword(pdev, 0x4a4, val);
848 pci_read_config_dword(pdev, 0x54c, &val);
850 pci_write_config_dword(pdev, 0x54c, val);
852 pci_read_config_dword(pdev, 0xf8, &val);
854 pci_write_config_dword(pdev, 0xf8, val);
857 static bool is_mcp89_apple(struct pci_dev *pdev)
859 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
860 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
861 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
862 pdev->subsystem_device == 0xcb89;
865 /* only some SB600 ahci controllers can do 64bit DMA */
866 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
868 static const struct dmi_system_id sysids[] = {
870 * The oldest version known to be broken is 0901 and
871 * working is 1501 which was released on 2007-10-26.
872 * Enable 64bit DMA on 1501 and anything newer.
874 * Please read bko#9412 for more info.
877 .ident = "ASUS M2A-VM",
879 DMI_MATCH(DMI_BOARD_VENDOR,
880 "ASUSTeK Computer INC."),
881 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
883 .driver_data = "20071026", /* yyyymmdd */
886 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
889 * BIOS versions earlier than 1.5 had the Manufacturer DMI
890 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
891 * This spelling mistake was fixed in BIOS version 1.5, so
892 * 1.5 and later have the Manufacturer as
893 * "MICRO-STAR INTERNATIONAL CO.,LTD".
894 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
896 * BIOS versions earlier than 1.9 had a Board Product Name
897 * DMI field of "MS-7376". This was changed to be
898 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
899 * match on DMI_BOARD_NAME of "MS-7376".
902 .ident = "MSI K9A2 Platinum",
904 DMI_MATCH(DMI_BOARD_VENDOR,
906 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
910 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
913 * This board also had the typo mentioned above in the
914 * Manufacturer DMI field (fixed in BIOS version 1.5), so
915 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
918 .ident = "MSI K9AGM2",
920 DMI_MATCH(DMI_BOARD_VENDOR,
922 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
926 * All BIOS versions for the Asus M3A support 64bit DMA.
927 * (all release versions from 0301 to 1206 were tested)
932 DMI_MATCH(DMI_BOARD_VENDOR,
933 "ASUSTeK Computer INC."),
934 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
939 const struct dmi_system_id *match;
940 int year, month, date;
943 match = dmi_first_match(sysids);
944 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
948 if (!match->driver_data)
951 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
952 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
954 if (strcmp(buf, match->driver_data) >= 0)
958 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
964 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
968 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
970 static const struct dmi_system_id broken_systems[] = {
972 .ident = "HP Compaq nx6310",
974 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
975 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
977 /* PCI slot number of the controller */
978 .driver_data = (void *)0x1FUL,
981 .ident = "HP Compaq 6720s",
983 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
984 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
986 /* PCI slot number of the controller */
987 .driver_data = (void *)0x1FUL,
990 { } /* terminate list */
992 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
995 unsigned long slot = (unsigned long)dmi->driver_data;
996 /* apply the quirk only to on-board controllers */
997 return slot == PCI_SLOT(pdev->devfn);
1003 static bool ahci_broken_suspend(struct pci_dev *pdev)
1005 static const struct dmi_system_id sysids[] = {
1007 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1008 * to the harddisk doesn't become online after
1009 * resuming from STR. Warn and fail suspend.
1011 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1013 * Use dates instead of versions to match as HP is
1014 * apparently recycling both product and version
1017 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1022 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1023 DMI_MATCH(DMI_PRODUCT_NAME,
1024 "HP Pavilion dv4 Notebook PC"),
1026 .driver_data = "20090105", /* F.30 */
1031 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1032 DMI_MATCH(DMI_PRODUCT_NAME,
1033 "HP Pavilion dv5 Notebook PC"),
1035 .driver_data = "20090506", /* F.16 */
1040 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1041 DMI_MATCH(DMI_PRODUCT_NAME,
1042 "HP Pavilion dv6 Notebook PC"),
1044 .driver_data = "20090423", /* F.21 */
1049 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1050 DMI_MATCH(DMI_PRODUCT_NAME,
1051 "HP HDX18 Notebook PC"),
1053 .driver_data = "20090430", /* F.23 */
1056 * Acer eMachines G725 has the same problem. BIOS
1057 * V1.03 is known to be broken. V3.04 is known to
1058 * work. Between, there are V1.06, V2.06 and V3.03
1059 * that we don't have much idea about. For now,
1060 * blacklist anything older than V3.04.
1062 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1067 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1068 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1070 .driver_data = "20091216", /* V3.04 */
1072 { } /* terminate list */
1074 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1075 int year, month, date;
1078 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1081 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1082 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1084 return strcmp(buf, dmi->driver_data) < 0;
1087 static bool ahci_broken_online(struct pci_dev *pdev)
1089 #define ENCODE_BUSDEVFN(bus, slot, func) \
1090 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1091 static const struct dmi_system_id sysids[] = {
1093 * There are several gigabyte boards which use
1094 * SIMG5723s configured as hardware RAID. Certain
1095 * 5723 firmware revisions shipped there keep the link
1096 * online but fail to answer properly to SRST or
1097 * IDENTIFY when no device is attached downstream
1098 * causing libata to retry quite a few times leading
1099 * to excessive detection delay.
1101 * As these firmwares respond to the second reset try
1102 * with invalid device signature, considering unknown
1103 * sig as offline works around the problem acceptably.
1106 .ident = "EP45-DQ6",
1108 DMI_MATCH(DMI_BOARD_VENDOR,
1109 "Gigabyte Technology Co., Ltd."),
1110 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1112 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1115 .ident = "EP45-DS5",
1117 DMI_MATCH(DMI_BOARD_VENDOR,
1118 "Gigabyte Technology Co., Ltd."),
1119 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1121 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1123 { } /* terminate list */
1125 #undef ENCODE_BUSDEVFN
1126 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1132 val = (unsigned long)dmi->driver_data;
1134 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1137 #ifdef CONFIG_ATA_ACPI
1138 static void ahci_gtf_filter_workaround(struct ata_host *host)
1140 static const struct dmi_system_id sysids[] = {
1142 * Aspire 3810T issues a bunch of SATA enable commands
1143 * via _GTF including an invalid one and one which is
1144 * rejected by the device. Among the successful ones
1145 * is FPDMA non-zero offset enable which when enabled
1146 * only on the drive side leads to NCQ command
1147 * failures. Filter it out.
1150 .ident = "Aspire 3810T",
1152 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1153 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1155 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1159 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1160 unsigned int filter;
1166 filter = (unsigned long)dmi->driver_data;
1167 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1168 filter, dmi->ident);
1170 for (i = 0; i < host->n_ports; i++) {
1171 struct ata_port *ap = host->ports[i];
1172 struct ata_link *link;
1173 struct ata_device *dev;
1175 ata_for_each_link(link, ap, EDGE)
1176 ata_for_each_dev(dev, link, ALL)
1177 dev->gtf_filter |= filter;
1181 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1185 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1186 struct ahci_host_priv *hpriv)
1190 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1193 rc = pci_msi_vec_count(pdev);
1198 * If number of MSIs is less than number of ports then Sharing Last
1199 * Message mode could be enforced. In this case assume that advantage
1200 * of multipe MSIs is negated and use single MSI mode instead.
1206 rc = pci_enable_msi_block(pdev, nvec);
1212 /* fallback to single MSI mode if the controller enforced MRSM mode */
1213 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1214 pci_disable_msi(pdev);
1215 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1222 rc = pci_enable_msi(pdev);
1233 * ahci_host_activate - start AHCI host, request IRQs and register it
1234 * @host: target ATA host
1235 * @irq: base IRQ number to request
1236 * @n_msis: number of MSIs allocated for this host
1237 * @irq_handler: irq_handler used when requesting IRQs
1238 * @irq_flags: irq_flags used when requesting IRQs
1240 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1241 * when multiple MSIs were allocated. That is one MSI per port, starting
1245 * Inherited from calling layer (may sleep).
1248 * 0 on success, -errno otherwise.
1250 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1254 /* Sharing Last Message among several ports is not supported */
1255 if (n_msis < host->n_ports)
1258 rc = ata_host_start(host);
1262 for (i = 0; i < host->n_ports; i++) {
1263 struct ahci_port_priv *pp = host->ports[i]->private_data;
1265 /* Do not receive interrupts sent by dummy ports */
1267 disable_irq(irq + i);
1271 rc = devm_request_threaded_irq(host->dev, irq + i,
1273 ahci_thread_fn, IRQF_SHARED,
1274 pp->irq_desc, host->ports[i]);
1279 for (i = 0; i < host->n_ports; i++)
1280 ata_port_desc(host->ports[i], "irq %d", irq + i);
1282 rc = ata_host_register(host, &ahci_sht);
1284 goto out_free_all_irqs;
1291 for (i--; i >= 0; i--)
1292 devm_free_irq(host->dev, irq + i, host->ports[i]);
1297 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1299 unsigned int board_id = ent->driver_data;
1300 struct ata_port_info pi = ahci_port_info[board_id];
1301 const struct ata_port_info *ppi[] = { &pi, NULL };
1302 struct device *dev = &pdev->dev;
1303 struct ahci_host_priv *hpriv;
1304 struct ata_host *host;
1305 int n_ports, n_msis, i, rc;
1306 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1310 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1312 ata_print_version_once(&pdev->dev, DRV_VERSION);
1314 /* The AHCI driver can only drive the SATA ports, the PATA driver
1315 can drive them all so if both drivers are selected make sure
1316 AHCI stays out of the way */
1317 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1320 /* Apple BIOS on MCP89 prevents us using AHCI */
1321 if (is_mcp89_apple(pdev))
1322 ahci_mcp89_apple_enable(pdev);
1324 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1325 * At the moment, we can only use the AHCI mode. Let the users know
1326 * that for SAS drives they're out of luck.
1328 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1329 dev_info(&pdev->dev,
1330 "PDC42819 can only drive SATA devices with this driver\n");
1332 /* Both Connext and Enmotus devices use non-standard BARs */
1333 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1334 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1335 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1336 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1338 /* acquire resources */
1339 rc = pcim_enable_device(pdev);
1343 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1344 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1347 /* ICH6s share the same PCI ID for both piix and ahci
1348 * modes. Enabling ahci mode while MAP indicates
1349 * combined mode is a bad idea. Yield to ata_piix.
1351 pci_read_config_byte(pdev, ICH_MAP, &map);
1353 dev_info(&pdev->dev,
1354 "controller is in combined mode, can't enable AHCI mode\n");
1359 /* AHCI controllers often implement SFF compatible interface.
1360 * Grab all PCI BARs just in case.
1362 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1364 pcim_pin_device(pdev);
1368 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1371 hpriv->flags |= (unsigned long)pi.private_data;
1373 /* MCP65 revision A1 and A2 can't do MSI */
1374 if (board_id == board_ahci_mcp65 &&
1375 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1376 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1378 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1379 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1380 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1382 /* only some SB600s can do 64bit DMA */
1383 if (ahci_sb600_enable_64bit(pdev))
1384 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1386 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1388 /* save initial config */
1389 ahci_pci_save_initial_config(pdev, hpriv);
1392 if (hpriv->cap & HOST_CAP_NCQ) {
1393 pi.flags |= ATA_FLAG_NCQ;
1395 * Auto-activate optimization is supposed to be
1396 * supported on all AHCI controllers indicating NCQ
1397 * capability, but it seems to be broken on some
1398 * chipsets including NVIDIAs.
1400 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1401 pi.flags |= ATA_FLAG_FPDMA_AA;
1404 * All AHCI controllers should be forward-compatible
1405 * with the new auxiliary field. This code should be
1406 * conditionalized if any buggy AHCI controllers are
1409 pi.flags |= ATA_FLAG_FPDMA_AUX;
1412 if (hpriv->cap & HOST_CAP_PMP)
1413 pi.flags |= ATA_FLAG_PMP;
1415 ahci_set_em_messages(hpriv, &pi);
1417 if (ahci_broken_system_poweroff(pdev)) {
1418 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1419 dev_info(&pdev->dev,
1420 "quirky BIOS, skipping spindown on poweroff\n");
1423 if (ahci_broken_suspend(pdev)) {
1424 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1425 dev_warn(&pdev->dev,
1426 "BIOS update required for suspend/resume\n");
1429 if (ahci_broken_online(pdev)) {
1430 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1431 dev_info(&pdev->dev,
1432 "online status unreliable, applying workaround\n");
1435 /* CAP.NP sometimes indicate the index of the last enabled
1436 * port, at other times, that of the last possible port, so
1437 * determining the maximum port number requires looking at
1438 * both CAP.NP and port_map.
1440 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1442 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1444 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1446 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1449 host->private_data = hpriv;
1451 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1452 host->flags |= ATA_HOST_PARALLEL_SCAN;
1454 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1456 if (pi.flags & ATA_FLAG_EM)
1457 ahci_reset_em(host);
1459 for (i = 0; i < host->n_ports; i++) {
1460 struct ata_port *ap = host->ports[i];
1462 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1463 ata_port_pbar_desc(ap, ahci_pci_bar,
1464 0x100 + ap->port_no * 0x80, "port");
1466 /* set enclosure management message type */
1467 if (ap->flags & ATA_FLAG_EM)
1468 ap->em_message_type = hpriv->em_msg_type;
1471 /* disabled/not-implemented port */
1472 if (!(hpriv->port_map & (1 << i)))
1473 ap->ops = &ata_dummy_port_ops;
1476 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1477 ahci_p5wdh_workaround(host);
1479 /* apply gtf filter quirk */
1480 ahci_gtf_filter_workaround(host);
1482 /* initialize adapter */
1483 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1487 rc = ahci_pci_reset_controller(host);
1491 ahci_pci_init_controller(host);
1492 ahci_pci_print_info(host);
1494 pci_set_master(pdev);
1496 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1497 return ahci_host_activate(host, pdev->irq, n_msis);
1499 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1503 module_pci_driver(ahci_pci_driver);
1505 MODULE_AUTHOR("Jeff Garzik");
1506 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1507 MODULE_LICENSE("GPL");
1508 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1509 MODULE_VERSION(DRV_VERSION);