2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
96 static struct scsi_host_template ahci_sht = {
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
110 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
125 [board_ahci_noncq] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_nosntf] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
139 [board_ahci_yes_fbs] = {
140 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
147 [board_ahci_mcp65] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
150 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
155 [board_ahci_mcp77] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_mcp89] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
177 [board_ahci_sb600] = {
178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_pmp_retry_srst_ops,
186 [board_ahci_sb700] = { /* for SB700 and SB800 */
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_vt8251] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
202 static const struct pci_device_id ahci_pci_tbl[] = {
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
272 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
280 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
288 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
297 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
301 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
306 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
310 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
311 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
312 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
313 /* JMicron 362B and 362C have an AHCI function with IDE class code */
314 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
315 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
318 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
319 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
324 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
328 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
329 /* AMD is using RAID class only for ahci controllers */
330 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
331 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
334 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
335 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
338 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
425 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
426 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
428 /* ST Microelectronics */
429 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
432 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
433 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
435 .class = PCI_CLASS_STORAGE_SATA_AHCI,
436 .class_mask = 0xffffff,
437 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
439 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
440 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
441 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
450 .driver_data = board_ahci_yes_fbs },
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
452 .driver_data = board_ahci_yes_fbs },
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
454 .driver_data = board_ahci_yes_fbs },
455 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
456 .driver_data = board_ahci_yes_fbs },
459 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
460 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
463 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
464 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
465 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
466 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
469 * Samsung SSDs found on some macbooks. NCQ times out.
470 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
472 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
475 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
477 /* Generic, PCI class code for AHCI */
478 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
481 { } /* terminate list */
485 static struct pci_driver ahci_pci_driver = {
487 .id_table = ahci_pci_tbl,
488 .probe = ahci_init_one,
489 .remove = ata_pci_remove_one,
491 .suspend = ahci_pci_device_suspend,
492 .resume = ahci_pci_device_resume,
496 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
497 static int marvell_enable;
499 static int marvell_enable = 1;
501 module_param(marvell_enable, int, 0644);
502 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
505 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
506 struct ahci_host_priv *hpriv)
508 unsigned int force_port_map = 0;
509 unsigned int mask_port_map = 0;
511 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
512 dev_info(&pdev->dev, "JMB361 has only one port\n");
517 * Temporary Marvell 6145 hack: PATA port presence
518 * is asserted through the standard AHCI port
519 * presence register, as bit 4 (counting from 0)
521 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
522 if (pdev->device == 0x6121)
527 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
530 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
534 static int ahci_pci_reset_controller(struct ata_host *host)
536 struct pci_dev *pdev = to_pci_dev(host->dev);
538 ahci_reset_controller(host);
540 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
541 struct ahci_host_priv *hpriv = host->private_data;
545 pci_read_config_word(pdev, 0x92, &tmp16);
546 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
547 tmp16 |= hpriv->port_map;
548 pci_write_config_word(pdev, 0x92, tmp16);
555 static void ahci_pci_init_controller(struct ata_host *host)
557 struct ahci_host_priv *hpriv = host->private_data;
558 struct pci_dev *pdev = to_pci_dev(host->dev);
559 void __iomem *port_mmio;
563 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
564 if (pdev->device == 0x6121)
568 port_mmio = __ahci_port_base(host, mv);
570 writel(0, port_mmio + PORT_IRQ_MASK);
573 tmp = readl(port_mmio + PORT_IRQ_STAT);
574 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
576 writel(tmp, port_mmio + PORT_IRQ_STAT);
579 ahci_init_controller(host);
582 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
583 unsigned long deadline)
585 struct ata_port *ap = link->ap;
591 ahci_stop_engine(ap);
593 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
594 deadline, &online, NULL);
596 ahci_start_engine(ap);
598 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
600 /* vt8251 doesn't clear BSY on signature FIS reception,
601 * request follow-up softreset.
603 return online ? -EAGAIN : rc;
606 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
607 unsigned long deadline)
609 struct ata_port *ap = link->ap;
610 struct ahci_port_priv *pp = ap->private_data;
611 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
612 struct ata_taskfile tf;
616 ahci_stop_engine(ap);
618 /* clear D2H reception area to properly wait for D2H FIS */
619 ata_tf_init(link->device, &tf);
620 tf.command = ATA_BUSY;
621 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
623 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
624 deadline, &online, NULL);
626 ahci_start_engine(ap);
628 /* The pseudo configuration device on SIMG4726 attached to
629 * ASUS P5W-DH Deluxe doesn't send signature FIS after
630 * hardreset if no device is attached to the first downstream
631 * port && the pseudo device locks up on SRST w/ PMP==0. To
632 * work around this, wait for !BSY only briefly. If BSY isn't
633 * cleared, perform CLO and proceed to IDENTIFY (achieved by
634 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
636 * Wait for two seconds. Devices attached to downstream port
637 * which can't process the following IDENTIFY after this will
638 * have to be reset again. For most cases, this should
639 * suffice while making probing snappish enough.
642 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
645 ahci_kick_engine(ap);
651 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
653 struct ata_host *host = pci_get_drvdata(pdev);
654 struct ahci_host_priv *hpriv = host->private_data;
655 void __iomem *mmio = hpriv->mmio;
658 if (mesg.event & PM_EVENT_SUSPEND &&
659 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
661 "BIOS update required for suspend/resume\n");
665 if (mesg.event & PM_EVENT_SLEEP) {
666 /* AHCI spec rev1.1 section 8.3.3:
667 * Software must disable interrupts prior to requesting a
668 * transition of the HBA to D3 state.
670 ctl = readl(mmio + HOST_CTL);
672 writel(ctl, mmio + HOST_CTL);
673 readl(mmio + HOST_CTL); /* flush */
676 return ata_pci_device_suspend(pdev, mesg);
679 static int ahci_pci_device_resume(struct pci_dev *pdev)
681 struct ata_host *host = pci_get_drvdata(pdev);
684 rc = ata_pci_device_do_resume(pdev);
688 /* Apple BIOS helpfully mangles the registers on resume */
689 if (is_mcp89_apple(pdev))
690 ahci_mcp89_apple_enable(pdev);
692 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
693 rc = ahci_pci_reset_controller(host);
697 ahci_pci_init_controller(host);
700 ata_host_resume(host);
706 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
711 * If the device fixup already set the dma_mask to some non-standard
712 * value, don't extend it here. This happens on STA2X11, for example.
714 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
718 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
719 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
721 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
724 "64-bit DMA enable failed\n");
729 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
731 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
734 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
737 "32-bit consistent DMA enable failed\n");
744 static void ahci_pci_print_info(struct ata_host *host)
746 struct pci_dev *pdev = to_pci_dev(host->dev);
750 pci_read_config_word(pdev, 0x0a, &cc);
751 if (cc == PCI_CLASS_STORAGE_IDE)
753 else if (cc == PCI_CLASS_STORAGE_SATA)
755 else if (cc == PCI_CLASS_STORAGE_RAID)
760 ahci_print_info(host, scc_s);
763 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
764 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
765 * support PMP and the 4726 either directly exports the device
766 * attached to the first downstream port or acts as a hardware storage
767 * controller and emulate a single ATA device (can be RAID 0/1 or some
768 * other configuration).
770 * When there's no device attached to the first downstream port of the
771 * 4726, "Config Disk" appears, which is a pseudo ATA device to
772 * configure the 4726. However, ATA emulation of the device is very
773 * lame. It doesn't send signature D2H Reg FIS after the initial
774 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
776 * The following function works around the problem by always using
777 * hardreset on the port and not depending on receiving signature FIS
778 * afterward. If signature FIS isn't received soon, ATA class is
779 * assumed without follow-up softreset.
781 static void ahci_p5wdh_workaround(struct ata_host *host)
783 static struct dmi_system_id sysids[] = {
785 .ident = "P5W DH Deluxe",
787 DMI_MATCH(DMI_SYS_VENDOR,
788 "ASUSTEK COMPUTER INC"),
789 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
794 struct pci_dev *pdev = to_pci_dev(host->dev);
796 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
797 dmi_check_system(sysids)) {
798 struct ata_port *ap = host->ports[1];
801 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
803 ap->ops = &ahci_p5wdh_ops;
804 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
809 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
810 * booting in BIOS compatibility mode. We restore the registers but not ID.
812 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
816 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
818 pci_read_config_dword(pdev, 0xf8, &val);
820 /* the following changes the device ID, but appears not to affect function */
821 /* val = (val & ~0xf0000000) | 0x80000000; */
822 pci_write_config_dword(pdev, 0xf8, val);
824 pci_read_config_dword(pdev, 0x54c, &val);
826 pci_write_config_dword(pdev, 0x54c, val);
828 pci_read_config_dword(pdev, 0x4a4, &val);
831 pci_write_config_dword(pdev, 0x4a4, val);
833 pci_read_config_dword(pdev, 0x54c, &val);
835 pci_write_config_dword(pdev, 0x54c, val);
837 pci_read_config_dword(pdev, 0xf8, &val);
839 pci_write_config_dword(pdev, 0xf8, val);
842 static bool is_mcp89_apple(struct pci_dev *pdev)
844 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
845 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
846 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
847 pdev->subsystem_device == 0xcb89;
850 /* only some SB600 ahci controllers can do 64bit DMA */
851 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
853 static const struct dmi_system_id sysids[] = {
855 * The oldest version known to be broken is 0901 and
856 * working is 1501 which was released on 2007-10-26.
857 * Enable 64bit DMA on 1501 and anything newer.
859 * Please read bko#9412 for more info.
862 .ident = "ASUS M2A-VM",
864 DMI_MATCH(DMI_BOARD_VENDOR,
865 "ASUSTeK Computer INC."),
866 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
868 .driver_data = "20071026", /* yyyymmdd */
871 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
874 * BIOS versions earlier than 1.5 had the Manufacturer DMI
875 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
876 * This spelling mistake was fixed in BIOS version 1.5, so
877 * 1.5 and later have the Manufacturer as
878 * "MICRO-STAR INTERNATIONAL CO.,LTD".
879 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
881 * BIOS versions earlier than 1.9 had a Board Product Name
882 * DMI field of "MS-7376". This was changed to be
883 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
884 * match on DMI_BOARD_NAME of "MS-7376".
887 .ident = "MSI K9A2 Platinum",
889 DMI_MATCH(DMI_BOARD_VENDOR,
891 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
895 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
898 * This board also had the typo mentioned above in the
899 * Manufacturer DMI field (fixed in BIOS version 1.5), so
900 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
903 .ident = "MSI K9AGM2",
905 DMI_MATCH(DMI_BOARD_VENDOR,
907 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
911 * All BIOS versions for the Asus M3A support 64bit DMA.
912 * (all release versions from 0301 to 1206 were tested)
917 DMI_MATCH(DMI_BOARD_VENDOR,
918 "ASUSTeK Computer INC."),
919 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
924 const struct dmi_system_id *match;
925 int year, month, date;
928 match = dmi_first_match(sysids);
929 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
933 if (!match->driver_data)
936 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
937 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
939 if (strcmp(buf, match->driver_data) >= 0)
943 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
949 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
953 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
955 static const struct dmi_system_id broken_systems[] = {
957 .ident = "HP Compaq nx6310",
959 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
962 /* PCI slot number of the controller */
963 .driver_data = (void *)0x1FUL,
966 .ident = "HP Compaq 6720s",
968 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
969 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
971 /* PCI slot number of the controller */
972 .driver_data = (void *)0x1FUL,
975 { } /* terminate list */
977 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
980 unsigned long slot = (unsigned long)dmi->driver_data;
981 /* apply the quirk only to on-board controllers */
982 return slot == PCI_SLOT(pdev->devfn);
988 static bool ahci_broken_suspend(struct pci_dev *pdev)
990 static const struct dmi_system_id sysids[] = {
992 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
993 * to the harddisk doesn't become online after
994 * resuming from STR. Warn and fail suspend.
996 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
998 * Use dates instead of versions to match as HP is
999 * apparently recycling both product and version
1002 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1007 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1008 DMI_MATCH(DMI_PRODUCT_NAME,
1009 "HP Pavilion dv4 Notebook PC"),
1011 .driver_data = "20090105", /* F.30 */
1016 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1017 DMI_MATCH(DMI_PRODUCT_NAME,
1018 "HP Pavilion dv5 Notebook PC"),
1020 .driver_data = "20090506", /* F.16 */
1025 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1026 DMI_MATCH(DMI_PRODUCT_NAME,
1027 "HP Pavilion dv6 Notebook PC"),
1029 .driver_data = "20090423", /* F.21 */
1034 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1035 DMI_MATCH(DMI_PRODUCT_NAME,
1036 "HP HDX18 Notebook PC"),
1038 .driver_data = "20090430", /* F.23 */
1041 * Acer eMachines G725 has the same problem. BIOS
1042 * V1.03 is known to be broken. V3.04 is known to
1043 * work. Between, there are V1.06, V2.06 and V3.03
1044 * that we don't have much idea about. For now,
1045 * blacklist anything older than V3.04.
1047 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1052 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1053 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1055 .driver_data = "20091216", /* V3.04 */
1057 { } /* terminate list */
1059 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1060 int year, month, date;
1063 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1066 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1067 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1069 return strcmp(buf, dmi->driver_data) < 0;
1072 static bool ahci_broken_online(struct pci_dev *pdev)
1074 #define ENCODE_BUSDEVFN(bus, slot, func) \
1075 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1076 static const struct dmi_system_id sysids[] = {
1078 * There are several gigabyte boards which use
1079 * SIMG5723s configured as hardware RAID. Certain
1080 * 5723 firmware revisions shipped there keep the link
1081 * online but fail to answer properly to SRST or
1082 * IDENTIFY when no device is attached downstream
1083 * causing libata to retry quite a few times leading
1084 * to excessive detection delay.
1086 * As these firmwares respond to the second reset try
1087 * with invalid device signature, considering unknown
1088 * sig as offline works around the problem acceptably.
1091 .ident = "EP45-DQ6",
1093 DMI_MATCH(DMI_BOARD_VENDOR,
1094 "Gigabyte Technology Co., Ltd."),
1095 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1097 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1100 .ident = "EP45-DS5",
1102 DMI_MATCH(DMI_BOARD_VENDOR,
1103 "Gigabyte Technology Co., Ltd."),
1104 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1106 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1108 { } /* terminate list */
1110 #undef ENCODE_BUSDEVFN
1111 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1117 val = (unsigned long)dmi->driver_data;
1119 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1122 #ifdef CONFIG_ATA_ACPI
1123 static void ahci_gtf_filter_workaround(struct ata_host *host)
1125 static const struct dmi_system_id sysids[] = {
1127 * Aspire 3810T issues a bunch of SATA enable commands
1128 * via _GTF including an invalid one and one which is
1129 * rejected by the device. Among the successful ones
1130 * is FPDMA non-zero offset enable which when enabled
1131 * only on the drive side leads to NCQ command
1132 * failures. Filter it out.
1135 .ident = "Aspire 3810T",
1137 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1138 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1140 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1144 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1145 unsigned int filter;
1151 filter = (unsigned long)dmi->driver_data;
1152 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1153 filter, dmi->ident);
1155 for (i = 0; i < host->n_ports; i++) {
1156 struct ata_port *ap = host->ports[i];
1157 struct ata_link *link;
1158 struct ata_device *dev;
1160 ata_for_each_link(link, ap, EDGE)
1161 ata_for_each_dev(dev, link, ALL)
1162 dev->gtf_filter |= filter;
1166 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1170 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1171 struct ahci_host_priv *hpriv)
1175 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1178 rc = pci_msi_vec_count(pdev);
1183 * If number of MSIs is less than number of ports then Sharing Last
1184 * Message mode could be enforced. In this case assume that advantage
1185 * of multipe MSIs is negated and use single MSI mode instead.
1191 rc = pci_enable_msi_block(pdev, nvec);
1197 /* fallback to single MSI mode if the controller enforced MRSM mode */
1198 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1199 pci_disable_msi(pdev);
1200 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1207 rc = pci_enable_msi(pdev);
1218 * ahci_host_activate - start AHCI host, request IRQs and register it
1219 * @host: target ATA host
1220 * @irq: base IRQ number to request
1221 * @n_msis: number of MSIs allocated for this host
1222 * @irq_handler: irq_handler used when requesting IRQs
1223 * @irq_flags: irq_flags used when requesting IRQs
1225 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1226 * when multiple MSIs were allocated. That is one MSI per port, starting
1230 * Inherited from calling layer (may sleep).
1233 * 0 on success, -errno otherwise.
1235 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1239 /* Sharing Last Message among several ports is not supported */
1240 if (n_msis < host->n_ports)
1243 rc = ata_host_start(host);
1247 for (i = 0; i < host->n_ports; i++) {
1248 struct ahci_port_priv *pp = host->ports[i]->private_data;
1250 /* Do not receive interrupts sent by dummy ports */
1252 disable_irq(irq + i);
1256 rc = devm_request_threaded_irq(host->dev, irq + i,
1258 ahci_thread_fn, IRQF_SHARED,
1259 pp->irq_desc, host->ports[i]);
1264 for (i = 0; i < host->n_ports; i++)
1265 ata_port_desc(host->ports[i], "irq %d", irq + i);
1267 rc = ata_host_register(host, &ahci_sht);
1269 goto out_free_all_irqs;
1276 for (i--; i >= 0; i--)
1277 devm_free_irq(host->dev, irq + i, host->ports[i]);
1282 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1284 unsigned int board_id = ent->driver_data;
1285 struct ata_port_info pi = ahci_port_info[board_id];
1286 const struct ata_port_info *ppi[] = { &pi, NULL };
1287 struct device *dev = &pdev->dev;
1288 struct ahci_host_priv *hpriv;
1289 struct ata_host *host;
1290 int n_ports, n_msis, i, rc;
1291 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1295 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1297 ata_print_version_once(&pdev->dev, DRV_VERSION);
1299 /* The AHCI driver can only drive the SATA ports, the PATA driver
1300 can drive them all so if both drivers are selected make sure
1301 AHCI stays out of the way */
1302 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1305 /* Apple BIOS on MCP89 prevents us using AHCI */
1306 if (is_mcp89_apple(pdev))
1307 ahci_mcp89_apple_enable(pdev);
1309 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1310 * At the moment, we can only use the AHCI mode. Let the users know
1311 * that for SAS drives they're out of luck.
1313 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1314 dev_info(&pdev->dev,
1315 "PDC42819 can only drive SATA devices with this driver\n");
1317 /* Both Connext and Enmotus devices use non-standard BARs */
1318 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1319 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1320 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1321 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1323 /* acquire resources */
1324 rc = pcim_enable_device(pdev);
1328 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1329 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1332 /* ICH6s share the same PCI ID for both piix and ahci
1333 * modes. Enabling ahci mode while MAP indicates
1334 * combined mode is a bad idea. Yield to ata_piix.
1336 pci_read_config_byte(pdev, ICH_MAP, &map);
1338 dev_info(&pdev->dev,
1339 "controller is in combined mode, can't enable AHCI mode\n");
1344 /* AHCI controllers often implement SFF compatible interface.
1345 * Grab all PCI BARs just in case.
1347 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1349 pcim_pin_device(pdev);
1353 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1356 hpriv->flags |= (unsigned long)pi.private_data;
1358 /* MCP65 revision A1 and A2 can't do MSI */
1359 if (board_id == board_ahci_mcp65 &&
1360 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1361 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1363 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1364 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1365 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1367 /* only some SB600s can do 64bit DMA */
1368 if (ahci_sb600_enable_64bit(pdev))
1369 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1371 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1373 /* save initial config */
1374 ahci_pci_save_initial_config(pdev, hpriv);
1377 if (hpriv->cap & HOST_CAP_NCQ) {
1378 pi.flags |= ATA_FLAG_NCQ;
1380 * Auto-activate optimization is supposed to be
1381 * supported on all AHCI controllers indicating NCQ
1382 * capability, but it seems to be broken on some
1383 * chipsets including NVIDIAs.
1385 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1386 pi.flags |= ATA_FLAG_FPDMA_AA;
1389 * All AHCI controllers should be forward-compatible
1390 * with the new auxiliary field. This code should be
1391 * conditionalized if any buggy AHCI controllers are
1394 pi.flags |= ATA_FLAG_FPDMA_AUX;
1397 if (hpriv->cap & HOST_CAP_PMP)
1398 pi.flags |= ATA_FLAG_PMP;
1400 ahci_set_em_messages(hpriv, &pi);
1402 if (ahci_broken_system_poweroff(pdev)) {
1403 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1404 dev_info(&pdev->dev,
1405 "quirky BIOS, skipping spindown on poweroff\n");
1408 if (ahci_broken_suspend(pdev)) {
1409 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1410 dev_warn(&pdev->dev,
1411 "BIOS update required for suspend/resume\n");
1414 if (ahci_broken_online(pdev)) {
1415 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1416 dev_info(&pdev->dev,
1417 "online status unreliable, applying workaround\n");
1420 /* CAP.NP sometimes indicate the index of the last enabled
1421 * port, at other times, that of the last possible port, so
1422 * determining the maximum port number requires looking at
1423 * both CAP.NP and port_map.
1425 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1427 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1429 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1431 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1434 host->private_data = hpriv;
1436 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1437 host->flags |= ATA_HOST_PARALLEL_SCAN;
1439 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1441 if (pi.flags & ATA_FLAG_EM)
1442 ahci_reset_em(host);
1444 for (i = 0; i < host->n_ports; i++) {
1445 struct ata_port *ap = host->ports[i];
1447 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1448 ata_port_pbar_desc(ap, ahci_pci_bar,
1449 0x100 + ap->port_no * 0x80, "port");
1451 /* set enclosure management message type */
1452 if (ap->flags & ATA_FLAG_EM)
1453 ap->em_message_type = hpriv->em_msg_type;
1456 /* disabled/not-implemented port */
1457 if (!(hpriv->port_map & (1 << i)))
1458 ap->ops = &ata_dummy_port_ops;
1461 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1462 ahci_p5wdh_workaround(host);
1464 /* apply gtf filter quirk */
1465 ahci_gtf_filter_workaround(host);
1467 /* initialize adapter */
1468 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1472 rc = ahci_pci_reset_controller(host);
1476 ahci_pci_init_controller(host);
1477 ahci_pci_print_info(host);
1479 pci_set_master(pdev);
1481 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1482 return ahci_host_activate(host, pdev->irq, n_msis);
1484 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1488 module_pci_driver(ahci_pci_driver);
1490 MODULE_AUTHOR("Jeff Garzik");
1491 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1492 MODULE_LICENSE("GPL");
1493 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1494 MODULE_VERSION(DRV_VERSION);