1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
50 /* board IDs by feature in alphabetical order */
59 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_sb700, /* for SB700 and SB800 */
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
92 static bool is_mcp89_apple(struct pci_dev *pdev);
93 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
96 static int ahci_pci_device_runtime_suspend(struct device *dev);
97 static int ahci_pci_device_runtime_resume(struct device *dev);
98 #ifdef CONFIG_PM_SLEEP
99 static int ahci_pci_device_suspend(struct device *dev);
100 static int ahci_pci_device_resume(struct device *dev);
102 #endif /* CONFIG_PM */
104 static struct scsi_host_template ahci_sht = {
108 static struct ata_port_operations ahci_vt8251_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_vt8251_hardreset,
113 static struct ata_port_operations ahci_p5wdh_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_p5wdh_hardreset,
118 static struct ata_port_operations ahci_avn_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_avn_hardreset,
123 static const struct ata_port_info ahci_port_info[] = {
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
131 [board_ahci_ign_iferr] = {
132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
138 [board_ahci_mobile] = {
139 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
145 [board_ahci_nomsi] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
152 [board_ahci_noncq] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
159 [board_ahci_nosntf] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
166 [board_ahci_yes_fbs] = {
167 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_avn_ops,
187 [board_ahci_mcp65] = {
188 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
190 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_ops,
195 [board_ahci_mcp77] = {
196 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
202 [board_ahci_mcp89] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
210 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
211 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
212 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
217 [board_ahci_sb600] = {
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
219 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
220 AHCI_HFLAG_32BIT_ONLY),
221 .flags = AHCI_FLAG_COMMON,
222 .pio_mask = ATA_PIO4,
223 .udma_mask = ATA_UDMA6,
224 .port_ops = &ahci_pmp_retry_srst_ops,
226 [board_ahci_sb700] = { /* for SB700 and SB800 */
227 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
233 [board_ahci_vt8251] = {
234 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_vt8251_ops,
240 [board_ahci_pcs7] = {
241 .flags = AHCI_FLAG_COMMON,
242 .pio_mask = ATA_PIO4,
243 .udma_mask = ATA_UDMA6,
244 .port_ops = &ahci_ops,
248 static const struct pci_device_id ahci_pci_tbl[] = {
250 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
251 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
252 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
253 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
254 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
255 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
256 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
257 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
260 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
261 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
264 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
266 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
271 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
276 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
280 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
283 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
285 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
287 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
288 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
290 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
313 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
314 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
315 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
317 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
318 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
321 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
324 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
327 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
328 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
329 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
331 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
332 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
333 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
334 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
336 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
337 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
348 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
356 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
364 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
368 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
369 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
373 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
378 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
383 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
384 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
385 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
386 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
388 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
389 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
390 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
392 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
393 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
394 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
396 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
397 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
398 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
399 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
400 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
403 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
407 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
411 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
413 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
415 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
416 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
417 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
419 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
421 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
422 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
423 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
424 /* JMicron 362B and 362C have an AHCI function with IDE class code */
425 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
426 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
427 /* May need to update quirk_jmicron_async_suspend() for additions */
430 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
431 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
438 /* Amazon's Annapurna Labs support */
439 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
440 .class = PCI_CLASS_STORAGE_SATA_AHCI,
441 .class_mask = 0xffffff,
444 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
445 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
446 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
447 /* AMD is using RAID class only for ahci controllers */
448 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
449 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
452 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
453 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
456 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
457 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
460 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
467 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
468 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
479 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
480 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
532 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
542 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
543 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
546 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
547 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
548 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
550 /* ST Microelectronics */
551 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
554 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
555 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
556 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
557 .class = PCI_CLASS_STORAGE_SATA_AHCI,
558 .class_mask = 0xffffff,
559 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
561 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
562 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
563 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
564 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
566 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
568 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
570 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
572 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
582 .driver_data = board_ahci_yes_fbs },
583 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
584 .driver_data = board_ahci_yes_fbs },
587 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
588 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
591 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
592 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
593 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
594 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
595 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
596 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
599 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
600 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
602 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
603 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
606 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
609 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
611 /* Generic, PCI class code for AHCI */
612 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
613 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
615 { } /* terminate list */
618 static const struct dev_pm_ops ahci_pci_pm_ops = {
619 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
620 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
621 ahci_pci_device_runtime_resume, NULL)
624 static struct pci_driver ahci_pci_driver = {
626 .id_table = ahci_pci_tbl,
627 .probe = ahci_init_one,
628 .remove = ahci_remove_one,
629 .shutdown = ahci_shutdown_one,
631 .pm = &ahci_pci_pm_ops,
635 #if IS_ENABLED(CONFIG_PATA_MARVELL)
636 static int marvell_enable;
638 static int marvell_enable = 1;
640 module_param(marvell_enable, int, 0644);
641 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
643 static int mobile_lpm_policy = -1;
644 module_param(mobile_lpm_policy, int, 0644);
645 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
647 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
648 struct ahci_host_priv *hpriv)
650 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
651 dev_info(&pdev->dev, "JMB361 has only one port\n");
652 hpriv->force_port_map = 1;
656 * Temporary Marvell 6145 hack: PATA port presence
657 * is asserted through the standard AHCI port
658 * presence register, as bit 4 (counting from 0)
660 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
661 if (pdev->device == 0x6121)
662 hpriv->mask_port_map = 0x3;
664 hpriv->mask_port_map = 0xf;
666 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
669 ahci_save_initial_config(&pdev->dev, hpriv);
672 static int ahci_pci_reset_controller(struct ata_host *host)
674 struct pci_dev *pdev = to_pci_dev(host->dev);
675 struct ahci_host_priv *hpriv = host->private_data;
678 rc = ahci_reset_controller(host);
683 * If platform firmware failed to enable ports, try to enable
686 ahci_intel_pcs_quirk(pdev, hpriv);
691 static void ahci_pci_init_controller(struct ata_host *host)
693 struct ahci_host_priv *hpriv = host->private_data;
694 struct pci_dev *pdev = to_pci_dev(host->dev);
695 void __iomem *port_mmio;
699 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
700 if (pdev->device == 0x6121)
704 port_mmio = __ahci_port_base(host, mv);
706 writel(0, port_mmio + PORT_IRQ_MASK);
709 tmp = readl(port_mmio + PORT_IRQ_STAT);
710 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
712 writel(tmp, port_mmio + PORT_IRQ_STAT);
715 ahci_init_controller(host);
718 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
719 unsigned long deadline)
721 struct ata_port *ap = link->ap;
722 struct ahci_host_priv *hpriv = ap->host->private_data;
728 hpriv->stop_engine(ap);
730 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
731 deadline, &online, NULL);
733 hpriv->start_engine(ap);
735 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
737 /* vt8251 doesn't clear BSY on signature FIS reception,
738 * request follow-up softreset.
740 return online ? -EAGAIN : rc;
743 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
744 unsigned long deadline)
746 struct ata_port *ap = link->ap;
747 struct ahci_port_priv *pp = ap->private_data;
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
750 struct ata_taskfile tf;
754 hpriv->stop_engine(ap);
756 /* clear D2H reception area to properly wait for D2H FIS */
757 ata_tf_init(link->device, &tf);
758 tf.status = ATA_BUSY;
759 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
761 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
762 deadline, &online, NULL);
764 hpriv->start_engine(ap);
766 /* The pseudo configuration device on SIMG4726 attached to
767 * ASUS P5W-DH Deluxe doesn't send signature FIS after
768 * hardreset if no device is attached to the first downstream
769 * port && the pseudo device locks up on SRST w/ PMP==0. To
770 * work around this, wait for !BSY only briefly. If BSY isn't
771 * cleared, perform CLO and proceed to IDENTIFY (achieved by
772 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
774 * Wait for two seconds. Devices attached to downstream port
775 * which can't process the following IDENTIFY after this will
776 * have to be reset again. For most cases, this should
777 * suffice while making probing snappish enough.
780 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
783 ahci_kick_engine(ap);
789 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
791 * It has been observed with some SSDs that the timing of events in the
792 * link synchronization phase can leave the port in a state that can not
793 * be recovered by a SATA-hard-reset alone. The failing signature is
794 * SStatus.DET stuck at 1 ("Device presence detected but Phy
795 * communication not established"). It was found that unloading and
796 * reloading the driver when this problem occurs allows the drive
797 * connection to be recovered (DET advanced to 0x3). The critical
798 * component of reloading the driver is that the port state machines are
799 * reset by bouncing "port enable" in the AHCI PCS configuration
800 * register. So, reproduce that effect by bouncing a port whenever we
801 * see DET==1 after a reset.
803 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
804 unsigned long deadline)
806 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
807 struct ata_port *ap = link->ap;
808 struct ahci_port_priv *pp = ap->private_data;
809 struct ahci_host_priv *hpriv = ap->host->private_data;
810 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
811 unsigned long tmo = deadline - jiffies;
812 struct ata_taskfile tf;
818 hpriv->stop_engine(ap);
820 for (i = 0; i < 2; i++) {
823 int port = ap->port_no;
824 struct ata_host *host = ap->host;
825 struct pci_dev *pdev = to_pci_dev(host->dev);
827 /* clear D2H reception area to properly wait for D2H FIS */
828 ata_tf_init(link->device, &tf);
829 tf.status = ATA_BUSY;
830 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
832 rc = sata_link_hardreset(link, timing, deadline, &online,
835 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
836 (sstatus & 0xf) != 1)
839 ata_link_info(link, "avn bounce port%d\n", port);
841 pci_read_config_word(pdev, 0x92, &val);
843 pci_write_config_word(pdev, 0x92, val);
844 ata_msleep(ap, 1000);
846 pci_write_config_word(pdev, 0x92, val);
850 hpriv->start_engine(ap);
853 *class = ahci_dev_classify(ap);
855 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
861 static void ahci_pci_disable_interrupts(struct ata_host *host)
863 struct ahci_host_priv *hpriv = host->private_data;
864 void __iomem *mmio = hpriv->mmio;
867 /* AHCI spec rev1.1 section 8.3.3:
868 * Software must disable interrupts prior to requesting a
869 * transition of the HBA to D3 state.
871 ctl = readl(mmio + HOST_CTL);
873 writel(ctl, mmio + HOST_CTL);
874 readl(mmio + HOST_CTL); /* flush */
877 static int ahci_pci_device_runtime_suspend(struct device *dev)
879 struct pci_dev *pdev = to_pci_dev(dev);
880 struct ata_host *host = pci_get_drvdata(pdev);
882 ahci_pci_disable_interrupts(host);
886 static int ahci_pci_device_runtime_resume(struct device *dev)
888 struct pci_dev *pdev = to_pci_dev(dev);
889 struct ata_host *host = pci_get_drvdata(pdev);
892 rc = ahci_pci_reset_controller(host);
895 ahci_pci_init_controller(host);
899 #ifdef CONFIG_PM_SLEEP
900 static int ahci_pci_device_suspend(struct device *dev)
902 struct pci_dev *pdev = to_pci_dev(dev);
903 struct ata_host *host = pci_get_drvdata(pdev);
904 struct ahci_host_priv *hpriv = host->private_data;
906 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
908 "BIOS update required for suspend/resume\n");
912 ahci_pci_disable_interrupts(host);
913 return ata_host_suspend(host, PMSG_SUSPEND);
916 static int ahci_pci_device_resume(struct device *dev)
918 struct pci_dev *pdev = to_pci_dev(dev);
919 struct ata_host *host = pci_get_drvdata(pdev);
922 /* Apple BIOS helpfully mangles the registers on resume */
923 if (is_mcp89_apple(pdev))
924 ahci_mcp89_apple_enable(pdev);
926 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
927 rc = ahci_pci_reset_controller(host);
931 ahci_pci_init_controller(host);
934 ata_host_resume(host);
940 #endif /* CONFIG_PM */
942 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
944 const int dma_bits = using_dac ? 64 : 32;
948 * If the device fixup already set the dma_mask to some non-standard
949 * value, don't extend it here. This happens on STA2X11, for example.
951 * XXX: manipulating the DMA mask from platform code is completely
952 * bogus, platform code should use dev->bus_dma_limit instead..
954 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
957 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
959 dev_err(&pdev->dev, "DMA enable failed\n");
963 static void ahci_pci_print_info(struct ata_host *host)
965 struct pci_dev *pdev = to_pci_dev(host->dev);
969 pci_read_config_word(pdev, 0x0a, &cc);
970 if (cc == PCI_CLASS_STORAGE_IDE)
972 else if (cc == PCI_CLASS_STORAGE_SATA)
974 else if (cc == PCI_CLASS_STORAGE_RAID)
979 ahci_print_info(host, scc_s);
982 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
983 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
984 * support PMP and the 4726 either directly exports the device
985 * attached to the first downstream port or acts as a hardware storage
986 * controller and emulate a single ATA device (can be RAID 0/1 or some
987 * other configuration).
989 * When there's no device attached to the first downstream port of the
990 * 4726, "Config Disk" appears, which is a pseudo ATA device to
991 * configure the 4726. However, ATA emulation of the device is very
992 * lame. It doesn't send signature D2H Reg FIS after the initial
993 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
995 * The following function works around the problem by always using
996 * hardreset on the port and not depending on receiving signature FIS
997 * afterward. If signature FIS isn't received soon, ATA class is
998 * assumed without follow-up softreset.
1000 static void ahci_p5wdh_workaround(struct ata_host *host)
1002 static const struct dmi_system_id sysids[] = {
1004 .ident = "P5W DH Deluxe",
1006 DMI_MATCH(DMI_SYS_VENDOR,
1007 "ASUSTEK COMPUTER INC"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1013 struct pci_dev *pdev = to_pci_dev(host->dev);
1015 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1016 dmi_check_system(sysids)) {
1017 struct ata_port *ap = host->ports[1];
1019 dev_info(&pdev->dev,
1020 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1022 ap->ops = &ahci_p5wdh_ops;
1023 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1028 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1029 * booting in BIOS compatibility mode. We restore the registers but not ID.
1031 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1035 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1037 pci_read_config_dword(pdev, 0xf8, &val);
1039 /* the following changes the device ID, but appears not to affect function */
1040 /* val = (val & ~0xf0000000) | 0x80000000; */
1041 pci_write_config_dword(pdev, 0xf8, val);
1043 pci_read_config_dword(pdev, 0x54c, &val);
1045 pci_write_config_dword(pdev, 0x54c, val);
1047 pci_read_config_dword(pdev, 0x4a4, &val);
1050 pci_write_config_dword(pdev, 0x4a4, val);
1052 pci_read_config_dword(pdev, 0x54c, &val);
1054 pci_write_config_dword(pdev, 0x54c, val);
1056 pci_read_config_dword(pdev, 0xf8, &val);
1057 val &= ~(1 << 0x1b);
1058 pci_write_config_dword(pdev, 0xf8, val);
1061 static bool is_mcp89_apple(struct pci_dev *pdev)
1063 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1064 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1065 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1066 pdev->subsystem_device == 0xcb89;
1069 /* only some SB600 ahci controllers can do 64bit DMA */
1070 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1072 static const struct dmi_system_id sysids[] = {
1074 * The oldest version known to be broken is 0901 and
1075 * working is 1501 which was released on 2007-10-26.
1076 * Enable 64bit DMA on 1501 and anything newer.
1078 * Please read bko#9412 for more info.
1081 .ident = "ASUS M2A-VM",
1083 DMI_MATCH(DMI_BOARD_VENDOR,
1084 "ASUSTeK Computer INC."),
1085 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1087 .driver_data = "20071026", /* yyyymmdd */
1090 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1091 * support 64bit DMA.
1093 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1094 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1095 * This spelling mistake was fixed in BIOS version 1.5, so
1096 * 1.5 and later have the Manufacturer as
1097 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1098 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1100 * BIOS versions earlier than 1.9 had a Board Product Name
1101 * DMI field of "MS-7376". This was changed to be
1102 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1103 * match on DMI_BOARD_NAME of "MS-7376".
1106 .ident = "MSI K9A2 Platinum",
1108 DMI_MATCH(DMI_BOARD_VENDOR,
1109 "MICRO-STAR INTER"),
1110 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1114 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1117 * This board also had the typo mentioned above in the
1118 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1119 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1122 .ident = "MSI K9AGM2",
1124 DMI_MATCH(DMI_BOARD_VENDOR,
1125 "MICRO-STAR INTER"),
1126 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1130 * All BIOS versions for the Asus M3A support 64bit DMA.
1131 * (all release versions from 0301 to 1206 were tested)
1134 .ident = "ASUS M3A",
1136 DMI_MATCH(DMI_BOARD_VENDOR,
1137 "ASUSTeK Computer INC."),
1138 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1143 const struct dmi_system_id *match;
1144 int year, month, date;
1147 match = dmi_first_match(sysids);
1148 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1152 if (!match->driver_data)
1155 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1156 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1158 if (strcmp(buf, match->driver_data) >= 0)
1161 dev_warn(&pdev->dev,
1162 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1168 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1172 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1174 static const struct dmi_system_id broken_systems[] = {
1176 .ident = "HP Compaq nx6310",
1178 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1179 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1181 /* PCI slot number of the controller */
1182 .driver_data = (void *)0x1FUL,
1185 .ident = "HP Compaq 6720s",
1187 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1188 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1190 /* PCI slot number of the controller */
1191 .driver_data = (void *)0x1FUL,
1194 { } /* terminate list */
1196 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1199 unsigned long slot = (unsigned long)dmi->driver_data;
1200 /* apply the quirk only to on-board controllers */
1201 return slot == PCI_SLOT(pdev->devfn);
1207 static bool ahci_broken_suspend(struct pci_dev *pdev)
1209 static const struct dmi_system_id sysids[] = {
1211 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1212 * to the harddisk doesn't become online after
1213 * resuming from STR. Warn and fail suspend.
1215 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1217 * Use dates instead of versions to match as HP is
1218 * apparently recycling both product and version
1221 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1227 DMI_MATCH(DMI_PRODUCT_NAME,
1228 "HP Pavilion dv4 Notebook PC"),
1230 .driver_data = "20090105", /* F.30 */
1235 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1236 DMI_MATCH(DMI_PRODUCT_NAME,
1237 "HP Pavilion dv5 Notebook PC"),
1239 .driver_data = "20090506", /* F.16 */
1244 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1245 DMI_MATCH(DMI_PRODUCT_NAME,
1246 "HP Pavilion dv6 Notebook PC"),
1248 .driver_data = "20090423", /* F.21 */
1253 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1254 DMI_MATCH(DMI_PRODUCT_NAME,
1255 "HP HDX18 Notebook PC"),
1257 .driver_data = "20090430", /* F.23 */
1260 * Acer eMachines G725 has the same problem. BIOS
1261 * V1.03 is known to be broken. V3.04 is known to
1262 * work. Between, there are V1.06, V2.06 and V3.03
1263 * that we don't have much idea about. For now,
1264 * blacklist anything older than V3.04.
1266 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1271 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1272 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1274 .driver_data = "20091216", /* V3.04 */
1276 { } /* terminate list */
1278 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1279 int year, month, date;
1282 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1285 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1286 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1288 return strcmp(buf, dmi->driver_data) < 0;
1291 static bool ahci_broken_lpm(struct pci_dev *pdev)
1293 static const struct dmi_system_id sysids[] = {
1294 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1297 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1300 .driver_data = "20180406", /* 1.31 */
1304 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1305 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1307 .driver_data = "20180420", /* 1.28 */
1311 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1312 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1314 .driver_data = "20180315", /* 1.33 */
1318 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1319 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1322 * Note date based on release notes, 2.35 has been
1323 * reported to be good, but I've been unable to get
1324 * a hold of the reporter to get the DMI BIOS date.
1327 .driver_data = "20180310", /* 2.35 */
1329 { } /* terminate list */
1331 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1332 int year, month, date;
1338 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1339 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1341 return strcmp(buf, dmi->driver_data) < 0;
1344 static bool ahci_broken_online(struct pci_dev *pdev)
1346 #define ENCODE_BUSDEVFN(bus, slot, func) \
1347 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1348 static const struct dmi_system_id sysids[] = {
1350 * There are several gigabyte boards which use
1351 * SIMG5723s configured as hardware RAID. Certain
1352 * 5723 firmware revisions shipped there keep the link
1353 * online but fail to answer properly to SRST or
1354 * IDENTIFY when no device is attached downstream
1355 * causing libata to retry quite a few times leading
1356 * to excessive detection delay.
1358 * As these firmwares respond to the second reset try
1359 * with invalid device signature, considering unknown
1360 * sig as offline works around the problem acceptably.
1363 .ident = "EP45-DQ6",
1365 DMI_MATCH(DMI_BOARD_VENDOR,
1366 "Gigabyte Technology Co., Ltd."),
1367 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1369 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1372 .ident = "EP45-DS5",
1374 DMI_MATCH(DMI_BOARD_VENDOR,
1375 "Gigabyte Technology Co., Ltd."),
1376 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1378 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1380 { } /* terminate list */
1382 #undef ENCODE_BUSDEVFN
1383 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1389 val = (unsigned long)dmi->driver_data;
1391 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1394 static bool ahci_broken_devslp(struct pci_dev *pdev)
1396 /* device with broken DEVSLP but still showing SDS capability */
1397 static const struct pci_device_id ids[] = {
1398 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1402 return pci_match_id(ids, pdev);
1405 #ifdef CONFIG_ATA_ACPI
1406 static void ahci_gtf_filter_workaround(struct ata_host *host)
1408 static const struct dmi_system_id sysids[] = {
1410 * Aspire 3810T issues a bunch of SATA enable commands
1411 * via _GTF including an invalid one and one which is
1412 * rejected by the device. Among the successful ones
1413 * is FPDMA non-zero offset enable which when enabled
1414 * only on the drive side leads to NCQ command
1415 * failures. Filter it out.
1418 .ident = "Aspire 3810T",
1420 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1421 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1423 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1427 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1428 unsigned int filter;
1434 filter = (unsigned long)dmi->driver_data;
1435 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1436 filter, dmi->ident);
1438 for (i = 0; i < host->n_ports; i++) {
1439 struct ata_port *ap = host->ports[i];
1440 struct ata_link *link;
1441 struct ata_device *dev;
1443 ata_for_each_link(link, ap, EDGE)
1444 ata_for_each_dev(dev, link, ALL)
1445 dev->gtf_filter |= filter;
1449 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1454 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1455 * as DUMMY, or detected but eventually get a "link down" and never get up
1456 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1457 * port_map may hold a value of 0x00.
1459 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1460 * and can significantly reduce the occurrence of the problem.
1462 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1464 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1465 struct pci_dev *pdev)
1467 static const struct dmi_system_id sysids[] = {
1469 .ident = "Acer Switch Alpha 12",
1471 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1472 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1478 if (dmi_check_system(sysids)) {
1479 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1480 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1481 hpriv->port_map = 0x7;
1482 hpriv->cap = 0xC734FF02;
1489 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1490 * Workaround is to make sure all pending IRQs are served before leaving
1493 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1495 struct ata_host *host = dev_instance;
1496 struct ahci_host_priv *hpriv;
1497 unsigned int rc = 0;
1499 u32 irq_stat, irq_masked;
1500 unsigned int handled = 1;
1503 hpriv = host->private_data;
1505 irq_stat = readl(mmio + HOST_IRQ_STAT);
1510 irq_masked = irq_stat & hpriv->port_map;
1511 spin_lock(&host->lock);
1512 rc = ahci_handle_port_intr(host, irq_masked);
1515 writel(irq_stat, mmio + HOST_IRQ_STAT);
1516 irq_stat = readl(mmio + HOST_IRQ_STAT);
1517 spin_unlock(&host->lock);
1521 return IRQ_RETVAL(handled);
1525 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1526 struct ahci_host_priv *hpriv)
1532 * Check if this device might have remapped nvme devices.
1534 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1535 pci_resource_len(pdev, bar) < SZ_512K ||
1536 bar != AHCI_PCI_BAR_STANDARD ||
1537 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1540 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1541 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1542 if ((cap & (1 << i)) == 0)
1544 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1545 != PCI_CLASS_STORAGE_EXPRESS)
1548 /* We've found a remapped device */
1549 hpriv->remapped_nvme++;
1552 if (!hpriv->remapped_nvme)
1555 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1556 hpriv->remapped_nvme);
1557 dev_warn(&pdev->dev,
1558 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1561 * Don't rely on the msi-x capability in the remap case,
1562 * share the legacy interrupt across ahci and remapped devices.
1564 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1567 static int ahci_get_irq_vector(struct ata_host *host, int port)
1569 return pci_irq_vector(to_pci_dev(host->dev), port);
1572 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1573 struct ahci_host_priv *hpriv)
1577 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1581 * If number of MSIs is less than number of ports then Sharing Last
1582 * Message mode could be enforced. In this case assume that advantage
1583 * of multipe MSIs is negated and use single MSI mode instead.
1586 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1587 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1589 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1590 hpriv->get_irq_vector = ahci_get_irq_vector;
1591 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1596 * Fallback to single MSI mode if the controller
1597 * enforced MRSM mode.
1600 "ahci: MRSM is on, fallback to single MSI\n");
1601 pci_free_irq_vectors(pdev);
1606 * If the host is not capable of supporting per-port vectors, fall
1607 * back to single MSI before finally attempting single MSI-X.
1609 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1612 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1615 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1616 struct ahci_host_priv *hpriv)
1618 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1621 /* Ignore processing for non mobile platforms */
1622 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1625 /* user modified policy via module param */
1626 if (mobile_lpm_policy != -1) {
1627 policy = mobile_lpm_policy;
1632 if (policy > ATA_LPM_MED_POWER &&
1633 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1634 if (hpriv->cap & HOST_CAP_PART)
1635 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1636 else if (hpriv->cap & HOST_CAP_SSC)
1637 policy = ATA_LPM_MIN_POWER;
1642 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1643 ap->target_lpm_policy = policy;
1646 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1648 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1652 * Only apply the 6-port PCS quirk for known legacy platforms.
1654 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1657 /* Skip applying the quirk on Denverton and beyond */
1658 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1662 * port_map is determined from PORTS_IMPL PCI register which is
1663 * implemented as write or write-once register. If the register
1664 * isn't programmed, ahci automatically generates it from number
1665 * of ports, which is good enough for PCS programming. It is
1666 * otherwise expected that platform firmware enables the ports
1667 * before the OS boots.
1669 pci_read_config_word(pdev, PCS_6, &tmp16);
1670 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1671 tmp16 |= hpriv->port_map;
1672 pci_write_config_word(pdev, PCS_6, tmp16);
1676 static ssize_t remapped_nvme_show(struct device *dev,
1677 struct device_attribute *attr,
1680 struct ata_host *host = dev_get_drvdata(dev);
1681 struct ahci_host_priv *hpriv = host->private_data;
1683 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1686 static DEVICE_ATTR_RO(remapped_nvme);
1688 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1690 unsigned int board_id = ent->driver_data;
1691 struct ata_port_info pi = ahci_port_info[board_id];
1692 const struct ata_port_info *ppi[] = { &pi, NULL };
1693 struct device *dev = &pdev->dev;
1694 struct ahci_host_priv *hpriv;
1695 struct ata_host *host;
1697 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1701 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1703 ata_print_version_once(&pdev->dev, DRV_VERSION);
1705 /* The AHCI driver can only drive the SATA ports, the PATA driver
1706 can drive them all so if both drivers are selected make sure
1707 AHCI stays out of the way */
1708 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1711 /* Apple BIOS on MCP89 prevents us using AHCI */
1712 if (is_mcp89_apple(pdev))
1713 ahci_mcp89_apple_enable(pdev);
1715 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1716 * At the moment, we can only use the AHCI mode. Let the users know
1717 * that for SAS drives they're out of luck.
1719 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1720 dev_info(&pdev->dev,
1721 "PDC42819 can only drive SATA devices with this driver\n");
1723 /* Some devices use non-standard BARs */
1724 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1725 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1726 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1727 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1728 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1729 if (pdev->device == 0xa01c)
1730 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1731 if (pdev->device == 0xa084)
1732 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1733 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1734 if (pdev->device == 0x7a08)
1735 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1738 /* acquire resources */
1739 rc = pcim_enable_device(pdev);
1743 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1744 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1747 /* ICH6s share the same PCI ID for both piix and ahci
1748 * modes. Enabling ahci mode while MAP indicates
1749 * combined mode is a bad idea. Yield to ata_piix.
1751 pci_read_config_byte(pdev, ICH_MAP, &map);
1753 dev_info(&pdev->dev,
1754 "controller is in combined mode, can't enable AHCI mode\n");
1759 /* AHCI controllers often implement SFF compatible interface.
1760 * Grab all PCI BARs just in case.
1762 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1764 pcim_pin_device(pdev);
1768 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1771 hpriv->flags |= (unsigned long)pi.private_data;
1773 /* MCP65 revision A1 and A2 can't do MSI */
1774 if (board_id == board_ahci_mcp65 &&
1775 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1776 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1778 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1779 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1780 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1782 /* only some SB600s can do 64bit DMA */
1783 if (ahci_sb600_enable_64bit(pdev))
1784 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1786 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1788 /* detect remapped nvme devices */
1789 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1791 sysfs_add_file_to_group(&pdev->dev.kobj,
1792 &dev_attr_remapped_nvme.attr,
1795 /* must set flag prior to save config in order to take effect */
1796 if (ahci_broken_devslp(pdev))
1797 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1800 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1801 pdev->device == 0xa235 &&
1802 pdev->revision < 0x30)
1803 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1805 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1806 hpriv->irq_handler = ahci_thunderx_irq_handler;
1809 /* save initial config */
1810 ahci_pci_save_initial_config(pdev, hpriv);
1813 if (hpriv->cap & HOST_CAP_NCQ) {
1814 pi.flags |= ATA_FLAG_NCQ;
1816 * Auto-activate optimization is supposed to be
1817 * supported on all AHCI controllers indicating NCQ
1818 * capability, but it seems to be broken on some
1819 * chipsets including NVIDIAs.
1821 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1822 pi.flags |= ATA_FLAG_FPDMA_AA;
1825 * All AHCI controllers should be forward-compatible
1826 * with the new auxiliary field. This code should be
1827 * conditionalized if any buggy AHCI controllers are
1830 pi.flags |= ATA_FLAG_FPDMA_AUX;
1833 if (hpriv->cap & HOST_CAP_PMP)
1834 pi.flags |= ATA_FLAG_PMP;
1836 ahci_set_em_messages(hpriv, &pi);
1838 if (ahci_broken_system_poweroff(pdev)) {
1839 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1840 dev_info(&pdev->dev,
1841 "quirky BIOS, skipping spindown on poweroff\n");
1844 if (ahci_broken_lpm(pdev)) {
1845 pi.flags |= ATA_FLAG_NO_LPM;
1846 dev_warn(&pdev->dev,
1847 "BIOS update required for Link Power Management support\n");
1850 if (ahci_broken_suspend(pdev)) {
1851 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1852 dev_warn(&pdev->dev,
1853 "BIOS update required for suspend/resume\n");
1856 if (ahci_broken_online(pdev)) {
1857 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1858 dev_info(&pdev->dev,
1859 "online status unreliable, applying workaround\n");
1863 /* Acer SA5-271 workaround modifies private_data */
1864 acer_sa5_271_workaround(hpriv, pdev);
1866 /* CAP.NP sometimes indicate the index of the last enabled
1867 * port, at other times, that of the last possible port, so
1868 * determining the maximum port number requires looking at
1869 * both CAP.NP and port_map.
1871 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1873 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1876 host->private_data = hpriv;
1878 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1879 /* legacy intx interrupts */
1882 hpriv->irq = pci_irq_vector(pdev, 0);
1884 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1885 host->flags |= ATA_HOST_PARALLEL_SCAN;
1887 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1889 if (pi.flags & ATA_FLAG_EM)
1890 ahci_reset_em(host);
1892 for (i = 0; i < host->n_ports; i++) {
1893 struct ata_port *ap = host->ports[i];
1895 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1896 ata_port_pbar_desc(ap, ahci_pci_bar,
1897 0x100 + ap->port_no * 0x80, "port");
1899 /* set enclosure management message type */
1900 if (ap->flags & ATA_FLAG_EM)
1901 ap->em_message_type = hpriv->em_msg_type;
1903 ahci_update_initial_lpm_policy(ap, hpriv);
1905 /* disabled/not-implemented port */
1906 if (!(hpriv->port_map & (1 << i)))
1907 ap->ops = &ata_dummy_port_ops;
1910 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1911 ahci_p5wdh_workaround(host);
1913 /* apply gtf filter quirk */
1914 ahci_gtf_filter_workaround(host);
1916 /* initialize adapter */
1917 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1921 rc = ahci_pci_reset_controller(host);
1925 ahci_pci_init_controller(host);
1926 ahci_pci_print_info(host);
1928 pci_set_master(pdev);
1930 rc = ahci_host_activate(host, &ahci_sht);
1934 pm_runtime_put_noidle(&pdev->dev);
1938 static void ahci_shutdown_one(struct pci_dev *pdev)
1940 ata_pci_shutdown_one(pdev);
1943 static void ahci_remove_one(struct pci_dev *pdev)
1945 sysfs_remove_file_from_group(&pdev->dev.kobj,
1946 &dev_attr_remapped_nvme.attr,
1948 pm_runtime_get_noresume(&pdev->dev);
1949 ata_pci_remove_one(pdev);
1952 module_pci_driver(ahci_pci_driver);
1954 MODULE_AUTHOR("Jeff Garzik");
1955 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1956 MODULE_LICENSE("GPL");
1957 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1958 MODULE_VERSION(DRV_VERSION);