2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (C) 2011 Google, Inc.
6 * Jay Cheng <jacheng@nvidia.com>
7 * James Wylder <james.wylder@motorola.com>
8 * Benoit Goby <benoit@android.com>
9 * Colin Cross <ccross@android.com>
10 * Hiroshi DOYU <hdoyu@nvidia.com>
12 * This software is licensed under the terms of the GNU General Public
13 * License version 2, as published by the Free Software Foundation, and
14 * may be copied, distributed, and modified under those terms.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
27 #include <linux/tegra-ahb.h>
29 #define DRV_NAME "tegra-ahb"
31 #define AHB_ARBITRATION_DISABLE 0x00
32 #define AHB_ARBITRATION_PRIORITY_CTRL 0x04
33 #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
34 #define PRIORITY_SELECT_USB BIT(6)
35 #define PRIORITY_SELECT_USB2 BIT(18)
36 #define PRIORITY_SELECT_USB3 BIT(17)
38 #define AHB_GIZMO_AHB_MEM 0x0c
39 #define ENB_FAST_REARBITRATE BIT(2)
40 #define DONT_SPLIT_AHB_WR BIT(7)
42 #define AHB_GIZMO_APB_DMA 0x10
43 #define AHB_GIZMO_IDE 0x18
44 #define AHB_GIZMO_USB 0x1c
45 #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x20
46 #define AHB_GIZMO_CPU_AHB_BRIDGE 0x24
47 #define AHB_GIZMO_COP_AHB_BRIDGE 0x28
48 #define AHB_GIZMO_XBAR_APB_CTLR 0x2c
49 #define AHB_GIZMO_VCP_AHB_BRIDGE 0x30
50 #define AHB_GIZMO_NAND 0x3c
51 #define AHB_GIZMO_SDMMC4 0x44
52 #define AHB_GIZMO_XIO 0x48
53 #define AHB_GIZMO_BSEV 0x60
54 #define AHB_GIZMO_BSEA 0x70
55 #define AHB_GIZMO_NOR 0x74
56 #define AHB_GIZMO_USB2 0x78
57 #define AHB_GIZMO_USB3 0x7c
58 #define IMMEDIATE BIT(18)
60 #define AHB_GIZMO_SDMMC1 0x80
61 #define AHB_GIZMO_SDMMC2 0x84
62 #define AHB_GIZMO_SDMMC3 0x88
63 #define AHB_MEM_PREFETCH_CFG_X 0xd8
64 #define AHB_ARBITRATION_XBAR_CTRL 0xdc
65 #define AHB_MEM_PREFETCH_CFG3 0xe0
66 #define AHB_MEM_PREFETCH_CFG4 0xe4
67 #define AHB_MEM_PREFETCH_CFG1 0xec
68 #define AHB_MEM_PREFETCH_CFG2 0xf0
69 #define PREFETCH_ENB BIT(31)
70 #define MST_ID(x) (((x) & 0x1f) << 26)
71 #define AHBDMA_MST_ID MST_ID(5)
72 #define USB_MST_ID MST_ID(6)
73 #define USB2_MST_ID MST_ID(18)
74 #define USB3_MST_ID MST_ID(17)
75 #define ADDR_BNDRY(x) (((x) & 0xf) << 21)
76 #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
78 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xf8
80 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
82 static struct platform_driver tegra_ahb_driver;
84 static const u32 tegra_ahb_gizmo[] = {
85 AHB_ARBITRATION_DISABLE,
86 AHB_ARBITRATION_PRIORITY_CTRL,
91 AHB_GIZMO_AHB_XBAR_BRIDGE,
92 AHB_GIZMO_CPU_AHB_BRIDGE,
93 AHB_GIZMO_COP_AHB_BRIDGE,
94 AHB_GIZMO_XBAR_APB_CTLR,
95 AHB_GIZMO_VCP_AHB_BRIDGE,
107 AHB_MEM_PREFETCH_CFG_X,
108 AHB_ARBITRATION_XBAR_CTRL,
109 AHB_MEM_PREFETCH_CFG3,
110 AHB_MEM_PREFETCH_CFG4,
111 AHB_MEM_PREFETCH_CFG1,
112 AHB_MEM_PREFETCH_CFG2,
113 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
122 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
124 return readl(ahb->regs + offset);
127 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
129 writel(value, ahb->regs + offset);
132 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
133 static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
135 struct tegra_ahb *ahb = dev_get_drvdata(dev);
136 struct device_node *dn = data;
138 return (ahb->dev->of_node == dn) ? 1 : 0;
141 int tegra_ahb_enable_smmu(struct device_node *dn)
145 struct tegra_ahb *ahb;
147 dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
148 tegra_ahb_match_by_smmu);
150 return -EPROBE_DEFER;
151 ahb = dev_get_drvdata(dev);
152 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
153 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
154 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
157 EXPORT_SYMBOL(tegra_ahb_enable_smmu);
160 #ifdef CONFIG_PM_SLEEP
161 static int tegra_ahb_suspend(struct device *dev)
164 struct tegra_ahb *ahb = dev_get_drvdata(dev);
166 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
167 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
171 static int tegra_ahb_resume(struct device *dev)
174 struct tegra_ahb *ahb = dev_get_drvdata(dev);
176 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
177 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
182 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
184 tegra_ahb_resume, NULL);
186 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
190 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
191 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
192 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
194 val = gizmo_readl(ahb, AHB_GIZMO_USB);
196 gizmo_writel(ahb, val, AHB_GIZMO_USB);
198 val = gizmo_readl(ahb, AHB_GIZMO_USB2);
200 gizmo_writel(ahb, val, AHB_GIZMO_USB2);
202 val = gizmo_readl(ahb, AHB_GIZMO_USB3);
204 gizmo_writel(ahb, val, AHB_GIZMO_USB3);
206 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
207 val |= PRIORITY_SELECT_USB |
208 PRIORITY_SELECT_USB2 |
209 PRIORITY_SELECT_USB3 |
210 AHB_PRIORITY_WEIGHT(7);
211 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
213 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
215 val |= PREFETCH_ENB |
218 INACTIVITY_TIMEOUT(0x1000);
219 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
221 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
223 val |= PREFETCH_ENB |
226 INACTIVITY_TIMEOUT(0x1000);
227 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
229 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
231 val |= PREFETCH_ENB |
234 INACTIVITY_TIMEOUT(0x1000);
235 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
237 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
239 val |= PREFETCH_ENB |
242 INACTIVITY_TIMEOUT(0x1000);
243 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
246 static int tegra_ahb_probe(struct platform_device *pdev)
248 struct resource *res;
249 struct tegra_ahb *ahb;
252 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
253 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
260 ahb->regs = devm_request_and_ioremap(&pdev->dev, res);
264 ahb->dev = &pdev->dev;
265 platform_set_drvdata(pdev, ahb);
266 tegra_ahb_gizmo_init(ahb);
270 static const struct of_device_id tegra_ahb_of_match[] = {
271 { .compatible = "nvidia,tegra30-ahb", },
272 { .compatible = "nvidia,tegra20-ahb", },
276 static struct platform_driver tegra_ahb_driver = {
277 .probe = tegra_ahb_probe,
280 .owner = THIS_MODULE,
281 .of_match_table = tegra_ahb_of_match,
285 module_platform_driver(tegra_ahb_driver);
287 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
288 MODULE_DESCRIPTION("Tegra AHB driver");
289 MODULE_LICENSE("GPL v2");
290 MODULE_ALIAS("platform:" DRV_NAME);