drivers/acpi/pci_root.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
   4  *
   5  *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
   6  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) "ACPI: " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/types.h>
  15 #include <linux/mutex.h>
  16 #include <linux/pm.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci-acpi.h>
  20 #include <linux/dmar.h>
  21 #include <linux/acpi.h>
  22 #include <linux/slab.h>
  23 #include <linux/dmi.h>
  24 #include <linux/platform_data/x86/apple.h>
  25 #include "internal.h"
  26
  27 #define ACPI_PCI_ROOT_CLASS             "pci_bridge"
  28 #define ACPI_PCI_ROOT_DEVICE_NAME       "PCI Root Bridge"
  29 static int acpi_pci_root_add(struct acpi_device *device,
  30                              const struct acpi_device_id *not_used);
  31 static void acpi_pci_root_remove(struct acpi_device *device);
  32
  33 static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
  34 {
  35         acpiphp_check_host_bridge(adev);
  36         return 0;
  37 }
  38
  39 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
  40                                 | OSC_PCI_ASPM_SUPPORT \
  41                                 | OSC_PCI_CLOCK_PM_SUPPORT \
  42                                 | OSC_PCI_MSI_SUPPORT)
  43
  44 static const struct acpi_device_id root_device_ids[] = {
  45         {"PNP0A03", 0},
  46         {"", 0},
  47 };
  48
  49 static struct acpi_scan_handler pci_root_handler = {
  50         .ids = root_device_ids,
  51         .attach = acpi_pci_root_add,
  52         .detach = acpi_pci_root_remove,
  53         .hotplug = {
  54                 .enabled = true,
  55                 .scan_dependent = acpi_pci_root_scan_dependent,
  56         },
  57 };
  58
  59 /**
  60  * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
  61  * @handle:  the ACPI CA node in question.
  62  *
  63  * Note: we could make this API take a struct acpi_device * instead, but
  64  * for now, it's more convenient to operate on an acpi_handle.
  65  */
  66 int acpi_is_root_bridge(acpi_handle handle)
  67 {
  68         struct acpi_device *device = acpi_fetch_acpi_dev(handle);
  69         int ret;
  70
  71         if (!device)
  72                 return 0;
  73
  74         ret = acpi_match_device_ids(device, root_device_ids);
  75         if (ret)
  76                 return 0;
  77         else
  78                 return 1;
  79 }
  80 EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
  81
  82 static acpi_status
  83 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
  84 {
  85         struct resource *res = data;
  86         struct acpi_resource_address64 address;
  87         acpi_status status;
  88
  89         status = acpi_resource_to_address64(resource, &address);
  90         if (ACPI_FAILURE(status))
  91                 return AE_OK;
  92
  93         if ((address.address.address_length > 0) &&
  94             (address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
  95                 res->start = address.address.minimum;
  96                 res->end = address.address.minimum + address.address.address_length - 1;
  97         }
  98
  99         return AE_OK;
 100 }
 101
 102 static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
 103                                              struct resource *res)
 104 {
 105         acpi_status status;
 106
 107         res->start = -1;
 108         status =
 109             acpi_walk_resources(handle, METHOD_NAME__CRS,
 110                                 get_root_bridge_busnr_callback, res);
 111         if (ACPI_FAILURE(status))
 112                 return status;
 113         if (res->start == -1)
 114                 return AE_ERROR;
 115         return AE_OK;
 116 }
 117
 118 struct pci_osc_bit_struct {
 119         u32 bit;
 120         char *desc;
 121 };
 122
 123 static struct pci_osc_bit_struct pci_osc_support_bit[] = {
 124         { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
 125         { OSC_PCI_ASPM_SUPPORT, "ASPM" },
 126         { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
 127         { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
 128         { OSC_PCI_MSI_SUPPORT, "MSI" },
 129         { OSC_PCI_EDR_SUPPORT, "EDR" },
 130         { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
 131 };
 132
 133 static struct pci_osc_bit_struct pci_osc_control_bit[] = {
 134         { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
 135         { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
 136         { OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
 137         { OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
 138         { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
 139         { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
 140         { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
 141 };
 142
 143 static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
 144         { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
 145         { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
 146         { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
 147         { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
 148 };
 149
 150 static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
 151         { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
 152 };
 153
 154 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
 155                             struct pci_osc_bit_struct *table, int size)
 156 {
 157         char buf[80];
 158         int i, len = 0;
 159         struct pci_osc_bit_struct *entry;
 160
 161         buf[0] = '\0';
 162         for (i = 0, entry = table; i < size; i++, entry++)
 163                 if (word & entry->bit)
 164                         len += scnprintf(buf + len, sizeof(buf) - len, "%s%s",
 165                                         len ? " " : "", entry->desc);
 166
 167         dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
 168 }
 169
 170 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
 171 {
 172         decode_osc_bits(root, msg, word, pci_osc_support_bit,
 173                         ARRAY_SIZE(pci_osc_support_bit));
 174 }
 175
 176 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
 177 {
 178         decode_osc_bits(root, msg, word, pci_osc_control_bit,
 179                         ARRAY_SIZE(pci_osc_control_bit));
 180 }
 181
 182 static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
 183 {
 184         decode_osc_bits(root, msg, word, cxl_osc_support_bit,
 185                         ARRAY_SIZE(cxl_osc_support_bit));
 186 }
 187
 188 static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
 189 {
 190         decode_osc_bits(root, msg, word, cxl_osc_control_bit,
 191                         ARRAY_SIZE(cxl_osc_control_bit));
 192 }
 193
 194 static inline bool is_pcie(struct acpi_pci_root *root)
 195 {
 196         return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE;
 197 }
 198
 199 static inline bool is_cxl(struct acpi_pci_root *root)
 200 {
 201         return root->bridge_type == ACPI_BRIDGE_TYPE_CXL;
 202 }
 203
 204 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
 205 static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
 206
 207 static char *to_uuid(struct acpi_pci_root *root)
 208 {
 209         if (is_cxl(root))
 210                 return cxl_osc_uuid_str;
 211         return pci_osc_uuid_str;
 212 }
 213
 214 static int cap_length(struct acpi_pci_root *root)
 215 {
 216         if (is_cxl(root))
 217                 return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS;
 218         return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS;
 219 }
 220
 221 static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
 222                                     const u32 *capbuf, u32 *pci_control,
 223                                     u32 *cxl_control)
 224 {
 225         struct acpi_osc_context context = {
 226                 .uuid_str = to_uuid(root),
 227                 .rev = 1,
 228                 .cap.length = cap_length(root),
 229                 .cap.pointer = (void *)capbuf,
 230         };
 231         acpi_status status;
 232
 233         status = acpi_run_osc(root->device->handle, &context);
 234         if (ACPI_SUCCESS(status)) {
 235                 *pci_control = acpi_osc_ctx_get_pci_control(&context);
 236                 if (is_cxl(root))
 237                         *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
 238                 kfree(context.ret.pointer);
 239         }
 240         return status;
 241 }
 242
 243 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
 244                                       u32 *control, u32 cxl_support,
 245                                       u32 *cxl_control)
 246 {
 247         acpi_status status;
 248         u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS];
 249
 250         support |= root->osc_support_set;
 251
 252         capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
 253         capbuf[OSC_SUPPORT_DWORD] = support;
 254         capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
 255
 256         if (is_cxl(root)) {
 257                 cxl_support |= root->osc_ext_support_set;
 258                 capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support;
 259                 capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set;
 260         }
 261
 262 retry:
 263         status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
 264         if (ACPI_SUCCESS(status)) {
 265                 root->osc_support_set = support;
 266                 *control = pci_result;
 267                 if (is_cxl(root)) {
 268                         root->osc_ext_support_set = cxl_support;
 269                         *cxl_control = cxl_result;
 270                 }
 271         } else if (is_cxl(root)) {
 272                 /*
 273                  * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
 274                  * upon any failure using CXL _OSC.
 275                  */
 276                 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
 277                 goto retry;
 278         }
 279         return status;
 280 }
 281
 282 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
 283 {
 284         struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 285         struct acpi_pci_root *root;
 286
 287         if (!device || acpi_match_device_ids(device, root_device_ids))
 288                 return NULL;
 289
 290         root = acpi_driver_data(device);
 291
 292         return root;
 293 }
 294 EXPORT_SYMBOL_GPL(acpi_pci_find_root);
 295
 296 struct acpi_handle_node {
 297         struct list_head node;
 298         acpi_handle handle;
 299 };
 300
 301 /**
 302  * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
 303  * @handle: the handle in question
 304  *
 305  * Given an ACPI CA handle, the desired PCI device is located in the
 306  * list of PCI devices.
 307  *
 308  * If the device is found, its reference count is increased and this
 309  * function returns a pointer to its data structure.  The caller must
 310  * decrement the reference count by calling pci_dev_put().
 311  * If no device is found, %NULL is returned.
 312  */
 313 struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
 314 {
 315         struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
 316         struct acpi_device_physical_node *pn;
 317         struct pci_dev *pci_dev = NULL;
 318
 319         if (!adev)
 320                 return NULL;
 321
 322         mutex_lock(&adev->physical_node_lock);
 323
 324         list_for_each_entry(pn, &adev->physical_node_list, node) {
 325                 if (dev_is_pci(pn->dev)) {
 326                         pci_dev = to_pci_dev(pn->dev);
 327                         break;
 328                 }
 329         }
 330
 331         mutex_unlock(&adev->physical_node_lock);
 332
 333         return pci_dev;
 334 }
 335 EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
 336
 337 /**
 338  * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
 339  * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
 340  * @mask: Mask of _OSC bits to request control of, place to store control mask.
 341  * @support: _OSC supported capability.
 342  * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
 343  * @cxl_support: CXL _OSC supported capability.
 344  *
 345  * Run _OSC query for @mask and if that is successful, compare the returned
 346  * mask of control bits with @req.  If all of the @req bits are set in the
 347  * returned mask, run _OSC request for it.
 348  *
 349  * The variable at the @mask address may be modified regardless of whether or
 350  * not the function returns success.  On success it will contain the mask of
 351  * _OSC bits the BIOS has granted control of, but its contents are meaningless
 352  * on failure.
 353  **/
 354 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
 355                                             u32 support, u32 *cxl_mask,
 356                                             u32 cxl_support)
 357 {
 358         u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
 359         struct acpi_pci_root *root;
 360         acpi_status status;
 361         u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS];
 362
 363         if (!mask)
 364                 return AE_BAD_PARAMETER;
 365
 366         root = acpi_pci_find_root(handle);
 367         if (!root)
 368                 return AE_NOT_EXIST;
 369
 370         ctrl   = *mask;
 371         *mask |= root->osc_control_set;
 372
 373         if (is_cxl(root)) {
 374                 cxl_ctrl = *cxl_mask;
 375                 *cxl_mask |= root->osc_ext_control_set;
 376         }
 377
 378         /* Need to check the available controls bits before requesting them. */
 379         do {
 380                 u32 pci_missing = 0, cxl_missing = 0;
 381
 382                 status = acpi_pci_query_osc(root, support, mask, cxl_support,
 383                                             cxl_mask);
 384                 if (ACPI_FAILURE(status))
 385                         return status;
 386                 if (is_cxl(root)) {
 387                         if (ctrl == *mask && cxl_ctrl == *cxl_mask)
 388                                 break;
 389                         pci_missing = ctrl & ~(*mask);
 390                         cxl_missing = cxl_ctrl & ~(*cxl_mask);
 391                 } else {
 392                         if (ctrl == *mask)
 393                                 break;
 394                         pci_missing = ctrl & ~(*mask);
 395                 }
 396                 if (pci_missing)
 397                         decode_osc_control(root, "platform does not support",
 398                                            pci_missing);
 399                 if (cxl_missing)
 400                         decode_cxl_osc_control(root, "CXL platform does not support",
 401                                            cxl_missing);
 402                 ctrl = *mask;
 403                 cxl_ctrl = *cxl_mask;
 404         } while (*mask || *cxl_mask);
 405
 406         /* No need to request _OSC if the control was already granted. */
 407         if ((root->osc_control_set & ctrl) == ctrl &&
 408             (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl)
 409                 return AE_OK;
 410
 411         if ((ctrl & req) != req) {
 412                 decode_osc_control(root, "not requesting control; platform does not support",
 413                                    req & ~(ctrl));
 414                 return AE_SUPPORT;
 415         }
 416
 417         capbuf[OSC_QUERY_DWORD] = 0;
 418         capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
 419         capbuf[OSC_CONTROL_DWORD] = ctrl;
 420         if (is_cxl(root)) {
 421                 capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set;
 422                 capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl;
 423         }
 424
 425         status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
 426         if (ACPI_FAILURE(status))
 427                 return status;
 428
 429         root->osc_control_set = *mask;
 430         root->osc_ext_control_set = *cxl_mask;
 431         return AE_OK;
 432 }
 433
 434 static u32 calculate_support(void)
 435 {
 436         u32 support;
 437
 438         /*
 439          * All supported architectures that use ACPI have support for
 440          * PCI domains, so we indicate this in _OSC support capabilities.
 441          */
 442         support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
 443         support |= OSC_PCI_HPX_TYPE_3_SUPPORT;
 444         if (pci_ext_cfg_avail())
 445                 support |= OSC_PCI_EXT_CONFIG_SUPPORT;
 446         if (pcie_aspm_support_enabled())
 447                 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
 448         if (pci_msi_enabled())
 449                 support |= OSC_PCI_MSI_SUPPORT;
 450         if (IS_ENABLED(CONFIG_PCIE_EDR))
 451                 support |= OSC_PCI_EDR_SUPPORT;
 452
 453         return support;
 454 }
 455
 456 /*
 457  * Background on hotplug support, and making it depend on only
 458  * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG:
 459  *
 460  * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but
 461  * there is no existing _OSC for memory hotplug support. The reason is that
 462  * ACPI memory hotplug requires the OS to acknowledge / coordinate with
 463  * memory plug events via a scan handler. On the CXL side the equivalent
 464  * would be if Linux supported the Mechanical Retention Lock [1], or
 465  * otherwise had some coordination for the driver of a PCI device
 466  * undergoing hotplug to be consulted on whether the hotplug should
 467  * proceed or not.
 468  *
 469  * The concern is that if Linux says no to supporting CXL hotplug then
 470  * the BIOS may say no to giving the OS hotplug control of any other PCIe
 471  * device. So the question here is not whether hotplug is enabled, it's
 472  * whether it is handled natively by the at all OS, and if
 473  * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes".
 474  *
 475  * Otherwise, the plan for CXL coordinated remove, since the kernel does
 476  * not support blocking hotplug, is to require the memory device to be
 477  * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is
 478  * disabled that step will fail and the remove attempt cancelled by the
 479  * user. If that is not honored and the card is removed anyway then it
 480  * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will
 481  * cause a crash and other badness.
 482  *
 483  * Therefore, just say yes to CXL hotplug and require removal to
 484  * be coordinated by userspace unless and until the kernel grows better
 485  * mechanisms for doing "managed" removal of devices in consultation with
 486  * the driver.
 487  *
 488  * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/
 489  */
 490 static u32 calculate_cxl_support(void)
 491 {
 492         u32 support;
 493
 494         support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
 495         if (pci_aer_available())
 496                 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
 497         if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
 498                 support |= OSC_CXL_NATIVE_HP_SUPPORT;
 499
 500         return support;
 501 }
 502
 503 static u32 calculate_control(void)
 504 {
 505         u32 control;
 506
 507         control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
 508                 | OSC_PCI_EXPRESS_PME_CONTROL;
 509
 510         if (IS_ENABLED(CONFIG_PCIEASPM))
 511                 control |= OSC_PCI_EXPRESS_LTR_CONTROL;
 512
 513         if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
 514                 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
 515
 516         if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
 517                 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
 518
 519         if (pci_aer_available())
 520                 control |= OSC_PCI_EXPRESS_AER_CONTROL;
 521
 522         /*
 523          * Per the Downstream Port Containment Related Enhancements ECN to
 524          * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
 525          * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
 526          * and EDR.
 527          */
 528         if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
 529                 control |= OSC_PCI_EXPRESS_DPC_CONTROL;
 530
 531         return control;
 532 }
 533
 534 static u32 calculate_cxl_control(void)
 535 {
 536         u32 control = 0;
 537
 538         if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
 539                 control |= OSC_CXL_ERROR_REPORTING_CONTROL;
 540
 541         return control;
 542 }
 543
 544 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
 545 {
 546         struct acpi_device *device = root->device;
 547
 548         if (pcie_ports_disabled) {
 549                 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
 550                 return false;
 551         }
 552
 553         if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
 554                 decode_osc_support(root, "not requesting OS control; OS requires",
 555                                    ACPI_PCIE_REQ_SUPPORT);
 556                 return false;
 557         }
 558
 559         return true;
 560 }
 561
 562 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
 563 {
 564         u32 support, control = 0, requested = 0;
 565         u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;
 566         acpi_status status;
 567         struct acpi_device *device = root->device;
 568         acpi_handle handle = device->handle;
 569
 570         /*
 571          * Apple always return failure on _OSC calls when _OSI("Darwin") has
 572          * been called successfully. We know the feature set supported by the
 573          * platform, so avoid calling _OSC at all
 574          */
 575         if (x86_apple_machine) {
 576                 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
 577                 decode_osc_control(root, "OS assumes control of",
 578                                    root->osc_control_set);
 579                 return;
 580         }
 581
 582         support = calculate_support();
 583
 584         decode_osc_support(root, "OS supports", support);
 585
 586         if (os_control_query_checks(root, support))
 587                 requested = control = calculate_control();
 588
 589         if (is_cxl(root)) {
 590                 cxl_support = calculate_cxl_support();
 591                 decode_cxl_osc_support(root, "OS supports", cxl_support);
 592                 cxl_requested = cxl_control = calculate_cxl_control();
 593         }
 594
 595         status = acpi_pci_osc_control_set(handle, &control, support,
 596                                           &cxl_control, cxl_support);
 597         if (ACPI_SUCCESS(status)) {
 598                 if (control)
 599                         decode_osc_control(root, "OS now controls", control);
 600                 if (cxl_control)
 601                         decode_cxl_osc_control(root, "OS now controls",
 602                                            cxl_control);
 603
 604                 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
 605                         /*
 606                          * We have ASPM control, but the FADT indicates that
 607                          * it's unsupported. Leave existing configuration
 608                          * intact and prevent the OS from touching it.
 609                          */
 610                         dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
 611                         *no_aspm = 1;
 612                 }
 613         } else {
 614                 /*
 615                  * We want to disable ASPM here, but aspm_disabled
 616                  * needs to remain in its state from boot so that we
 617                  * properly handle PCIe 1.1 devices.  So we set this
 618                  * flag here, to defer the action until after the ACPI
 619                  * root scan.
 620                  */
 621                 *no_aspm = 1;
 622
 623                 /* _OSC is optional for PCI host bridges */
 624                 if (status == AE_NOT_FOUND && !is_pcie(root))
 625                         return;
 626
 627                 if (control) {
 628                         decode_osc_control(root, "OS requested", requested);
 629                         decode_osc_control(root, "platform willing to grant", control);
 630                 }
 631                 if (cxl_control) {
 632                         decode_cxl_osc_control(root, "OS requested", cxl_requested);
 633                         decode_cxl_osc_control(root, "platform willing to grant",
 634                                            cxl_control);
 635                 }
 636
 637                 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
 638                          acpi_format_exception(status));
 639         }
 640 }
 641
 642 static int acpi_pci_root_add(struct acpi_device *device,
 643                              const struct acpi_device_id *not_used)
 644 {
 645         unsigned long long segment, bus;
 646         acpi_status status;
 647         int result;
 648         struct acpi_pci_root *root;
 649         acpi_handle handle = device->handle;
 650         int no_aspm = 0;
 651         bool hotadd = system_state == SYSTEM_RUNNING;
 652         const char *acpi_hid;
 653
 654         root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
 655         if (!root)
 656                 return -ENOMEM;
 657
 658         segment = 0;
 659         status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
 660                                        &segment);
 661         if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
 662                 dev_err(&device->dev,  "can't evaluate _SEG\n");
 663                 result = -ENODEV;
 664                 goto end;
 665         }
 666
 667         /* Check _CRS first, then _BBN.  If no _BBN, default to zero. */
 668         root->secondary.flags = IORESOURCE_BUS;
 669         status = try_get_root_bridge_busnr(handle, &root->secondary);
 670         if (ACPI_FAILURE(status)) {
 671                 /*
 672                  * We need both the start and end of the downstream bus range
 673                  * to interpret _CBA (MMCONFIG base address), so it really is
 674                  * supposed to be in _CRS.  If we don't find it there, all we
 675                  * can do is assume [_BBN-0xFF] or [0-0xFF].
 676                  */
 677                 root->secondary.end = 0xFF;
 678                 dev_warn(&device->dev,
 679                          FW_BUG "no secondary bus range in _CRS\n");
 680                 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
 681                                                NULL, &bus);
 682                 if (ACPI_SUCCESS(status))
 683                         root->secondary.start = bus;
 684                 else if (status == AE_NOT_FOUND)
 685                         root->secondary.start = 0;
 686                 else {
 687                         dev_err(&device->dev, "can't evaluate _BBN\n");
 688                         result = -ENODEV;
 689                         goto end;
 690                 }
 691         }
 692
 693         root->device = device;
 694         root->segment = segment & 0xFFFF;
 695         strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
 696         strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
 697         device->driver_data = root;
 698
 699         if (hotadd && dmar_device_add(handle)) {
 700                 result = -ENXIO;
 701                 goto end;
 702         }
 703
 704         pr_info("%s [%s] (domain %04x %pR)\n",
 705                acpi_device_name(device), acpi_device_bid(device),
 706                root->segment, &root->secondary);
 707
 708         root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
 709
 710         acpi_hid = acpi_device_hid(root->device);
 711         if (strcmp(acpi_hid, "PNP0A08") == 0)
 712                 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
 713         else if (strcmp(acpi_hid, "ACPI0016") == 0)
 714                 root->bridge_type = ACPI_BRIDGE_TYPE_CXL;
 715         else
 716                 dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n");
 717
 718         negotiate_os_control(root, &no_aspm);
 719
 720         /*
 721          * TBD: Need PCI interface for enumeration/configuration of roots.
 722          */
 723
 724         /*
 725          * Scan the Root Bridge
 726          * --------------------
 727          * Must do this prior to any attempt to bind the root device, as the
 728          * PCI namespace does not get created until this call is made (and
 729          * thus the root bridge's pci_dev does not exist).
 730          */
 731         root->bus = pci_acpi_scan_root(root);
 732         if (!root->bus) {
 733                 dev_err(&device->dev,
 734                         "Bus %04x:%02x not present in PCI namespace\n",
 735                         root->segment, (unsigned int)root->secondary.start);
 736                 device->driver_data = NULL;
 737                 result = -ENODEV;
 738                 goto remove_dmar;
 739         }
 740
 741         if (no_aspm)
 742                 pcie_no_aspm();
 743
 744         pci_acpi_add_bus_pm_notifier(device);
 745         device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
 746
 747         if (hotadd) {
 748                 pcibios_resource_survey_bus(root->bus);
 749                 pci_assign_unassigned_root_bus_resources(root->bus);
 750                 /*
 751                  * This is only called for the hotadd case. For the boot-time
 752                  * case, we need to wait until after PCI initialization in
 753                  * order to deal with IOAPICs mapped in on a PCI BAR.
 754                  *
 755                  * This is currently x86-specific, because acpi_ioapic_add()
 756                  * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
 757                  * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
 758                  * (see drivers/acpi/Kconfig).
 759                  */
 760                 acpi_ioapic_add(root->device->handle);
 761         }
 762
 763         pci_lock_rescan_remove();
 764         pci_bus_add_devices(root->bus);
 765         pci_unlock_rescan_remove();
 766         return 1;
 767
 768 remove_dmar:
 769         if (hotadd)
 770                 dmar_device_remove(handle);
 771 end:
 772         kfree(root);
 773         return result;
 774 }
 775
 776 static void acpi_pci_root_remove(struct acpi_device *device)
 777 {
 778         struct acpi_pci_root *root = acpi_driver_data(device);
 779
 780         pci_lock_rescan_remove();
 781
 782         pci_stop_root_bus(root->bus);
 783
 784         pci_ioapic_remove(root);
 785         device_set_wakeup_capable(root->bus->bridge, false);
 786         pci_acpi_remove_bus_pm_notifier(device);
 787
 788         pci_remove_root_bus(root->bus);
 789         WARN_ON(acpi_ioapic_remove(root));
 790
 791         dmar_device_remove(device->handle);
 792
 793         pci_unlock_rescan_remove();
 794
 795         kfree(root);
 796 }
 797
 798 /*
 799  * Following code to support acpi_pci_root_create() is copied from
 800  * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
 801  * and ARM64.
 802  */
 803 static void acpi_pci_root_validate_resources(struct device *dev,
 804                                              struct list_head *resources,
 805                                              unsigned long type)
 806 {
 807         LIST_HEAD(list);
 808         struct resource *res1, *res2, *root = NULL;
 809         struct resource_entry *tmp, *entry, *entry2;
 810
 811         BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
 812         root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
 813
 814         list_splice_init(resources, &list);
 815         resource_list_for_each_entry_safe(entry, tmp, &list) {
 816                 bool free = false;
 817                 resource_size_t end;
 818
 819                 res1 = entry->res;
 820                 if (!(res1->flags & type))
 821                         goto next;
 822
 823                 /* Exclude non-addressable range or non-addressable portion */
 824                 end = min(res1->end, root->end);
 825                 if (end <= res1->start) {
 826                         dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
 827                                  res1);
 828                         free = true;
 829                         goto next;
 830                 } else if (res1->end != end) {
 831                         dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
 832                                  res1, (unsigned long long)end + 1,
 833                                  (unsigned long long)res1->end);
 834                         res1->end = end;
 835                 }
 836
 837                 resource_list_for_each_entry(entry2, resources) {
 838                         res2 = entry2->res;
 839                         if (!(res2->flags & type))
 840                                 continue;
 841
 842                         /*
 843                          * I don't like throwing away windows because then
 844                          * our resources no longer match the ACPI _CRS, but
 845                          * the kernel resource tree doesn't allow overlaps.
 846                          */
 847                         if (resource_union(res1, res2, res2)) {
 848                                 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
 849                                          res2, res1);
 850                                 free = true;
 851                                 goto next;
 852                         }
 853                 }
 854
 855 next:
 856                 resource_list_del(entry);
 857                 if (free)
 858                         resource_list_free_entry(entry);
 859                 else
 860                         resource_list_add_tail(entry, resources);
 861         }
 862 }
 863
 864 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
 865                         struct resource_entry *entry)
 866 {
 867 #ifdef PCI_IOBASE
 868         struct resource *res = entry->res;
 869         resource_size_t cpu_addr = res->start;
 870         resource_size_t pci_addr = cpu_addr - entry->offset;
 871         resource_size_t length = resource_size(res);
 872         unsigned long port;
 873
 874         if (pci_register_io_range(fwnode, cpu_addr, length))
 875                 goto err;
 876
 877         port = pci_address_to_pio(cpu_addr);
 878         if (port == (unsigned long)-1)
 879                 goto err;
 880
 881         res->start = port;
 882         res->end = port + length - 1;
 883         entry->offset = port - pci_addr;
 884
 885         if (pci_remap_iospace(res, cpu_addr) < 0)
 886                 goto err;
 887
 888         pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
 889         return;
 890 err:
 891         res->flags |= IORESOURCE_DISABLED;
 892 #endif
 893 }
 894
 895 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
 896 {
 897         int ret;
 898         struct list_head *list = &info->resources;
 899         struct acpi_device *device = info->bridge;
 900         struct resource_entry *entry, *tmp;
 901         unsigned long flags;
 902
 903         flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
 904         ret = acpi_dev_get_resources(device, list,
 905                                      acpi_dev_filter_resource_type_cb,
 906                                      (void *)flags);
 907         if (ret < 0)
 908                 dev_warn(&device->dev,
 909                          "failed to parse _CRS method, error code %d\n", ret);
 910         else if (ret == 0)
 911                 dev_dbg(&device->dev,
 912                         "no IO and memory resources present in _CRS\n");
 913         else {
 914                 resource_list_for_each_entry_safe(entry, tmp, list) {
 915                         if (entry->res->flags & IORESOURCE_IO)
 916                                 acpi_pci_root_remap_iospace(&device->fwnode,
 917                                                 entry);
 918
 919                         if (entry->res->flags & IORESOURCE_DISABLED)
 920                                 resource_list_destroy_entry(entry);
 921                         else
 922                                 entry->res->name = info->name;
 923                 }
 924                 acpi_pci_root_validate_resources(&device->dev, list,
 925                                                  IORESOURCE_MEM);
 926                 acpi_pci_root_validate_resources(&device->dev, list,
 927                                                  IORESOURCE_IO);
 928         }
 929
 930         return ret;
 931 }
 932
 933 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
 934 {
 935         struct resource_entry *entry, *tmp;
 936         struct resource *res, *conflict, *root = NULL;
 937
 938         resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
 939                 res = entry->res;
 940                 if (res->flags & IORESOURCE_MEM)
 941                         root = &iomem_resource;
 942                 else if (res->flags & IORESOURCE_IO)
 943                         root = &ioport_resource;
 944                 else
 945                         continue;
 946
 947                 /*
 948                  * Some legacy x86 host bridge drivers use iomem_resource and
 949                  * ioport_resource as default resource pool, skip it.
 950                  */
 951                 if (res == root)
 952                         continue;
 953
 954                 conflict = insert_resource_conflict(root, res);
 955                 if (conflict) {
 956                         dev_info(&info->bridge->dev,
 957                                  "ignoring host bridge window %pR (conflicts with %s %pR)\n",
 958                                  res, conflict->name, conflict);
 959                         resource_list_destroy_entry(entry);
 960                 }
 961         }
 962 }
 963
 964 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
 965 {
 966         struct resource *res;
 967         struct resource_entry *entry, *tmp;
 968
 969         if (!info)
 970                 return;
 971
 972         resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
 973                 res = entry->res;
 974                 if (res->parent &&
 975                     (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 976                         release_resource(res);
 977                 resource_list_destroy_entry(entry);
 978         }
 979
 980         info->ops->release_info(info);
 981 }
 982
 983 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
 984 {
 985         struct resource *res;
 986         struct resource_entry *entry;
 987
 988         resource_list_for_each_entry(entry, &bridge->windows) {
 989                 res = entry->res;
 990                 if (res->flags & IORESOURCE_IO)
 991                         pci_unmap_iospace(res);
 992                 if (res->parent &&
 993                     (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 994                         release_resource(res);
 995         }
 996         __acpi_pci_root_release_info(bridge->release_data);
 997 }
 998
 999 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
1000                                      struct acpi_pci_root_ops *ops,
1001                                      struct acpi_pci_root_info *info,
1002                                      void *sysdata)
1003 {
1004         int ret, busnum = root->secondary.start;
1005         struct acpi_device *device = root->device;
1006         int node = acpi_get_node(device->handle);
1007         struct pci_bus *bus;
1008         struct pci_host_bridge *host_bridge;
1009         union acpi_object *obj;
1010
1011         info->root = root;
1012         info->bridge = device;
1013         info->ops = ops;
1014         INIT_LIST_HEAD(&info->resources);
1015         snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
1016                  root->segment, busnum);
1017
1018         if (ops->init_info && ops->init_info(info))
1019                 goto out_release_info;
1020         if (ops->prepare_resources)
1021                 ret = ops->prepare_resources(info);
1022         else
1023                 ret = acpi_pci_probe_root_resources(info);
1024         if (ret < 0)
1025                 goto out_release_info;
1026
1027         pci_acpi_root_add_resources(info);
1028         pci_add_resource(&info->resources, &root->secondary);
1029         bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
1030                                   sysdata, &info->resources);
1031         if (!bus)
1032                 goto out_release_info;
1033
1034         host_bridge = to_pci_host_bridge(bus->bridge);
1035         if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
1036                 host_bridge->native_pcie_hotplug = 0;
1037         if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
1038                 host_bridge->native_shpc_hotplug = 0;
1039         if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
1040                 host_bridge->native_aer = 0;
1041         if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
1042                 host_bridge->native_pme = 0;
1043         if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
1044                 host_bridge->native_ltr = 0;
1045         if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
1046                 host_bridge->native_dpc = 0;
1047
1048         /*
1049          * Evaluate the "PCI Boot Configuration" _DSM Function.  If it
1050          * exists and returns 0, we must preserve any PCI resource
1051          * assignments made by firmware for this host bridge.
1052          */
1053         obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
1054                                 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
1055         if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
1056                 host_bridge->preserve_config = 1;
1057         ACPI_FREE(obj);
1058
1059         acpi_dev_power_up_children_with_adr(device);
1060
1061         pci_scan_child_bus(bus);
1062         pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
1063                                     info);
1064         if (node != NUMA_NO_NODE)
1065                 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
1066         return bus;
1067
1068 out_release_info:
1069         __acpi_pci_root_release_info(info);
1070         return NULL;
1071 }
1072
1073 void __init acpi_pci_root_init(void)
1074 {
1075         if (acpi_pci_disabled)
1076                 return;
1077
1078         pci_acpi_crs_quirks();
1079         acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
1080 }