2 * Copyright (C) 2016 Broadcom
3 * Author: Jayachandran C <jchandra@broadcom.com>
4 * Copyright (C) 2016 Semihalf
5 * Author: Tomasz Nowicki <tn@semihalf.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2, as
9 * published by the Free Software Foundation (the "GPL").
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License version 2 (GPLv2) for more details.
16 * You should have received a copy of the GNU General Public License
17 * version 2 (GPLv2) along with this source code.
20 #define pr_fmt(fmt) "ACPI: " fmt
22 #include <linux/kernel.h>
23 #include <linux/pci.h>
24 #include <linux/pci-acpi.h>
25 #include <linux/pci-ecam.h>
27 /* Structure to hold entries from the MCFG table */
29 struct list_head list;
36 #ifdef CONFIG_PCI_QUIRKS
38 char oem_id[ACPI_OEM_ID_SIZE + 1];
39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
42 struct resource bus_range;
43 struct pci_ecam_ops *ops;
44 struct resource cfgres;
47 #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
48 ((end) - (start) + 1), \
50 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
52 static struct mcfg_fixup mcfg_quirks[] = {
53 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
55 #define QCOM_ECAM32(seg) \
56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
66 #define HISI_QUAD_DOM(table_id, seg, ops) \
67 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
68 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
69 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
71 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
72 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
73 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
74 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
75 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
76 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
78 #define THUNDER_PEM_RES(addr, node) \
79 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
80 #define THUNDER_PEM_QUIRK(rev, node) \
81 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
82 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
83 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
84 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
85 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
86 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
87 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
88 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
89 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
91 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
94 THUNDER_PEM_QUIRK(1, 0),
95 THUNDER_PEM_QUIRK(1, 1),
97 #define THUNDER_ECAM_QUIRK(rev, seg) \
98 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
99 &pci_thunder_ecam_ops }
101 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
102 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
103 THUNDER_ECAM_QUIRK(2, 0),
104 THUNDER_ECAM_QUIRK(2, 1),
105 THUNDER_ECAM_QUIRK(2, 2),
106 THUNDER_ECAM_QUIRK(2, 3),
107 THUNDER_ECAM_QUIRK(2, 10),
108 THUNDER_ECAM_QUIRK(2, 11),
109 THUNDER_ECAM_QUIRK(2, 12),
110 THUNDER_ECAM_QUIRK(2, 13),
113 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
114 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
115 static u32 mcfg_oem_revision;
117 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
118 struct resource *bus_range)
120 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
121 !memcmp(f->oem_table_id, mcfg_oem_table_id,
122 ACPI_OEM_TABLE_ID_SIZE) &&
123 f->oem_revision == mcfg_oem_revision &&
124 f->segment == segment &&
125 resource_contains(&f->bus_range, bus_range))
132 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
133 struct resource *cfgres,
134 struct pci_ecam_ops **ecam_ops)
136 #ifdef CONFIG_PCI_QUIRKS
137 u16 segment = root->segment;
138 struct resource *bus_range = &root->secondary;
139 struct mcfg_fixup *f;
142 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
143 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
148 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
149 cfgres, bus_range, *ecam_ops);
156 /* List to save MCFG entries */
157 static LIST_HEAD(pci_mcfg_list);
159 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
160 struct pci_ecam_ops **ecam_ops)
162 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
163 struct resource *bus_res = &root->secondary;
164 u16 seg = root->segment;
165 struct mcfg_entry *e;
168 /* Use address from _CBA if present, otherwise lookup MCFG */
173 * We expect exact match, unless MCFG entry end bus covers more than
174 * specified by caller.
176 list_for_each_entry(e, &pci_mcfg_list, list) {
177 if (e->segment == seg && e->bus_start == bus_res->start &&
178 e->bus_end >= bus_res->end) {
179 root->mcfg_addr = e->addr;
185 memset(&res, 0, sizeof(res));
186 if (root->mcfg_addr) {
187 res.start = root->mcfg_addr + (bus_res->start << 20);
188 res.end = res.start + (resource_size(bus_res) << 20) - 1;
189 res.flags = IORESOURCE_MEM;
193 * Allow quirks to override default ECAM ops and CFG resource
194 * range. This may even fabricate a CFG resource range in case
195 * MCFG does not have it. Invalid CFG start address means MCFG
196 * firmware bug or we need another quirk in array.
198 pci_mcfg_apply_quirks(root, &res, &ops);
207 static __init int pci_mcfg_parse(struct acpi_table_header *header)
209 struct acpi_table_mcfg *mcfg;
210 struct acpi_mcfg_allocation *mptr;
211 struct mcfg_entry *e, *arr;
214 if (header->length < sizeof(struct acpi_table_mcfg))
217 n = (header->length - sizeof(struct acpi_table_mcfg)) /
218 sizeof(struct acpi_mcfg_allocation);
219 mcfg = (struct acpi_table_mcfg *)header;
220 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
222 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
226 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
227 e->segment = mptr->pci_segment;
228 e->addr = mptr->address;
229 e->bus_start = mptr->start_bus_number;
230 e->bus_end = mptr->end_bus_number;
231 list_add(&e->list, &pci_mcfg_list);
234 #ifdef CONFIG_PCI_QUIRKS
235 /* Save MCFG IDs and revision for quirks matching */
236 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
237 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
238 mcfg_oem_revision = header->oem_revision;
241 pr_info("MCFG table detected, %d entries\n", n);
245 /* Interface called by ACPI - parse and save MCFG table */
246 void __init pci_mmcfg_late_init(void)
248 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
250 pr_err("Failed to parse MCFG (%d)\n", err);