1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI support for Intel Lynxpoint LPSS.
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/suspend.h>
25 #include <linux/delay.h>
29 #ifdef CONFIG_X86_INTEL_LPSS
31 #include <asm/cpu_device_id.h>
32 #include <asm/intel-family.h>
33 #include <asm/iosf_mbi.h>
35 #define LPSS_ADDR(desc) ((unsigned long)&desc)
37 #define LPSS_CLK_SIZE 0x04
38 #define LPSS_LTR_SIZE 0x18
40 /* Offsets relative to LPSS_PRIVATE_OFFSET */
41 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
42 #define LPSS_RESETS 0x04
43 #define LPSS_RESETS_RESET_FUNC BIT(0)
44 #define LPSS_RESETS_RESET_APB BIT(1)
45 #define LPSS_GENERAL 0x08
46 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
47 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
48 #define LPSS_SW_LTR 0x10
49 #define LPSS_AUTO_LTR 0x14
50 #define LPSS_LTR_SNOOP_REQ BIT(15)
51 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
52 #define LPSS_LTR_SNOOP_LAT_1US 0x800
53 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
54 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
55 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
56 #define LPSS_LTR_MAX_VAL 0x3FF
57 #define LPSS_TX_INT 0x20
58 #define LPSS_TX_INT_MASK BIT(1)
60 #define LPSS_PRV_REG_COUNT 9
63 #define LPSS_CLK BIT(0)
64 #define LPSS_CLK_GATE BIT(1)
65 #define LPSS_CLK_DIVIDER BIT(2)
66 #define LPSS_LTR BIT(3)
67 #define LPSS_SAVE_CTX BIT(4)
69 * For some devices the DSDT AML code for another device turns off the device
70 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
71 * as ctx register values.
72 * Luckily these devices always use the same ctx register values, so we can
73 * work around this by saving the ctx registers once on activation.
75 #define LPSS_SAVE_CTX_ONCE BIT(5)
76 #define LPSS_NO_D3_DELAY BIT(6)
78 struct lpss_private_data;
80 struct lpss_device_desc {
82 const char *clk_con_id;
83 unsigned int prv_offset;
84 size_t prv_size_override;
85 struct property_entry *properties;
86 void (*setup)(struct lpss_private_data *pdata);
87 bool resume_from_noirq;
90 static const struct lpss_device_desc lpss_dma_desc = {
94 struct lpss_private_data {
95 struct acpi_device *adev;
96 void __iomem *mmio_base;
97 resource_size_t mmio_size;
98 unsigned int fixed_clk_rate;
100 const struct lpss_device_desc *dev_desc;
101 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
104 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
105 static u32 pmc_atom_d3_mask = 0xfe000ffe;
107 /* LPSS run time quirks */
108 static unsigned int lpss_quirks;
111 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
113 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
114 * it can be powered off automatically whenever the last LPSS device goes down.
115 * In case of no power any access to the DMA controller will hang the system.
116 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
117 * well as on ASuS T100TA transformer.
119 * This quirk overrides power state of entire LPSS island to keep DMA powered
120 * on whenever we have at least one other device in use.
122 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
124 /* UART Component Parameter Register */
125 #define LPSS_UART_CPR 0xF4
126 #define LPSS_UART_CPR_AFCE BIT(4)
128 static void lpss_uart_setup(struct lpss_private_data *pdata)
133 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
134 val = readl(pdata->mmio_base + offset);
135 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
137 val = readl(pdata->mmio_base + LPSS_UART_CPR);
138 if (!(val & LPSS_UART_CPR_AFCE)) {
139 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
140 val = readl(pdata->mmio_base + offset);
141 val |= LPSS_GENERAL_UART_RTS_OVRD;
142 writel(val, pdata->mmio_base + offset);
146 static void lpss_deassert_reset(struct lpss_private_data *pdata)
151 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
152 val = readl(pdata->mmio_base + offset);
153 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
154 writel(val, pdata->mmio_base + offset);
158 * BYT PWM used for backlight control by the i915 driver on systems without
159 * the Crystal Cove PMIC.
161 static struct pwm_lookup byt_pwm_lookup[] = {
162 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
163 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
164 "pwm-lpss-platform"),
167 static void byt_pwm_setup(struct lpss_private_data *pdata)
169 struct acpi_device *adev = pdata->adev;
171 /* Only call pwm_add_table for the first PWM controller */
172 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
175 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
178 #define LPSS_I2C_ENABLE 0x6c
180 static void byt_i2c_setup(struct lpss_private_data *pdata)
182 const char *uid_str = acpi_device_uid(pdata->adev);
183 acpi_handle handle = pdata->adev->handle;
184 unsigned long long shared_host = 0;
188 /* Expected to always be true, but better safe then sorry */
189 if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) {
190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
192 if (ACPI_SUCCESS(status) && shared_host)
193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
196 lpss_deassert_reset(pdata);
198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
199 pdata->fixed_clk_rate = 133000000;
201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
204 /* BSW PWM used for backlight control by the i915 driver */
205 static struct pwm_lookup bsw_pwm_lookup[] = {
206 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
207 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
208 "pwm-lpss-platform"),
211 static void bsw_pwm_setup(struct lpss_private_data *pdata)
213 struct acpi_device *adev = pdata->adev;
215 /* Only call pwm_add_table for the first PWM controller */
216 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
219 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
222 static const struct lpss_device_desc lpt_dev_desc = {
223 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
228 static const struct lpss_device_desc lpt_i2c_dev_desc = {
229 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
233 static struct property_entry uart_properties[] = {
234 PROPERTY_ENTRY_U32("reg-io-width", 4),
235 PROPERTY_ENTRY_U32("reg-shift", 2),
236 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
240 static const struct lpss_device_desc lpt_uart_dev_desc = {
241 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
243 .clk_con_id = "baudclk",
245 .setup = lpss_uart_setup,
246 .properties = uart_properties,
249 static const struct lpss_device_desc lpt_sdio_dev_desc = {
251 .prv_offset = 0x1000,
252 .prv_size_override = 0x1018,
255 static const struct lpss_device_desc byt_pwm_dev_desc = {
256 .flags = LPSS_SAVE_CTX,
258 .setup = byt_pwm_setup,
261 static const struct lpss_device_desc bsw_pwm_dev_desc = {
262 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
264 .setup = bsw_pwm_setup,
265 .resume_from_noirq = true,
268 static const struct lpss_device_desc byt_uart_dev_desc = {
269 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
270 .clk_con_id = "baudclk",
272 .setup = lpss_uart_setup,
273 .properties = uart_properties,
276 static const struct lpss_device_desc bsw_uart_dev_desc = {
277 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
279 .clk_con_id = "baudclk",
281 .setup = lpss_uart_setup,
282 .properties = uart_properties,
285 static const struct lpss_device_desc byt_spi_dev_desc = {
286 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
290 static const struct lpss_device_desc byt_sdio_dev_desc = {
294 static const struct lpss_device_desc byt_i2c_dev_desc = {
295 .flags = LPSS_CLK | LPSS_SAVE_CTX,
297 .setup = byt_i2c_setup,
298 .resume_from_noirq = true,
301 static const struct lpss_device_desc bsw_i2c_dev_desc = {
302 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
304 .setup = byt_i2c_setup,
305 .resume_from_noirq = true,
308 static const struct lpss_device_desc bsw_spi_dev_desc = {
309 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
312 .setup = lpss_deassert_reset,
315 static const struct x86_cpu_id lpss_cpu_ids[] = {
316 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
317 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
323 #define LPSS_ADDR(desc) (0UL)
325 #endif /* CONFIG_X86_INTEL_LPSS */
327 static const struct acpi_device_id acpi_lpss_device_ids[] = {
328 /* Generic LPSS devices */
329 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
331 /* Lynxpoint LPSS devices */
332 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
333 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
334 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
335 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
336 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
337 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
338 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
341 /* BayTrail LPSS devices */
342 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
343 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
344 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
345 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
346 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
350 /* Braswell LPSS devices */
351 { "80862286", LPSS_ADDR(lpss_dma_desc) },
352 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
353 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
354 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
355 { "808622C0", LPSS_ADDR(lpss_dma_desc) },
356 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
358 /* Broadwell LPSS devices */
359 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
360 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
361 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
362 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
363 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
364 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
365 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
368 /* Wildcat Point LPSS devices */
369 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
374 #ifdef CONFIG_X86_INTEL_LPSS
376 static int is_memory(struct acpi_resource *res, void *not_used)
380 return !acpi_dev_resource_memory(res, &r);
383 /* LPSS main clock device. */
384 static struct platform_device *lpss_clk_dev;
386 static inline void lpt_register_clock_device(void)
388 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
393 static int register_device_clock(struct acpi_device *adev,
394 struct lpss_private_data *pdata)
396 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
397 const char *devname = dev_name(&adev->dev);
399 struct lpss_clk_data *clk_data;
400 const char *parent, *clk_name;
401 void __iomem *prv_base;
404 lpt_register_clock_device();
406 if (IS_ERR(lpss_clk_dev))
407 return PTR_ERR(lpss_clk_dev);
409 clk_data = platform_get_drvdata(lpss_clk_dev);
414 if (!pdata->mmio_base
415 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
418 parent = clk_data->name;
419 prv_base = pdata->mmio_base + dev_desc->prv_offset;
421 if (pdata->fixed_clk_rate) {
422 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
423 pdata->fixed_clk_rate);
427 if (dev_desc->flags & LPSS_CLK_GATE) {
428 clk = clk_register_gate(NULL, devname, parent, 0,
429 prv_base, 0, 0, NULL);
433 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
434 /* Prevent division by zero */
435 if (!readl(prv_base))
436 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
438 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
441 clk = clk_register_fractional_divider(NULL, clk_name, parent,
442 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
443 prv_base, 1, 15, 16, 15, 0, NULL);
446 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
451 clk = clk_register_gate(NULL, clk_name, parent,
452 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
453 prv_base, 31, 0, NULL);
462 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
466 struct lpss_device_links {
467 const char *supplier_hid;
468 const char *supplier_uid;
469 const char *consumer_hid;
470 const char *consumer_uid;
472 const struct dmi_system_id *dep_missing_ids;
475 /* Please keep this list sorted alphabetically by vendor and model */
476 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
479 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
480 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
487 * The _DEP method is used to identify dependencies but instead of creating
488 * device links for every handle in _DEP, only links in the following list are
489 * created. That is necessary because, in the general case, _DEP can refer to
490 * devices that might not have drivers, or that are on different buses, or where
491 * the supplier is not enumerated until after the consumer is probed.
493 static const struct lpss_device_links lpss_device_links[] = {
494 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
495 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
496 /* CHT iGPU depends on PMIC I2C controller */
497 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
498 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
499 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
500 i2c1_dep_missing_dmi_ids},
501 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
502 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
503 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
504 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
507 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
508 const struct lpss_device_links *link)
510 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
513 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
514 const struct lpss_device_links *link)
516 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
524 static int match_hid_uid(struct device *dev, const void *data)
526 struct acpi_device *adev = ACPI_COMPANION(dev);
527 const struct hid_uid *id = data;
532 return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
535 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
539 struct hid_uid data = {
544 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
548 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
551 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
553 struct acpi_handle_list dep_devices;
557 if (!acpi_has_method(adev->handle, "_DEP"))
560 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
562 if (ACPI_FAILURE(status)) {
563 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
567 for (i = 0; i < dep_devices.count; i++) {
568 if (dep_devices.handles[i] == handle)
575 static void acpi_lpss_link_consumer(struct device *dev1,
576 const struct lpss_device_links *link)
580 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
584 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
585 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
586 device_link_add(dev2, dev1, link->flags);
591 static void acpi_lpss_link_supplier(struct device *dev1,
592 const struct lpss_device_links *link)
596 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
600 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
601 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
602 device_link_add(dev1, dev2, link->flags);
607 static void acpi_lpss_create_device_links(struct acpi_device *adev,
608 struct platform_device *pdev)
612 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
613 const struct lpss_device_links *link = &lpss_device_links[i];
615 if (acpi_lpss_is_supplier(adev, link))
616 acpi_lpss_link_consumer(&pdev->dev, link);
618 if (acpi_lpss_is_consumer(adev, link))
619 acpi_lpss_link_supplier(&pdev->dev, link);
623 static int acpi_lpss_create_device(struct acpi_device *adev,
624 const struct acpi_device_id *id)
626 const struct lpss_device_desc *dev_desc;
627 struct lpss_private_data *pdata;
628 struct resource_entry *rentry;
629 struct list_head resource_list;
630 struct platform_device *pdev;
633 dev_desc = (const struct lpss_device_desc *)id->driver_data;
635 pdev = acpi_create_platform_device(adev, NULL);
636 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
638 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
642 INIT_LIST_HEAD(&resource_list);
643 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
647 list_for_each_entry(rentry, &resource_list, node)
648 if (resource_type(rentry->res) == IORESOURCE_MEM) {
649 if (dev_desc->prv_size_override)
650 pdata->mmio_size = dev_desc->prv_size_override;
652 pdata->mmio_size = resource_size(rentry->res);
653 pdata->mmio_base = ioremap(rentry->res->start,
658 acpi_dev_free_resource_list(&resource_list);
660 if (!pdata->mmio_base) {
661 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
662 adev->pnp.type.platform_id = 0;
663 /* Skip the device, but continue the namespace scan. */
669 pdata->dev_desc = dev_desc;
672 dev_desc->setup(pdata);
674 if (dev_desc->flags & LPSS_CLK) {
675 ret = register_device_clock(adev, pdata);
677 /* Skip the device, but continue the namespace scan. */
684 * This works around a known issue in ACPI tables where LPSS devices
685 * have _PS0 and _PS3 without _PSC (and no power resources), so
686 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
688 acpi_device_fix_up_power(adev);
690 adev->driver_data = pdata;
691 pdev = acpi_create_platform_device(adev, dev_desc->properties);
692 if (!IS_ERR_OR_NULL(pdev)) {
693 acpi_lpss_create_device_links(adev, pdev);
698 adev->driver_data = NULL;
705 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
707 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
710 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
713 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
716 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
718 struct acpi_device *adev;
719 struct lpss_private_data *pdata;
723 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
727 spin_lock_irqsave(&dev->power.lock, flags);
728 if (pm_runtime_suspended(dev)) {
732 pdata = acpi_driver_data(adev);
733 if (WARN_ON(!pdata || !pdata->mmio_base)) {
737 *val = __lpss_reg_read(pdata, reg);
740 spin_unlock_irqrestore(&dev->power.lock, flags);
744 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
751 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
752 ret = lpss_reg_read(dev, reg, <r_value);
756 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
759 static ssize_t lpss_ltr_mode_show(struct device *dev,
760 struct device_attribute *attr, char *buf)
766 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
770 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
771 return sprintf(buf, "%s\n", outstr);
774 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
775 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
776 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
778 static struct attribute *lpss_attrs[] = {
779 &dev_attr_auto_ltr.attr,
780 &dev_attr_sw_ltr.attr,
781 &dev_attr_ltr_mode.attr,
785 static const struct attribute_group lpss_attr_group = {
790 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
792 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
793 u32 ltr_mode, ltr_val;
795 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
797 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
798 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
799 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
803 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
804 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
805 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
806 val = LPSS_LTR_MAX_VAL;
807 } else if (val > LPSS_LTR_MAX_VAL) {
808 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
809 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
811 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
814 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
815 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
816 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
817 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
823 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
825 * @pdata: pointer to the private data of the LPSS device
827 * Most LPSS devices have private registers which may loose their context when
828 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
831 static void acpi_lpss_save_ctx(struct device *dev,
832 struct lpss_private_data *pdata)
836 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
837 unsigned long offset = i * sizeof(u32);
839 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
840 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
841 pdata->prv_reg_ctx[i], offset);
846 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
848 * @pdata: pointer to the private data of the LPSS device
850 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
852 static void acpi_lpss_restore_ctx(struct device *dev,
853 struct lpss_private_data *pdata)
857 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
858 unsigned long offset = i * sizeof(u32);
860 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
861 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
862 pdata->prv_reg_ctx[i], offset);
866 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
869 * The following delay is needed or the subsequent write operations may
870 * fail. The LPSS devices are actually PCI devices and the PCI spec
871 * expects 10ms delay before the device can be accessed after D3 to D0
872 * transition. However some platforms like BSW does not need this delay.
874 unsigned int delay = 10; /* default 10ms delay */
876 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
882 static int acpi_lpss_activate(struct device *dev)
884 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
887 ret = acpi_dev_resume(dev);
891 acpi_lpss_d3_to_d0_delay(pdata);
894 * This is called only on ->probe() stage where a device is either in
895 * known state defined by BIOS or most likely powered off. Due to this
896 * we have to deassert reset line to be sure that ->probe() will
897 * recognize the device.
899 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
900 lpss_deassert_reset(pdata);
903 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
904 acpi_lpss_save_ctx(dev, pdata);
910 static void acpi_lpss_dismiss(struct device *dev)
912 acpi_dev_suspend(dev, false);
915 /* IOSF SB for LPSS island */
916 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
917 #define LPSS_IOSF_UNIT_LPIO1 0xAB
918 #define LPSS_IOSF_UNIT_LPIO2 0xAC
920 #define LPSS_IOSF_PMCSR 0x84
921 #define LPSS_PMCSR_D0 0
922 #define LPSS_PMCSR_D3hot 3
923 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
925 #define LPSS_IOSF_GPIODEF0 0x154
926 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
927 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
928 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
929 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
931 static DEFINE_MUTEX(lpss_iosf_mutex);
932 static bool lpss_iosf_d3_entered = true;
934 static void lpss_iosf_enter_d3_state(void)
937 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
938 u32 value2 = LPSS_PMCSR_D3hot;
939 u32 mask2 = LPSS_PMCSR_Dx_MASK;
941 * PMC provides an information about actual status of the LPSS devices.
942 * Here we read the values related to LPSS power island, i.e. LPSS
943 * devices, excluding both LPSS DMA controllers, along with SCC domain.
945 u32 func_dis, d3_sts_0, pmc_status;
948 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
952 mutex_lock(&lpss_iosf_mutex);
954 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
959 * Get the status of entire LPSS power island per device basis.
960 * Shutdown both LPSS DMA controllers if and only if all other devices
961 * are already in D3hot.
963 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
967 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
968 LPSS_IOSF_PMCSR, value2, mask2);
970 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
971 LPSS_IOSF_PMCSR, value2, mask2);
973 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
974 LPSS_IOSF_GPIODEF0, value1, mask1);
976 lpss_iosf_d3_entered = true;
979 mutex_unlock(&lpss_iosf_mutex);
982 static void lpss_iosf_exit_d3_state(void)
984 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
985 LPSS_GPIODEF0_DMA_LLP;
986 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
987 u32 value2 = LPSS_PMCSR_D0;
988 u32 mask2 = LPSS_PMCSR_Dx_MASK;
990 mutex_lock(&lpss_iosf_mutex);
992 if (!lpss_iosf_d3_entered)
995 lpss_iosf_d3_entered = false;
997 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
998 LPSS_IOSF_GPIODEF0, value1, mask1);
1000 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1001 LPSS_IOSF_PMCSR, value2, mask2);
1003 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1004 LPSS_IOSF_PMCSR, value2, mask2);
1007 mutex_unlock(&lpss_iosf_mutex);
1010 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1012 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1015 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1016 acpi_lpss_save_ctx(dev, pdata);
1018 ret = acpi_dev_suspend(dev, wakeup);
1021 * This call must be last in the sequence, otherwise PMC will return
1022 * wrong status for devices being about to be powered off. See
1023 * lpss_iosf_enter_d3_state() for further information.
1025 if (acpi_target_system_state() == ACPI_STATE_S0 &&
1026 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1027 lpss_iosf_enter_d3_state();
1032 static int acpi_lpss_resume(struct device *dev)
1034 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1038 * This call is kept first to be in symmetry with
1039 * acpi_lpss_runtime_suspend() one.
1041 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1042 lpss_iosf_exit_d3_state();
1044 ret = acpi_dev_resume(dev);
1048 acpi_lpss_d3_to_d0_delay(pdata);
1050 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1051 acpi_lpss_restore_ctx(dev, pdata);
1056 #ifdef CONFIG_PM_SLEEP
1057 static int acpi_lpss_do_suspend_late(struct device *dev)
1061 if (dev_pm_skip_suspend(dev))
1064 ret = pm_generic_suspend_late(dev);
1065 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1068 static int acpi_lpss_suspend_late(struct device *dev)
1070 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1072 if (pdata->dev_desc->resume_from_noirq)
1075 return acpi_lpss_do_suspend_late(dev);
1078 static int acpi_lpss_suspend_noirq(struct device *dev)
1080 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1083 if (pdata->dev_desc->resume_from_noirq) {
1085 * The driver's ->suspend_late callback will be invoked by
1086 * acpi_lpss_do_suspend_late(), with the assumption that the
1087 * driver really wanted to run that code in ->suspend_noirq, but
1088 * it could not run after acpi_dev_suspend() and the driver
1089 * expected the latter to be called in the "late" phase.
1091 ret = acpi_lpss_do_suspend_late(dev);
1096 return acpi_subsys_suspend_noirq(dev);
1099 static int acpi_lpss_do_resume_early(struct device *dev)
1101 int ret = acpi_lpss_resume(dev);
1103 return ret ? ret : pm_generic_resume_early(dev);
1106 static int acpi_lpss_resume_early(struct device *dev)
1108 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1110 if (pdata->dev_desc->resume_from_noirq)
1113 if (dev_pm_skip_resume(dev))
1116 return acpi_lpss_do_resume_early(dev);
1119 static int acpi_lpss_resume_noirq(struct device *dev)
1121 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1124 /* Follow acpi_subsys_resume_noirq(). */
1125 if (dev_pm_skip_resume(dev))
1128 ret = pm_generic_resume_noirq(dev);
1132 if (!pdata->dev_desc->resume_from_noirq)
1136 * The driver's ->resume_early callback will be invoked by
1137 * acpi_lpss_do_resume_early(), with the assumption that the driver
1138 * really wanted to run that code in ->resume_noirq, but it could not
1139 * run before acpi_dev_resume() and the driver expected the latter to be
1140 * called in the "early" phase.
1142 return acpi_lpss_do_resume_early(dev);
1145 static int acpi_lpss_do_restore_early(struct device *dev)
1147 int ret = acpi_lpss_resume(dev);
1149 return ret ? ret : pm_generic_restore_early(dev);
1152 static int acpi_lpss_restore_early(struct device *dev)
1154 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1156 if (pdata->dev_desc->resume_from_noirq)
1159 return acpi_lpss_do_restore_early(dev);
1162 static int acpi_lpss_restore_noirq(struct device *dev)
1164 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1167 ret = pm_generic_restore_noirq(dev);
1171 if (!pdata->dev_desc->resume_from_noirq)
1174 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1175 return acpi_lpss_do_restore_early(dev);
1178 static int acpi_lpss_do_poweroff_late(struct device *dev)
1180 int ret = pm_generic_poweroff_late(dev);
1182 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1185 static int acpi_lpss_poweroff_late(struct device *dev)
1187 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1189 if (dev_pm_skip_suspend(dev))
1192 if (pdata->dev_desc->resume_from_noirq)
1195 return acpi_lpss_do_poweroff_late(dev);
1198 static int acpi_lpss_poweroff_noirq(struct device *dev)
1200 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1202 if (dev_pm_skip_suspend(dev))
1205 if (pdata->dev_desc->resume_from_noirq) {
1206 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1207 int ret = acpi_lpss_do_poweroff_late(dev);
1213 return pm_generic_poweroff_noirq(dev);
1215 #endif /* CONFIG_PM_SLEEP */
1217 static int acpi_lpss_runtime_suspend(struct device *dev)
1219 int ret = pm_generic_runtime_suspend(dev);
1221 return ret ? ret : acpi_lpss_suspend(dev, true);
1224 static int acpi_lpss_runtime_resume(struct device *dev)
1226 int ret = acpi_lpss_resume(dev);
1228 return ret ? ret : pm_generic_runtime_resume(dev);
1230 #endif /* CONFIG_PM */
1232 static struct dev_pm_domain acpi_lpss_pm_domain = {
1234 .activate = acpi_lpss_activate,
1235 .dismiss = acpi_lpss_dismiss,
1239 #ifdef CONFIG_PM_SLEEP
1240 .prepare = acpi_subsys_prepare,
1241 .complete = acpi_subsys_complete,
1242 .suspend = acpi_subsys_suspend,
1243 .suspend_late = acpi_lpss_suspend_late,
1244 .suspend_noirq = acpi_lpss_suspend_noirq,
1245 .resume_noirq = acpi_lpss_resume_noirq,
1246 .resume_early = acpi_lpss_resume_early,
1247 .freeze = acpi_subsys_freeze,
1248 .poweroff = acpi_subsys_poweroff,
1249 .poweroff_late = acpi_lpss_poweroff_late,
1250 .poweroff_noirq = acpi_lpss_poweroff_noirq,
1251 .restore_noirq = acpi_lpss_restore_noirq,
1252 .restore_early = acpi_lpss_restore_early,
1254 .runtime_suspend = acpi_lpss_runtime_suspend,
1255 .runtime_resume = acpi_lpss_runtime_resume,
1260 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1261 unsigned long action, void *data)
1263 struct platform_device *pdev = to_platform_device(data);
1264 struct lpss_private_data *pdata;
1265 struct acpi_device *adev;
1266 const struct acpi_device_id *id;
1268 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1269 if (!id || !id->driver_data)
1272 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1275 pdata = acpi_driver_data(adev);
1279 if (pdata->mmio_base &&
1280 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1281 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1286 case BUS_NOTIFY_BIND_DRIVER:
1287 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1289 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1290 case BUS_NOTIFY_UNBOUND_DRIVER:
1291 dev_pm_domain_set(&pdev->dev, NULL);
1293 case BUS_NOTIFY_ADD_DEVICE:
1294 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1295 if (pdata->dev_desc->flags & LPSS_LTR)
1296 return sysfs_create_group(&pdev->dev.kobj,
1299 case BUS_NOTIFY_DEL_DEVICE:
1300 if (pdata->dev_desc->flags & LPSS_LTR)
1301 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1302 dev_pm_domain_set(&pdev->dev, NULL);
1311 static struct notifier_block acpi_lpss_nb = {
1312 .notifier_call = acpi_lpss_platform_notify,
1315 static void acpi_lpss_bind(struct device *dev)
1317 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1319 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1322 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1323 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1325 dev_err(dev, "MMIO size insufficient to access LTR\n");
1328 static void acpi_lpss_unbind(struct device *dev)
1330 dev->power.set_latency_tolerance = NULL;
1333 static struct acpi_scan_handler lpss_handler = {
1334 .ids = acpi_lpss_device_ids,
1335 .attach = acpi_lpss_create_device,
1336 .bind = acpi_lpss_bind,
1337 .unbind = acpi_lpss_unbind,
1340 void __init acpi_lpss_init(void)
1342 const struct x86_cpu_id *id;
1345 ret = lpss_atom_clk_init();
1349 id = x86_match_cpu(lpss_cpu_ids);
1351 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1353 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1354 acpi_scan_add_handler(&lpss_handler);
1359 static struct acpi_scan_handler lpss_handler = {
1360 .ids = acpi_lpss_device_ids,
1363 void __init acpi_lpss_init(void)
1365 acpi_scan_add_handler(&lpss_handler);
1368 #endif /* CONFIG_X86_INTEL_LPSS */