1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI support for Intel Lynxpoint LPSS.
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/pxa2xx_ssp.h>
25 #include <linux/suspend.h>
26 #include <linux/delay.h>
30 #ifdef CONFIG_X86_INTEL_LPSS
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
61 #define LPSS_PRV_REG_COUNT 9
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
70 * For some devices the DSDT AML code for another device turns off the device
71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
72 * as ctx register values.
73 * Luckily these devices always use the same ctx register values, so we can
74 * work around this by saving the ctx registers once on activation.
76 #define LPSS_SAVE_CTX_ONCE BIT(5)
77 #define LPSS_NO_D3_DELAY BIT(6)
79 struct lpss_private_data;
81 struct lpss_device_desc {
83 const char *clk_con_id;
84 unsigned int prv_offset;
85 size_t prv_size_override;
86 const struct property_entry *properties;
87 void (*setup)(struct lpss_private_data *pdata);
88 bool resume_from_noirq;
91 static const struct lpss_device_desc lpss_dma_desc = {
95 struct lpss_private_data {
96 struct acpi_device *adev;
97 void __iomem *mmio_base;
98 resource_size_t mmio_size;
99 unsigned int fixed_clk_rate;
101 const struct lpss_device_desc *dev_desc;
102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
108 /* LPSS run time quirks */
109 static unsigned int lpss_quirks;
112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
115 * it can be powered off automatically whenever the last LPSS device goes down.
116 * In case of no power any access to the DMA controller will hang the system.
117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
118 * well as on ASuS T100TA transformer.
120 * This quirk overrides power state of entire LPSS island to keep DMA powered
121 * on whenever we have at least one other device in use.
123 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
125 /* UART Component Parameter Register */
126 #define LPSS_UART_CPR 0xF4
127 #define LPSS_UART_CPR_AFCE BIT(4)
129 static void lpss_uart_setup(struct lpss_private_data *pdata)
134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
135 val = readl(pdata->mmio_base + offset);
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
138 val = readl(pdata->mmio_base + LPSS_UART_CPR);
139 if (!(val & LPSS_UART_CPR_AFCE)) {
140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
141 val = readl(pdata->mmio_base + offset);
142 val |= LPSS_GENERAL_UART_RTS_OVRD;
143 writel(val, pdata->mmio_base + offset);
147 static void lpss_deassert_reset(struct lpss_private_data *pdata)
152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
153 val = readl(pdata->mmio_base + offset);
154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
155 writel(val, pdata->mmio_base + offset);
159 * BYT PWM used for backlight control by the i915 driver on systems without
160 * the Crystal Cove PMIC.
162 static struct pwm_lookup byt_pwm_lookup[] = {
163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
165 "pwm-lpss-platform"),
168 static void byt_pwm_setup(struct lpss_private_data *pdata)
172 /* Only call pwm_add_table for the first PWM controller */
173 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
179 #define LPSS_I2C_ENABLE 0x6c
181 static void byt_i2c_setup(struct lpss_private_data *pdata)
183 acpi_handle handle = pdata->adev->handle;
184 unsigned long long shared_host = 0;
188 /* Expected to always be successfull, but better safe then sorry */
189 if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
192 if (ACPI_SUCCESS(status) && shared_host)
193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
196 lpss_deassert_reset(pdata);
198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
199 pdata->fixed_clk_rate = 133000000;
201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
205 * BSW PWM1 is used for backlight control by the i915 driver
206 * BSW PWM2 is used for backlight control for fixed (etched into the glass)
207 * touch controls on some models. These touch-controls have specialized
208 * drivers which know they need the "pwm_soc_lpss_2" con-id.
210 static struct pwm_lookup bsw_pwm_lookup[] = {
211 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
212 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
213 "pwm-lpss-platform"),
214 PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL,
215 "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL,
216 "pwm-lpss-platform"),
219 static void bsw_pwm_setup(struct lpss_private_data *pdata)
223 /* Only call pwm_add_table for the first PWM controller */
224 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
227 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
230 static const struct property_entry lpt_spi_properties[] = {
231 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
235 static const struct lpss_device_desc lpt_spi_dev_desc = {
236 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
239 .properties = lpt_spi_properties,
242 static const struct lpss_device_desc lpt_i2c_dev_desc = {
243 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
247 static struct property_entry uart_properties[] = {
248 PROPERTY_ENTRY_U32("reg-io-width", 4),
249 PROPERTY_ENTRY_U32("reg-shift", 2),
250 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
254 static const struct lpss_device_desc lpt_uart_dev_desc = {
255 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
257 .clk_con_id = "baudclk",
259 .setup = lpss_uart_setup,
260 .properties = uart_properties,
263 static const struct lpss_device_desc lpt_sdio_dev_desc = {
265 .prv_offset = 0x1000,
266 .prv_size_override = 0x1018,
269 static const struct lpss_device_desc byt_pwm_dev_desc = {
270 .flags = LPSS_SAVE_CTX,
272 .setup = byt_pwm_setup,
275 static const struct lpss_device_desc bsw_pwm_dev_desc = {
276 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
278 .setup = bsw_pwm_setup,
279 .resume_from_noirq = true,
282 static const struct lpss_device_desc bsw_pwm2_dev_desc = {
283 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
285 .resume_from_noirq = true,
288 static const struct lpss_device_desc byt_uart_dev_desc = {
289 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
290 .clk_con_id = "baudclk",
292 .setup = lpss_uart_setup,
293 .properties = uart_properties,
296 static const struct lpss_device_desc bsw_uart_dev_desc = {
297 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
299 .clk_con_id = "baudclk",
301 .setup = lpss_uart_setup,
302 .properties = uart_properties,
305 static const struct property_entry byt_spi_properties[] = {
306 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
310 static const struct lpss_device_desc byt_spi_dev_desc = {
311 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
313 .properties = byt_spi_properties,
316 static const struct lpss_device_desc byt_sdio_dev_desc = {
320 static const struct lpss_device_desc byt_i2c_dev_desc = {
321 .flags = LPSS_CLK | LPSS_SAVE_CTX,
323 .setup = byt_i2c_setup,
324 .resume_from_noirq = true,
327 static const struct lpss_device_desc bsw_i2c_dev_desc = {
328 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
330 .setup = byt_i2c_setup,
331 .resume_from_noirq = true,
334 static const struct property_entry bsw_spi_properties[] = {
335 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
339 static const struct lpss_device_desc bsw_spi_dev_desc = {
340 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
343 .setup = lpss_deassert_reset,
344 .properties = bsw_spi_properties,
347 static const struct x86_cpu_id lpss_cpu_ids[] = {
348 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
349 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
355 #define LPSS_ADDR(desc) (0UL)
357 #endif /* CONFIG_X86_INTEL_LPSS */
359 static const struct acpi_device_id acpi_lpss_device_ids[] = {
360 /* Generic LPSS devices */
361 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
363 /* Lynxpoint LPSS devices */
364 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
365 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
366 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
367 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
368 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
369 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
370 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
373 /* BayTrail LPSS devices */
374 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
375 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
376 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
377 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
378 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
382 /* Braswell LPSS devices */
383 { "80862286", LPSS_ADDR(lpss_dma_desc) },
384 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
385 { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) },
386 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
387 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
388 { "808622C0", LPSS_ADDR(lpss_dma_desc) },
389 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
391 /* Broadwell LPSS devices */
392 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
393 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
394 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
395 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
396 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
397 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
398 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
401 /* Wildcat Point LPSS devices */
402 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
407 #ifdef CONFIG_X86_INTEL_LPSS
409 /* LPSS main clock device. */
410 static struct platform_device *lpss_clk_dev;
412 static inline void lpt_register_clock_device(void)
414 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
419 static int register_device_clock(struct acpi_device *adev,
420 struct lpss_private_data *pdata)
422 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
423 const char *devname = dev_name(&adev->dev);
425 struct lpss_clk_data *clk_data;
426 const char *parent, *clk_name;
427 void __iomem *prv_base;
430 lpt_register_clock_device();
432 if (IS_ERR(lpss_clk_dev))
433 return PTR_ERR(lpss_clk_dev);
435 clk_data = platform_get_drvdata(lpss_clk_dev);
440 if (!pdata->mmio_base
441 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
444 parent = clk_data->name;
445 prv_base = pdata->mmio_base + dev_desc->prv_offset;
447 if (pdata->fixed_clk_rate) {
448 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
449 pdata->fixed_clk_rate);
453 if (dev_desc->flags & LPSS_CLK_GATE) {
454 clk = clk_register_gate(NULL, devname, parent, 0,
455 prv_base, 0, 0, NULL);
459 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
460 /* Prevent division by zero */
461 if (!readl(prv_base))
462 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
464 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
467 clk = clk_register_fractional_divider(NULL, clk_name, parent,
468 0, prv_base, 1, 15, 16, 15,
469 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
473 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
478 clk = clk_register_gate(NULL, clk_name, parent,
479 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
480 prv_base, 31, 0, NULL);
489 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
493 struct lpss_device_links {
494 const char *supplier_hid;
495 const char *supplier_uid;
496 const char *consumer_hid;
497 const char *consumer_uid;
499 const struct dmi_system_id *dep_missing_ids;
502 /* Please keep this list sorted alphabetically by vendor and model */
503 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
506 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
507 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
514 * The _DEP method is used to identify dependencies but instead of creating
515 * device links for every handle in _DEP, only links in the following list are
516 * created. That is necessary because, in the general case, _DEP can refer to
517 * devices that might not have drivers, or that are on different buses, or where
518 * the supplier is not enumerated until after the consumer is probed.
520 static const struct lpss_device_links lpss_device_links[] = {
521 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
522 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
523 /* CHT iGPU depends on PMIC I2C controller */
524 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
525 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
526 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
527 i2c1_dep_missing_dmi_ids},
528 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
529 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
530 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
531 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
534 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
535 const struct lpss_device_links *link)
537 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
540 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
541 const struct lpss_device_links *link)
543 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
551 static int match_hid_uid(struct device *dev, const void *data)
553 struct acpi_device *adev = ACPI_COMPANION(dev);
554 const struct hid_uid *id = data;
559 return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
562 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
566 struct hid_uid data = {
571 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
575 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
578 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
580 struct acpi_handle_list dep_devices;
584 if (!acpi_has_method(adev->handle, "_DEP"))
587 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
589 if (ACPI_FAILURE(status)) {
590 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
594 for (i = 0; i < dep_devices.count; i++) {
595 if (dep_devices.handles[i] == handle)
602 static void acpi_lpss_link_consumer(struct device *dev1,
603 const struct lpss_device_links *link)
607 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
611 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
612 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
613 device_link_add(dev2, dev1, link->flags);
618 static void acpi_lpss_link_supplier(struct device *dev1,
619 const struct lpss_device_links *link)
623 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
627 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
628 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
629 device_link_add(dev1, dev2, link->flags);
634 static void acpi_lpss_create_device_links(struct acpi_device *adev,
635 struct platform_device *pdev)
639 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
640 const struct lpss_device_links *link = &lpss_device_links[i];
642 if (acpi_lpss_is_supplier(adev, link))
643 acpi_lpss_link_consumer(&pdev->dev, link);
645 if (acpi_lpss_is_consumer(adev, link))
646 acpi_lpss_link_supplier(&pdev->dev, link);
650 static int acpi_lpss_create_device(struct acpi_device *adev,
651 const struct acpi_device_id *id)
653 const struct lpss_device_desc *dev_desc;
654 struct lpss_private_data *pdata;
655 struct resource_entry *rentry;
656 struct list_head resource_list;
657 struct platform_device *pdev;
660 dev_desc = (const struct lpss_device_desc *)id->driver_data;
662 pdev = acpi_create_platform_device(adev, NULL);
663 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
665 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
669 INIT_LIST_HEAD(&resource_list);
670 ret = acpi_dev_get_memory_resources(adev, &resource_list);
674 rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
676 if (dev_desc->prv_size_override)
677 pdata->mmio_size = dev_desc->prv_size_override;
679 pdata->mmio_size = resource_size(rentry->res);
680 pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
683 acpi_dev_free_resource_list(&resource_list);
685 if (!pdata->mmio_base) {
686 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
687 adev->pnp.type.platform_id = 0;
692 pdata->dev_desc = dev_desc;
695 dev_desc->setup(pdata);
697 if (dev_desc->flags & LPSS_CLK) {
698 ret = register_device_clock(adev, pdata);
704 * This works around a known issue in ACPI tables where LPSS devices
705 * have _PS0 and _PS3 without _PSC (and no power resources), so
706 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
708 acpi_device_fix_up_power(adev);
710 adev->driver_data = pdata;
711 pdev = acpi_create_platform_device(adev, dev_desc->properties);
712 if (IS_ERR_OR_NULL(pdev)) {
713 adev->driver_data = NULL;
718 acpi_lpss_create_device_links(adev, pdev);
722 /* Skip the device, but continue the namespace scan */
729 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
731 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
734 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
737 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
740 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
742 struct acpi_device *adev = ACPI_COMPANION(dev);
743 struct lpss_private_data *pdata;
750 spin_lock_irqsave(&dev->power.lock, flags);
751 if (pm_runtime_suspended(dev)) {
755 pdata = acpi_driver_data(adev);
756 if (WARN_ON(!pdata || !pdata->mmio_base)) {
760 *val = __lpss_reg_read(pdata, reg);
764 spin_unlock_irqrestore(&dev->power.lock, flags);
768 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
775 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
776 ret = lpss_reg_read(dev, reg, <r_value);
780 return sysfs_emit(buf, "%08x\n", ltr_value);
783 static ssize_t lpss_ltr_mode_show(struct device *dev,
784 struct device_attribute *attr, char *buf)
790 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
794 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
795 return sprintf(buf, "%s\n", outstr);
798 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
799 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
800 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
802 static struct attribute *lpss_attrs[] = {
803 &dev_attr_auto_ltr.attr,
804 &dev_attr_sw_ltr.attr,
805 &dev_attr_ltr_mode.attr,
809 static const struct attribute_group lpss_attr_group = {
814 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
816 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
817 u32 ltr_mode, ltr_val;
819 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
821 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
822 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
823 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
827 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
828 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
829 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
830 val = LPSS_LTR_MAX_VAL;
831 } else if (val > LPSS_LTR_MAX_VAL) {
832 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
833 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
835 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
838 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
839 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
840 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
841 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
847 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
849 * @pdata: pointer to the private data of the LPSS device
851 * Most LPSS devices have private registers which may loose their context when
852 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
855 static void acpi_lpss_save_ctx(struct device *dev,
856 struct lpss_private_data *pdata)
860 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
861 unsigned long offset = i * sizeof(u32);
863 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
864 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
865 pdata->prv_reg_ctx[i], offset);
870 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
872 * @pdata: pointer to the private data of the LPSS device
874 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
876 static void acpi_lpss_restore_ctx(struct device *dev,
877 struct lpss_private_data *pdata)
881 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
882 unsigned long offset = i * sizeof(u32);
884 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
885 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
886 pdata->prv_reg_ctx[i], offset);
890 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
893 * The following delay is needed or the subsequent write operations may
894 * fail. The LPSS devices are actually PCI devices and the PCI spec
895 * expects 10ms delay before the device can be accessed after D3 to D0
896 * transition. However some platforms like BSW does not need this delay.
898 unsigned int delay = 10; /* default 10ms delay */
900 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
906 static int acpi_lpss_activate(struct device *dev)
908 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
911 ret = acpi_dev_resume(dev);
915 acpi_lpss_d3_to_d0_delay(pdata);
918 * This is called only on ->probe() stage where a device is either in
919 * known state defined by BIOS or most likely powered off. Due to this
920 * we have to deassert reset line to be sure that ->probe() will
921 * recognize the device.
923 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
924 lpss_deassert_reset(pdata);
927 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
928 acpi_lpss_save_ctx(dev, pdata);
934 static void acpi_lpss_dismiss(struct device *dev)
936 acpi_dev_suspend(dev, false);
939 /* IOSF SB for LPSS island */
940 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
941 #define LPSS_IOSF_UNIT_LPIO1 0xAB
942 #define LPSS_IOSF_UNIT_LPIO2 0xAC
944 #define LPSS_IOSF_PMCSR 0x84
945 #define LPSS_PMCSR_D0 0
946 #define LPSS_PMCSR_D3hot 3
947 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
949 #define LPSS_IOSF_GPIODEF0 0x154
950 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
951 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
952 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
953 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
955 static DEFINE_MUTEX(lpss_iosf_mutex);
956 static bool lpss_iosf_d3_entered = true;
958 static void lpss_iosf_enter_d3_state(void)
961 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
962 u32 value2 = LPSS_PMCSR_D3hot;
963 u32 mask2 = LPSS_PMCSR_Dx_MASK;
965 * PMC provides an information about actual status of the LPSS devices.
966 * Here we read the values related to LPSS power island, i.e. LPSS
967 * devices, excluding both LPSS DMA controllers, along with SCC domain.
969 u32 func_dis, d3_sts_0, pmc_status;
972 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
976 mutex_lock(&lpss_iosf_mutex);
978 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
983 * Get the status of entire LPSS power island per device basis.
984 * Shutdown both LPSS DMA controllers if and only if all other devices
985 * are already in D3hot.
987 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
991 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
992 LPSS_IOSF_PMCSR, value2, mask2);
994 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
995 LPSS_IOSF_PMCSR, value2, mask2);
997 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
998 LPSS_IOSF_GPIODEF0, value1, mask1);
1000 lpss_iosf_d3_entered = true;
1003 mutex_unlock(&lpss_iosf_mutex);
1006 static void lpss_iosf_exit_d3_state(void)
1008 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
1009 LPSS_GPIODEF0_DMA_LLP;
1010 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
1011 u32 value2 = LPSS_PMCSR_D0;
1012 u32 mask2 = LPSS_PMCSR_Dx_MASK;
1014 mutex_lock(&lpss_iosf_mutex);
1016 if (!lpss_iosf_d3_entered)
1019 lpss_iosf_d3_entered = false;
1021 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
1022 LPSS_IOSF_GPIODEF0, value1, mask1);
1024 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1025 LPSS_IOSF_PMCSR, value2, mask2);
1027 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1028 LPSS_IOSF_PMCSR, value2, mask2);
1031 mutex_unlock(&lpss_iosf_mutex);
1034 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1036 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1039 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1040 acpi_lpss_save_ctx(dev, pdata);
1042 ret = acpi_dev_suspend(dev, wakeup);
1045 * This call must be last in the sequence, otherwise PMC will return
1046 * wrong status for devices being about to be powered off. See
1047 * lpss_iosf_enter_d3_state() for further information.
1049 if (acpi_target_system_state() == ACPI_STATE_S0 &&
1050 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1051 lpss_iosf_enter_d3_state();
1056 static int acpi_lpss_resume(struct device *dev)
1058 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1062 * This call is kept first to be in symmetry with
1063 * acpi_lpss_runtime_suspend() one.
1065 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1066 lpss_iosf_exit_d3_state();
1068 ret = acpi_dev_resume(dev);
1072 acpi_lpss_d3_to_d0_delay(pdata);
1074 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1075 acpi_lpss_restore_ctx(dev, pdata);
1080 #ifdef CONFIG_PM_SLEEP
1081 static int acpi_lpss_do_suspend_late(struct device *dev)
1085 if (dev_pm_skip_suspend(dev))
1088 ret = pm_generic_suspend_late(dev);
1089 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1092 static int acpi_lpss_suspend_late(struct device *dev)
1094 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1096 if (pdata->dev_desc->resume_from_noirq)
1099 return acpi_lpss_do_suspend_late(dev);
1102 static int acpi_lpss_suspend_noirq(struct device *dev)
1104 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1107 if (pdata->dev_desc->resume_from_noirq) {
1109 * The driver's ->suspend_late callback will be invoked by
1110 * acpi_lpss_do_suspend_late(), with the assumption that the
1111 * driver really wanted to run that code in ->suspend_noirq, but
1112 * it could not run after acpi_dev_suspend() and the driver
1113 * expected the latter to be called in the "late" phase.
1115 ret = acpi_lpss_do_suspend_late(dev);
1120 return acpi_subsys_suspend_noirq(dev);
1123 static int acpi_lpss_do_resume_early(struct device *dev)
1125 int ret = acpi_lpss_resume(dev);
1127 return ret ? ret : pm_generic_resume_early(dev);
1130 static int acpi_lpss_resume_early(struct device *dev)
1132 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1134 if (pdata->dev_desc->resume_from_noirq)
1137 if (dev_pm_skip_resume(dev))
1140 return acpi_lpss_do_resume_early(dev);
1143 static int acpi_lpss_resume_noirq(struct device *dev)
1145 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1148 /* Follow acpi_subsys_resume_noirq(). */
1149 if (dev_pm_skip_resume(dev))
1152 ret = pm_generic_resume_noirq(dev);
1156 if (!pdata->dev_desc->resume_from_noirq)
1160 * The driver's ->resume_early callback will be invoked by
1161 * acpi_lpss_do_resume_early(), with the assumption that the driver
1162 * really wanted to run that code in ->resume_noirq, but it could not
1163 * run before acpi_dev_resume() and the driver expected the latter to be
1164 * called in the "early" phase.
1166 return acpi_lpss_do_resume_early(dev);
1169 static int acpi_lpss_do_restore_early(struct device *dev)
1171 int ret = acpi_lpss_resume(dev);
1173 return ret ? ret : pm_generic_restore_early(dev);
1176 static int acpi_lpss_restore_early(struct device *dev)
1178 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1180 if (pdata->dev_desc->resume_from_noirq)
1183 return acpi_lpss_do_restore_early(dev);
1186 static int acpi_lpss_restore_noirq(struct device *dev)
1188 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1191 ret = pm_generic_restore_noirq(dev);
1195 if (!pdata->dev_desc->resume_from_noirq)
1198 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1199 return acpi_lpss_do_restore_early(dev);
1202 static int acpi_lpss_do_poweroff_late(struct device *dev)
1204 int ret = pm_generic_poweroff_late(dev);
1206 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1209 static int acpi_lpss_poweroff_late(struct device *dev)
1211 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1213 if (dev_pm_skip_suspend(dev))
1216 if (pdata->dev_desc->resume_from_noirq)
1219 return acpi_lpss_do_poweroff_late(dev);
1222 static int acpi_lpss_poweroff_noirq(struct device *dev)
1224 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1226 if (dev_pm_skip_suspend(dev))
1229 if (pdata->dev_desc->resume_from_noirq) {
1230 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1231 int ret = acpi_lpss_do_poweroff_late(dev);
1237 return pm_generic_poweroff_noirq(dev);
1239 #endif /* CONFIG_PM_SLEEP */
1241 static int acpi_lpss_runtime_suspend(struct device *dev)
1243 int ret = pm_generic_runtime_suspend(dev);
1245 return ret ? ret : acpi_lpss_suspend(dev, true);
1248 static int acpi_lpss_runtime_resume(struct device *dev)
1250 int ret = acpi_lpss_resume(dev);
1252 return ret ? ret : pm_generic_runtime_resume(dev);
1254 #endif /* CONFIG_PM */
1256 static struct dev_pm_domain acpi_lpss_pm_domain = {
1258 .activate = acpi_lpss_activate,
1259 .dismiss = acpi_lpss_dismiss,
1263 #ifdef CONFIG_PM_SLEEP
1264 .prepare = acpi_subsys_prepare,
1265 .complete = acpi_subsys_complete,
1266 .suspend = acpi_subsys_suspend,
1267 .suspend_late = acpi_lpss_suspend_late,
1268 .suspend_noirq = acpi_lpss_suspend_noirq,
1269 .resume_noirq = acpi_lpss_resume_noirq,
1270 .resume_early = acpi_lpss_resume_early,
1271 .freeze = acpi_subsys_freeze,
1272 .poweroff = acpi_subsys_poweroff,
1273 .poweroff_late = acpi_lpss_poweroff_late,
1274 .poweroff_noirq = acpi_lpss_poweroff_noirq,
1275 .restore_noirq = acpi_lpss_restore_noirq,
1276 .restore_early = acpi_lpss_restore_early,
1278 .runtime_suspend = acpi_lpss_runtime_suspend,
1279 .runtime_resume = acpi_lpss_runtime_resume,
1284 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1285 unsigned long action, void *data)
1287 struct platform_device *pdev = to_platform_device(data);
1288 struct lpss_private_data *pdata;
1289 struct acpi_device *adev;
1290 const struct acpi_device_id *id;
1292 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1293 if (!id || !id->driver_data)
1296 adev = ACPI_COMPANION(&pdev->dev);
1300 pdata = acpi_driver_data(adev);
1304 if (pdata->mmio_base &&
1305 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1306 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1311 case BUS_NOTIFY_BIND_DRIVER:
1312 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1314 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1315 case BUS_NOTIFY_UNBOUND_DRIVER:
1316 dev_pm_domain_set(&pdev->dev, NULL);
1318 case BUS_NOTIFY_ADD_DEVICE:
1319 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1320 if (pdata->dev_desc->flags & LPSS_LTR)
1321 return sysfs_create_group(&pdev->dev.kobj,
1324 case BUS_NOTIFY_DEL_DEVICE:
1325 if (pdata->dev_desc->flags & LPSS_LTR)
1326 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1327 dev_pm_domain_set(&pdev->dev, NULL);
1336 static struct notifier_block acpi_lpss_nb = {
1337 .notifier_call = acpi_lpss_platform_notify,
1340 static void acpi_lpss_bind(struct device *dev)
1342 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1344 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1347 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1348 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1350 dev_err(dev, "MMIO size insufficient to access LTR\n");
1353 static void acpi_lpss_unbind(struct device *dev)
1355 dev->power.set_latency_tolerance = NULL;
1358 static struct acpi_scan_handler lpss_handler = {
1359 .ids = acpi_lpss_device_ids,
1360 .attach = acpi_lpss_create_device,
1361 .bind = acpi_lpss_bind,
1362 .unbind = acpi_lpss_unbind,
1365 void __init acpi_lpss_init(void)
1367 const struct x86_cpu_id *id;
1370 ret = lpss_atom_clk_init();
1374 id = x86_match_cpu(lpss_cpu_ids);
1376 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1378 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1379 acpi_scan_add_handler(&lpss_handler);
1384 static struct acpi_scan_handler lpss_handler = {
1385 .ids = acpi_lpss_device_ids,
1388 void __init acpi_lpss_init(void)
1390 acpi_scan_add_handler(&lpss_handler);
1393 #endif /* CONFIG_X86_INTEL_LPSS */