drivers/accel/ivpu/ivpu_hw_40xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020-2023 Intel Corporation
   4  */
   5
   6 #include "ivpu_drv.h"
   7 #include "ivpu_fw.h"
   8 #include "ivpu_hw.h"
   9 #include "ivpu_hw_40xx_reg.h"
  10 #include "ivpu_hw_reg_io.h"
  11 #include "ivpu_ipc.h"
  12 #include "ivpu_mmu.h"
  13 #include "ivpu_pm.h"
  14
  15 #include <linux/dmi.h>
  16
  17 #define TILE_MAX_NUM                 6
  18 #define TILE_MAX_MASK                0x3f
  19
  20 #define LNL_HW_ID                    0x4040
  21
  22 #define SKU_TILE_SHIFT               0u
  23 #define SKU_TILE_MASK                0x0000ffffu
  24 #define SKU_HW_ID_SHIFT              16u
  25 #define SKU_HW_ID_MASK               0xffff0000u
  26
  27 #define PLL_CONFIG_DEFAULT           0x1
  28 #define PLL_CDYN_DEFAULT             0x80
  29 #define PLL_EPP_DEFAULT              0x80
  30 #define PLL_REF_CLK_FREQ             (50 * 1000000)
  31 #define PLL_RATIO_TO_FREQ(x)         ((x) * PLL_REF_CLK_FREQ)
  32
  33 #define PLL_PROFILING_FREQ_DEFAULT   38400000
  34 #define PLL_PROFILING_FREQ_HIGH      400000000
  35
  36 #define TIM_SAFE_ENABLE              0xf1d0dead
  37 #define TIM_WATCHDOG_RESET_VALUE     0xffffffff
  38
  39 #define TIMEOUT_US                   (150 * USEC_PER_MSEC)
  40 #define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
  41 #define PLL_TIMEOUT_US               (1500 * USEC_PER_MSEC)
  42
  43 #define WEIGHTS_DEFAULT              0xf711f711u
  44 #define WEIGHTS_ATS_DEFAULT          0x0000f711u
  45
  46 #define ICB_0_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
  47                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
  48                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
  49                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
  50                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
  51                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
  52                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
  53
  54 #define ICB_1_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
  55                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
  56                         (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
  57
  58 #define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
  59
  60 #define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)) | \
  61                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
  62                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \
  63                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \
  64                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \
  65                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \
  66                            (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR)))
  67
  68 #define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
  69 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
  70
  71 #define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
  72                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
  73                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
  74                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
  75                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
  76                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
  77                                      (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
  78
  79 static char *ivpu_platform_to_str(u32 platform)
  80 {
  81         switch (platform) {
  82         case IVPU_PLATFORM_SILICON:
  83                 return "IVPU_PLATFORM_SILICON";
  84         case IVPU_PLATFORM_SIMICS:
  85                 return "IVPU_PLATFORM_SIMICS";
  86         case IVPU_PLATFORM_FPGA:
  87                 return "IVPU_PLATFORM_FPGA";
  88         default:
  89                 return "Invalid platform";
  90         }
  91 }
  92
  93 static const struct dmi_system_id ivpu_dmi_platform_simulation[] = {
  94         {
  95                 .ident = "Intel Simics",
  96                 .matches = {
  97                         DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
  98                         DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
  99                         DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
 100                 },
 101         },
 102         {
 103                 .ident = "Intel Simics",
 104                 .matches = {
 105                         DMI_MATCH(DMI_BOARD_NAME, "Simics"),
 106                 },
 107         },
 108         { }
 109 };
 110
 111 static void ivpu_hw_read_platform(struct ivpu_device *vdev)
 112 {
 113         if (dmi_check_system(ivpu_dmi_platform_simulation))
 114                 vdev->platform = IVPU_PLATFORM_SIMICS;
 115         else
 116                 vdev->platform = IVPU_PLATFORM_SILICON;
 117
 118         ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
 119                  ivpu_platform_to_str(vdev->platform), vdev->platform);
 120 }
 121
 122 static void ivpu_hw_wa_init(struct ivpu_device *vdev)
 123 {
 124         vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
 125         vdev->wa.clear_runtime_mem = false;
 126
 127         if (ivpu_hw_gen(vdev) == IVPU_HW_40XX)
 128                 vdev->wa.disable_clock_relinquish = true;
 129 }
 130
 131 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
 132 {
 133         if (ivpu_is_fpga(vdev)) {
 134                 vdev->timeout.boot = 100000;
 135                 vdev->timeout.jsm = 50000;
 136                 vdev->timeout.tdr = 2000000;
 137                 vdev->timeout.reschedule_suspend = 1000;
 138         } else if (ivpu_is_simics(vdev)) {
 139                 vdev->timeout.boot = 50;
 140                 vdev->timeout.jsm = 500;
 141                 vdev->timeout.tdr = 10000;
 142                 vdev->timeout.reschedule_suspend = 10;
 143         } else {
 144                 vdev->timeout.boot = 1000;
 145                 vdev->timeout.jsm = 500;
 146                 vdev->timeout.tdr = 2000;
 147                 vdev->timeout.reschedule_suspend = 10;
 148         }
 149 }
 150
 151 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
 152 {
 153         return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
 154 }
 155
 156 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
 157                              u16 target_ratio, u16 epp, u16 config, u16 cdyn)
 158 {
 159         int ret;
 160         u32 val;
 161
 162         ret = ivpu_pll_wait_for_cmd_send(vdev);
 163         if (ret) {
 164                 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
 165                 return ret;
 166         }
 167
 168         val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
 169         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
 170         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
 171         REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
 172
 173         val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
 174         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
 175         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
 176         REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
 177
 178         val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
 179         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
 180         val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
 181         REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
 182
 183         val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
 184         val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
 185         REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
 186
 187         ret = ivpu_pll_wait_for_cmd_send(vdev);
 188         if (ret)
 189                 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
 190
 191         return ret;
 192 }
 193
 194 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
 195 {
 196         return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
 197 }
 198
 199 static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
 200 {
 201         if (ivpu_is_simics(vdev))
 202                 return 0;
 203
 204         return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
 205 }
 206
 207 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
 208 {
 209         struct ivpu_hw_info *hw = vdev->hw;
 210         u8 fuse_min_ratio, fuse_pn_ratio, fuse_max_ratio;
 211         u32 fmin_fuse, fmax_fuse;
 212
 213         fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE);
 214         fuse_min_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
 215         fuse_pn_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
 216
 217         fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE);
 218         fuse_max_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
 219
 220         hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
 221         hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
 222         hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
 223 }
 224
 225 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
 226 {
 227         u16 config = enable ? PLL_CONFIG_DEFAULT : 0;
 228         u16 cdyn = enable ? PLL_CDYN_DEFAULT : 0;
 229         u16 epp = enable ? PLL_EPP_DEFAULT : 0;
 230         struct ivpu_hw_info *hw = vdev->hw;
 231         u16 target_ratio = hw->pll.pn_ratio;
 232         int ret;
 233
 234         ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n",
 235                  PLL_RATIO_TO_FREQ(target_ratio), epp, config, cdyn);
 236
 237         ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio,
 238                                 target_ratio, epp, config, cdyn);
 239         if (ret) {
 240                 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
 241                 return ret;
 242         }
 243
 244         if (enable) {
 245                 ret = ivpu_pll_wait_for_status_ready(vdev);
 246                 if (ret) {
 247                         ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
 248                         return ret;
 249                 }
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int ivpu_pll_enable(struct ivpu_device *vdev)
 256 {
 257         return ivpu_pll_drive(vdev, true);
 258 }
 259
 260 static int ivpu_pll_disable(struct ivpu_device *vdev)
 261 {
 262         return ivpu_pll_drive(vdev, false);
 263 }
 264
 265 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
 266 {
 267         u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
 268
 269         if (enable) {
 270                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
 271                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
 272                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
 273         } else {
 274                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
 275                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
 276                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
 277         }
 278
 279         REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
 280 }
 281
 282 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
 283 {
 284         u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
 285
 286         if (enable) {
 287                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
 288                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
 289                 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
 290         } else {
 291                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
 292                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
 293                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
 294         }
 295
 296         REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
 297 }
 298
 299 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
 300 {
 301         u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
 302
 303         if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
 304                 return -EIO;
 305
 306         return 0;
 307 }
 308
 309 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
 310 {
 311         u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
 312
 313         if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
 314                 return -EIO;
 315
 316         return 0;
 317 }
 318
 319 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
 320 {
 321         u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
 322
 323         if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
 324                 return -EIO;
 325
 326         return 0;
 327 }
 328
 329 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
 330 {
 331         u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
 332
 333         if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
 334             !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
 335                 return -EIO;
 336
 337         return 0;
 338 }
 339
 340 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
 341 {
 342         u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
 343
 344         if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
 345             !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
 346                 return -EIO;
 347
 348         return 0;
 349 }
 350
 351 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
 352 {
 353         u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
 354
 355         if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
 356             !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
 357                 return -EIO;
 358
 359         return 0;
 360 }
 361
 362 static void ivpu_boot_idle_gen_drive(struct ivpu_device *vdev, bool enable)
 363 {
 364         u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
 365
 366         if (enable)
 367                 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
 368         else
 369                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
 370
 371         REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
 372 }
 373
 374 static int ivpu_boot_host_ss_check(struct ivpu_device *vdev)
 375 {
 376         int ret;
 377
 378         ret = ivpu_boot_noc_qreqn_check(vdev, 0x0);
 379         if (ret) {
 380                 ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
 381                 return ret;
 382         }
 383
 384         ret = ivpu_boot_noc_qacceptn_check(vdev, 0x0);
 385         if (ret) {
 386                 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
 387                 return ret;
 388         }
 389
 390         ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
 391         if (ret)
 392                 ivpu_err(vdev, "Failed qdeny check %d\n", ret);
 393
 394         return ret;
 395 }
 396
 397 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
 398 {
 399         int ret;
 400         u32 val;
 401
 402         val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
 403         if (enable)
 404                 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
 405         else
 406                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
 407         REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
 408
 409         ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
 410         if (ret) {
 411                 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
 412                 return ret;
 413         }
 414
 415         ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
 416         if (ret) {
 417                 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
 418                 return ret;
 419         }
 420
 421         if (enable) {
 422                 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
 423                 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
 424         }
 425
 426         return ret;
 427 }
 428
 429 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
 430 {
 431         return ivpu_boot_host_ss_axi_drive(vdev, true);
 432 }
 433
 434 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
 435 {
 436         int ret;
 437         u32 val;
 438
 439         val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
 440         if (enable) {
 441                 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
 442                 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
 443         } else {
 444                 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
 445                 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
 446         }
 447         REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
 448
 449         ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
 450         if (ret) {
 451                 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
 452                 return ret;
 453         }
 454
 455         ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
 456         if (ret)
 457                 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
 458
 459         return ret;
 460 }
 461
 462 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
 463 {
 464         return ivpu_boot_host_ss_top_noc_drive(vdev, true);
 465 }
 466
 467 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
 468 {
 469         u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
 470
 471         if (enable)
 472                 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
 473         else
 474                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
 475
 476         REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
 477
 478         if (enable)
 479                 ndelay(500);
 480 }
 481
 482 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
 483 {
 484         u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
 485
 486         if (enable)
 487                 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
 488         else
 489                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
 490
 491         REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
 492
 493         if (!enable)
 494                 ndelay(500);
 495 }
 496
 497 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
 498 {
 499         if (ivpu_is_fpga(vdev))
 500                 return 0;
 501
 502         return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU,
 503                              exp_val, PWR_ISLAND_STATUS_TIMEOUT_US);
 504 }
 505
 506 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
 507 {
 508         u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
 509
 510         if (enable)
 511                 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
 512         else
 513                 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
 514
 515         REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
 516 }
 517
 518 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
 519 {
 520         u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
 521
 522         val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
 523         val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
 524         val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
 525
 526         REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
 527 }
 528
 529 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
 530 {
 531         u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
 532
 533         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
 534         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
 535         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
 536         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
 537         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
 538         val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
 539
 540         REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
 541 }
 542
 543 static int ivpu_boot_cpu_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
 544 {
 545         u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
 546
 547         if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
 548                 return -EIO;
 549
 550         return 0;
 551 }
 552
 553 static int ivpu_boot_cpu_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
 554 {
 555         u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
 556
 557         if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
 558                 return -EIO;
 559
 560         return 0;
 561 }
 562
 563 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
 564 {
 565         int ret;
 566
 567         ret = ivpu_wait_for_clock_own_resource_ack(vdev);
 568         if (ret) {
 569                 ivpu_err(vdev, "Timed out waiting for clock own resource ACK\n");
 570                 return ret;
 571         }
 572
 573         ivpu_boot_pwr_island_trickle_drive(vdev, true);
 574         ivpu_boot_pwr_island_drive(vdev, true);
 575
 576         ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
 577         if (ret) {
 578                 ivpu_err(vdev, "Timed out waiting for power island status\n");
 579                 return ret;
 580         }
 581
 582         ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
 583         if (ret) {
 584                 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
 585                 return ret;
 586         }
 587
 588         ivpu_boot_host_ss_clk_drive(vdev, true);
 589         ivpu_boot_host_ss_rst_drive(vdev, true);
 590         ivpu_boot_pwr_island_isolation_drive(vdev, false);
 591
 592         return ret;
 593 }
 594
 595 static int ivpu_boot_soc_cpu_drive(struct ivpu_device *vdev, bool enable)
 596 {
 597         int ret;
 598         u32 val;
 599
 600         val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
 601         if (enable)
 602                 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
 603         else
 604                 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
 605         REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
 606
 607         ret = ivpu_boot_cpu_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
 608         if (ret) {
 609                 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
 610                 return ret;
 611         }
 612
 613         ret = ivpu_boot_cpu_noc_qdeny_check(vdev, 0x0);
 614         if (ret)
 615                 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
 616
 617         return ret;
 618 }
 619
 620 static int ivpu_boot_soc_cpu_enable(struct ivpu_device *vdev)
 621 {
 622         return ivpu_boot_soc_cpu_drive(vdev, true);
 623 }
 624
 625 static int ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
 626 {
 627         int ret;
 628         u32 val;
 629         u64 val64;
 630
 631         ret = ivpu_boot_soc_cpu_enable(vdev);
 632         if (ret) {
 633                 ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
 634                 return ret;
 635         }
 636
 637         val64 = vdev->fw->entry_point;
 638         val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1;
 639         REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64);
 640
 641         val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
 642         val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
 643         REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
 644
 645         ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
 646                  ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
 647
 648         return 0;
 649 }
 650
 651 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
 652 {
 653         int ret;
 654         u32 val;
 655
 656         ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
 657         if (ret) {
 658                 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
 659                 return ret;
 660         }
 661
 662         val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
 663         if (enable)
 664                 val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
 665         else
 666                 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
 667         REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
 668
 669         ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
 670         if (ret) {
 671                 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
 672                 return ret;
 673         }
 674
 675         return 0;
 676 }
 677
 678 static bool ivpu_tile_disable_check(u32 config)
 679 {
 680         /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
 681         if (config == 0)
 682                 return true;
 683
 684         if (config > BIT(TILE_MAX_NUM - 1))
 685                 return false;
 686
 687         if ((config & (config - 1)) == 0)
 688                 return true;
 689
 690         return false;
 691 }
 692
 693 static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
 694 {
 695         struct ivpu_hw_info *hw = vdev->hw;
 696         u32 tile_disable;
 697         u32 tile_enable;
 698         u32 fuse;
 699
 700         fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);
 701         if (!REG_TEST_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, VALID, fuse)) {
 702                 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
 703                 return -EIO;
 704         }
 705
 706         tile_disable = REG_GET_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, CONFIG, fuse);
 707         if (!ivpu_tile_disable_check(tile_disable)) {
 708                 ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable);
 709                 return -EIO;
 710         }
 711
 712         if (tile_disable)
 713                 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
 714                          TILE_MAX_NUM - 1, ffs(tile_disable) - 1);
 715         else
 716                 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);
 717
 718         tile_enable = (~tile_disable) & TILE_MAX_MASK;
 719
 720         hw->sku = REG_SET_FLD_NUM(SKU, HW_ID, LNL_HW_ID, hw->sku);
 721         hw->sku = REG_SET_FLD_NUM(SKU, TILE, tile_enable, hw->sku);
 722         hw->tile_fuse = tile_disable;
 723         hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
 724
 725         ivpu_pll_init_frequency_ratios(vdev);
 726
 727         ivpu_hw_init_range(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
 728         ivpu_hw_init_range(&vdev->hw->ranges.user,   0x80000000, SZ_256M);
 729         ivpu_hw_init_range(&vdev->hw->ranges.shave,  0x80000000 + SZ_256M, SZ_2G - SZ_256M);
 730         ivpu_hw_init_range(&vdev->hw->ranges.dma,   0x200000000, SZ_8G);
 731
 732         return 0;
 733 }
 734
 735 static int ivpu_hw_40xx_reset(struct ivpu_device *vdev)
 736 {
 737         int ret;
 738         u32 val;
 739
 740         ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
 741         if (ret) {
 742                 ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
 743                 return ret;
 744         }
 745
 746         val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
 747         val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
 748         REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
 749
 750         ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
 751         if (ret)
 752                 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
 753
 754         return ret;
 755 }
 756
 757 static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev)
 758 {
 759         int ret;
 760
 761         if (IVPU_WA(punit_disabled))
 762                 return 0;
 763
 764         ret = ivpu_boot_d0i3_drive(vdev, true);
 765         if (ret)
 766                 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
 767
 768         udelay(5); /* VPU requires 5 us to complete the transition */
 769
 770         return ret;
 771 }
 772
 773 static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev)
 774 {
 775         int ret;
 776
 777         if (IVPU_WA(punit_disabled))
 778                 return 0;
 779
 780         ret = ivpu_boot_d0i3_drive(vdev, false);
 781         if (ret)
 782                 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
 783
 784         return ret;
 785 }
 786
 787 static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev)
 788 {
 789         u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
 790
 791         if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
 792                 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
 793         else
 794                 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
 795
 796         REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
 797 }
 798
 799 static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev)
 800 {
 801         ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
 802                  REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable");
 803 }
 804
 805 static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev)
 806 {
 807         u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
 808
 809         val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
 810         REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
 811 }
 812
 813 static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev)
 814 {
 815         int ret;
 816
 817         ret = ivpu_hw_40xx_reset(vdev);
 818         if (ret) {
 819                 ivpu_err(vdev, "Failed to reset HW: %d\n", ret);
 820                 return ret;
 821         }
 822
 823         ivpu_hw_read_platform(vdev);
 824         ivpu_hw_wa_init(vdev);
 825         ivpu_hw_timeouts_init(vdev);
 826
 827         ret = ivpu_hw_40xx_d0i3_disable(vdev);
 828         if (ret)
 829                 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
 830
 831         ret = ivpu_pll_enable(vdev);
 832         if (ret) {
 833                 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
 834                 return ret;
 835         }
 836
 837         if (IVPU_WA(disable_clock_relinquish))
 838                 ivpu_hw_40xx_clock_relinquish_disable(vdev);
 839         ivpu_hw_40xx_profiling_freq_reg_set(vdev);
 840         ivpu_hw_40xx_ats_print(vdev);
 841
 842         ret = ivpu_boot_host_ss_check(vdev);
 843         if (ret) {
 844                 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
 845                 return ret;
 846         }
 847
 848         ivpu_boot_idle_gen_drive(vdev, false);
 849
 850         ret = ivpu_boot_pwr_domain_enable(vdev);
 851         if (ret) {
 852                 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
 853                 return ret;
 854         }
 855
 856         ret = ivpu_boot_host_ss_axi_enable(vdev);
 857         if (ret) {
 858                 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
 859                 return ret;
 860         }
 861
 862         ret = ivpu_boot_host_ss_top_noc_enable(vdev);
 863         if (ret)
 864                 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
 865
 866         return ret;
 867 }
 868
 869 static int ivpu_hw_40xx_boot_fw(struct ivpu_device *vdev)
 870 {
 871         int ret;
 872
 873         ivpu_boot_no_snoop_enable(vdev);
 874         ivpu_boot_tbu_mmu_enable(vdev);
 875
 876         ret = ivpu_boot_soc_cpu_boot(vdev);
 877         if (ret)
 878                 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
 879
 880         return ret;
 881 }
 882
 883 static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev)
 884 {
 885         u32 val;
 886
 887         if (IVPU_WA(punit_disabled))
 888                 return true;
 889
 890         val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
 891         return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
 892                REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
 893 }
 894
 895 static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev)
 896 {
 897         int ret = 0;
 898
 899         if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_reset(vdev))
 900                 ivpu_warn(vdev, "Failed to reset the VPU\n");
 901
 902         if (ivpu_pll_disable(vdev)) {
 903                 ivpu_err(vdev, "Failed to disable PLL\n");
 904                 ret = -EIO;
 905         }
 906
 907         if (ivpu_hw_40xx_d0i3_enable(vdev)) {
 908                 ivpu_err(vdev, "Failed to enter D0I3\n");
 909                 ret = -EIO;
 910         }
 911
 912         return ret;
 913 }
 914
 915 static void ivpu_hw_40xx_wdt_disable(struct ivpu_device *vdev)
 916 {
 917         u32 val;
 918
 919         REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
 920         REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
 921
 922         REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
 923         REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
 924
 925         val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
 926         val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
 927         REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
 928 }
 929
 930 /* Register indirect accesses */
 931 static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev)
 932 {
 933         u32 pll_curr_ratio;
 934
 935         pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ);
 936         pll_curr_ratio &= VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK;
 937
 938         return PLL_RATIO_TO_FREQ(pll_curr_ratio);
 939 }
 940
 941 static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
 942 {
 943         return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
 944 }
 945
 946 static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev)
 947 {
 948         return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE);
 949 }
 950
 951 static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
 952 {
 953         return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
 954 }
 955
 956 static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
 957 {
 958         u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0;
 959         u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
 960
 961         REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
 962 }
 963
 964 static u32 ivpu_hw_40xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
 965 {
 966         return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
 967 }
 968
 969 static u32 ivpu_hw_40xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
 970 {
 971         u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT);
 972
 973         return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
 974 }
 975
 976 static void ivpu_hw_40xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
 977 {
 978         REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
 979 }
 980
 981 static void ivpu_hw_40xx_irq_clear(struct ivpu_device *vdev)
 982 {
 983         REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK);
 984 }
 985
 986 static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev)
 987 {
 988         REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
 989         REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
 990         REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
 991         REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
 992 }
 993
 994 static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev)
 995 {
 996         REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
 997         REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
 998         REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
 999         REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
1000 }
1001
1002 static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
1003 {
1004         /* TODO: For LNN hang consider engine reset instead of full recovery */
1005         ivpu_pm_schedule_recovery(vdev);
1006 }
1007
1008 static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
1009 {
1010         ivpu_hw_wdt_disable(vdev);
1011         ivpu_pm_schedule_recovery(vdev);
1012 }
1013
1014 static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
1015 {
1016         ivpu_pm_schedule_recovery(vdev);
1017 }
1018
1019 /* Handler for IRQs from VPU core (irqV) */
1020 static irqreturn_t ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq)
1021 {
1022         u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1023         irqreturn_t ret = IRQ_NONE;
1024
1025         if (!status)
1026                 return IRQ_NONE;
1027
1028         REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
1029
1030         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
1031                 ivpu_mmu_irq_evtq_handler(vdev);
1032
1033         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
1034                 ret |= ivpu_ipc_irq_handler(vdev);
1035
1036         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
1037                 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1038
1039         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
1040                 ivpu_mmu_irq_gerr_handler(vdev);
1041
1042         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
1043                 ivpu_hw_40xx_irq_wdt_mss_handler(vdev);
1044
1045         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
1046                 ivpu_hw_40xx_irq_wdt_nce_handler(vdev);
1047
1048         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
1049                 ivpu_hw_40xx_irq_noc_firewall_handler(vdev);
1050
1051         return ret;
1052 }
1053
1054 /* Handler for IRQs from Buttress core (irqB) */
1055 static irqreturn_t ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
1056 {
1057         bool schedule_recovery = false;
1058         u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1059
1060         if (status == 0)
1061                 return IRQ_NONE;
1062
1063         /* Disable global interrupt before handling local buttress interrupts */
1064         REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
1065
1066         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
1067                 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
1068
1069         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
1070                 ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1071                          REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1072                          REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1073                 REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
1074                 schedule_recovery = true;
1075         }
1076
1077         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, status)) {
1078                 ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1079                 REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1);
1080                 schedule_recovery = true;
1081         }
1082
1083         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, status)) {
1084                 ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1085                 REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1);
1086                 schedule_recovery = true;
1087         }
1088
1089         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, status)) {
1090                 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
1091                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1092                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1093                 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1);
1094                 schedule_recovery = true;
1095         }
1096
1097         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, status)) {
1098                 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
1099                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1100                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1101                 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1);
1102                 schedule_recovery = true;
1103         }
1104
1105         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, status)) {
1106                 ivpu_err(vdev, "Survivability error detected\n");
1107                 schedule_recovery = true;
1108         }
1109
1110         /* This must be done after interrupts are cleared at the source. */
1111         REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
1112
1113         /* Re-enable global interrupt */
1114         REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1115
1116         if (schedule_recovery)
1117                 ivpu_pm_schedule_recovery(vdev);
1118
1119         return IRQ_HANDLED;
1120 }
1121
1122 static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr)
1123 {
1124         struct ivpu_device *vdev = ptr;
1125         irqreturn_t ret = IRQ_NONE;
1126
1127         ret |= ivpu_hw_40xx_irqv_handler(vdev, irq);
1128         ret |= ivpu_hw_40xx_irqb_handler(vdev, irq);
1129
1130         if (ret & IRQ_WAKE_THREAD)
1131                 return IRQ_WAKE_THREAD;
1132
1133         return ret;
1134 }
1135
1136 static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
1137 {
1138         u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1139         u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1140
1141         if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev))
1142                 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1143
1144         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv))
1145                 ivpu_err(vdev, "WDT MSS timeout detected\n");
1146
1147         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv))
1148                 ivpu_err(vdev, "WDT NCE timeout detected\n");
1149
1150         if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
1151                 ivpu_err(vdev, "NOC Firewall irq detected\n");
1152
1153         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) {
1154                 ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1155                          REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1156                          REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1157         }
1158
1159         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, irqb))
1160                 ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1161
1162         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, irqb))
1163                 ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1164
1165         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, irqb))
1166                 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
1167                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1168                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1169
1170         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, irqb))
1171                 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
1172                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1173                          REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1174
1175         if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, irqb))
1176                 ivpu_err(vdev, "Survivability error detected\n");
1177 }
1178
1179 const struct ivpu_hw_ops ivpu_hw_40xx_ops = {
1180         .info_init = ivpu_hw_40xx_info_init,
1181         .power_up = ivpu_hw_40xx_power_up,
1182         .is_idle = ivpu_hw_40xx_is_idle,
1183         .power_down = ivpu_hw_40xx_power_down,
1184         .boot_fw = ivpu_hw_40xx_boot_fw,
1185         .wdt_disable = ivpu_hw_40xx_wdt_disable,
1186         .diagnose_failure = ivpu_hw_40xx_diagnose_failure,
1187         .reg_pll_freq_get = ivpu_hw_40xx_reg_pll_freq_get,
1188         .reg_telemetry_offset_get = ivpu_hw_40xx_reg_telemetry_offset_get,
1189         .reg_telemetry_size_get = ivpu_hw_40xx_reg_telemetry_size_get,
1190         .reg_telemetry_enable_get = ivpu_hw_40xx_reg_telemetry_enable_get,
1191         .reg_db_set = ivpu_hw_40xx_reg_db_set,
1192         .reg_ipc_rx_addr_get = ivpu_hw_40xx_reg_ipc_rx_addr_get,
1193         .reg_ipc_rx_count_get = ivpu_hw_40xx_reg_ipc_rx_count_get,
1194         .reg_ipc_tx_set = ivpu_hw_40xx_reg_ipc_tx_set,
1195         .irq_clear = ivpu_hw_40xx_irq_clear,
1196         .irq_enable = ivpu_hw_40xx_irq_enable,
1197         .irq_disable = ivpu_hw_40xx_irq_disable,
1198         .irq_handler = ivpu_hw_40xx_irq_handler,
1199 };