3 \# Source code to NASM documentation
5 \M{category}{Programming}
6 \M{title}{NASM: The Netwide Assembler}
8 \M{author}{The NASM Development Team}
9 \M{license}{All rights reserved. This document is redistributable under the licence given in the file "COPYING" distributed in the NASM archive.}
10 \M{summary}{This file documents NASM, the Netwide Assembler: an assembler targetting the Intel x86 series of processors, with portable source.}
13 \M{infotitle}{The Netwide Assembler for x86}
14 \M{epslogo}{nasmlogo.eps}
20 \IR{-On} \c{-On} option
36 \IR{!=} \c{!=} operator
37 \IR{$ here} \c{$} Here token
40 \IR{%%} \c{%%} operator
41 \IR{%+1} \c{%+1} and \c{%-1} syntax
43 \IR{%0} \c{%0} parameter count
45 \IR{&&} \c{&&} operator
47 \IR{..@} \c{..@} symbol prefix
49 \IR{//} \c{//} operator
51 \IR{<<} \c{<<} operator
52 \IR{<=} \c{<=} operator
53 \IR{<>} \c{<>} operator
55 \IR{==} \c{==} operator
57 \IR{>=} \c{>=} operator
58 \IR{>>} \c{>>} operator
59 \IR{?} \c{?} MASM syntax
61 \IR{^^} \c{^^} operator
63 \IR{||} \c{||} operator
65 \IR{%$} \c{%$} and \c{%$$} prefixes
67 \IR{+ opaddition} \c{+} operator, binary
68 \IR{+ opunary} \c{+} operator, unary
69 \IR{+ modifier} \c{+} modifier
70 \IR{- opsubtraction} \c{-} operator, binary
71 \IR{- opunary} \c{-} operator, unary
72 \IR{alignment, in bin sections} alignment, in \c{bin} sections
73 \IR{alignment, in elf sections} alignment, in \c{elf} sections
74 \IR{alignment, in win32 sections} alignment, in \c{win32} sections
75 \IR{alignment, of elf common variables} alignment, of \c{elf} common
77 \IR{alignment, in obj sections} alignment, in \c{obj} sections
78 \IR{a.out, bsd version} \c{a.out}, BSD version
79 \IR{a.out, linux version} \c{a.out}, Linux version
80 \IR{autoconf} Autoconf
81 \IR{bitwise and} bitwise AND
82 \IR{bitwise or} bitwise OR
83 \IR{bitwise xor} bitwise XOR
84 \IR{block ifs} block IFs
85 \IR{borland pascal} Borland, Pascal
86 \IR{borland's win32 compilers} Borland, Win32 compilers
87 \IR{braces, after % sign} braces, after \c{%} sign
89 \IR{c calling convention} C calling convention
90 \IR{c symbol names} C symbol names
91 \IA{critical expressions}{critical expression}
92 \IA{command line}{command-line}
93 \IA{case sensitivity}{case sensitive}
94 \IA{case-sensitive}{case sensitive}
95 \IA{case-insensitive}{case sensitive}
96 \IA{character constants}{character constant}
97 \IR{common object file format} Common Object File Format
98 \IR{common variables, alignment in elf} common variables, alignment
100 \IR{common, elf extensions to} \c{COMMON}, \c{elf} extensions to
101 \IR{common, obj extensions to} \c{COMMON}, \c{obj} extensions to
102 \IR{declaring structure} declaring structures
103 \IR{default-wrt mechanism} default-\c{WRT} mechanism
106 \IR{dll symbols, exporting} DLL symbols, exporting
107 \IR{dll symbols, importing} DLL symbols, importing
109 \IR{dos archive} DOS archive
110 \IR{dos source archive} DOS source archive
111 \IA{effective address}{effective addresses}
112 \IA{effective-address}{effective addresses}
113 \IR{elf shared libraries} \c{elf} shared libraries
115 \IR{freelink} FreeLink
116 \IR{functions, c calling convention} functions, C calling convention
117 \IR{functions, pascal calling convention} functions, Pascal calling
119 \IR{global, aoutb extensions to} \c{GLOBAL}, \c{aoutb} extensions to
120 \IR{global, elf extensions to} \c{GLOBAL}, \c{elf} extensions to
121 \IR{global, rdf extensions to} \c{GLOBAL}, \c{rdf} extensions to
123 \IR{got relocations} \c{GOT} relocations
124 \IR{gotoff relocation} \c{GOTOFF} relocations
125 \IR{gotpc relocation} \c{GOTPC} relocations
126 \IR{linux elf} Linux ELF
127 \IR{logical and} logical AND
128 \IR{logical or} logical OR
129 \IR{logical xor} logical XOR
131 \IA{memory reference}{memory references}
132 \IA{misc directory}{misc subdirectory}
133 \IR{misc subdirectory} \c{misc} subdirectory
134 \IR{microsoft omf} Microsoft OMF
135 \IR{mmx registers} MMX registers
136 \IA{modr/m}{modr/m byte}
137 \IR{modr/m byte} ModR/M byte
139 \IR{ms-dos device drivers} MS-DOS device drivers
140 \IR{multipush} \c{multipush} macro
141 \IR{nasm version} NASM version
145 \IR{operating-system} operating system
147 \IR{pascal calling convention}Pascal calling convention
148 \IR{passes} passes, assembly
153 \IR{plt} \c{PLT} relocations
154 \IA{pre-defining macros}{pre-define}
156 \IA{rdoff subdirectory}{rdoff}
157 \IR{rdoff} \c{rdoff} subdirectory
158 \IR{relocatable dynamic object file format} Relocatable Dynamic
160 \IR{relocations, pic-specific} relocations, PIC-specific
161 \IA{repeating}{repeating code}
162 \IR{section alignment, in elf} section alignment, in \c{elf}
163 \IR{section alignment, in bin} section alignment, in \c{bin}
164 \IR{section alignment, in obj} section alignment, in \c{obj}
165 \IR{section alignment, in win32} section alignment, in \c{win32}
166 \IR{section, elf extensions to} \c{SECTION}, \c{elf} extensions to
167 \IR{section, win32 extensions to} \c{SECTION}, \c{win32} extensions to
168 \IR{segment alignment, in bin} segment alignment, in \c{bin}
169 \IR{segment alignment, in obj} segment alignment, in \c{obj}
170 \IR{segment, obj extensions to} \c{SEGMENT}, \c{elf} extensions to
171 \IR{segment names, borland pascal} segment names, Borland Pascal
172 \IR{shift command} \c{shift} command
174 \IR{sib byte} SIB byte
175 \IA{standard section names}{standardised section names}
176 \IR{symbols, exporting from dlls} symbols, exporting from DLLs
177 \IR{symbols, importing from dlls} symbols, importing from DLLs
179 \IR{test subdirectory} \c{test} subdirectory
181 \IR{underscore, in c symbols} underscore, in C symbols
183 \IR{unix source archive} Unix source archive
185 \IR{version number of nasm} version number of NASM
186 \IR{visual c++} Visual C++
187 \IR{www page} WWW page
190 \IR{windows 95} Windows 95
191 \IR{windows nt} Windows NT
192 \# \IC{program entry point}{entry point, program}
193 \# \IC{program entry point}{start point, program}
194 \# \IC{MS-DOS device drivers}{device drivers, MS-DOS}
195 \# \IC{16-bit mode, versus 32-bit mode}{32-bit mode, versus 16-bit mode}
196 \# \IC{c symbol names}{symbol names, in C}
199 \C{intro} Introduction
201 \H{whatsnasm} What Is NASM?
203 The Netwide Assembler, NASM, is an 80x86 assembler designed for
204 portability and modularity. It supports a range of object file
205 formats, including Linux \c{a.out} and \c{ELF}, \c{NetBSD/FreeBSD},
206 \c{COFF}, Microsoft 16-bit \c{OBJ} and \c{Win32}. It will also output
207 plain binary files. Its syntax is designed to be simple and easy to
208 understand, similar to Intel's but less complex. It supports \c{Pentium},
209 \c{P6}, \c{MMX}, \c{3DNow!}, \c{SSE} and \c{SSE2} opcodes, and has
213 \S{yaasm} Why Yet Another Assembler?
215 The Netwide Assembler grew out of an idea on \i\c{comp.lang.asm.x86}
216 (or possibly \i\c{alt.lang.asm} - I forget which), which was
217 essentially that there didn't seem to be a good \e{free} x86-series
218 assembler around, and that maybe someone ought to write one.
220 \b \i\c{a86} is good, but not free, and in particular you don't get any
221 32-bit capability until you pay. It's DOS only, too.
223 \b \i\c{gas} is free, and ports over DOS and Unix, but it's not
224 very good, since it's designed to be a back end to \i\c{gcc}, which
225 always feeds it correct code. So its error checking is minimal. Also,
226 its syntax is horrible, from the point of view of anyone trying to
227 actually \e{write} anything in it. Plus you can't write 16-bit code in
230 \b \i\c{as86} is Linux-specific, and (my version at least) doesn't
231 seem to have much (or any) documentation.
233 \b \i\c{MASM} isn't very good, and it's expensive, and it runs only under
236 \b \i\c{TASM} is better, but still strives for MASM compatibility,
237 which means millions of directives and tons of red tape. And its syntax
238 is essentially MASM's, with the contradictions and quirks that
239 entails (although it sorts out some of those by means of Ideal mode).
240 It's expensive too. And it's DOS-only.
242 So here, for your coding pleasure, is NASM. At present it's
243 still in prototype stage - we don't promise that it can outperform
244 any of these assemblers. But please, \e{please} send us bug reports,
245 fixes, helpful information, and anything else you can get your hands
246 on (and thanks to the many people who've done this already! You all
247 know who you are), and we'll improve it out of all recognition.
251 \S{legal} Licence Conditions
253 Please see the file \c{Licence}, supplied as part of any NASM
254 distribution archive, for the \i{licence} conditions under which you
258 \H{contact} Contact Information
260 The current version of NASM (since about 0.98.08) are maintained by a
261 team of developers, accessible through the \c{nasm-devel} mailing list
262 (see below for the link).
263 If you want to report a bug, please read \k{bugs} first.
265 NASM has a \i{WWW page} at
266 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm},
267 and another, with additional information, at
268 \W{http://nasm.2y.net/}\c{http://nasm.2y.net/}
270 The original authors are \i{e\-mail}able as
271 \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} and
272 \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}.
273 The latter is no longer involved in the development team.
275 \i{New releases} of NASM are uploaded to the official sites
276 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm}
278 \W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org}
280 \W{ftp://ibiblio.org/pub/Linux/devel/lang/assemblers/}\i\c{ibiblio.org}.
282 Announcements are posted to
283 \W{news:comp.lang.asm.x86}\i\c{comp.lang.asm.x86},
284 \W{news:alt.lang.asm}\i\c{alt.lang.asm} and
285 \W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce}
287 If you want information about NASM beta releases, and the current
288 development status, please subscribe to the \i\c{nasm-devel} email list
290 \W{http://groups.yahoo.com/group/nasm-devel}\c{http://groups.yahoo.com/group/nasm-devel},
291 \W{http://www.pairlist.net/mailman/listinfo/nasm-devel}\c{http://www.pairlist.net/mailman/listinfo/nasm-devel}
293 \W{http://sourceforge.net/projects/nasm}\c{http://sourceforge.net/projects/nasm}.
295 The preferred list is the list at Sourceforge, which is also the home to
296 the latest nasm source code and releases. The other lists are open, but
297 may not continue to be supported in the long term.
300 \H{install} Installation
302 \S{instdos} \i{Installing} NASM under MS-\i{DOS} or Windows
304 Once you've obtained the \i{DOS archive} for NASM, \i\c{nasmXXX.zip}
305 (where \c{XXX} denotes the version number of NASM contained in the
306 archive), unpack it into its own directory (for example \c{c:\\nasm}).
308 The archive will contain four executable files: the NASM executable
309 files \i\c{nasm.exe} and \i\c{nasmw.exe}, and the NDISASM executable
310 files \i\c{ndisasm.exe} and \i\c{ndisasmw.exe}. In each case, the
311 file whose name ends in \c{w} is a \I{Win32}\c{Win32} executable,
312 designed to run under \I{Windows 95}\c{Windows 95} or \I{Windows NT}
313 \c{Windows NT} Intel, and the other one is a 16-bit \I{DOS}\c{DOS}
316 The only file NASM needs to run is its own executable, so copy
317 (at least) one of \c{nasm.exe} and \c{nasmw.exe} to a directory on
318 your PATH, or alternatively edit \i\c{autoexec.bat} to add the
319 \c{nasm} directory to your \i\c{PATH}. (If you're only installing the
320 \c{Win32} version, you may wish to rename it to \c{nasm.exe}.)
322 That's it - NASM is installed. You don't need the nasm directory
323 to be present to run NASM (unless you've added it to your \c{PATH}),
324 so you can delete it if you need to save space; however, you may
325 want to keep the documentation or test programs.
327 If you've downloaded the \i{DOS source archive}, \i\c{nasmXXXs.zip},
328 the \c{nasm} directory will also contain the full NASM \i{source
329 code}, and a selection of \i{Makefiles} you can (hopefully) use to
330 rebuild your copy of NASM from scratch.
332 Note that the source files \c{insnsa.c}, \c{insnsd.c}, \c{insnsi.h}
333 and \c{insnsn.c} are automatically generated from the master
334 instruction table \c{insns.dat} by a Perl script; the file
335 \c{macros.c} is generated from \c{standard.mac} by another Perl
336 script. Although the NASM 0.98 distribution includes these generated
337 files, you will need to rebuild them (and hence, will need a Perl
338 interpreter) if you change insns.dat, standard.mac or the
339 documentation. It is possible future source distributions may not
340 include these files at all. Ports of \i{Perl} for a variety of
341 platforms, including DOS and Windows, are available from
342 \W{http://www.cpan.org/ports/}\i{www.cpan.org}.
345 \S{instdos} Installing NASM under \i{Unix}
347 Once you've obtained the \i{Unix source archive} for NASM,
348 \i\c{nasm-X.XX.tar.gz} (where \c{X.XX} denotes the version number of
349 NASM contained in the archive), unpack it into a directory such
350 as \c{/usr/local/src}. The archive, when unpacked, will create its
351 own subdirectory \c{nasm-X.XX}.
353 NASM is an \I{Autoconf}\I\c{configure}auto-configuring package: once
354 you've unpacked it, \c{cd} to the directory it's been unpacked into
355 and type \c{./configure}. This shell script will find the best C
356 compiler to use for building NASM and set up \i{Makefiles}
359 Once NASM has auto-configured, you can type \i\c{make} to build the
360 \c{nasm} and \c{ndisasm} binaries, and then \c{make install} to
361 install them in \c{/usr/local/bin} and install the \i{man pages}
362 \i\c{nasm.1} and \i\c{ndisasm.1} in \c{/usr/local/man/man1}.
363 Alternatively, you can give options such as \c{--prefix} to the
364 configure script (see the file \i\c{INSTALL} for more details), or
365 install the programs yourself.
367 NASM also comes with a set of utilities for handling the \c{RDOFF}
368 custom object-file format, which are in the \i\c{rdoff} subdirectory
369 of the NASM archive. You can build these with \c{make rdf} and
370 install them with \c{make rdf_install}, if you want them.
372 If NASM fails to auto-configure, you may still be able to make it
373 compile by using the fall-back Unix makefile \i\c{Makefile.unx}.
374 Copy or rename that file to \c{Makefile} and try typing \c{make}.
375 There is also a Makefile.unx file in the \c{rdoff} subdirectory.
378 \C{running} Running NASM
380 \H{syntax} NASM \i{Command-Line} Syntax
382 To assemble a file, you issue a command of the form
384 \c nasm -f <format> <filename> [-o <output>]
388 \c nasm -f elf myfile.asm
390 will assemble \c{myfile.asm} into an \c{ELF} object file \c{myfile.o}. And
392 \c nasm -f bin myfile.asm -o myfile.com
394 will assemble \c{myfile.asm} into a raw binary file \c{myfile.com}.
396 To produce a listing file, with the hex codes output from NASM
397 displayed on the left of the original sources, use the \c{-l} option
398 to give a listing file name, for example:
400 \c nasm -f coff myfile.asm -l myfile.lst
402 To get further usage instructions from NASM, try typing
406 This will also list the available output file formats, and what they
409 If you use Linux but aren't sure whether your system is \c{a.out} or
414 (in the directory in which you put the NASM binary when you
415 installed it). If it says something like
417 \c nasm: ELF 32-bit LSB executable i386 (386 and up) Version 1
419 then your system is \c{ELF}, and you should use the option \c{-f elf}
420 when you want NASM to produce Linux object files. If it says
422 \c nasm: Linux/i386 demand-paged executable (QMAGIC)
424 or something similar, your system is \c{a.out}, and you should use
425 \c{-f aout} instead (Linux \c{a.out} systems are considered obsolete,
426 and are rare these days.)
428 Like Unix compilers and assemblers, NASM is silent unless it
429 goes wrong: you won't see any output at all, unless it gives error
433 \S{opt-o} The \i\c{-o} Option: Specifying the Output File Name
435 NASM will normally choose the name of your output file for you;
436 precisely how it does this is dependent on the object file format.
437 For Microsoft object file formats (\i\c{obj} and \i\c{win32}), it
438 will remove the \c{.asm} \i{extension} (or whatever extension you
439 like to use - NASM doesn't care) from your source file name and
440 substitute \c{.obj}. For Unix object file formats (\i\c{aout},
441 \i\c{coff}, \i\c{elf} and \i\c{as86}) it will substitute \c{.o}. For
442 \i\c{rdf}, it will use \c{.rdf}, and for the \i\c{bin} format it
443 will simply remove the extension, so that \c{myfile.asm} produces
444 the output file \c{myfile}.
446 If the output file already exists, NASM will overwrite it, unless it
447 has the same name as the input file, in which case it will give a
448 warning and use \i\c{nasm.out} as the output file name instead.
450 For situations in which this behaviour is unacceptable, NASM
451 provides the \c{-o} command-line option, which allows you to specify
452 your desired output file name. You invoke \c{-o} by following it
453 with the name you wish for the output file, either with or without
454 an intervening space. For example:
456 \c nasm -f bin program.asm -o program.com
457 \c nasm -f bin driver.asm -odriver.sys
459 Note that this is a small o, and is different from a capital O , which
460 is used to specify the number of optimisation passes required. See \k{opt-On}.
463 \S{opt-f} The \i\c{-f} Option: Specifying the \i{Output File Format}
465 If you do not supply the \c{-f} option to NASM, it will choose an
466 output file format for you itself. In the distribution versions of
467 NASM, the default is always \i\c{bin}; if you've compiled your own
468 copy of NASM, you can redefine \i\c{OF_DEFAULT} at compile time and
469 choose what you want the default to be.
471 Like \c{-o}, the intervening space between \c{-f} and the output
472 file format is optional; so \c{-f elf} and \c{-felf} are both valid.
474 A complete list of the available output file formats can be given by
475 issuing the command \i\c{nasm -hf}.
478 \S{opt-l} The \i\c{-l} Option: Generating a \i{Listing File}
480 If you supply the \c{-l} option to NASM, followed (with the usual
481 optional space) by a file name, NASM will generate a
482 \i{source-listing file} for you, in which addresses and generated
483 code are listed on the left, and the actual source code, with
484 expansions of multi-line macros (except those which specifically
485 request no expansion in source listings: see \k{nolist}) on the
488 \c nasm -f elf myfile.asm -l myfile.lst
491 \S{opt-M} The \i\c{-M} Option: Generate \i{Makefile Dependencies}.
493 This option can be used to generate makefile dependencies on stdout.
494 This can be redirected to a file for further processing. For example:
496 \c NASM -M myfile.asm > myfile.dep
499 \S{opt-F} The \i\c{-F} Option: Selecting a \i{Debugging Format}
501 This option can be used to select a debugging format for the output file.
502 The syntax is the same as for the -f option, except that it produces
503 output in a debugging format.
505 A complete list of the available debug file formats for an output format
506 can be seen by issuing the command \i\c{nasm -f <format> -y}.
508 This option is not built into NASM by default. For information on how
509 to enable it when building from the sources, see \k{dbgfmt}
512 \S{opt-g} The \i\c{-g} Option: Enabling \i{Debug Information}.
514 This option can be used to generate debugging information in the specified
517 See \k{opt-F} for more information.
520 \S{opt-E} The \i\c{-E} Option: Send Errors to a File
522 Under \I{DOS}\c{MS-DOS} it can be difficult (though there are ways) to
523 redirect the standard-error output of a program to a file. Since
524 NASM usually produces its warning and \i{error messages} on
525 \i\c{stderr}, this can make it hard to capture the errors if (for
526 example) you want to load them into an editor.
528 NASM therefore provides the \c{-E} option, taking a filename argument
529 which causes errors to be sent to the specified files rather than
530 standard error. Therefore you can \I{redirecting errors}redirect
531 the errors into a file by typing
533 \c nasm -E myfile.err -f obj myfile.asm
536 \S{opt-s} The \i\c{-s} Option: Send Errors to \i\c{stdout}
538 The \c{-s} option redirects \i{error messages} to \c{stdout} rather
539 than \c{stderr}, so it can be redirected under \I{DOS}\c{MS-DOS}. To
540 assemble the file \c{myfile.asm} and pipe its output to the \c{more}
541 program, you can type:
543 \c nasm -s -f obj myfile.asm | more
545 See also the \c{-E} option, \k{opt-E}.
548 \S{opt-i} The \i\c{-i}\I\c{-I} Option: Include File Search Directories
550 When NASM sees the \i\c{%include} directive in a source file (see
551 \k{include}), it will search for the given file not only in the
552 current directory, but also in any directories specified on the
553 command line by the use of the \c{-i} option. Therefore you can
554 include files from a \i{macro library}, for example, by typing
556 \c nasm -ic:\\macrolib\\ -f obj myfile.asm
558 (As usual, a space between \c{-i} and the path name is allowed, and
561 NASM, in the interests of complete source-code portability, does not
562 understand the file naming conventions of the OS it is running on;
563 the string you provide as an argument to the \c{-i} option will be
564 prepended exactly as written to the name of the include file.
565 Therefore the trailing backslash in the above example is necessary.
566 Under Unix, a trailing forward slash is similarly necessary.
568 (You can use this to your advantage, if you're really \i{perverse},
569 by noting that the option \c{-ifoo} will cause \c{%include "bar.i"}
570 to search for the file \c{foobar.i}...)
572 If you want to define a \e{standard} \i{include search path},
573 similar to \c{/usr/include} on Unix systems, you should place one or
574 more \c{-i} directives in the \c{NASMENV} environment variable (see
577 For Makefile compatibility with many C compilers, this option can also
578 be specified as \c{-I}.
581 \S{opt-p} The \i\c{-p}\I\c{-P} Option: \I{pre-including files}Pre-Include a File
583 \I\c{%include}NASM allows you to specify files to be
584 \e{pre-included} into your source file, by the use of the \c{-p}
587 \c nasm myfile.asm -p myinc.inc
589 is equivalent to running \c{nasm myfile.asm} and placing the
590 directive \c{%include "myinc.inc"} at the start of the file.
592 For consistency with the \c{-I}, \c{-D} and \c{-U} options, this
593 option can also be specified as \c{-P}.
596 \S{opt-d} The \i\c{-d}\I\c{-D} Option: \I{pre-defining macros} Pre-Define a Macro
598 \I\c{%define}Just as the \c{-p} option gives an alternative to placing
599 \c{%include} directives at the start of a source file, the \c{-d}
600 option gives an alternative to placing a \c{%define} directive. You
603 \c nasm myfile.asm -dFOO=100
605 as an alternative to placing the directive
609 at the start of the file. You can miss off the macro value, as well:
610 the option \c{-dFOO} is equivalent to coding \c{%define FOO}. This
611 form of the directive may be useful for selecting \i{assembly-time
612 options} which are then tested using \c{%ifdef}, for example
615 For Makefile compatibility with many C compilers, this option can also
616 be specified as \c{-D}.
619 \S{opt-u} The \i\c{-u}\I\c{-U} Option: \I{Undefining macros} Undefine a Macro
621 \I\c{%undef}The \c{-u} option undefines a macro that would otherwise
622 have been pre-defined, either automatically or by a \c{-p} or \c{-d}
623 option specified earlier on the command lines.
625 For example, the following command line:
627 \c nasm myfile.asm -dFOO=100 -uFOO
629 would result in \c{FOO} \e{not} being a predefined macro in the
630 program. This is useful to override options specified at a different
633 For Makefile compatibility with many C compilers, this option can also
634 be specified as \c{-U}.
637 \S{opt-e} The \i\c{-e} Option: Preprocess Only
639 NASM allows the \i{preprocessor} to be run on its own, up to a
640 point. Using the \c{-e} option (which requires no arguments) will
641 cause NASM to preprocess its input file, expand all the macro
642 references, remove all the comments and preprocessor directives, and
643 print the resulting file on standard output (or save it to a file,
644 if the \c{-o} option is also used).
646 This option cannot be applied to programs which require the
647 preprocessor to evaluate \I{preprocessor expressions}\i{expressions}
648 which depend on the values of symbols: so code such as
650 \c %assign tablesize ($-tablestart)
652 will cause an error in \i{preprocess-only mode}.
655 \S{opt-a} The \i\c{-a} Option: Don't Preprocess At All
657 If NASM is being used as the back end to a compiler, it might be
658 desirable to \I{suppressing preprocessing}suppress preprocessing
659 completely and assume the compiler has already done it, to save time
660 and increase compilation speeds. The \c{-a} option, requiring no
661 argument, instructs NASM to replace its powerful \i{preprocessor}
662 with a \i{stub preprocessor} which does nothing.
665 \S{opt-On} The \i\c{-On} Option: Specifying \i{Multipass Optimization}.
667 NASM defaults to being a two pass assembler. This means that if you
668 have a complex source file which needs more than 2 passes to assemble
669 correctly, you have to tell it.
671 Using the \c{-O} option, you can tell NASM to carry out multiple passes.
674 \b \c{-O0} strict two-pass assembly, JMP and Jcc are handled more
675 like v0.98, except that backward JMPs are short, if possible.
676 Immediate operands take their long forms if a short form is
679 \b \c{-O1} strict two-pass assembly, but forward branches are assembled
680 with code guaranteed to reach; may produce larger code than
681 -O0, but will produce successful assembly more often if
682 branch offset sizes are not specified.
683 Additionally, immediate operands which will fit in a signed byte
684 are optimised, unless the long form is specified.
686 \b \c{-On} multi-pass optimization, minimize branch offsets; also will
687 minimize signed immediate bytes, overriding size specification.
688 If 2 <= n <= 3, then there are 5 * n passes, otherwise there
692 Note that this is a capital O, and is different from a small o, which
693 is used to specify the output format. See \k{opt-o}.
696 \S{opt-t} The \i\c{-t} option: Enable TASM Compatibility Mode
698 NASM includes a limited form of compatibility with Borland's \c{TASM}.
699 When NASM's \c{-t} option is used, the following changes are made:
701 \b local labels may be prefixed with \c{@@} instead of \c{.}
703 \b TASM-style response files beginning with \c{@} may be specified on
704 the command line. This is different from the \c{-@resp} style that NASM
707 \b size override is supported within brackets. In TASM compatible mode,
708 a size override inside square brackets changes the size of the operand,
709 and not the address type of the operand as it does in NASM syntax. E.g.
710 \c{mov eax,[DWORD val]} is valid syntax in TASM compatibility mode.
711 Note that you lose the ability to override the default address type for
714 \b \c{%arg} preprocessor directive is supported which is similar to
715 TASM's \c{ARG} directive.
717 \b \c{%local} preprocessor directive
719 \b \c{%stacksize} preprocessor directive
721 \b unprefixed forms of some directives supported (\c{arg}, \c{elif},
722 \c{else}, \c{endif}, \c{if}, \c{ifdef}, \c{ifdifi}, \c{ifndef},
723 \c{include}, \c{local})
727 For more information on the directives, see the section on TASM
728 Compatiblity preprocessor directives in \k{tasmcompat}.
731 \S{opt-w} The \i\c{-w} Option: Enable or Disable Assembly \i{Warnings}
733 NASM can observe many conditions during the course of assembly which
734 are worth mentioning to the user, but not a sufficiently severe
735 error to justify NASM refusing to generate an output file. These
736 conditions are reported like errors, but come up with the word
737 `warning' before the message. Warnings do not prevent NASM from
738 generating an output file and returning a success status to the
741 Some conditions are even less severe than that: they are only
742 sometimes worth mentioning to the user. Therefore NASM supports the
743 \c{-w} command-line option, which enables or disables certain
744 classes of assembly warning. Such warning classes are described by a
745 name, for example \c{orphan-labels}; you can enable warnings of
746 this class by the command-line option \c{-w+orphan-labels} and
747 disable it by \c{-w-orphan-labels}.
749 The \i{suppressible warning} classes are:
751 \b \i\c{macro-params} covers warnings about \i{multi-line macros}
752 being invoked with the wrong number of parameters. This warning
753 class is enabled by default; see \k{mlmacover} for an example of why
754 you might want to disable it.
756 \b \i\c{orphan-labels} covers warnings about source lines which
757 contain no instruction but define a label without a trailing colon.
758 NASM does not warn about this somewhat obscure condition by default;
759 see \k{syntax} for an example of why you might want it to.
761 \b \i\c{number-overflow} covers warnings about numeric constants which
762 don't fit in 32 bits (for example, it's easy to type one too many Fs
763 and produce \c{0x7ffffffff} by mistake). This warning class is
767 \S{opt-v} The \i\c{-v} Option: Display \i{Version} Info
769 Typing \c{NASM -v} will display the version of NASM which you are using,
770 and the date on which it was compiled.
772 You will need the version number if you report a bug.
775 \S{nasmenv} The \c{NASMENV} \i{Environment} Variable
777 If you define an environment variable called \c{NASMENV}, the program
778 will interpret it as a list of extra command-line options, which are
779 processed before the real command line. You can use this to define
780 standard search directories for include files, by putting \c{-i}
781 options in the \c{NASMENV} variable.
783 The value of the variable is split up at white space, so that the
784 value \c{-s -ic:\\nasmlib} will be treated as two separate options.
785 However, that means that the value \c{-dNAME="my name"} won't do
786 what you might want, because it will be split at the space and the
787 NASM command-line processing will get confused by the two
788 nonsensical words \c{-dNAME="my} and \c{name"}.
790 To get round this, NASM provides a feature whereby, if you begin the
791 \c{NASMENV} environment variable with some character that isn't a minus
792 sign, then NASM will treat this character as the \i{separator
793 character} for options. So setting the \c{NASMENV} variable to the
794 value \c{!-s!-ic:\\nasmlib} is equivalent to setting it to \c{-s
795 -ic:\\nasmlib}, but \c{!-dNAME="my name"} will work.
797 This environment variable was previously called \c{NASM}. This was
798 changed with version 0.98.31.
801 \H{qstart} \i{Quick Start} for \i{MASM} Users
803 If you're used to writing programs with MASM, or with \i{TASM} in
804 MASM-compatible (non-Ideal) mode, or with \i\c{a86}, this section
805 attempts to outline the major differences between MASM's syntax and
806 NASM's. If you're not already used to MASM, it's probably worth
807 skipping this section.
810 \S{qscs} NASM Is \I{case sensitivity}Case-Sensitive
812 One simple difference is that NASM is case-sensitive. It makes a
813 difference whether you call your label \c{foo}, \c{Foo} or \c{FOO}.
814 If you're assembling to \c{DOS} or \c{OS/2} \c{.OBJ} files, you can
815 invoke the \i\c{UPPERCASE} directive (documented in \k{objfmt}) to
816 ensure that all symbols exported to other code modules are forced
817 to be upper case; but even then, \e{within} a single module, NASM
818 will distinguish between labels differing only in case.
821 \S{qsbrackets} NASM Requires \i{Square Brackets} For \i{Memory References}
823 NASM was designed with simplicity of syntax in mind. One of the
824 \i{design goals} of NASM is that it should be possible, as far as is
825 practical, for the user to look at a single line of NASM code
826 and tell what opcode is generated by it. You can't do this in MASM:
827 if you declare, for example,
832 then the two lines of code
837 generate completely different opcodes, despite having
838 identical-looking syntaxes.
840 NASM avoids this undesirable situation by having a much simpler
841 syntax for memory references. The rule is simply that any access to
842 the \e{contents} of a memory location requires square brackets
843 around the address, and any access to the \e{address} of a variable
844 doesn't. So an instruction of the form \c{mov ax,foo} will
845 \e{always} refer to a compile-time constant, whether it's an \c{EQU}
846 or the address of a variable; and to access the \e{contents} of the
847 variable \c{bar}, you must code \c{mov ax,[bar]}.
849 This also means that NASM has no need for MASM's \i\c{OFFSET}
850 keyword, since the MASM code \c{mov ax,offset bar} means exactly the
851 same thing as NASM's \c{mov ax,bar}. If you're trying to get
852 large amounts of MASM code to assemble sensibly under NASM, you
853 can always code \c{%idefine offset} to make the preprocessor treat
854 the \c{OFFSET} keyword as a no-op.
856 This issue is even more confusing in \i\c{a86}, where declaring a
857 label with a trailing colon defines it to be a `label' as opposed to
858 a `variable' and causes \c{a86} to adopt NASM-style semantics; so in
859 \c{a86}, \c{mov ax,var} has different behaviour depending on whether
860 \c{var} was declared as \c{var: dw 0} (a label) or \c{var dw 0} (a
861 word-size variable). NASM is very simple by comparison:
862 \e{everything} is a label.
864 NASM, in the interests of simplicity, also does not support the
865 \i{hybrid syntaxes} supported by MASM and its clones, such as
866 \c{mov ax,table[bx]}, where a memory reference is denoted by one
867 portion outside square brackets and another portion inside. The
868 correct syntax for the above is \c{mov ax,[table+bx]}. Likewise,
869 \c{mov ax,es:[di]} is wrong and \c{mov ax,[es:di]} is right.
872 \S{qstypes} NASM Doesn't Store \i{Variable Types}
874 NASM, by design, chooses not to remember the types of variables you
875 declare. Whereas MASM will remember, on seeing \c{var dw 0}, that
876 you declared \c{var} as a word-size variable, and will then be able
877 to fill in the \i{ambiguity} in the size of the instruction \c{mov
878 var,2}, NASM will deliberately remember nothing about the symbol
879 \c{var} except where it begins, and so you must explicitly code
880 \c{mov word [var],2}.
882 For this reason, NASM doesn't support the \c{LODS}, \c{MOVS},
883 \c{STOS}, \c{SCAS}, \c{CMPS}, \c{INS}, or \c{OUTS} instructions,
884 but only supports the forms such as \c{LODSB}, \c{MOVSW}, and
885 \c{SCASD}, which explicitly specify the size of the components of
886 the strings being manipulated.
889 \S{qsassume} NASM Doesn't \i\c{ASSUME}
891 As part of NASM's drive for simplicity, it also does not support the
892 \c{ASSUME} directive. NASM will not keep track of what values you
893 choose to put in your segment registers, and will never
894 \e{automatically} generate a \i{segment override} prefix.
897 \S{qsmodel} NASM Doesn't Support \i{Memory Models}
899 NASM also does not have any directives to support different 16-bit
900 memory models. The programmer has to keep track of which functions
901 are supposed to be called with a \i{far call} and which with a
902 \i{near call}, and is responsible for putting the correct form of
903 \c{RET} instruction (\c{RETN} or \c{RETF}; NASM accepts \c{RET}
904 itself as an alternate form for \c{RETN}); in addition, the
905 programmer is responsible for coding CALL FAR instructions where
906 necessary when calling \e{external} functions, and must also keep
907 track of which external variable definitions are far and which are
911 \S{qsfpu} \i{Floating-Point} Differences
913 NASM uses different names to refer to floating-point registers from
914 MASM: where MASM would call them \c{ST(0)}, \c{ST(1)} and so on, and
915 \i\c{a86} would call them simply \c{0}, \c{1} and so on, NASM
916 chooses to call them \c{st0}, \c{st1} etc.
918 As of version 0.96, NASM now treats the instructions with
919 \i{`nowait'} forms in the same way as MASM-compatible assemblers.
920 The idiosyncratic treatment employed by 0.95 and earlier was based
921 on a misunderstanding by the authors.
924 \S{qsother} Other Differences
926 For historical reasons, NASM uses the keyword \i\c{TWORD} where MASM
927 and compatible assemblers use \i\c{TBYTE}.
929 NASM does not declare \i{uninitialised storage} in the same way as
930 MASM: where a MASM programmer might use \c{stack db 64 dup (?)},
931 NASM requires \c{stack resb 64}, intended to be read as `reserve 64
932 bytes'. For a limited amount of compatibility, since NASM treats
933 \c{?} as a valid character in symbol names, you can code \c{? equ 0}
934 and then writing \c{dw ?} will at least do something vaguely useful.
935 \I\c{RESB}\i\c{DUP} is still not a supported syntax, however.
937 In addition to all of this, macros and directives work completely
938 differently to MASM. See \k{preproc} and \k{directive} for further
942 \C{lang} The NASM Language
944 \H{syntax} Layout of a NASM Source Line
946 Like most assemblers, each NASM source line contains (unless it
947 is a macro, a preprocessor directive or an assembler directive: see
948 \k{preproc} and \k{directive}) some combination of the four fields
950 \c label: instruction operands ; comment
952 As usual, most of these fields are optional; the presence or absence
953 of any combination of a label, an instruction and a comment is allowed.
954 Of course, the operand field is either required or forbidden by the
955 presence and nature of the instruction field.
957 NASM uses backslash (\\) as the line continuation character; if a line
958 ends with backslash, the next line is considered to be a part of the
959 backslash-ended line.
961 NASM places no restrictions on white space within a line: labels may
962 have white space before them, or instructions may have no space
963 before them, or anything. The \i{colon} after a label is also
964 optional. (Note that this means that if you intend to code \c{lodsb}
965 alone on a line, and type \c{lodab} by accident, then that's still a
966 valid source line which does nothing but define a label. Running
967 NASM with the command-line option
968 \I{orphan-labels}\c{-w+orphan-labels} will cause it to warn you if
969 you define a label alone on a line without a \i{trailing colon}.)
971 \i{Valid characters} in labels are letters, numbers, \c{_}, \c{$},
972 \c{#}, \c{@}, \c{~}, \c{.}, and \c{?}. The only characters which may
973 be used as the \e{first} character of an identifier are letters,
974 \c{.} (with special meaning: see \k{locallab}), \c{_} and \c{?}.
975 An identifier may also be prefixed with a \I{$prefix}\c{$} to
976 indicate that it is intended to be read as an identifier and not a
977 reserved word; thus, if some other module you are linking with
978 defines a symbol called \c{eax}, you can refer to \c{$eax} in NASM
979 code to distinguish the symbol from the register.
981 The instruction field may contain any machine instruction: Pentium
982 and P6 instructions, FPU instructions, MMX instructions and even
983 undocumented instructions are all supported. The instruction may be
984 prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or
985 \c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size
986 prefixes}address-size and \i{operand-size prefixes} \c{A16},
987 \c{A32}, \c{O16} and \c{O32} are provided - one example of their use
988 is given in \k{mixsize}. You can also use the name of a \I{segment
989 override}segment register as an instruction prefix: coding
990 \c{es mov [bx],ax} is equivalent to coding \c{mov [es:bx],ax}. We
991 recommend the latter syntax, since it is consistent with other
992 syntactic features of the language, but for instructions such as
993 \c{LODSB}, which has no operands and yet can require a segment
994 override, there is no clean syntactic way to proceed apart from
997 An instruction is not required to use a prefix: prefixes such as
998 \c{CS}, \c{A32}, \c{LOCK} or \c{REPE} can appear on a line by
999 themselves, and NASM will just generate the prefix bytes.
1001 In addition to actual machine instructions, NASM also supports a
1002 number of pseudo-instructions, described in \k{pseudop}.
1004 Instruction \i{operands} may take a number of forms: they can be
1005 registers, described simply by the register name (e.g. \c{ax},
1006 \c{bp}, \c{ebx}, \c{cr0}: NASM does not use the \c{gas}-style
1007 syntax in which register names must be prefixed by a \c{%} sign), or
1008 they can be \i{effective addresses} (see \k{effaddr}), constants
1009 (\k{const}) or expressions (\k{expr}).
1011 For \i{floating-point} instructions, NASM accepts a wide range of
1012 syntaxes: you can use two-operand forms like MASM supports, or you
1013 can use NASM's native single-operand forms in most cases. Details of
1014 all forms of each supported instruction are given in
1015 \k{iref}. For example, you can code:
1017 \c fadd st1 ; this sets st0 := st0 + st1
1018 \c fadd st0,st1 ; so does this
1020 \c fadd st1,st0 ; this sets st1 := st1 + st0
1021 \c fadd to st1 ; so does this
1023 Almost any floating-point instruction that references memory must
1024 use one of the prefixes \i\c{DWORD}, \i\c{QWORD} or \i\c{TWORD} to
1025 indicate what size of \i{memory operand} it refers to.
1028 \H{pseudop} \i{Pseudo-Instructions}
1030 Pseudo-instructions are things which, though not real x86 machine
1031 instructions, are used in the instruction field anyway because
1032 that's the most convenient place to put them. The current
1033 pseudo-instructions are \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and
1034 \i\c{DT}, their \i{uninitialised} counterparts \i\c{RESB},
1035 \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST}, the \i\c{INCBIN}
1036 command, the \i\c{EQU} command, and the \i\c{TIMES} prefix.
1039 \S{db} \c{DB} and friends: Declaring Initialised Data
1041 \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and \i\c{DT} are used, much
1042 as in MASM, to declare initialised data in the output file. They can
1043 be invoked in a wide range of ways:
1044 \I{floating-point}\I{character constant}\I{string constant}
1046 \c db 0x55 ; just the byte 0x55
1047 \c db 0x55,0x56,0x57 ; three bytes in succession
1048 \c db 'a',0x55 ; character constants are OK
1049 \c db 'hello',13,10,'$' ; so are string constants
1050 \c dw 0x1234 ; 0x34 0x12
1051 \c dw 'a' ; 0x41 0x00 (it's just a number)
1052 \c dw 'ab' ; 0x41 0x42 (character constant)
1053 \c dw 'abc' ; 0x41 0x42 0x43 0x00 (string)
1054 \c dd 0x12345678 ; 0x78 0x56 0x34 0x12
1055 \c dd 1.234567e20 ; floating-point constant
1056 \c dq 1.234567e20 ; double-precision float
1057 \c dt 1.234567e20 ; extended-precision float
1059 \c{DQ} and \c{DT} do not accept \i{numeric constants} or string
1060 constants as operands.
1063 \S{resb} \c{RESB} and friends: Declaring \i{Uninitialised} Data
1065 \i\c{RESB}, \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST} are
1066 designed to be used in the BSS section of a module: they declare
1067 \e{uninitialised} storage space. Each takes a single operand, which
1068 is the number of bytes, words, doublewords or whatever to reserve.
1069 As stated in \k{qsother}, NASM does not support the MASM/TASM syntax
1070 of reserving uninitialised space by writing \I\c{?}\c{DW ?} or
1071 similar things: this is what it does instead. The operand to a
1072 \c{RESB}-type pseudo-instruction is a \i\e{critical expression}: see
1077 \c buffer: resb 64 ; reserve 64 bytes
1078 \c wordvar: resw 1 ; reserve a word
1079 \c realarray resq 10 ; array of ten reals
1082 \S{incbin} \i\c{INCBIN}: Including External \i{Binary Files}
1084 \c{INCBIN} is borrowed from the old Amiga assembler \i{DevPac}: it
1085 includes a binary file verbatim into the output file. This can be
1086 handy for (for example) including \i{graphics} and \i{sound} data
1087 directly into a game executable file. It can be called in one of
1090 \c incbin "file.dat" ; include the whole file
1091 \c incbin "file.dat",1024 ; skip the first 1024 bytes
1092 \c incbin "file.dat",1024,512 ; skip the first 1024, and
1093 \c ; actually include at most 512
1096 \S{equ} \i\c{EQU}: Defining Constants
1098 \c{EQU} defines a symbol to a given constant value: when \c{EQU} is
1099 used, the source line must contain a label. The action of \c{EQU} is
1100 to define the given label name to the value of its (only) operand.
1101 This definition is absolute, and cannot change later. So, for
1104 \c message db 'hello, world'
1105 \c msglen equ $-message
1107 defines \c{msglen} to be the constant 12. \c{msglen} may not then be
1108 redefined later. This is not a \i{preprocessor} definition either:
1109 the value of \c{msglen} is evaluated \e{once}, using the value of
1110 \c{$} (see \k{expr} for an explanation of \c{$}) at the point of
1111 definition, rather than being evaluated wherever it is referenced
1112 and using the value of \c{$} at the point of reference. Note that
1113 the operand to an \c{EQU} is also a \i{critical expression}
1117 \S{times} \i\c{TIMES}: \i{Repeating} Instructions or Data
1119 The \c{TIMES} prefix causes the instruction to be assembled multiple
1120 times. This is partly present as NASM's equivalent of the \i\c{DUP}
1121 syntax supported by \i{MASM}-compatible assemblers, in that you can
1124 \c zerobuf: times 64 db 0
1126 or similar things; but \c{TIMES} is more versatile than that. The
1127 argument to \c{TIMES} is not just a numeric constant, but a numeric
1128 \e{expression}, so you can do things like
1130 \c buffer: db 'hello, world'
1131 \c times 64-$+buffer db ' '
1133 which will store exactly enough spaces to make the total length of
1134 \c{buffer} up to 64. Finally, \c{TIMES} can be applied to ordinary
1135 instructions, so you can code trivial \i{unrolled loops} in it:
1139 Note that there is no effective difference between \c{times 100 resb
1140 1} and \c{resb 100}, except that the latter will be assembled about
1141 100 times faster due to the internal structure of the assembler.
1143 The operand to \c{TIMES}, like that of \c{EQU} and those of \c{RESB}
1144 and friends, is a critical expression (\k{crit}).
1146 Note also that \c{TIMES} can't be applied to \i{macros}: the reason
1147 for this is that \c{TIMES} is processed after the macro phase, which
1148 allows the argument to \c{TIMES} to contain expressions such as
1149 \c{64-$+buffer} as above. To repeat more than one line of code, or a
1150 complex macro, use the preprocessor \i\c{%rep} directive.
1153 \H{effaddr} Effective Addresses
1155 An \i{effective address} is any operand to an instruction which
1156 \I{memory reference}references memory. Effective addresses, in NASM,
1157 have a very simple syntax: they consist of an expression evaluating
1158 to the desired address, enclosed in \i{square brackets}. For
1163 \c mov ax,[wordvar+1]
1164 \c mov ax,[es:wordvar+bx]
1166 Anything not conforming to this simple system is not a valid memory
1167 reference in NASM, for example \c{es:wordvar[bx]}.
1169 More complicated effective addresses, such as those involving more
1170 than one register, work in exactly the same way:
1172 \c mov eax,[ebx*2+ecx+offset]
1175 NASM is capable of doing \i{algebra} on these effective addresses,
1176 so that things which don't necessarily \e{look} legal are perfectly
1179 \c mov eax,[ebx*5] ; assembles as [ebx*4+ebx]
1180 \c mov eax,[label1*2-label2] ; ie [label1+(label1-label2)]
1182 Some forms of effective address have more than one assembled form;
1183 in most such cases NASM will generate the smallest form it can. For
1184 example, there are distinct assembled forms for the 32-bit effective
1185 addresses \c{[eax*2+0]} and \c{[eax+eax]}, and NASM will generally
1186 generate the latter on the grounds that the former requires four
1187 bytes to store a zero offset.
1189 NASM has a hinting mechanism which will cause \c{[eax+ebx]} and
1190 \c{[ebx+eax]} to generate different opcodes; this is occasionally
1191 useful because \c{[esi+ebp]} and \c{[ebp+esi]} have different
1192 default segment registers.
1194 However, you can force NASM to generate an effective address in a
1195 particular form by the use of the keywords \c{BYTE}, \c{WORD},
1196 \c{DWORD} and \c{NOSPLIT}. If you need \c{[eax+3]} to be assembled
1197 using a double-word offset field instead of the one byte NASM will
1198 normally generate, you can code \c{[dword eax+3]}. Similarly, you
1199 can force NASM to use a byte offset for a small value which it
1200 hasn't seen on the first pass (see \k{crit} for an example of such a
1201 code fragment) by using \c{[byte eax+offset]}. As special cases,
1202 \c{[byte eax]} will code \c{[eax+0]} with a byte offset of zero, and
1203 \c{[dword eax]} will code it with a double-word offset of zero. The
1204 normal form, \c{[eax]}, will be coded with no offset field.
1206 Similarly, NASM will split \c{[eax*2]} into \c{[eax+eax]} because
1207 that allows the offset field to be absent and space to be saved; in
1208 fact, it will also split \c{[eax*2+offset]} into
1209 \c{[eax+eax+offset]}. You can combat this behaviour by the use of
1210 the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force
1211 \c{[eax*2+0]} to be generated literally.
1214 \H{const} \i{Constants}
1216 NASM understands four different types of constant: numeric,
1217 character, string and floating-point.
1220 \S{numconst} \i{Numeric Constants}
1222 A numeric constant is simply a number. NASM allows you to specify
1223 numbers in a variety of number bases, in a variety of ways: you can
1224 suffix \c{H}, \c{Q} and \c{B} for \i{hex}, \i{octal} and \i{binary},
1225 or you can prefix \c{0x} for hex in the style of C, or you can
1226 prefix \c{$} for hex in the style of Borland Pascal. Note, though,
1227 that the \I{$prefix}\c{$} prefix does double duty as a prefix on
1228 identifiers (see \k{syntax}), so a hex number prefixed with a \c{$}
1229 sign must have a digit after the \c{$} rather than a letter.
1233 \c mov ax,100 ; decimal
1234 \c mov ax,0a2h ; hex
1235 \c mov ax,$0a2 ; hex again: the 0 is required
1236 \c mov ax,0xa2 ; hex yet again
1237 \c mov ax,777q ; octal
1238 \c mov ax,10010011b ; binary
1241 \S{chrconst} \i{Character Constants}
1243 A character constant consists of up to four characters enclosed in
1244 either single or double quotes. The type of quote makes no
1245 difference to NASM, except of course that surrounding the constant
1246 with single quotes allows double quotes to appear within it and vice
1249 A character constant with more than one character will be arranged
1250 with \i{little-endian} order in mind: if you code
1254 then the constant generated is not \c{0x61626364}, but
1255 \c{0x64636261}, so that if you were then to store the value into
1256 memory, it would read \c{abcd} rather than \c{dcba}. This is also
1257 the sense of character constants understood by the Pentium's
1258 \i\c{CPUID} instruction (see \k{insCPUID}).
1261 \S{strconst} String Constants
1263 String constants are only acceptable to some pseudo-instructions,
1264 namely the \I\c{DW}\I\c{DD}\I\c{DQ}\I\c{DT}\i\c{DB} family and
1267 A string constant looks like a character constant, only longer. It
1268 is treated as a concatenation of maximum-size character constants
1269 for the conditions. So the following are equivalent:
1271 \c db 'hello' ; string constant
1272 \c db 'h','e','l','l','o' ; equivalent character constants
1274 And the following are also equivalent:
1276 \c dd 'ninechars' ; doubleword string constant
1277 \c dd 'nine','char','s' ; becomes three doublewords
1278 \c db 'ninechars',0,0,0 ; and really looks like this
1280 Note that when used as an operand to \c{db}, a constant like
1281 \c{'ab'} is treated as a string constant despite being short enough
1282 to be a character constant, because otherwise \c{db 'ab'} would have
1283 the same effect as \c{db 'a'}, which would be silly. Similarly,
1284 three-character or four-character constants are treated as strings
1285 when they are operands to \c{dw}.
1288 \S{fltconst} \I{floating-point, constants}Floating-Point Constants
1290 \i{Floating-point} constants are acceptable only as arguments to
1291 \i\c{DD}, \i\c{DQ} and \i\c{DT}. They are expressed in the
1292 traditional form: digits, then a period, then optionally more
1293 digits, then optionally an \c{E} followed by an exponent. The period
1294 is mandatory, so that NASM can distinguish between \c{dd 1}, which
1295 declares an integer constant, and \c{dd 1.0} which declares a
1296 floating-point constant.
1300 \c dd 1.2 ; an easy one
1301 \c dq 1.e10 ; 10,000,000,000
1302 \c dq 1.e+10 ; synonymous with 1.e10
1303 \c dq 1.e-10 ; 0.000 000 000 1
1304 \c dt 3.141592653589793238462 ; pi
1306 NASM cannot do compile-time arithmetic on floating-point constants.
1307 This is because NASM is designed to be portable - although it always
1308 generates code to run on x86 processors, the assembler itself can
1309 run on any system with an ANSI C compiler. Therefore, the assembler
1310 cannot guarantee the presence of a floating-point unit capable of
1311 handling the \i{Intel number formats}, and so for NASM to be able to
1312 do floating arithmetic it would have to include its own complete set
1313 of floating-point routines, which would significantly increase the
1314 size of the assembler for very little benefit.
1317 \H{expr} \i{Expressions}
1319 Expressions in NASM are similar in syntax to those in C.
1321 NASM does not guarantee the size of the integers used to evaluate
1322 expressions at compile time: since NASM can compile and run on
1323 64-bit systems quite happily, don't assume that expressions are
1324 evaluated in 32-bit registers and so try to make deliberate use of
1325 \i{integer overflow}. It might not always work. The only thing NASM
1326 will guarantee is what's guaranteed by ANSI C: you always have \e{at
1327 least} 32 bits to work in.
1329 NASM supports two special tokens in expressions, allowing
1330 calculations to involve the current assembly position: the
1331 \I{$ here}\c{$} and \i\c{$$} tokens. \c{$} evaluates to the assembly
1332 position at the beginning of the line containing the expression; so
1333 you can code an \i{infinite loop} using \c{JMP $}. \c{$$} evaluates
1334 to the beginning of the current section; so you can tell how far
1335 into the section you are by using \c{($-$$)}.
1337 The arithmetic \i{operators} provided by NASM are listed here, in
1338 increasing order of \i{precedence}.
1341 \S{expor} \i\c{|}: \i{Bitwise OR} Operator
1343 The \c{|} operator gives a bitwise OR, exactly as performed by the
1344 \c{OR} machine instruction. Bitwise OR is the lowest-priority
1345 arithmetic operator supported by NASM.
1348 \S{expxor} \i\c{^}: \i{Bitwise XOR} Operator
1350 \c{^} provides the bitwise XOR operation.
1353 \S{expand} \i\c{&}: \i{Bitwise AND} Operator
1355 \c{&} provides the bitwise AND operation.
1358 \S{expshift} \i\c{<<} and \i\c{>>}: \i{Bit Shift} Operators
1360 \c{<<} gives a bit-shift to the left, just as it does in C. So \c{5<<3}
1361 evaluates to 5 times 8, or 40. \c{>>} gives a bit-shift to the
1362 right; in NASM, such a shift is \e{always} unsigned, so that
1363 the bits shifted in from the left-hand end are filled with zero
1364 rather than a sign-extension of the previous highest bit.
1367 \S{expplmi} \I{+ opaddition}\c{+} and \I{- opsubtraction}\c{-}:
1368 \i{Addition} and \i{Subtraction} Operators
1370 The \c{+} and \c{-} operators do perfectly ordinary addition and
1374 \S{expmul} \i\c{*}, \i\c{/}, \i\c{//}, \i\c{%} and \i\c{%%}:
1375 \i{Multiplication} and \i{Division}
1377 \c{*} is the multiplication operator. \c{/} and \c{//} are both
1378 division operators: \c{/} is \i{unsigned division} and \c{//} is
1379 \i{signed division}. Similarly, \c{%} and \c{%%} provide \I{unsigned
1380 modulo}\I{modulo operators}unsigned and
1381 \i{signed modulo} operators respectively.
1383 NASM, like ANSI C, provides no guarantees about the sensible
1384 operation of the signed modulo operator.
1386 Since the \c{%} character is used extensively by the macro
1387 \i{preprocessor}, you should ensure that both the signed and unsigned
1388 modulo operators are followed by white space wherever they appear.
1391 \S{expmul} \i{Unary Operators}: \I{+ opunary}\c{+}, \I{- opunary}\c{-},
1392 \i\c{~} and \i\c{SEG}
1394 The highest-priority operators in NASM's expression grammar are
1395 those which only apply to one argument. \c{-} negates its operand,
1396 \c{+} does nothing (it's provided for symmetry with \c{-}), \c{~}
1397 computes the \i{one's complement} of its operand, and \c{SEG}
1398 provides the \i{segment address} of its operand (explained in more
1399 detail in \k{segwrt}).
1402 \H{segwrt} \i\c{SEG} and \i\c{WRT}
1404 When writing large 16-bit programs, which must be split into
1405 multiple \i{segments}, it is often necessary to be able to refer to
1406 the \I{segment address}segment part of the address of a symbol. NASM
1407 supports the \c{SEG} operator to perform this function.
1409 The \c{SEG} operator returns the \i\e{preferred} segment base of a
1410 symbol, defined as the segment base relative to which the offset of
1411 the symbol makes sense. So the code
1413 \c mov ax,seg symbol
1417 will load \c{ES:BX} with a valid pointer to the symbol \c{symbol}.
1419 Things can be more complex than this: since 16-bit segments and
1420 \i{groups} may \I{overlapping segments}overlap, you might occasionally
1421 want to refer to some symbol using a different segment base from the
1422 preferred one. NASM lets you do this, by the use of the \c{WRT}
1423 (With Reference To) keyword. So you can do things like
1425 \c mov ax,weird_seg ; weird_seg is a segment base
1427 \c mov bx,symbol wrt weird_seg
1429 to load \c{ES:BX} with a different, but functionally equivalent,
1430 pointer to the symbol \c{symbol}.
1432 NASM supports far (inter-segment) calls and jumps by means of the
1433 syntax \c{call segment:offset}, where \c{segment} and \c{offset}
1434 both represent immediate values. So to call a far procedure, you
1435 could code either of
1437 \c call (seg procedure):procedure
1438 \c call weird_seg:(procedure wrt weird_seg)
1440 (The parentheses are included for clarity, to show the intended
1441 parsing of the above instructions. They are not necessary in
1444 NASM supports the syntax \I\c{CALL FAR}\c{call far procedure} as a
1445 synonym for the first of the above usages. \c{JMP} works identically
1446 to \c{CALL} in these examples.
1448 To declare a \i{far pointer} to a data item in a data segment, you
1451 \c dw symbol, seg symbol
1453 NASM supports no convenient synonym for this, though you can always
1454 invent one using the macro processor.
1457 \H{crit} \i{Critical Expressions}
1459 A limitation of NASM is that it is a \i{two-pass assembler}; unlike
1460 TASM and others, it will always do exactly two \I{passes}\i{assembly
1461 passes}. Therefore it is unable to cope with source files that are
1462 complex enough to require three or more passes.
1464 The first pass is used to determine the size of all the assembled
1465 code and data, so that the second pass, when generating all the
1466 code, knows all the symbol addresses the code refers to. So one
1467 thing NASM can't handle is code whose size depends on the value of a
1468 symbol declared after the code in question. For example,
1470 \c times (label-$) db 0
1471 \c label: db 'Where am I?'
1473 The argument to \i\c{TIMES} in this case could equally legally
1474 evaluate to anything at all; NASM will reject this example because
1475 it cannot tell the size of the \c{TIMES} line when it first sees it.
1476 It will just as firmly reject the slightly \I{paradox}paradoxical
1479 \c times (label-$+1) db 0
1480 \c label: db 'NOW where am I?'
1482 in which \e{any} value for the \c{TIMES} argument is by definition
1485 NASM rejects these examples by means of a concept called a
1486 \e{critical expression}, which is defined to be an expression whose
1487 value is required to be computable in the first pass, and which must
1488 therefore depend only on symbols defined before it. The argument to
1489 the \c{TIMES} prefix is a critical expression; for the same reason,
1490 the arguments to the \i\c{RESB} family of pseudo-instructions are
1491 also critical expressions.
1493 Critical expressions can crop up in other contexts as well: consider
1497 \c symbol1 equ symbol2
1500 On the first pass, NASM cannot determine the value of \c{symbol1},
1501 because \c{symbol1} is defined to be equal to \c{symbol2} which NASM
1502 hasn't seen yet. On the second pass, therefore, when it encounters
1503 the line \c{mov ax,symbol1}, it is unable to generate the code for
1504 it because it still doesn't know the value of \c{symbol1}. On the
1505 next line, it would see the \i\c{EQU} again and be able to determine
1506 the value of \c{symbol1}, but by then it would be too late.
1508 NASM avoids this problem by defining the right-hand side of an
1509 \c{EQU} statement to be a critical expression, so the definition of
1510 \c{symbol1} would be rejected in the first pass.
1512 There is a related issue involving \i{forward references}: consider
1515 \c mov eax,[ebx+offset]
1518 NASM, on pass one, must calculate the size of the instruction \c{mov
1519 eax,[ebx+offset]} without knowing the value of \c{offset}. It has no
1520 way of knowing that \c{offset} is small enough to fit into a
1521 one-byte offset field and that it could therefore get away with
1522 generating a shorter form of the \i{effective-address} encoding; for
1523 all it knows, in pass one, \c{offset} could be a symbol in the code
1524 segment, and it might need the full four-byte form. So it is forced
1525 to compute the size of the instruction to accommodate a four-byte
1526 address part. In pass two, having made this decision, it is now
1527 forced to honour it and keep the instruction large, so the code
1528 generated in this case is not as small as it could have been. This
1529 problem can be solved by defining \c{offset} before using it, or by
1530 forcing byte size in the effective address by coding \c{[byte
1534 \H{locallab} \i{Local Labels}
1536 NASM gives special treatment to symbols beginning with a \i{period}.
1537 A label beginning with a single period is treated as a \e{local}
1538 label, which means that it is associated with the previous non-local
1539 label. So, for example:
1541 \c label1 ; some code
1549 \c label2 ; some code
1557 In the above code fragment, each \c{JNE} instruction jumps to the
1558 line immediately before it, because the two definitions of \c{.loop}
1559 are kept separate by virtue of each being associated with the
1560 previous non-local label.
1562 This form of local label handling is borrowed from the old Amiga
1563 assembler \i{DevPac}; however, NASM goes one step further, in
1564 allowing access to local labels from other parts of the code. This
1565 is achieved by means of \e{defining} a local label in terms of the
1566 previous non-local label: the first definition of \c{.loop} above is
1567 really defining a symbol called \c{label1.loop}, and the second
1568 defines a symbol called \c{label2.loop}. So, if you really needed
1571 \c label3 ; some more code
1576 Sometimes it is useful - in a macro, for instance - to be able to
1577 define a label which can be referenced from anywhere but which
1578 doesn't interfere with the normal local-label mechanism. Such a
1579 label can't be non-local because it would interfere with subsequent
1580 definitions of, and references to, local labels; and it can't be
1581 local because the macro that defined it wouldn't know the label's
1582 full name. NASM therefore introduces a third type of label, which is
1583 probably only useful in macro definitions: if a label begins with
1584 the \I{label prefix}special prefix \i\c{..@}, then it does nothing
1585 to the local label mechanism. So you could code
1587 \c label1: ; a non-local label
1588 \c .local: ; this is really label1.local
1589 \c ..@foo: ; this is a special symbol
1590 \c label2: ; another non-local label
1591 \c .local: ; this is really label2.local
1593 \c jmp ..@foo ; this will jump three lines up
1595 NASM has the capacity to define other special symbols beginning with
1596 a double period: for example, \c{..start} is used to specify the
1597 entry point in the \c{obj} output format (see \k{dotdotstart}).
1600 \C{preproc} The NASM \i{Preprocessor}
1602 NASM contains a powerful \i{macro processor}, which supports
1603 conditional assembly, multi-level file inclusion, two forms of macro
1604 (single-line and multi-line), and a `context stack' mechanism for
1605 extra macro power. Preprocessor directives all begin with a \c{%}
1608 The preprocessor collapses all lines which end with a backslash (\\)
1609 character into a single line. Thus:
1611 \c %define THIS_VERY_LONG_MACRO_NAME_IS_DEFINED_TO \\
1614 will work as expected.
1616 \H{slmacro} \i{Single-Line Macros}
1618 \S{define} The Normal Way: \I\c{%idefine}\i\c{%define}
1620 Single-line macros are defined using the \c{%define} preprocessor
1621 directive. The definitions work in a similar way to C; so you can do
1624 \c %define ctrl 0x1F &
1625 \c %define param(a,b) ((a)+(a)*(b))
1627 \c mov byte [param(2,ebx)], ctrl 'D'
1629 which will expand to
1631 \c mov byte [(2)+(2)*(ebx)], 0x1F & 'D'
1633 When the expansion of a single-line macro contains tokens which
1634 invoke another macro, the expansion is performed at invocation time,
1635 not at definition time. Thus the code
1637 \c %define a(x) 1+b(x)
1642 will evaluate in the expected way to \c{mov ax,1+2*8}, even though
1643 the macro \c{b} wasn't defined at the time of definition of \c{a}.
1645 Macros defined with \c{%define} are \i{case sensitive}: after
1646 \c{%define foo bar}, only \c{foo} will expand to \c{bar}: \c{Foo} or
1647 \c{FOO} will not. By using \c{%idefine} instead of \c{%define} (the
1648 `i' stands for `insensitive') you can define all the case variants
1649 of a macro at once, so that \c{%idefine foo bar} would cause
1650 \c{foo}, \c{Foo}, \c{FOO}, \c{fOO} and so on all to expand to
1653 There is a mechanism which detects when a macro call has occurred as
1654 a result of a previous expansion of the same macro, to guard against
1655 \i{circular references} and infinite loops. If this happens, the
1656 preprocessor will only expand the first occurrence of the macro.
1659 \c %define a(x) 1+a(x)
1663 the macro \c{a(3)} will expand once, becoming \c{1+a(3)}, and will
1664 then expand no further. This behaviour can be useful: see \k{32c}
1665 for an example of its use.
1667 You can \I{overloading, single-line macros}overload single-line
1668 macros: if you write
1670 \c %define foo(x) 1+x
1671 \c %define foo(x,y) 1+x*y
1673 the preprocessor will be able to handle both types of macro call,
1674 by counting the parameters you pass; so \c{foo(3)} will become
1675 \c{1+3} whereas \c{foo(ebx,2)} will become \c{1+ebx*2}. However, if
1680 then no other definition of \c{foo} will be accepted: a macro with
1681 no parameters prohibits the definition of the same name as a macro
1682 \e{with} parameters, and vice versa.
1684 This doesn't prevent single-line macros being \e{redefined}: you can
1685 perfectly well define a macro with
1689 and then re-define it later in the same source file with
1693 Then everywhere the macro \c{foo} is invoked, it will be expanded
1694 according to the most recent definition. This is particularly useful
1695 when defining single-line macros with \c{%assign} (see \k{assign}).
1697 You can \i{pre-define} single-line macros using the `-d' option on
1698 the NASM command line: see \k{opt-d}.
1701 \S{concat%+} Concatenating Single Line Macro Tokens: \i\c{%+}
1703 Individual tokens in single line macros can be concatenated, to produce
1704 longer tokens for later processing. This can be useful if there are
1705 several similar macros that perform similar functions.
1707 As an example, consider the following:
1709 \c %define BDASTART 400h ; Start of BIOS data area
1711 \c struc tBIOSDA ; its structure
1717 Now, if we need to access the elements of tBIOSDA in different places,
1720 \c mov ax,BDASTART + tBIOSDA.COM1addr
1721 \c mov bx,BDASTART + tBIOSDA.COM2addr
1723 This will become pretty ugly (and tedious) if used in many places, and
1724 can be reduced in size significantly by using the following macro:
1726 \c ; Macro to access BIOS variables by their names (from tBDA):
1728 \c %define BDA(x) BDASTART + tBIOSDA. %+ x
1730 Now the above code can be written as:
1732 \c mov ax,BDA(COM1addr)
1733 \c mov bx,BDA(COM2addr)
1735 Using this feature, we can simplify references to a lot of macros (and,
1736 in turn, reduce typing errors).
1739 \S{undef} Undefining macros: \i\c{%undef}
1741 Single-line macros can be removed with the \c{%undef} command. For
1742 example, the following sequence:
1749 will expand to the instruction \c{mov eax, foo}, since after
1750 \c{%undef} the macro \c{foo} is no longer defined.
1752 Macros that would otherwise be pre-defined can be undefined on the
1753 command-line using the `-u' option on the NASM command line: see
1757 \S{assign} \i{Preprocessor Variables}: \i\c{%assign}
1759 An alternative way to define single-line macros is by means of the
1760 \c{%assign} command (and its \i{case sensitive}case-insensitive
1761 counterpart \i\c{%iassign}, which differs from \c{%assign} in
1762 exactly the same way that \c{%idefine} differs from \c{%define}).
1764 \c{%assign} is used to define single-line macros which take no
1765 parameters and have a numeric value. This value can be specified in
1766 the form of an expression, and it will be evaluated once, when the
1767 \c{%assign} directive is processed.
1769 Like \c{%define}, macros defined using \c{%assign} can be re-defined
1770 later, so you can do things like
1774 to increment the numeric value of a macro.
1776 \c{%assign} is useful for controlling the termination of \c{%rep}
1777 preprocessor loops: see \k{rep} for an example of this. Another
1778 use for \c{%assign} is given in \k{16c} and \k{32c}.
1780 The expression passed to \c{%assign} is a \i{critical expression}
1781 (see \k{crit}), and must also evaluate to a pure number (rather than
1782 a relocatable reference such as a code or data address, or anything
1783 involving a register).
1786 \H{strlen} \i{String Handling in Macros}: \i\c{%strlen} and \i\c{%substr}
1788 It's often useful to be able to handle strings in macros. NASM
1789 supports two simple string handling macro operators from which
1790 more complex operations can be constructed.
1793 \S{strlen} \i{String Length}: \i\c{%strlen}
1795 The \c{%strlen} macro is like \c{%assign} macro in that it creates
1796 (or redefines) a numeric value to a macro. The difference is that
1797 with \c{%strlen}, the numeric value is the length of a string. An
1798 example of the use of this would be:
1800 \c %strlen charcnt 'my string'
1802 In this example, \c{charcnt} would receive the value 8, just as
1803 if an \c{%assign} had been used. In this example, \c{'my string'}
1804 was a literal string but it could also have been a single-line
1805 macro that expands to a string, as in the following example:
1807 \c %define sometext 'my string'
1808 \c %strlen charcnt sometext
1810 As in the first case, this would result in \c{charcnt} being
1811 assigned the value of 8.
1814 \S{substr} \i{Sub-strings}: \i\c{%substr}
1816 Individual letters in strings can be extracted using \c{%substr}.
1817 An example of its use is probably more useful than the description:
1819 \c %substr mychar 'xyz' 1 ; equivalent to %define mychar 'x'
1820 \c %substr mychar 'xyz' 2 ; equivalent to %define mychar 'y'
1821 \c %substr mychar 'xyz' 3 ; equivalent to %define mychar 'z'
1823 In this example, mychar gets the value of 'y'. As with \c{%strlen}
1824 (see \k{strlen}), the first parameter is the single-line macro to
1825 be created and the second is the string. The third parameter
1826 specifies which character is to be selected. Note that the first
1827 index is 1, not 0 and the last index is equal to the value that
1828 \c{%strlen} would assign given the same string. Index values out
1829 of range result in an empty string.
1832 \H{mlmacro} \i{Multi-Line Macros}: \I\c{%imacro}\i\c{%macro}
1834 Multi-line macros are much more like the type of macro seen in MASM
1835 and TASM: a multi-line macro definition in NASM looks something like
1838 \c %macro prologue 1
1846 This defines a C-like function prologue as a macro: so you would
1847 invoke the macro with a call such as
1849 \c myfunc: prologue 12
1851 which would expand to the three lines of code
1857 The number \c{1} after the macro name in the \c{%macro} line defines
1858 the number of parameters the macro \c{prologue} expects to receive.
1859 The use of \c{%1} inside the macro definition refers to the first
1860 parameter to the macro call. With a macro taking more than one
1861 parameter, subsequent parameters would be referred to as \c{%2},
1864 Multi-line macros, like single-line macros, are \i{case-sensitive},
1865 unless you define them using the alternative directive \c{%imacro}.
1867 If you need to pass a comma as \e{part} of a parameter to a
1868 multi-line macro, you can do that by enclosing the entire parameter
1869 in \I{braces, around macro parameters}braces. So you could code
1878 \c silly 'a', letter_a ; letter_a: db 'a'
1879 \c silly 'ab', string_ab ; string_ab: db 'ab'
1880 \c silly {13,10}, crlf ; crlf: db 13,10
1883 \S{mlmacover} \i{Overloading Multi-Line Macros}
1885 As with single-line macros, multi-line macros can be overloaded by
1886 defining the same macro name several times with different numbers of
1887 parameters. This time, no exception is made for macros with no
1888 parameters at all. So you could define
1890 \c %macro prologue 0
1897 to define an alternative form of the function prologue which
1898 allocates no local stack space.
1900 Sometimes, however, you might want to `overload' a machine
1901 instruction; for example, you might want to define
1910 so that you could code
1912 \c push ebx ; this line is not a macro call
1913 \c push eax,ecx ; but this one is
1915 Ordinarily, NASM will give a warning for the first of the above two
1916 lines, since \c{push} is now defined to be a macro, and is being
1917 invoked with a number of parameters for which no definition has been
1918 given. The correct code will still be generated, but the assembler
1919 will give a warning. This warning can be disabled by the use of the
1920 \c{-w-macro-params} command-line option (see \k{opt-w}).
1923 \S{maclocal} \i{Macro-Local Labels}
1925 NASM allows you to define labels within a multi-line macro
1926 definition in such a way as to make them local to the macro call: so
1927 calling the same macro multiple times will use a different label
1928 each time. You do this by prefixing \i\c{%%} to the label name. So
1929 you can invent an instruction which executes a \c{RET} if the \c{Z}
1930 flag is set by doing this:
1940 You can call this macro as many times as you want, and every time
1941 you call it NASM will make up a different `real' name to substitute
1942 for the label \c{%%skip}. The names NASM invents are of the form
1943 \c{..@2345.skip}, where the number 2345 changes with every macro
1944 call. The \i\c{..@} prefix prevents macro-local labels from
1945 interfering with the local label mechanism, as described in
1946 \k{locallab}. You should avoid defining your own labels in this form
1947 (the \c{..@} prefix, then a number, then another period) in case
1948 they interfere with macro-local labels.
1951 \S{mlmacgre} \i{Greedy Macro Parameters}
1953 Occasionally it is useful to define a macro which lumps its entire
1954 command line into one parameter definition, possibly after
1955 extracting one or two smaller parameters from the front. An example
1956 might be a macro to write a text string to a file in MS-DOS, where
1957 you might want to be able to write
1959 \c writefile [filehandle],"hello, world",13,10
1961 NASM allows you to define the last parameter of a macro to be
1962 \e{greedy}, meaning that if you invoke the macro with more
1963 parameters than it expects, all the spare parameters get lumped into
1964 the last defined one along with the separating commas. So if you
1967 \c %macro writefile 2+
1973 \c mov cx,%%endstr-%%str
1980 then the example call to \c{writefile} above will work as expected:
1981 the text before the first comma, \c{[filehandle]}, is used as the
1982 first macro parameter and expanded when \c{%1} is referred to, and
1983 all the subsequent text is lumped into \c{%2} and placed after the
1986 The greedy nature of the macro is indicated to NASM by the use of
1987 the \I{+ modifier}\c{+} sign after the parameter count on the
1990 If you define a greedy macro, you are effectively telling NASM how
1991 it should expand the macro given \e{any} number of parameters from
1992 the actual number specified up to infinity; in this case, for
1993 example, NASM now knows what to do when it sees a call to
1994 \c{writefile} with 2, 3, 4 or more parameters. NASM will take this
1995 into account when overloading macros, and will not allow you to
1996 define another form of \c{writefile} taking 4 parameters (for
1999 Of course, the above macro could have been implemented as a
2000 non-greedy macro, in which case the call to it would have had to
2003 \c writefile [filehandle], {"hello, world",13,10}
2005 NASM provides both mechanisms for putting \i{commas in macro
2006 parameters}, and you choose which one you prefer for each macro
2009 See \k{sectmac} for a better way to write the above macro.
2012 \S{mlmacdef} \i{Default Macro Parameters}
2014 NASM also allows you to define a multi-line macro with a \e{range}
2015 of allowable parameter counts. If you do this, you can specify
2016 defaults for \i{omitted parameters}. So, for example:
2018 \c %macro die 0-1 "Painful program death has occurred."
2026 This macro (which makes use of the \c{writefile} macro defined in
2027 \k{mlmacgre}) can be called with an explicit error message, which it
2028 will display on the error output stream before exiting, or it can be
2029 called with no parameters, in which case it will use the default
2030 error message supplied in the macro definition.
2032 In general, you supply a minimum and maximum number of parameters
2033 for a macro of this type; the minimum number of parameters are then
2034 required in the macro call, and then you provide defaults for the
2035 optional ones. So if a macro definition began with the line
2037 \c %macro foobar 1-3 eax,[ebx+2]
2039 then it could be called with between one and three parameters, and
2040 \c{%1} would always be taken from the macro call. \c{%2}, if not
2041 specified by the macro call, would default to \c{eax}, and \c{%3} if
2042 not specified would default to \c{[ebx+2]}.
2044 You may omit parameter defaults from the macro definition, in which
2045 case the parameter default is taken to be blank. This can be useful
2046 for macros which can take a variable number of parameters, since the
2047 \i\c{%0} token (see \k{percent0}) allows you to determine how many
2048 parameters were really passed to the macro call.
2050 This defaulting mechanism can be combined with the greedy-parameter
2051 mechanism; so the \c{die} macro above could be made more powerful,
2052 and more useful, by changing the first line of the definition to
2054 \c %macro die 0-1+ "Painful program death has occurred.",13,10
2056 The maximum parameter count can be infinite, denoted by \c{*}. In
2057 this case, of course, it is impossible to provide a \e{full} set of
2058 default parameters. Examples of this usage are shown in \k{rotate}.
2061 \S{percent0} \i\c{%0}: \I{counting macro parameters}Macro Parameter Counter
2063 For a macro which can take a variable number of parameters, the
2064 parameter reference \c{%0} will return a numeric constant giving the
2065 number of parameters passed to the macro. This can be used as an
2066 argument to \c{%rep} (see \k{rep}) in order to iterate through all
2067 the parameters of a macro. Examples are given in \k{rotate}.
2070 \S{rotate} \i\c{%rotate}: \i{Rotating Macro Parameters}
2072 Unix shell programmers will be familiar with the \I{shift
2073 command}\c{shift} shell command, which allows the arguments passed
2074 to a shell script (referenced as \c{$1}, \c{$2} and so on) to be
2075 moved left by one place, so that the argument previously referenced
2076 as \c{$2} becomes available as \c{$1}, and the argument previously
2077 referenced as \c{$1} is no longer available at all.
2079 NASM provides a similar mechanism, in the form of \c{%rotate}. As
2080 its name suggests, it differs from the Unix \c{shift} in that no
2081 parameters are lost: parameters rotated off the left end of the
2082 argument list reappear on the right, and vice versa.
2084 \c{%rotate} is invoked with a single numeric argument (which may be
2085 an expression). The macro parameters are rotated to the left by that
2086 many places. If the argument to \c{%rotate} is negative, the macro
2087 parameters are rotated to the right.
2089 \I{iterating over macro parameters}So a pair of macros to save and
2090 restore a set of registers might work as follows:
2092 \c %macro multipush 1-*
2101 This macro invokes the \c{PUSH} instruction on each of its arguments
2102 in turn, from left to right. It begins by pushing its first
2103 argument, \c{%1}, then invokes \c{%rotate} to move all the arguments
2104 one place to the left, so that the original second argument is now
2105 available as \c{%1}. Repeating this procedure as many times as there
2106 were arguments (achieved by supplying \c{%0} as the argument to
2107 \c{%rep}) causes each argument in turn to be pushed.
2109 Note also the use of \c{*} as the maximum parameter count,
2110 indicating that there is no upper limit on the number of parameters
2111 you may supply to the \i\c{multipush} macro.
2113 It would be convenient, when using this macro, to have a \c{POP}
2114 equivalent, which \e{didn't} require the arguments to be given in
2115 reverse order. Ideally, you would write the \c{multipush} macro
2116 call, then cut-and-paste the line to where the pop needed to be
2117 done, and change the name of the called macro to \c{multipop}, and
2118 the macro would take care of popping the registers in the opposite
2119 order from the one in which they were pushed.
2121 This can be done by the following definition:
2123 \c %macro multipop 1-*
2132 This macro begins by rotating its arguments one place to the
2133 \e{right}, so that the original \e{last} argument appears as \c{%1}.
2134 This is then popped, and the arguments are rotated right again, so
2135 the second-to-last argument becomes \c{%1}. Thus the arguments are
2136 iterated through in reverse order.
2139 \S{concat} \i{Concatenating Macro Parameters}
2141 NASM can concatenate macro parameters on to other text surrounding
2142 them. This allows you to declare a family of symbols, for example,
2143 in a macro definition. If, for example, you wanted to generate a
2144 table of key codes along with offsets into the table, you could code
2147 \c %macro keytab_entry 2
2149 \c keypos%1 equ $-keytab
2155 \c keytab_entry F1,128+1
2156 \c keytab_entry F2,128+2
2157 \c keytab_entry Return,13
2159 which would expand to
2162 \c keyposF1 equ $-keytab
2164 \c keyposF2 equ $-keytab
2166 \c keyposReturn equ $-keytab
2169 You can just as easily concatenate text on to the other end of a
2170 macro parameter, by writing \c{%1foo}.
2172 If you need to append a \e{digit} to a macro parameter, for example
2173 defining labels \c{foo1} and \c{foo2} when passed the parameter
2174 \c{foo}, you can't code \c{%11} because that would be taken as the
2175 eleventh macro parameter. Instead, you must code
2176 \I{braces, after % sign}\c{%\{1\}1}, which will separate the first
2177 \c{1} (giving the number of the macro parameter) from the second
2178 (literal text to be concatenated to the parameter).
2180 This concatenation can also be applied to other preprocessor in-line
2181 objects, such as macro-local labels (\k{maclocal}) and context-local
2182 labels (\k{ctxlocal}). In all cases, ambiguities in syntax can be
2183 resolved by enclosing everything after the \c{%} sign and before the
2184 literal text in braces: so \c{%\{%foo\}bar} concatenates the text
2185 \c{bar} to the end of the real name of the macro-local label
2186 \c{%%foo}. (This is unnecessary, since the form NASM uses for the
2187 real names of macro-local labels means that the two usages
2188 \c{%\{%foo\}bar} and \c{%%foobar} would both expand to the same
2189 thing anyway; nevertheless, the capability is there.)
2192 \S{mlmaccc} \i{Condition Codes as Macro Parameters}
2194 NASM can give special treatment to a macro parameter which contains
2195 a condition code. For a start, you can refer to the macro parameter
2196 \c{%1} by means of the alternative syntax \i\c{%+1}, which informs
2197 NASM that this macro parameter is supposed to contain a condition
2198 code, and will cause the preprocessor to report an error message if
2199 the macro is called with a parameter which is \e{not} a valid
2202 Far more usefully, though, you can refer to the macro parameter by
2203 means of \i\c{%-1}, which NASM will expand as the \e{inverse}
2204 condition code. So the \c{retz} macro defined in \k{maclocal} can be
2205 replaced by a general \i{conditional-return macro} like this:
2215 This macro can now be invoked using calls like \c{retc ne}, which
2216 will cause the conditional-jump instruction in the macro expansion
2217 to come out as \c{JE}, or \c{retc po} which will make the jump a
2220 The \c{%+1} macro-parameter reference is quite happy to interpret
2221 the arguments \c{CXZ} and \c{ECXZ} as valid condition codes;
2222 however, \c{%-1} will report an error if passed either of these,
2223 because no inverse condition code exists.
2226 \S{nolist} \i{Disabling Listing Expansion}\I\c{.nolist}
2228 When NASM is generating a listing file from your program, it will
2229 generally expand multi-line macros by means of writing the macro
2230 call and then listing each line of the expansion. This allows you to
2231 see which instructions in the macro expansion are generating what
2232 code; however, for some macros this clutters the listing up
2235 NASM therefore provides the \c{.nolist} qualifier, which you can
2236 include in a macro definition to inhibit the expansion of the macro
2237 in the listing file. The \c{.nolist} qualifier comes directly after
2238 the number of parameters, like this:
2240 \c %macro foo 1.nolist
2244 \c %macro bar 1-5+.nolist a,b,c,d,e,f,g,h
2246 \H{condasm} \i{Conditional Assembly}\I\c{%if}
2248 Similarly to the C preprocessor, NASM allows sections of a source
2249 file to be assembled only if certain conditions are met. The general
2250 syntax of this feature looks like this:
2253 \c ; some code which only appears if <condition> is met
2254 \c %elif<condition2>
2255 \c ; only appears if <condition> is not met but <condition2> is
2257 \c ; this appears if neither <condition> nor <condition2> was met
2260 The \i\c{%else} clause is optional, as is the \i\c{%elif} clause.
2261 You can have more than one \c{%elif} clause as well.
2264 \S{ifdef} \i\c{%ifdef}: \i{Testing Single-Line Macro Existence}
2266 Beginning a conditional-assembly block with the line \c{%ifdef
2267 MACRO} will assemble the subsequent code if, and only if, a
2268 single-line macro called \c{MACRO} is defined. If not, then the
2269 \c{%elif} and \c{%else} blocks (if any) will be processed instead.
2271 For example, when debugging a program, you might want to write code
2274 \c ; perform some function
2276 \c writefile 2,"Function performed successfully",13,10
2278 \c ; go and do something else
2280 Then you could use the command-line option \c{-dDEBUG} to create a
2281 version of the program which produced debugging messages, and remove
2282 the option to generate the final release version of the program.
2284 You can test for a macro \e{not} being defined by using
2285 \i\c{%ifndef} instead of \c{%ifdef}. You can also test for macro
2286 definitions in \c{%elif} blocks by using \i\c{%elifdef} and
2290 \S{ifmacro} \i\c{ifmacro}: \i{Testing Multi-Line Macro Existence}
2292 The \c{%ifmacro} directive operates in the same way as the \c{%ifdef}
2293 directive, except that it checks for the existence of a multi-line macro.
2295 For example, you may be working with a large project and not have control
2296 over the macros in a library. You may want to create a macro with one
2297 name if it doesn't already exist, and another name if one with that name
2300 The %ifmacro is considered true if defining a macro with the given name
2301 and number of arguments would cause a definitions conflict. For example:
2303 \c %ifmacro MyMacro 1-3
2305 \c %error "MyMacro 1-3" causes a conflict with an existing macro.
2309 \c %macro MyMacro 1-3
2311 \c ; insert code to define the macro
2317 This will create the macro "MyMacro 1-3" if no macro already exists which
2318 would conflict with it, and emits a warning if there would be a definition
2321 You can test for the macro not existing by using the \i\c{ifnmacro} instead
2322 of \c{ifmacro}. Additional tests can be performed in %elif blocks by using
2323 \i\c{elifmacro} and \i\c{elifnmacro}.
2326 \S{ifctx} \i\c{%ifctx}: \i{Testing the Context Stack}
2328 The conditional-assembly construct \c{%ifctx ctxname} will cause the
2329 subsequent code to be assembled if and only if the top context on
2330 the preprocessor's context stack has the name \c{ctxname}. As with
2331 \c{%ifdef}, the inverse and \c{%elif} forms \i\c{%ifnctx},
2332 \i\c{%elifctx} and \i\c{%elifnctx} are also supported.
2334 For more details of the context stack, see \k{ctxstack}. For a
2335 sample use of \c{%ifctx}, see \k{blockif}.
2338 \S{if} \i\c{%if}: \i{Testing Arbitrary Numeric Expressions}
2340 The conditional-assembly construct \c{%if expr} will cause the
2341 subsequent code to be assembled if and only if the value of the
2342 numeric expression \c{expr} is non-zero. An example of the use of
2343 this feature is in deciding when to break out of a \c{%rep}
2344 preprocessor loop: see \k{rep} for a detailed example.
2346 The expression given to \c{%if}, and its counterpart \i\c{%elif}, is
2347 a critical expression (see \k{crit}).
2349 \c{%if} extends the normal NASM expression syntax, by providing a
2350 set of \i{relational operators} which are not normally available in
2351 expressions. The operators \i\c{=}, \i\c{<}, \i\c{>}, \i\c{<=},
2352 \i\c{>=} and \i\c{<>} test equality, less-than, greater-than,
2353 less-or-equal, greater-or-equal and not-equal respectively. The
2354 C-like forms \i\c{==} and \i\c{!=} are supported as alternative
2355 forms of \c{=} and \c{<>}. In addition, low-priority logical
2356 operators \i\c{&&}, \i\c{^^} and \i\c{||} are provided, supplying
2357 \i{logical AND}, \i{logical XOR} and \i{logical OR}. These work like
2358 the C logical operators (although C has no logical XOR), in that
2359 they always return either 0 or 1, and treat any non-zero input as 1
2360 (so that \c{^^}, for example, returns 1 if exactly one of its inputs
2361 is zero, and 0 otherwise). The relational operators also return 1
2362 for true and 0 for false.
2365 \S{ifidn} \i\c{%ifidn} and \i\c{%ifidni}: \i{Testing Exact Text
2368 The construct \c{%ifidn text1,text2} will cause the subsequent code
2369 to be assembled if and only if \c{text1} and \c{text2}, after
2370 expanding single-line macros, are identical pieces of text.
2371 Differences in white space are not counted.
2373 \c{%ifidni} is similar to \c{%ifidn}, but is \i{case-insensitive}.
2375 For example, the following macro pushes a register or number on the
2376 stack, and allows you to treat \c{IP} as a real register:
2378 \c %macro pushparam 1
2389 Like most other \c{%if} constructs, \c{%ifidn} has a counterpart
2390 \i\c{%elifidn}, and negative forms \i\c{%ifnidn} and \i\c{%elifnidn}.
2391 Similarly, \c{%ifidni} has counterparts \i\c{%elifidni},
2392 \i\c{%ifnidni} and \i\c{%elifnidni}.
2395 \S{iftyp} \i\c{%ifid}, \i\c{%ifnum}, \i\c{%ifstr}: \i{Testing Token
2398 Some macros will want to perform different tasks depending on
2399 whether they are passed a number, a string, or an identifier. For
2400 example, a string output macro might want to be able to cope with
2401 being passed either a string constant or a pointer to an existing
2404 The conditional assembly construct \c{%ifid}, taking one parameter
2405 (which may be blank), assembles the subsequent code if and only if
2406 the first token in the parameter exists and is an identifier.
2407 \c{%ifnum} works similarly, but tests for the token being a numeric
2408 constant; \c{%ifstr} tests for it being a string.
2410 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
2411 extended to take advantage of \c{%ifstr} in the following fashion:
2413 \c %macro writefile 2-3+
2422 \c %%endstr: mov dx,%%str
2423 \c mov cx,%%endstr-%%str
2434 Then the \c{writefile} macro can cope with being called in either of
2435 the following two ways:
2437 \c writefile [file], strpointer, length
2438 \c writefile [file], "hello", 13, 10
2440 In the first, \c{strpointer} is used as the address of an
2441 already-declared string, and \c{length} is used as its length; in
2442 the second, a string is given to the macro, which therefore declares
2443 it itself and works out the address and length for itself.
2445 Note the use of \c{%if} inside the \c{%ifstr}: this is to detect
2446 whether the macro was passed two arguments (so the string would be a
2447 single string constant, and \c{db %2} would be adequate) or more (in
2448 which case, all but the first two would be lumped together into
2449 \c{%3}, and \c{db %2,%3} would be required).
2451 \I\c{%ifnid}\I\c{%elifid}\I\c{%elifnid}\I\c{%ifnnum}\I\c{%elifnum}
2452 \I\c{%elifnnum}\I\c{%ifnstr}\I\c{%elifstr}\I\c{%elifnstr}
2453 The usual \c{%elifXXX}, \c{%ifnXXX} and \c{%elifnXXX} versions exist
2454 for each of \c{%ifid}, \c{%ifnum} and \c{%ifstr}.
2457 \S{pperror} \i\c{%error}: Reporting \i{User-Defined Errors}
2459 The preprocessor directive \c{%error} will cause NASM to report an
2460 error if it occurs in assembled code. So if other users are going to
2461 try to assemble your source files, you can ensure that they define
2462 the right macros by means of code like this:
2464 \c %ifdef SOME_MACRO
2466 \c %elifdef SOME_OTHER_MACRO
2467 \c ; do some different setup
2469 \c %error Neither SOME_MACRO nor SOME_OTHER_MACRO was defined.
2472 Then any user who fails to understand the way your code is supposed
2473 to be assembled will be quickly warned of their mistake, rather than
2474 having to wait until the program crashes on being run and then not
2475 knowing what went wrong.
2478 \H{rep} \i{Preprocessor Loops}\I{repeating code}: \i\c{%rep}
2480 NASM's \c{TIMES} prefix, though useful, cannot be used to invoke a
2481 multi-line macro multiple times, because it is processed by NASM
2482 after macros have already been expanded. Therefore NASM provides
2483 another form of loop, this time at the preprocessor level: \c{%rep}.
2485 The directives \c{%rep} and \i\c{%endrep} (\c{%rep} takes a numeric
2486 argument, which can be an expression; \c{%endrep} takes no
2487 arguments) can be used to enclose a chunk of code, which is then
2488 replicated as many times as specified by the preprocessor:
2492 \c inc word [table+2*i]
2496 This will generate a sequence of 64 \c{INC} instructions,
2497 incrementing every word of memory from \c{[table]} to
2500 For more complex termination conditions, or to break out of a repeat
2501 loop part way along, you can use the \i\c{%exitrep} directive to
2502 terminate the loop, like this:
2517 \c fib_number equ ($-fibonacci)/2
2519 This produces a list of all the Fibonacci numbers that will fit in
2520 16 bits. Note that a maximum repeat count must still be given to
2521 \c{%rep}. This is to prevent the possibility of NASM getting into an
2522 infinite loop in the preprocessor, which (on multitasking or
2523 multi-user systems) would typically cause all the system memory to
2524 be gradually used up and other applications to start crashing.
2527 \H{include} \i{Including Other Files}
2529 Using, once again, a very similar syntax to the C preprocessor,
2530 NASM's preprocessor lets you include other source files into your
2531 code. This is done by the use of the \i\c{%include} directive:
2533 \c %include "macros.mac"
2535 will include the contents of the file \c{macros.mac} into the source
2536 file containing the \c{%include} directive.
2538 Include files are \I{searching for include files}searched for in the
2539 current directory (the directory you're in when you run NASM, as
2540 opposed to the location of the NASM executable or the location of
2541 the source file), plus any directories specified on the NASM command
2542 line using the \c{-i} option.
2544 The standard C idiom for preventing a file being included more than
2545 once is just as applicable in NASM: if the file \c{macros.mac} has
2548 \c %ifndef MACROS_MAC
2549 \c %define MACROS_MAC
2550 \c ; now define some macros
2553 then including the file more than once will not cause errors,
2554 because the second time the file is included nothing will happen
2555 because the macro \c{MACROS_MAC} will already be defined.
2557 You can force a file to be included even if there is no \c{%include}
2558 directive that explicitly includes it, by using the \i\c{-p} option
2559 on the NASM command line (see \k{opt-p}).
2562 \H{ctxstack} The \i{Context Stack}
2564 Having labels that are local to a macro definition is sometimes not
2565 quite powerful enough: sometimes you want to be able to share labels
2566 between several macro calls. An example might be a \c{REPEAT} ...
2567 \c{UNTIL} loop, in which the expansion of the \c{REPEAT} macro
2568 would need to be able to refer to a label which the \c{UNTIL} macro
2569 had defined. However, for such a macro you would also want to be
2570 able to nest these loops.
2572 NASM provides this level of power by means of a \e{context stack}.
2573 The preprocessor maintains a stack of \e{contexts}, each of which is
2574 characterised by a name. You add a new context to the stack using
2575 the \i\c{%push} directive, and remove one using \i\c{%pop}. You can
2576 define labels that are local to a particular context on the stack.
2579 \S{pushpop} \i\c{%push} and \i\c{%pop}: \I{creating
2580 contexts}\I{removing contexts}Creating and Removing Contexts
2582 The \c{%push} directive is used to create a new context and place it
2583 on the top of the context stack. \c{%push} requires one argument,
2584 which is the name of the context. For example:
2588 This pushes a new context called \c{foobar} on the stack. You can
2589 have several contexts on the stack with the same name: they can
2590 still be distinguished.
2592 The directive \c{%pop}, requiring no arguments, removes the top
2593 context from the context stack and destroys it, along with any
2594 labels associated with it.
2597 \S{ctxlocal} \i{Context-Local Labels}
2599 Just as the usage \c{%%foo} defines a label which is local to the
2600 particular macro call in which it is used, the usage \I{%$}\c{%$foo}
2601 is used to define a label which is local to the context on the top
2602 of the context stack. So the \c{REPEAT} and \c{UNTIL} example given
2603 above could be implemented by means of:
2619 and invoked by means of, for example,
2627 which would scan every fourth byte of a string in search of the byte
2630 If you need to define, or access, labels local to the context
2631 \e{below} the top one on the stack, you can use \I{%$$}\c{%$$foo}, or
2632 \c{%$$$foo} for the context below that, and so on.
2635 \S{ctxdefine} \i{Context-Local Single-Line Macros}
2637 NASM also allows you to define single-line macros which are local to
2638 a particular context, in just the same way:
2640 \c %define %$localmac 3
2642 will define the single-line macro \c{%$localmac} to be local to the
2643 top context on the stack. Of course, after a subsequent \c{%push},
2644 it can then still be accessed by the name \c{%$$localmac}.
2647 \S{ctxrepl} \i\c{%repl}: \I{renaming contexts}Renaming a Context
2649 If you need to change the name of the top context on the stack (in
2650 order, for example, to have it respond differently to \c{%ifctx}),
2651 you can execute a \c{%pop} followed by a \c{%push}; but this will
2652 have the side effect of destroying all context-local labels and
2653 macros associated with the context that was just popped.
2655 NASM provides the directive \c{%repl}, which \e{replaces} a context
2656 with a different name, without touching the associated macros and
2657 labels. So you could replace the destructive code
2662 with the non-destructive version \c{%repl newname}.
2665 \S{blockif} Example Use of the \i{Context Stack}: \i{Block IFs}
2667 This example makes use of almost all the context-stack features,
2668 including the conditional-assembly construct \i\c{%ifctx}, to
2669 implement a block IF statement as a set of macros.
2685 \c %error "expected `if' before `else'"
2699 \c %error "expected `if' or `else' before `endif'"
2704 This code is more robust than the \c{REPEAT} and \c{UNTIL} macros
2705 given in \k{ctxlocal}, because it uses conditional assembly to check
2706 that the macros are issued in the right order (for example, not
2707 calling \c{endif} before \c{if}) and issues a \c{%error} if they're
2710 In addition, the \c{endif} macro has to be able to cope with the two
2711 distinct cases of either directly following an \c{if}, or following
2712 an \c{else}. It achieves this, again, by using conditional assembly
2713 to do different things depending on whether the context on top of
2714 the stack is \c{if} or \c{else}.
2716 The \c{else} macro has to preserve the context on the stack, in
2717 order to have the \c{%$ifnot} referred to by the \c{if} macro be the
2718 same as the one defined by the \c{endif} macro, but has to change
2719 the context's name so that \c{endif} will know there was an
2720 intervening \c{else}. It does this by the use of \c{%repl}.
2722 A sample usage of these macros might look like:
2744 The block-\c{IF} macros handle nesting quite happily, by means of
2745 pushing another context, describing the inner \c{if}, on top of the
2746 one describing the outer \c{if}; thus \c{else} and \c{endif} always
2747 refer to the last unmatched \c{if} or \c{else}.
2750 \H{stdmac} \i{Standard Macros}
2752 NASM defines a set of standard macros, which are already defined
2753 when it starts to process any source file. If you really need a
2754 program to be assembled with no pre-defined macros, you can use the
2755 \i\c{%clear} directive to empty the preprocessor of everything.
2757 Most \i{user-level assembler directives} (see \k{directive}) are
2758 implemented as macros which invoke primitive directives; these are
2759 described in \k{directive}. The rest of the standard macro set is
2763 \S{stdmacver} \i\c{__NASM_MAJOR__} and \i\c{__NASM_MINOR__}: \i{NASM
2766 The single-line macros \c{__NASM_MAJOR__} and \c{__NASM_MINOR__}
2767 expand to the major and minor parts of the \i{version number of
2768 NASM} being used. So, under NASM 0.96 for example,
2769 \c{__NASM_MAJOR__} would be defined to be 0 and \c{__NASM_MINOR__}
2770 would be defined as 96.
2773 \S{fileline} \i\c{__FILE__} and \i\c{__LINE__}: File Name and Line Number
2775 Like the C preprocessor, NASM allows the user to find out the file
2776 name and line number containing the current instruction. The macro
2777 \c{__FILE__} expands to a string constant giving the name of the
2778 current input file (which may change through the course of assembly
2779 if \c{%include} directives are used), and \c{__LINE__} expands to a
2780 numeric constant giving the current line number in the input file.
2782 These macros could be used, for example, to communicate debugging
2783 information to a macro, since invoking \c{__LINE__} inside a macro
2784 definition (either single-line or multi-line) will return the line
2785 number of the macro \e{call}, rather than \e{definition}. So to
2786 determine where in a piece of code a crash is occurring, for
2787 example, one could write a routine \c{stillhere}, which is passed a
2788 line number in \c{EAX} and outputs something like `line 155: still
2789 here'. You could then write a macro
2791 \c %macro notdeadyet 0
2800 and then pepper your code with calls to \c{notdeadyet} until you
2801 find the crash point.
2804 \S{struc} \i\c{STRUC} and \i\c{ENDSTRUC}: \i{Declaring Structure} Data Types
2806 The core of NASM contains no intrinsic means of defining data
2807 structures; instead, the preprocessor is sufficiently powerful that
2808 data structures can be implemented as a set of macros. The macros
2809 \c{STRUC} and \c{ENDSTRUC} are used to define a structure data type.
2811 \c{STRUC} takes one parameter, which is the name of the data type.
2812 This name is defined as a symbol with the value zero, and also has
2813 the suffix \c{_size} appended to it and is then defined as an
2814 \c{EQU} giving the size of the structure. Once \c{STRUC} has been
2815 issued, you are defining the structure, and should define fields
2816 using the \c{RESB} family of pseudo-instructions, and then invoke
2817 \c{ENDSTRUC} to finish the definition.
2819 For example, to define a structure called \c{mytype} containing a
2820 longword, a word, a byte and a string of bytes, you might code
2831 The above code defines six symbols: \c{mt_long} as 0 (the offset
2832 from the beginning of a \c{mytype} structure to the longword field),
2833 \c{mt_word} as 4, \c{mt_byte} as 6, \c{mt_str} as 7, \c{mytype_size}
2834 as 39, and \c{mytype} itself as zero.
2836 The reason why the structure type name is defined at zero is a side
2837 effect of allowing structures to work with the local label
2838 mechanism: if your structure members tend to have the same names in
2839 more than one structure, you can define the above structure like this:
2850 This defines the offsets to the structure fields as \c{mytype.long},
2851 \c{mytype.word}, \c{mytype.byte} and \c{mytype.str}.
2853 NASM, since it has no \e{intrinsic} structure support, does not
2854 support any form of period notation to refer to the elements of a
2855 structure once you have one (except the above local-label notation),
2856 so code such as \c{mov ax,[mystruc.mt_word]} is not valid.
2857 \c{mt_word} is a constant just like any other constant, so the
2858 correct syntax is \c{mov ax,[mystruc+mt_word]} or \c{mov
2859 ax,[mystruc+mytype.word]}.
2862 \S{istruc} \i\c{ISTRUC}, \i\c{AT} and \i\c{IEND}: Declaring
2863 \i{Instances of Structures}
2865 Having defined a structure type, the next thing you typically want
2866 to do is to declare instances of that structure in your data
2867 segment. NASM provides an easy way to do this in the \c{ISTRUC}
2868 mechanism. To declare a structure of type \c{mytype} in a program,
2869 you code something like this:
2874 \c at mt_long, dd 123456
2875 \c at mt_word, dw 1024
2876 \c at mt_byte, db 'x'
2877 \c at mt_str, db 'hello, world', 13, 10, 0
2881 The function of the \c{AT} macro is to make use of the \c{TIMES}
2882 prefix to advance the assembly position to the correct point for the
2883 specified structure field, and then to declare the specified data.
2884 Therefore the structure fields must be declared in the same order as
2885 they were specified in the structure definition.
2887 If the data to go in a structure field requires more than one source
2888 line to specify, the remaining source lines can easily come after
2889 the \c{AT} line. For example:
2891 \c at mt_str, db 123,134,145,156,167,178,189
2894 Depending on personal taste, you can also omit the code part of the
2895 \c{AT} line completely, and start the structure field on the next
2899 \c db 'hello, world'
2903 \S{align} \i\c{ALIGN} and \i\c{ALIGNB}: Data Alignment
2905 The \c{ALIGN} and \c{ALIGNB} macros provides a convenient way to
2906 align code or data on a word, longword, paragraph or other boundary.
2907 (Some assemblers call this directive \i\c{EVEN}.) The syntax of the
2908 \c{ALIGN} and \c{ALIGNB} macros is
2910 \c align 4 ; align on 4-byte boundary
2911 \c align 16 ; align on 16-byte boundary
2912 \c align 8,db 0 ; pad with 0s rather than NOPs
2913 \c align 4,resb 1 ; align to 4 in the BSS
2914 \c alignb 4 ; equivalent to previous line
2916 Both macros require their first argument to be a power of two; they
2917 both compute the number of additional bytes required to bring the
2918 length of the current section up to a multiple of that power of two,
2919 and then apply the \c{TIMES} prefix to their second argument to
2920 perform the alignment.
2922 If the second argument is not specified, the default for \c{ALIGN}
2923 is \c{NOP}, and the default for \c{ALIGNB} is \c{RESB 1}. So if the
2924 second argument is specified, the two macros are equivalent.
2925 Normally, you can just use \c{ALIGN} in code and data sections and
2926 \c{ALIGNB} in BSS sections, and never need the second argument
2927 except for special purposes.
2929 \c{ALIGN} and \c{ALIGNB}, being simple macros, perform no error
2930 checking: they cannot warn you if their first argument fails to be a
2931 power of two, or if their second argument generates more than one
2932 byte of code. In each of these cases they will silently do the wrong
2935 \c{ALIGNB} (or \c{ALIGN} with a second argument of \c{RESB 1}) can
2936 be used within structure definitions:
2953 This will ensure that the structure members are sensibly aligned
2954 relative to the base of the structure.
2956 A final caveat: \c{ALIGN} and \c{ALIGNB} work relative to the
2957 beginning of the \e{section}, not the beginning of the address space
2958 in the final executable. Aligning to a 16-byte boundary when the
2959 section you're in is only guaranteed to be aligned to a 4-byte
2960 boundary, for example, is a waste of effort. Again, NASM does not
2961 check that the section's alignment characteristics are sensible for
2962 the use of \c{ALIGN} or \c{ALIGNB}.
2965 \H{tasmcompat} \i{TASM Compatible Preprocessor Directives}
2967 The following preprocessor directives may only be used when TASM
2968 compatibility is turned on using the \c{-t} command line switch
2969 (This switch is described in \k{opt-t}.)
2971 \b\c{%arg} (see \k{arg})
2973 \b\c{%stacksize} (see \k{stacksize})
2975 \b\c{%local} (see \k{local})
2978 \S{arg} \i\c{%arg} Directive
2980 The \c{%arg} directive is used to simplify the handling of
2981 parameters passed on the stack. Stack based parameter passing
2982 is used by many high level languages, including C, C++ and Pascal.
2984 While NASM comes with macros which attempt to duplicate this
2985 functionality (see \k{16cmacro}), the syntax is not particularly
2986 convenient to use and is not TASM compatible. Here is an example
2987 which shows the use of \c{%arg} without any external macros:
2991 \c %push mycontext ; save the current context
2992 \c %stacksize large ; tell NASM to use bp
2993 \c %arg i:word, j_ptr:word
3000 \c %pop ; restore original context
3002 This is similar to the procedure defined in \k{16cmacro} and adds
3003 the value in i to the value pointed to by j_ptr and returns the
3004 sum in the ax register. See \k{pushpop} for an explanation of
3005 \c{push} and \c{pop} and the use of context stacks.
3008 \S{stacksize} \i\c{%stacksize} Directive
3010 The \c{%stacksize} directive is used in conjunction with the
3011 \c{%arg} (see \k{arg}) and the \c{%local} (see \k{local}) directives.
3012 It tells NASM the default size to use for subsequent \c{%arg} and
3013 \c{%local} directives. The \c{%stacksize} directive takes one
3014 required argument which is one of \c{flat}, \c{large} or \c{small}.
3018 This form causes NASM to use stack-based parameter addressing
3019 relative to \c{ebp} and it assumes that a near form of call was used
3020 to get to this label (i.e. that \c{eip} is on the stack).
3024 This form uses \c{bp} to do stack-based parameter addressing and
3025 assumes that a far form of call was used to get to this address
3026 (i.e. that \c{ip} and \c{cs} are on the stack).
3030 This form also uses \c{bp} to address stack parameters, but it is
3031 different from \c{large} because it also assumes that the old value
3032 of bp is pushed onto the stack (i.e. it expects an \c{ENTER}
3033 instruction). In other words, it expects that \c{bp}, \c{ip} and
3034 \c{cs} are on the top of the stack, underneath any local space which
3035 may have been allocated by \c{ENTER}. This form is probably most
3036 useful when used in combination with the \c{%local} directive
3040 \S{local} \i\c{%local} Directive
3042 The \c{%local} directive is used to simplify the use of local
3043 temporary stack variables allocated in a stack frame. Automatic
3044 local variables in C are an example of this kind of variable. The
3045 \c{%local} directive is most useful when used with the \c{%stacksize}
3046 (see \k{stacksize} and is also compatible with the \c{%arg} directive
3047 (see \k{arg}). It allows simplified reference to variables on the
3048 stack which have been allocated typically by using the \c{ENTER}
3049 instruction (see \k{insENTER} for a description of that instruction).
3050 An example of its use is the following:
3054 \c %push mycontext ; save the current context
3055 \c %stacksize small ; tell NASM to use bp
3056 \c %assign %$localsize 0 ; see text for explanation
3057 \c %local old_ax:word, old_dx:word
3059 \c enter %$localsize,0 ; see text for explanation
3060 \c mov [old_ax],ax ; swap ax & bx
3061 \c mov [old_dx],dx ; and swap dx & cx
3066 \c leave ; restore old bp
3069 \c %pop ; restore original context
3071 The \c{%$localsize} variable is used internally by the
3072 \c{%local} directive and \e{must} be defined within the
3073 current context before the \c{%local} directive may be used.
3074 Failure to do so will result in one expression syntax error for
3075 each \c{%local} variable declared. It then may be used in
3076 the construction of an appropriately sized ENTER instruction
3077 as shown in the example.
3080 \C{directive} \i{Assembler Directives}
3082 NASM, though it attempts to avoid the bureaucracy of assemblers like
3083 MASM and TASM, is nevertheless forced to support a \e{few}
3084 directives. These are described in this chapter.
3086 NASM's directives come in two types: \i{user-level
3087 directives}\e{user-level} directives and \i{primitive
3088 directives}\e{primitive} directives. Typically, each directive has a
3089 user-level form and a primitive form. In almost all cases, we
3090 recommend that users use the user-level forms of the directives,
3091 which are implemented as macros which call the primitive forms.
3093 Primitive directives are enclosed in square brackets; user-level
3096 In addition to the universal directives described in this chapter,
3097 each object file format can optionally supply extra directives in
3098 order to control particular features of that file format. These
3099 \i{format-specific directives}\e{format-specific} directives are
3100 documented along with the formats that implement them, in \k{outfmt}.
3103 \H{bits} \i\c{BITS}: Specifying Target \i{Processor Mode}
3105 The \c{BITS} directive specifies whether NASM should generate code
3106 \I{16-bit mode, versus 32-bit mode}designed to run on a processor
3107 operating in 16-bit mode, or code designed to run on a processor
3108 operating in 32-bit mode. The syntax is \c{BITS 16} or \c{BITS 32}.
3110 In most cases, you should not need to use \c{BITS} explicitly. The
3111 \c{aout}, \c{coff}, \c{elf} and \c{win32} object formats, which are
3112 designed for use in 32-bit operating systems, all cause NASM to
3113 select 32-bit mode by default. The \c{obj} object format allows you
3114 to specify each segment you define as either \c{USE16} or \c{USE32},
3115 and NASM will set its operating mode accordingly, so the use of the
3116 \c{BITS} directive is once again unnecessary.
3118 The most likely reason for using the \c{BITS} directive is to write
3119 32-bit code in a flat binary file; this is because the \c{bin}
3120 output format defaults to 16-bit mode in anticipation of it being
3121 used most frequently to write DOS \c{.COM} programs, DOS \c{.SYS}
3122 device drivers and boot loader software.
3124 You do \e{not} need to specify \c{BITS 32} merely in order to use
3125 32-bit instructions in a 16-bit DOS program; if you do, the
3126 assembler will generate incorrect code because it will be writing
3127 code targeted at a 32-bit platform, to be run on a 16-bit one.
3129 When NASM is in \c{BITS 16} state, instructions which use 32-bit
3130 data are prefixed with an 0x66 byte, and those referring to 32-bit
3131 addresses have an 0x67 prefix. In \c{BITS 32} state, the reverse is
3132 true: 32-bit instructions require no prefixes, whereas instructions
3133 using 16-bit data need an 0x66 and those working in 16-bit addresses
3136 The \c{BITS} directive has an exactly equivalent primitive form,
3137 \c{[BITS 16]} and \c{[BITS 32]}. The user-level form is a macro
3138 which has no function other than to call the primitive form.
3141 \S{USE16 & USE32} \i\c{USE16} & \i\c{USE32}: Aliases for BITS
3143 The `\c{USE16}' and `\c{USE32}' directives can be used in place of
3144 `\c{BIT 16}' and `\c{BITS 32}', for compatibility with other assemblers.
3147 \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining
3150 \I{changing sections}\I{switching between sections}The \c{SECTION}
3151 directive (\c{SEGMENT} is an exactly equivalent synonym) changes
3152 which section of the output file the code you write will be
3153 assembled into. In some object file formats, the number and names of
3154 sections are fixed; in others, the user may make up as many as they
3155 wish. Hence \c{SECTION} may sometimes give an error message, or may
3156 define a new section, if you try to switch to a section that does
3159 The Unix object formats, and the \c{bin} object format, all support
3160 the \i{standardised section names} \c{.text}, \c{.data} and \c{.bss}
3161 for the code, data and uninitialised-data sections. The \c{obj}
3162 format, by contrast, does not recognise these section names as being
3163 special, and indeed will strip off the leading period of any section
3167 \S{sectmac} The \i\c{__SECT__} Macro
3169 The \c{SECTION} directive is unusual in that its user-level form
3170 functions differently from its primitive form. The primitive form,
3171 \c{[SECTION xyz]}, simply switches the current target section to the
3172 one given. The user-level form, \c{SECTION xyz}, however, first
3173 defines the single-line macro \c{__SECT__} to be the primitive
3174 \c{[SECTION]} directive which it is about to issue, and then issues
3175 it. So the user-level directive
3179 expands to the two lines
3181 \c %define __SECT__ [SECTION .text]
3184 Users may find it useful to make use of this in their own macros.
3185 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
3186 usefully rewritten in the following more sophisticated form:
3188 \c %macro writefile 2+
3198 \c mov cx,%%endstr-%%str
3205 This form of the macro, once passed a string to output, first
3206 switches temporarily to the data section of the file, using the
3207 primitive form of the \c{SECTION} directive so as not to modify
3208 \c{__SECT__}. It then declares its string in the data section, and
3209 then invokes \c{__SECT__} to switch back to \e{whichever} section
3210 the user was previously working in. It thus avoids the need, in the
3211 previous version of the macro, to include a \c{JMP} instruction to
3212 jump over the data, and also does not fail if, in a complicated
3213 \c{OBJ} format module, the user could potentially be assembling the
3214 code in any of several separate code sections.
3217 \H{absolute} \i\c{ABSOLUTE}: Defining Absolute Labels
3219 The \c{ABSOLUTE} directive can be thought of as an alternative form
3220 of \c{SECTION}: it causes the subsequent code to be directed at no
3221 physical section, but at the hypothetical section starting at the
3222 given absolute address. The only instructions you can use in this
3223 mode are the \c{RESB} family.
3225 \c{ABSOLUTE} is used as follows:
3233 This example describes a section of the PC BIOS data area, at
3234 segment address 0x40: the above code defines \c{kbuf_chr} to be
3235 0x1A, \c{kbuf_free} to be 0x1C, and \c{kbuf} to be 0x1E.
3237 The user-level form of \c{ABSOLUTE}, like that of \c{SECTION},
3238 redefines the \i\c{__SECT__} macro when it is invoked.
3240 \i\c{STRUC} and \i\c{ENDSTRUC} are defined as macros which use
3241 \c{ABSOLUTE} (and also \c{__SECT__}).
3243 \c{ABSOLUTE} doesn't have to take an absolute constant as an
3244 argument: it can take an expression (actually, a \i{critical
3245 expression}: see \k{crit}) and it can be a value in a segment. For
3246 example, a TSR can re-use its setup code as run-time BSS like this:
3248 \c org 100h ; it's a .COM program
3250 \c jmp setup ; setup code comes last
3252 \c ; the resident part of the TSR goes here
3254 \c ; now write the code that installs the TSR here
3258 \c runtimevar1 resw 1
3259 \c runtimevar2 resd 20
3263 This defines some variables `on top of' the setup code, so that
3264 after the setup has finished running, the space it took up can be
3265 re-used as data storage for the running TSR. The symbol `tsr_end'
3266 can be used to calculate the total size of the part of the TSR that
3267 needs to be made resident.
3270 \H{extern} \i\c{EXTERN}: \i{Importing Symbols} from Other Modules
3272 \c{EXTERN} is similar to the MASM directive \c{EXTRN} and the C
3273 keyword \c{extern}: it is used to declare a symbol which is not
3274 defined anywhere in the module being assembled, but is assumed to be
3275 defined in some other module and needs to be referred to by this
3276 one. Not every object-file format can support external variables:
3277 the \c{bin} format cannot.
3279 The \c{EXTERN} directive takes as many arguments as you like. Each
3280 argument is the name of a symbol:
3283 \c extern _sscanf,_fscanf
3285 Some object-file formats provide extra features to the \c{EXTERN}
3286 directive. In all cases, the extra features are used by suffixing a
3287 colon to the symbol name followed by object-format specific text.
3288 For example, the \c{obj} format allows you to declare that the
3289 default segment base of an external should be the group \c{dgroup}
3290 by means of the directive
3292 \c extern _variable:wrt dgroup
3294 The primitive form of \c{EXTERN} differs from the user-level form
3295 only in that it can take only one argument at a time: the support
3296 for multiple arguments is implemented at the preprocessor level.
3298 You can declare the same variable as \c{EXTERN} more than once: NASM
3299 will quietly ignore the second and later redeclarations. You can't
3300 declare a variable as \c{EXTERN} as well as something else, though.
3303 \H{global} \i\c{GLOBAL}: \i{Exporting Symbols} to Other Modules
3305 \c{GLOBAL} is the other end of \c{EXTERN}: if one module declares a
3306 symbol as \c{EXTERN} and refers to it, then in order to prevent
3307 linker errors, some other module must actually \e{define} the
3308 symbol and declare it as \c{GLOBAL}. Some assemblers use the name
3309 \i\c{PUBLIC} for this purpose.
3311 The \c{GLOBAL} directive applying to a symbol must appear \e{before}
3312 the definition of the symbol.
3314 \c{GLOBAL} uses the same syntax as \c{EXTERN}, except that it must
3315 refer to symbols which \e{are} defined in the same module as the
3316 \c{GLOBAL} directive. For example:
3322 \c{GLOBAL}, like \c{EXTERN}, allows object formats to define private
3323 extensions by means of a colon. The \c{elf} object format, for
3324 example, lets you specify whether global data items are functions or
3327 \c global hashlookup:function, hashtable:data
3329 Like \c{EXTERN}, the primitive form of \c{GLOBAL} differs from the
3330 user-level form only in that it can take only one argument at a
3334 \H{common} \i\c{COMMON}: Defining Common Data Areas
3336 The \c{COMMON} directive is used to declare \i\e{common variables}.
3337 A common variable is much like a global variable declared in the
3338 uninitialised data section, so that
3342 is similar in function to
3349 The difference is that if more than one module defines the same
3350 common variable, then at link time those variables will be
3351 \e{merged}, and references to \c{intvar} in all modules will point
3352 at the same piece of memory.
3354 Like \c{GLOBAL} and \c{EXTERN}, \c{COMMON} supports object-format
3355 specific extensions. For example, the \c{obj} format allows common
3356 variables to be NEAR or FAR, and the \c{elf} format allows you to
3357 specify the alignment requirements of a common variable:
3359 \c common commvar 4:near ; works in OBJ
3360 \c common intarray 100:4 ; works in ELF: 4 byte aligned
3362 Once again, like \c{EXTERN} and \c{GLOBAL}, the primitive form of
3363 \c{COMMON} differs from the user-level form only in that it can take
3364 only one argument at a time.
3367 \H{CPU} \i\c{CPU XXX}: Defining CPU Dependencies
3369 The \i\c{CPU} directive restricts assembly to those instructions which
3370 are available on the specified CPU.
3374 \b\c{CPU 8086} Assemble only 8086 instruction set
3376 \b\c{CPU 186} Assemble instructions up to the 80186 instruction set
3378 \b\c{CPU 286} Assemble instructions up to the 286 instruction set
3380 \b\c{CPU 386} Assemble instructions up to the 386 instruction set
3382 \b\c{CPU 486} 486 instruction set
3384 \b\c{CPU 586} Pentium instruction set
3386 \b\c{CPU PENTIUM} Same as 586
3388 \b\c{CPU 686} P6 instruction set
3390 \b\c{CPU PPRO} Same as 686
3392 \b\c{CPU P2} Same as 686
3394 \b\c{CPU P3} Pentium III and Katmai instruction sets
3396 \b\c{CPU KATMAI} Same as P3
3398 \b\c{CPU P4} Pentium 4 (Willamette) instruction set
3400 \b\c{CPU WILLAMETTE} Same as P4
3402 All options are case insensitive. All instructions will
3403 be selected only if they apply to the selected cpu or lower.
3406 \C{outfmt} \i{Output Formats}
3408 NASM is a portable assembler, designed to be able to compile on any
3409 ANSI C-supporting platform and produce output to run on a variety of
3410 Intel x86 operating systems. For this reason, it has a large number
3411 of available output formats, selected using the \i\c{-f} option on
3412 the NASM \i{command line}. Each of these formats, along with its
3413 extensions to the base NASM syntax, is detailed in this chapter.
3415 As stated in \k{opt-o}, NASM chooses a \i{default name} for your
3416 output file based on the input file name and the chosen output
3417 format. This will be generated by removing the \i{extension}
3418 (\c{.asm}, \c{.s}, or whatever you like to use) from the input file
3419 name, and substituting an extension defined by the output format.
3420 The extensions are given with each format below.
3423 \H{binfmt} \i\c{bin}: \i{Flat-Form Binary}\I{pure binary} Output
3425 The \c{bin} format does not produce object files: it generates
3426 nothing in the output file except the code you wrote. Such `pure
3427 binary' files are used by \i{MS-DOS}: \i\c{.COM} executables and
3428 \i\c{.SYS} device drivers are pure binary files. Pure binary output
3429 is also useful for \i{operating-system} and \i{boot loader}
3432 \c{bin} supports the three \i{standardised section names} \i\c{.text},
3433 \i\c{.data} and \i\c{.bss} only. The file NASM outputs will contain the
3434 contents of the \c{.text} section first, followed by the contents of
3435 the \c{.data} section, aligned on a four-byte boundary. The \c{.bss}
3436 section is not stored in the output file at all, but is assumed to
3437 appear directly after the end of the \c{.data} section, again
3438 aligned on a four-byte boundary.
3440 If you specify no explicit \c{SECTION} directive, the code you write
3441 will be directed by default into the \c{.text} section.
3443 Using the \c{bin} format puts NASM by default into 16-bit mode (see
3444 \k{bits}). In order to use \c{bin} to write 32-bit code such as an
3445 OS kernel, you need to explicitly issue the \I\c{BITS}\c{BITS 32}
3448 \c{bin} has no default output file name extension: instead, it
3449 leaves your file name as it is once the original extension has been
3450 removed. Thus, the default is for NASM to assemble \c{binprog.asm}
3451 into a binary file called \c{binprog}.
3454 \S{org} \i\c{ORG}: Binary File \i{Program Origin}
3456 The \c{bin} format provides an additional directive to the list
3457 given in \k{directive}: \c{ORG}. The function of the \c{ORG}
3458 directive is to specify the origin address which NASM will assume
3459 the program begins at when it is loaded into memory.
3461 For example, the following code will generate the longword
3468 Unlike the \c{ORG} directive provided by MASM-compatible assemblers,
3469 which allows you to jump around in the object file and overwrite
3470 code you have already generated, NASM's \c{ORG} does exactly what
3471 the directive says: \e{origin}. Its sole function is to specify one
3472 offset which is added to all internal address references within the
3473 file; it does not permit any of the trickery that MASM's version
3474 does. See \k{proborg} for further comments.
3477 \S{binseg} \c{bin} Extensions to the \c{SECTION}
3478 Directive\I{SECTION, bin extensions to}
3480 The \c{bin} output format extends the \c{SECTION} (or \c{SEGMENT})
3481 directive to allow you to specify the alignment requirements of
3482 segments. This is done by appending the \i\c{ALIGN} qualifier to the
3483 end of the section-definition line. For example,
3485 \c section .data align=16
3487 switches to the section \c{.data} and also specifies that it must be
3488 aligned on a 16-byte boundary.
3490 The parameter to \c{ALIGN} specifies how many low bits of the
3491 section start address must be forced to zero. The alignment value
3492 given may be any power of two.\I{section alignment, in
3493 bin}\I{segment alignment, in bin}\I{alignment, in bin sections}
3496 \H{objfmt} \i\c{obj}: \i{Microsoft OMF}\I{OMF} Object Files
3498 The \c{obj} file format (NASM calls it \c{obj} rather than \c{omf}
3499 for historical reasons) is the one produced by \i{MASM} and
3500 \i{TASM}, which is typically fed to 16-bit DOS linkers to produce
3501 \i\c{.EXE} files. It is also the format used by \i{OS/2}.
3503 \c{obj} provides a default output file-name extension of \c{.obj}.
3505 \c{obj} is not exclusively a 16-bit format, though: NASM has full
3506 support for the 32-bit extensions to the format. In particular,
3507 32-bit \c{obj} format files are used by \i{Borland's Win32
3508 compilers}, instead of using Microsoft's newer \i\c{win32} object
3511 The \c{obj} format does not define any special segment names: you
3512 can call your segments anything you like. Typical names for segments
3513 in \c{obj} format files are \c{CODE}, \c{DATA} and \c{BSS}.
3515 If your source file contains code before specifying an explicit
3516 \c{SEGMENT} directive, then NASM will invent its own segment called
3517 \i\c{__NASMDEFSEG} for you.
3519 When you define a segment in an \c{obj} file, NASM defines the
3520 segment name as a symbol as well, so that you can access the segment
3521 address of the segment. So, for example:
3530 \c mov ax,data ; get segment address of data
3531 \c mov ds,ax ; and move it into DS
3532 \c inc word [dvar] ; now this reference will work
3535 The \c{obj} format also enables the use of the \i\c{SEG} and
3536 \i\c{WRT} operators, so that you can write code which does things
3541 \c mov ax,seg foo ; get preferred segment of foo
3543 \c mov ax,data ; a different segment
3545 \c mov ax,[ds:foo] ; this accesses `foo'
3546 \c mov [es:foo wrt data],bx ; so does this
3549 \S{objseg} \c{obj} Extensions to the \c{SEGMENT}
3550 Directive\I{SEGMENT, obj extensions to}
3552 The \c{obj} output format extends the \c{SEGMENT} (or \c{SECTION})
3553 directive to allow you to specify various properties of the segment
3554 you are defining. This is done by appending extra qualifiers to the
3555 end of the segment-definition line. For example,
3557 \c segment code private align=16
3559 defines the segment \c{code}, but also declares it to be a private
3560 segment, and requires that the portion of it described in this code
3561 module must be aligned on a 16-byte boundary.
3563 The available qualifiers are:
3565 \b \i\c{PRIVATE}, \i\c{PUBLIC}, \i\c{COMMON} and \i\c{STACK} specify
3566 the combination characteristics of the segment. \c{PRIVATE} segments
3567 do not get combined with any others by the linker; \c{PUBLIC} and
3568 \c{STACK} segments get concatenated together at link time; and
3569 \c{COMMON} segments all get overlaid on top of each other rather
3570 than stuck end-to-end.
3572 \b \i\c{ALIGN} is used, as shown above, to specify how many low bits
3573 of the segment start address must be forced to zero. The alignment
3574 value given may be any power of two from 1 to 4096; in reality, the
3575 only values supported are 1, 2, 4, 16, 256 and 4096, so if 8 is
3576 specified it will be rounded up to 16, and 32, 64 and 128 will all
3577 be rounded up to 256, and so on. Note that alignment to 4096-byte
3578 boundaries is a \i{PharLap} extension to the format and may not be
3579 supported by all linkers.\I{section alignment, in OBJ}\I{segment
3580 alignment, in OBJ}\I{alignment, in OBJ sections}
3582 \b \i\c{CLASS} can be used to specify the segment class; this feature
3583 indicates to the linker that segments of the same class should be
3584 placed near each other in the output file. The class name can be any
3585 word, e.g. \c{CLASS=CODE}.
3587 \b \i\c{OVERLAY}, like \c{CLASS}, is specified with an arbitrary word
3588 as an argument, and provides overlay information to an
3589 overlay-capable linker.
3591 \b Segments can be declared as \i\c{USE16} or \i\c{USE32}, which has
3592 the effect of recording the choice in the object file and also
3593 ensuring that NASM's default assembly mode when assembling in that
3594 segment is 16-bit or 32-bit respectively.
3596 \b When writing \i{OS/2} object files, you should declare 32-bit
3597 segments as \i\c{FLAT}, which causes the default segment base for
3598 anything in the segment to be the special group \c{FLAT}, and also
3599 defines the group if it is not already defined.
3601 \b The \c{obj} file format also allows segments to be declared as
3602 having a pre-defined absolute segment address, although no linkers
3603 are currently known to make sensible use of this feature;
3604 nevertheless, NASM allows you to declare a segment such as
3605 \c{SEGMENT SCREEN ABSOLUTE=0xB800} if you need to. The \i\c{ABSOLUTE}
3606 and \c{ALIGN} keywords are mutually exclusive.
3608 NASM's default segment attributes are \c{PUBLIC}, \c{ALIGN=1}, no
3609 class, no overlay, and \c{USE16}.
3612 \S{group} \i\c{GROUP}: Defining Groups of Segments\I{segments, groups of}
3614 The \c{obj} format also allows segments to be grouped, so that a
3615 single segment register can be used to refer to all the segments in
3616 a group. NASM therefore supplies the \c{GROUP} directive, whereby
3625 \c ; some uninitialised data
3627 \c group dgroup data bss
3629 which will define a group called \c{dgroup} to contain the segments
3630 \c{data} and \c{bss}. Like \c{SEGMENT}, \c{GROUP} causes the group
3631 name to be defined as a symbol, so that you can refer to a variable
3632 \c{var} in the \c{data} segment as \c{var wrt data} or as \c{var wrt
3633 dgroup}, depending on which segment value is currently in your
3636 If you just refer to \c{var}, however, and \c{var} is declared in a
3637 segment which is part of a group, then NASM will default to giving
3638 you the offset of \c{var} from the beginning of the \e{group}, not
3639 the \e{segment}. Therefore \c{SEG var}, also, will return the group
3640 base rather than the segment base.
3642 NASM will allow a segment to be part of more than one group, but
3643 will generate a warning if you do this. Variables declared in a
3644 segment which is part of more than one group will default to being
3645 relative to the first group that was defined to contain the segment.
3647 A group does not have to contain any segments; you can still make
3648 \c{WRT} references to a group which does not contain the variable
3649 you are referring to. OS/2, for example, defines the special group
3650 \c{FLAT} with no segments in it.
3653 \S{uppercase} \i\c{UPPERCASE}: Disabling Case Sensitivity in Output
3655 Although NASM itself is \i{case sensitive}, some OMF linkers are
3656 not; therefore it can be useful for NASM to output single-case
3657 object files. The \c{UPPERCASE} format-specific directive causes all
3658 segment, group and symbol names that are written to the object file
3659 to be forced to upper case just before being written. Within a
3660 source file, NASM is still case-sensitive; but the object file can
3661 be written entirely in upper case if desired.
3663 \c{UPPERCASE} is used alone on a line; it requires no parameters.
3666 \S{import} \i\c{IMPORT}: Importing DLL Symbols\I{DLL symbols,
3667 importing}\I{symbols, importing from DLLs}
3669 The \c{IMPORT} format-specific directive defines a symbol to be
3670 imported from a DLL, for use if you are writing a DLL's \i{import
3671 library} in NASM. You still need to declare the symbol as \c{EXTERN}
3672 as well as using the \c{IMPORT} directive.
3674 The \c{IMPORT} directive takes two required parameters, separated by
3675 white space, which are (respectively) the name of the symbol you
3676 wish to import and the name of the library you wish to import it
3679 \c import WSAStartup wsock32.dll
3681 A third optional parameter gives the name by which the symbol is
3682 known in the library you are importing it from, in case this is not
3683 the same as the name you wish the symbol to be known by to your code
3684 once you have imported it. For example:
3686 \c import asyncsel wsock32.dll WSAAsyncSelect
3689 \S{export} \i\c{EXPORT}: Exporting DLL Symbols\I{DLL symbols,
3690 exporting}\I{symbols, exporting from DLLs}
3692 The \c{EXPORT} format-specific directive defines a global symbol to
3693 be exported as a DLL symbol, for use if you are writing a DLL in
3694 NASM. You still need to declare the symbol as \c{GLOBAL} as well as
3695 using the \c{EXPORT} directive.
3697 \c{EXPORT} takes one required parameter, which is the name of the
3698 symbol you wish to export, as it was defined in your source file. An
3699 optional second parameter (separated by white space from the first)
3700 gives the \e{external} name of the symbol: the name by which you
3701 wish the symbol to be known to programs using the DLL. If this name
3702 is the same as the internal name, you may leave the second parameter
3705 Further parameters can be given to define attributes of the exported
3706 symbol. These parameters, like the second, are separated by white
3707 space. If further parameters are given, the external name must also
3708 be specified, even if it is the same as the internal name. The
3709 available attributes are:
3711 \b \c{resident} indicates that the exported name is to be kept
3712 resident by the system loader. This is an optimisation for
3713 frequently used symbols imported by name.
3715 \b \c{nodata} indicates that the exported symbol is a function which
3716 does not make use of any initialised data.
3718 \b \c{parm=NNN}, where \c{NNN} is an integer, sets the number of
3719 parameter words for the case in which the symbol is a call gate
3720 between 32-bit and 16-bit segments.
3722 \b An attribute which is just a number indicates that the symbol
3723 should be exported with an identifying number (ordinal), and gives
3729 \c export myfunc TheRealMoreFormalLookingFunctionName
3730 \c export myfunc myfunc 1234 ; export by ordinal
3731 \c export myfunc myfunc resident parm=23 nodata
3734 \S{dotdotstart} \i\c{..start}: Defining the \i{Program Entry
3737 \c{OMF} linkers require exactly one of the object files being linked to
3738 define the program entry point, where execution will begin when the
3739 program is run. If the object file that defines the entry point is
3740 assembled using NASM, you specify the entry point by declaring the
3741 special symbol \c{..start} at the point where you wish execution to
3745 \S{objextern} \c{obj} Extensions to the \c{EXTERN}
3746 Directive\I{EXTERN, obj extensions to}
3748 If you declare an external symbol with the directive
3752 then references such as \c{mov ax,foo} will give you the offset of
3753 \c{foo} from its preferred segment base (as specified in whichever
3754 module \c{foo} is actually defined in). So to access the contents of
3755 \c{foo} you will usually need to do something like
3757 \c mov ax,seg foo ; get preferred segment base
3758 \c mov es,ax ; move it into ES
3759 \c mov ax,[es:foo] ; and use offset `foo' from it
3761 This is a little unwieldy, particularly if you know that an external
3762 is going to be accessible from a given segment or group, say
3763 \c{dgroup}. So if \c{DS} already contained \c{dgroup}, you could
3766 \c mov ax,[foo wrt dgroup]
3768 However, having to type this every time you want to access \c{foo}
3769 can be a pain; so NASM allows you to declare \c{foo} in the
3772 \c extern foo:wrt dgroup
3774 This form causes NASM to pretend that the preferred segment base of
3775 \c{foo} is in fact \c{dgroup}; so the expression \c{seg foo} will
3776 now return \c{dgroup}, and the expression \c{foo} is equivalent to
3779 This \I{default-WRT mechanism}default-\c{WRT} mechanism can be used
3780 to make externals appear to be relative to any group or segment in
3781 your program. It can also be applied to common variables: see
3785 \S{objcommon} \c{obj} Extensions to the \c{COMMON}
3786 Directive\I{COMMON, obj extensions to}
3788 The \c{obj} format allows common variables to be either near\I{near
3789 common variables} or far\I{far common variables}; NASM allows you to
3790 specify which your variables should be by the use of the syntax
3792 \c common nearvar 2:near ; `nearvar' is a near common
3793 \c common farvar 10:far ; and `farvar' is far
3795 Far common variables may be greater in size than 64Kb, and so the
3796 OMF specification says that they are declared as a number of
3797 \e{elements} of a given size. So a 10-byte far common variable could
3798 be declared as ten one-byte elements, five two-byte elements, two
3799 five-byte elements or one ten-byte element.
3801 Some \c{OMF} linkers require the \I{element size, in common
3802 variables}\I{common variables, element size}element size, as well as
3803 the variable size, to match when resolving common variables declared
3804 in more than one module. Therefore NASM must allow you to specify
3805 the element size on your far common variables. This is done by the
3808 \c common c_5by2 10:far 5 ; two five-byte elements
3809 \c common c_2by5 10:far 2 ; five two-byte elements
3811 If no element size is specified, the default is 1. Also, the \c{FAR}
3812 keyword is not required when an element size is specified, since
3813 only far commons may have element sizes at all. So the above
3814 declarations could equivalently be
3816 \c common c_5by2 10:5 ; two five-byte elements
3817 \c common c_2by5 10:2 ; five two-byte elements
3819 In addition to these extensions, the \c{COMMON} directive in \c{obj}
3820 also supports default-\c{WRT} specification like \c{EXTERN} does
3821 (explained in \k{objextern}). So you can also declare things like
3823 \c common foo 10:wrt dgroup
3824 \c common bar 16:far 2:wrt data
3825 \c common baz 24:wrt data:6
3828 \H{win32fmt} \i\c{win32}: Microsoft Win32 Object Files
3830 The \c{win32} output format generates Microsoft Win32 object files,
3831 suitable for passing to Microsoft linkers such as \i{Visual C++}.
3832 Note that Borland Win32 compilers do not use this format, but use
3833 \c{obj} instead (see \k{objfmt}).
3835 \c{win32} provides a default output file-name extension of \c{.obj}.
3837 Note that although Microsoft say that Win32 object files follow the
3838 \c{COFF} (Common Object File Format) standard, the object files produced
3839 by Microsoft Win32 compilers are not compatible with COFF linkers
3840 such as DJGPP's, and vice versa. This is due to a difference of
3841 opinion over the precise semantics of PC-relative relocations. To
3842 produce COFF files suitable for DJGPP, use NASM's \c{coff} output
3843 format; conversely, the \c{coff} format does not produce object
3844 files that Win32 linkers can generate correct output from.
3847 \S{win32sect} \c{win32} Extensions to the \c{SECTION}
3848 Directive\I{SECTION, win32 extensions to}
3850 Like the \c{obj} format, \c{win32} allows you to specify additional
3851 information on the \c{SECTION} directive line, to control the type
3852 and properties of sections you declare. Section types and properties
3853 are generated automatically by NASM for the \i{standard section names}
3854 \c{.text}, \c{.data} and \c{.bss}, but may still be overridden by
3857 The available qualifiers are:
3859 \b \c{code}, or equivalently \c{text}, defines the section to be a
3860 code section. This marks the section as readable and executable, but
3861 not writable, and also indicates to the linker that the type of the
3864 \b \c{data} and \c{bss} define the section to be a data section,
3865 analogously to \c{code}. Data sections are marked as readable and
3866 writable, but not executable. \c{data} declares an initialised data
3867 section, whereas \c{bss} declares an uninitialised data section.
3869 \b \c{rdata} declares an initialised data section that is readable
3870 but not writable. Microsoft compilers use this section to place
3873 \b \c{info} defines the section to be an \i{informational section},
3874 which is not included in the executable file by the linker, but may
3875 (for example) pass information \e{to} the linker. For example,
3876 declaring an \c{info}-type section called \i\c{.drectve} causes the
3877 linker to interpret the contents of the section as command-line
3880 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
3881 \I{section alignment, in win32}\I{alignment, in win32
3882 sections}alignment requirements of the section. The maximum you may
3883 specify is 64: the Win32 object file format contains no means to
3884 request a greater section alignment than this. If alignment is not
3885 explicitly specified, the defaults are 16-byte alignment for code
3886 sections, 8-byte alignment for rdata sections and 4-byte alignment
3887 for data (and BSS) sections.
3888 Informational sections get a default alignment of 1 byte (no
3889 alignment), though the value does not matter.
3891 The defaults assumed by NASM if you do not specify the above
3894 \c section .text code align=16
3895 \c section .data data align=4
3896 \c section .rdata rdata align=8
3897 \c section .bss bss align=4
3899 Any other section name is treated by default like \c{.text}.
3902 \H{cofffmt} \i\c{coff}: \i{Common Object File Format}
3904 The \c{coff} output type produces \c{COFF} object files suitable for
3905 linking with the \i{DJGPP} linker.
3907 \c{coff} provides a default output file-name extension of \c{.o}.
3909 The \c{coff} format supports the same extensions to the \c{SECTION}
3910 directive as \c{win32} does, except that the \c{align} qualifier and
3911 the \c{info} section type are not supported.
3914 \H{elffmt} \i\c{elf}: \i{Linux ELF}\I{Executable and Linkable
3917 The \c{elf} output format generates \c{ELF32} (Executable and Linkable
3918 Format) object files, as used by Linux. \c{elf} provides a default
3919 output file-name extension of \c{.o}.
3922 \S{elfsect} \c{elf} Extensions to the \c{SECTION}
3923 Directive\I{SECTION, elf extensions to}
3925 Like the \c{obj} format, \c{elf} allows you to specify additional
3926 information on the \c{SECTION} directive line, to control the type
3927 and properties of sections you declare. Section types and properties
3928 are generated automatically by NASM for the \i{standard section
3929 names} \i\c{.text}, \i\c{.data} and \i\c{.bss}, but may still be
3930 overridden by these qualifiers.
3932 The available qualifiers are:
3934 \b \i\c{alloc} defines the section to be one which is loaded into
3935 memory when the program is run. \i\c{noalloc} defines it to be one
3936 which is not, such as an informational or comment section.
3938 \b \i\c{exec} defines the section to be one which should have execute
3939 permission when the program is run. \i\c{noexec} defines it as one
3942 \b \i\c{write} defines the section to be one which should be writable
3943 when the program is run. \i\c{nowrite} defines it as one which should
3946 \b \i\c{progbits} defines the section to be one with explicit contents
3947 stored in the object file: an ordinary code or data section, for
3948 example, \i\c{nobits} defines the section to be one with no explicit
3949 contents given, such as a BSS section.
3951 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
3952 \I{section alignment, in elf}\I{alignment, in elf sections}alignment
3953 requirements of the section.
3955 The defaults assumed by NASM if you do not specify the above
3958 \c section .text progbits alloc exec nowrite align=16
3959 \c section .data progbits alloc noexec write align=4
3960 \c section .bss nobits alloc noexec write align=4
3961 \c section other progbits alloc noexec nowrite align=1
3963 (Any section name other than \c{.text}, \c{.data} and \c{.bss} is
3964 treated by default like \c{other} in the above code.)
3967 \S{elfwrt} \i{Position-Independent Code}\I{PIC}: \c{elf} Special
3968 Symbols and \i\c{WRT}
3970 The \c{ELF} specification contains enough features to allow
3971 position-independent code (PIC) to be written, which makes \i{ELF
3972 shared libraries} very flexible. However, it also means NASM has to
3973 be able to generate a variety of strange relocation types in ELF
3974 object files, if it is to be an assembler which can write PIC.
3976 Since \c{ELF} does not support segment-base references, the \c{WRT}
3977 operator is not used for its normal purpose; therefore NASM's
3978 \c{elf} output format makes use of \c{WRT} for a different purpose,
3979 namely the PIC-specific \I{relocations, PIC-specific}relocation
3982 \c{elf} defines five special symbols which you can use as the
3983 right-hand side of the \c{WRT} operator to obtain PIC relocation
3984 types. They are \i\c{..gotpc}, \i\c{..gotoff}, \i\c{..got},
3985 \i\c{..plt} and \i\c{..sym}. Their functions are summarised here:
3987 \b Referring to the symbol marking the global offset table base
3988 using \c{wrt ..gotpc} will end up giving the distance from the
3989 beginning of the current section to the global offset table.
3990 (\i\c{_GLOBAL_OFFSET_TABLE_} is the standard symbol name used to
3991 refer to the \i{GOT}.) So you would then need to add \i\c{$$} to the
3992 result to get the real address of the GOT.
3994 \b Referring to a location in one of your own sections using \c{wrt
3995 ..gotoff} will give the distance from the beginning of the GOT to
3996 the specified location, so that adding on the address of the GOT
3997 would give the real address of the location you wanted.
3999 \b Referring to an external or global symbol using \c{wrt ..got}
4000 causes the linker to build an entry \e{in} the GOT containing the
4001 address of the symbol, and the reference gives the distance from the
4002 beginning of the GOT to the entry; so you can add on the address of
4003 the GOT, load from the resulting address, and end up with the
4004 address of the symbol.
4006 \b Referring to a procedure name using \c{wrt ..plt} causes the
4007 linker to build a \i{procedure linkage table} entry for the symbol,
4008 and the reference gives the address of the \i{PLT} entry. You can
4009 only use this in contexts which would generate a PC-relative
4010 relocation normally (i.e. as the destination for \c{CALL} or
4011 \c{JMP}), since ELF contains no relocation type to refer to PLT
4014 \b Referring to a symbol name using \c{wrt ..sym} causes NASM to
4015 write an ordinary relocation, but instead of making the relocation
4016 relative to the start of the section and then adding on the offset
4017 to the symbol, it will write a relocation record aimed directly at
4018 the symbol in question. The distinction is a necessary one due to a
4019 peculiarity of the dynamic linker.
4021 A fuller explanation of how to use these relocation types to write
4022 shared libraries entirely in NASM is given in \k{picdll}.
4025 \S{elfglob} \c{elf} Extensions to the \c{GLOBAL} Directive\I{GLOBAL,
4026 elf extensions to}\I{GLOBAL, aoutb extensions to}
4028 \c{ELF} object files can contain more information about a global symbol
4029 than just its address: they can contain the \I{symbol sizes,
4030 specifying}\I{size, of symbols}size of the symbol and its \I{symbol
4031 types, specifying}\I{type, of symbols}type as well. These are not
4032 merely debugger conveniences, but are actually necessary when the
4033 program being written is a \i{shared library}. NASM therefore
4034 supports some extensions to the \c{GLOBAL} directive, allowing you
4035 to specify these features.
4037 You can specify whether a global variable is a function or a data
4038 object by suffixing the name with a colon and the word
4039 \i\c{function} or \i\c{data}. (\i\c{object} is a synonym for
4040 \c{data}.) For example:
4042 \c global hashlookup:function, hashtable:data
4044 exports the global symbol \c{hashlookup} as a function and
4045 \c{hashtable} as a data object.
4047 You can also specify the size of the data associated with the
4048 symbol, as a numeric expression (which may involve labels, and even
4049 forward references) after the type specifier. Like this:
4051 \c global hashtable:data (hashtable.end - hashtable)
4054 \c db this,that,theother ; some data here
4057 This makes NASM automatically calculate the length of the table and
4058 place that information into the \c{ELF} symbol table.
4060 Declaring the type and size of global symbols is necessary when
4061 writing shared library code. For more information, see
4065 \S{elfcomm} \c{elf} Extensions to the \c{COMMON} Directive
4066 \I{COMMON, elf extensions to}
4068 \c{ELF} also allows you to specify alignment requirements \I{common
4069 variables, alignment in elf}\I{alignment, of elf common variables}on
4070 common variables. This is done by putting a number (which must be a
4071 power of two) after the name and size of the common variable,
4072 separated (as usual) by a colon. For example, an array of
4073 doublewords would benefit from 4-byte alignment:
4075 \c common dwordarray 128:4
4077 This declares the total size of the array to be 128 bytes, and
4078 requires that it be aligned on a 4-byte boundary.
4081 \H{aoutfmt} \i\c{aout}: Linux \I{a.out, Linux version}\c{a.out} Object Files
4083 The \c{aout} format generates \c{a.out} object files, in the form
4084 used by early Linux systems. (These differ from other \c{a.out}
4085 object files in that the magic number in the first four bytes of the
4086 file is different. Also, some implementations of \c{a.out}, for
4087 example NetBSD's, support position-independent code, which Linux's
4088 implementation doesn't.)
4090 \c{a.out} provides a default output file-name extension of \c{.o}.
4092 \c{a.out} is a very simple object format. It supports no special
4093 directives, no special symbols, no use of \c{SEG} or \c{WRT}, and no
4094 extensions to any standard directives. It supports only the three
4095 \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4098 \H{aoutfmt} \i\c{aoutb}: \i{NetBSD}/\i{FreeBSD}/\i{OpenBSD}
4099 \I{a.out, BSD version}\c{a.out} Object Files
4101 The \c{aoutb} format generates \c{a.out} object files, in the form
4102 used by the various free \c{BSD Unix} clones, \c{NetBSD}, \c{FreeBSD}
4103 and \c{OpenBSD}. For simple object files, this object format is exactly
4104 the same as \c{aout} except for the magic number in the first four bytes
4105 of the file. However, the \c{aoutb} format supports
4106 \I{PIC}\i{position-independent code} in the same way as the \c{elf}
4107 format, so you can use it to write \c{BSD} \i{shared libraries}.
4109 \c{aoutb} provides a default output file-name extension of \c{.o}.
4111 \c{aoutb} supports no special directives, no special symbols, and
4112 only the three \i{standard section names} \i\c{.text}, \i\c{.data}
4113 and \i\c{.bss}. However, it also supports the same use of \i\c{WRT} as
4114 \c{elf} does, to provide position-independent code relocation types.
4115 See \k{elfwrt} for full documentation of this feature.
4117 \c{aoutb} also supports the same extensions to the \c{GLOBAL}
4118 directive as \c{elf} does: see \k{elfglob} for documentation of
4122 \H{as86fmt} \c{as86}: Linux \i\c{as86} Object Files
4124 The Linux 16-bit assembler \c{as86} has its own non-standard object
4125 file format. Although its companion linker \i\c{ld86} produces
4126 something close to ordinary \c{a.out} binaries as output, the object
4127 file format used to communicate between \c{as86} and \c{ld86} is not
4130 NASM supports this format, just in case it is useful, as \c{as86}.
4131 \c{as86} provides a default output file-name extension of \c{.o}.
4133 \c{as86} is a very simple object format (from the NASM user's point
4134 of view). It supports no special directives, no special symbols, no
4135 use of \c{SEG} or \c{WRT}, and no extensions to any standard
4136 directives. It supports only the three \i{standard section names}
4137 \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4140 \H{rdffmt} \I{RDOFF}\i\c{rdf}: \i{Relocatable Dynamic Object File
4143 The \c{rdf} output format produces \c{RDOFF} object files. \c{RDOFF}
4144 (Relocatable Dynamic Object File Format) is a home-grown object-file
4145 format, designed alongside NASM itself and reflecting in its file
4146 format the internal structure of the assembler.
4148 \c{RDOFF} is not used by any well-known operating systems. Those
4149 writing their own systems, however, may well wish to use \c{RDOFF}
4150 as their object format, on the grounds that it is designed primarily
4151 for simplicity and contains very little file-header bureaucracy.
4153 The Unix NASM archive, and the DOS archive which includes sources,
4154 both contain an \I{rdoff subdirectory}\c{rdoff} subdirectory holding
4155 a set of RDOFF utilities: an RDF linker, an \c{RDF} static-library
4156 manager, an RDF file dump utility, and a program which will load and
4157 execute an RDF executable under Linux.
4159 \c{rdf} supports only the \i{standard section names} \i\c{.text},
4160 \i\c{.data} and \i\c{.bss}.
4163 \S{rdflib} Requiring a Library: The \i\c{LIBRARY} Directive
4165 \c{RDOFF} contains a mechanism for an object file to demand a given
4166 library to be linked to the module, either at load time or run time.
4167 This is done by the \c{LIBRARY} directive, which takes one argument
4168 which is the name of the module:
4170 \c library mylib.rdl
4173 \S{rdfmod} Specifying a Module Name: The \i\c{MODULE} Directive
4175 Special \c{RDOFF} header record is used to store the name of the module.
4176 It can be used, for example, by run-time loader to perform dynamic
4177 linking. \c{MODULE} directive takes one argument which is the name
4182 Note that when you statically link modules and tell linker to strip
4183 the symbols from output file, all module names will be stripped too.
4184 To avoid it, you should start module names with \I{$prefix}\c{$}, like:
4186 \c module $kernel.core
4189 \S{rdfglob} \c{rdf} Extensions to the \c{GLOBAL} directive\I{GLOBAL,
4192 \c{RDOFF} global symbols can contain additional information needed by
4193 the static linker. You can mark a global symbol as exported, thus
4194 telling the linker do not strip it from target executable or library
4195 file. Like in \c{ELF}, you can also specify whether an exported symbol
4196 is a procedure (function) or data object.
4198 Suffixing the name with a colon and the word \i\c{export} you make the
4201 \c global sys_open:export
4203 To specify that exported symbol is a procedure (function), you add the
4204 word \i\c{proc} or \i\c{function} after declaration:
4206 \c global sys_open:export proc
4208 Similarly, to specify exported data object, add the word \i\c{data}
4209 or \i\c{object} to the directive:
4211 \c global kernel_ticks:export data
4214 \H{dbgfmt} \i\c{dbg}: Debugging Format
4216 The \c{dbg} output format is not built into NASM in the default
4217 configuration. If you are building your own NASM executable from the
4218 sources, you can define \i\c{OF_DBG} in \c{outform.h} or on the
4219 compiler command line, and obtain the \c{dbg} output format.
4221 The \c{dbg} format does not output an object file as such; instead,
4222 it outputs a text file which contains a complete list of all the
4223 transactions between the main body of NASM and the output-format
4224 back end module. It is primarily intended to aid people who want to
4225 write their own output drivers, so that they can get a clearer idea
4226 of the various requests the main program makes of the output driver,
4227 and in what order they happen.
4229 For simple files, one can easily use the \c{dbg} format like this:
4231 \c nasm -f dbg filename.asm
4233 which will generate a diagnostic file called \c{filename.dbg}.
4234 However, this will not work well on files which were designed for a
4235 different object format, because each object format defines its own
4236 macros (usually user-level forms of directives), and those macros
4237 will not be defined in the \c{dbg} format. Therefore it can be
4238 useful to run NASM twice, in order to do the preprocessing with the
4239 native object format selected:
4241 \c nasm -e -f rdf -o rdfprog.i rdfprog.asm
4242 \c nasm -a -f dbg rdfprog.i
4244 This preprocesses \c{rdfprog.asm} into \c{rdfprog.i}, keeping the
4245 \c{rdf} object format selected in order to make sure RDF special
4246 directives are converted into primitive form correctly. Then the
4247 preprocessed source is fed through the \c{dbg} format to generate
4248 the final diagnostic output.
4250 This workaround will still typically not work for programs intended
4251 for \c{obj} format, because the \c{obj} \c{SEGMENT} and \c{GROUP}
4252 directives have side effects of defining the segment and group names
4253 as symbols; \c{dbg} will not do this, so the program will not
4254 assemble. You will have to work around that by defining the symbols
4255 yourself (using \c{EXTERN}, for example) if you really need to get a
4256 \c{dbg} trace of an \c{obj}-specific source file.
4258 \c{dbg} accepts any section name and any directives at all, and logs
4259 them all to its output file.
4262 \C{16bit} Writing 16-bit Code (DOS, Windows 3/3.1)
4264 This chapter attempts to cover some of the common issues encountered
4265 when writing 16-bit code to run under \c{MS-DOS} or \c{Windows 3.x}. It
4266 covers how to link programs to produce \c{.EXE} or \c{.COM} files,
4267 how to write \c{.SYS} device drivers, and how to interface assembly
4268 language code with 16-bit C compilers and with Borland Pascal.
4271 \H{exefiles} Producing \i\c{.EXE} Files
4273 Any large program written under DOS needs to be built as a \c{.EXE}
4274 file: only \c{.EXE} files have the necessary internal structure
4275 required to span more than one 64K segment. \i{Windows} programs,
4276 also, have to be built as \c{.EXE} files, since Windows does not
4277 support the \c{.COM} format.
4279 In general, you generate \c{.EXE} files by using the \c{obj} output
4280 format to produce one or more \i\c{.OBJ} files, and then linking
4281 them together using a linker. However, NASM also supports the direct
4282 generation of simple DOS \c{.EXE} files using the \c{bin} output
4283 format (by using \c{DB} and \c{DW} to construct the \c{.EXE} file
4284 header), and a macro package is supplied to do this. Thanks to
4285 Yann Guidon for contributing the code for this.
4287 NASM may also support \c{.EXE} natively as another output format in
4291 \S{objexe} Using the \c{obj} Format To Generate \c{.EXE} Files
4293 This section describes the usual method of generating \c{.EXE} files
4294 by linking \c{.OBJ} files together.
4296 Most 16-bit programming language packages come with a suitable
4297 linker; if you have none of these, there is a free linker called
4298 \i{VAL}\I{linker, free}, available in \c{LZH} archive format from
4299 \W{ftp://x2ftp.oulu.fi/pub/msdos/programming/lang/}\i\c{x2ftp.oulu.fi}.
4300 An LZH archiver can be found at
4301 \W{ftp://ftp.simtel.net/pub/simtelnet/msdos/arcers}\i\c{ftp.simtel.net}.
4302 There is another `free' linker (though this one doesn't come with
4303 sources) called \i{FREELINK}, available from
4304 \W{http://www.pcorner.com/tpc/old/3-101.html}\i\c{www.pcorner.com}.
4305 A third, \i\c{djlink}, written by DJ Delorie, is available at
4306 \W{http://www.delorie.com/djgpp/16bit/djlink/}\i\c{www.delorie.com}.
4307 A fourth linker, \i\c{ALINK}, written by Anthony A.J. Williams, is
4308 available at \W{http://alink.sourceforge.net}\i\c{alink.sourceforge.net}.
4310 When linking several \c{.OBJ} files into a \c{.EXE} file, you should
4311 ensure that exactly one of them has a start point defined (using the
4312 \I{program entry point}\i\c{..start} special symbol defined by the
4313 \c{obj} format: see \k{dotdotstart}). If no module defines a start
4314 point, the linker will not know what value to give the entry-point
4315 field in the output file header; if more than one defines a start
4316 point, the linker will not know \e{which} value to use.
4318 An example of a NASM source file which can be assembled to a
4319 \c{.OBJ} file and linked on its own to a \c{.EXE} is given here. It
4320 demonstrates the basic principles of defining a stack, initialising
4321 the segment registers, and declaring a start point. This file is
4322 also provided in the \I{test subdirectory}\c{test} subdirectory of
4323 the NASM archives, under the name \c{objexe.asm}.
4334 This initial piece of code sets up \c{DS} to point to the data
4335 segment, and initialises \c{SS} and \c{SP} to point to the top of
4336 the provided stack. Notice that interrupts are implicitly disabled
4337 for one instruction after a move into \c{SS}, precisely for this
4338 situation, so that there's no chance of an interrupt occurring
4339 between the loads of \c{SS} and \c{SP} and not having a stack to
4342 Note also that the special symbol \c{..start} is defined at the
4343 beginning of this code, which means that will be the entry point
4344 into the resulting executable file.
4350 The above is the main program: load \c{DS:DX} with a pointer to the
4351 greeting message (\c{hello} is implicitly relative to the segment
4352 \c{data}, which was loaded into \c{DS} in the setup code, so the
4353 full pointer is valid), and call the DOS print-string function.
4358 This terminates the program using another DOS system call.
4362 \c hello: db 'hello, world', 13, 10, '$'
4364 The data segment contains the string we want to display.
4366 \c segment stack stack
4370 The above code declares a stack segment containing 64 bytes of
4371 uninitialised stack space, and points \c{stacktop} at the top of it.
4372 The directive \c{segment stack stack} defines a segment \e{called}
4373 \c{stack}, and also of \e{type} \c{STACK}. The latter is not
4374 necessary to the correct running of the program, but linkers are
4375 likely to issue warnings or errors if your program has no segment of
4378 The above file, when assembled into a \c{.OBJ} file, will link on
4379 its own to a valid \c{.EXE} file, which when run will print `hello,
4380 world' and then exit.
4383 \S{binexe} Using the \c{bin} Format To Generate \c{.EXE} Files
4385 The \c{.EXE} file format is simple enough that it's possible to
4386 build a \c{.EXE} file by writing a pure-binary program and sticking
4387 a 32-byte header on the front. This header is simple enough that it
4388 can be generated using \c{DB} and \c{DW} commands by NASM itself, so
4389 that you can use the \c{bin} output format to directly generate
4392 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4393 subdirectory, is a file \i\c{exebin.mac} of macros. It defines three
4394 macros: \i\c{EXE_begin}, \i\c{EXE_stack} and \i\c{EXE_end}.
4396 To produce a \c{.EXE} file using this method, you should start by
4397 using \c{%include} to load the \c{exebin.mac} macro package into
4398 your source file. You should then issue the \c{EXE_begin} macro call
4399 (which takes no arguments) to generate the file header data. Then
4400 write code as normal for the \c{bin} format - you can use all three
4401 standard sections \c{.text}, \c{.data} and \c{.bss}. At the end of
4402 the file you should call the \c{EXE_end} macro (again, no arguments),
4403 which defines some symbols to mark section sizes, and these symbols
4404 are referred to in the header code generated by \c{EXE_begin}.
4406 In this model, the code you end up writing starts at \c{0x100}, just
4407 like a \c{.COM} file - in fact, if you strip off the 32-byte header
4408 from the resulting \c{.EXE} file, you will have a valid \c{.COM}
4409 program. All the segment bases are the same, so you are limited to a
4410 64K program, again just like a \c{.COM} file. Note that an \c{ORG}
4411 directive is issued by the \c{EXE_begin} macro, so you should not
4412 explicitly issue one of your own.
4414 You can't directly refer to your segment base value, unfortunately,
4415 since this would require a relocation in the header, and things
4416 would get a lot more complicated. So you should get your segment
4417 base by copying it out of \c{CS} instead.
4419 On entry to your \c{.EXE} file, \c{SS:SP} are already set up to
4420 point to the top of a 2Kb stack. You can adjust the default stack
4421 size of 2Kb by calling the \c{EXE_stack} macro. For example, to
4422 change the stack size of your program to 64 bytes, you would call
4425 A sample program which generates a \c{.EXE} file in this way is
4426 given in the \c{test} subdirectory of the NASM archive, as
4430 \H{comfiles} Producing \i\c{.COM} Files
4432 While large DOS programs must be written as \c{.EXE} files, small
4433 ones are often better written as \c{.COM} files. \c{.COM} files are
4434 pure binary, and therefore most easily produced using the \c{bin}
4438 \S{combinfmt} Using the \c{bin} Format To Generate \c{.COM} Files
4440 \c{.COM} files expect to be loaded at offset \c{100h} into their
4441 segment (though the segment may change). Execution then begins at
4442 \I\c{ORG}\c{100h}, i.e. right at the start of the program. So to
4443 write a \c{.COM} program, you would create a source file looking
4451 \c ; put your code here
4455 \c ; put data items here
4459 \c ; put uninitialised data here
4461 The \c{bin} format puts the \c{.text} section first in the file, so
4462 you can declare data or BSS items before beginning to write code if
4463 you want to and the code will still end up at the front of the file
4466 The BSS (uninitialised data) section does not take up space in the
4467 \c{.COM} file itself: instead, addresses of BSS items are resolved
4468 to point at space beyond the end of the file, on the grounds that
4469 this will be free memory when the program is run. Therefore you
4470 should not rely on your BSS being initialised to all zeros when you
4473 To assemble the above program, you should use a command line like
4475 \c nasm myprog.asm -fbin -o myprog.com
4477 The \c{bin} format would produce a file called \c{myprog} if no
4478 explicit output file name were specified, so you have to override it
4479 and give the desired file name.
4482 \S{comobjfmt} Using the \c{obj} Format To Generate \c{.COM} Files
4484 If you are writing a \c{.COM} program as more than one module, you
4485 may wish to assemble several \c{.OBJ} files and link them together
4486 into a \c{.COM} program. You can do this, provided you have a linker
4487 capable of outputting \c{.COM} files directly (\i{TLINK} does this),
4488 or alternatively a converter program such as \i\c{EXE2BIN} to
4489 transform the \c{.EXE} file output from the linker into a \c{.COM}
4492 If you do this, you need to take care of several things:
4494 \b The first object file containing code should start its code
4495 segment with a line like \c{RESB 100h}. This is to ensure that the
4496 code begins at offset \c{100h} relative to the beginning of the code
4497 segment, so that the linker or converter program does not have to
4498 adjust address references within the file when generating the
4499 \c{.COM} file. Other assemblers use an \i\c{ORG} directive for this
4500 purpose, but \c{ORG} in NASM is a format-specific directive to the
4501 \c{bin} output format, and does not mean the same thing as it does
4502 in MASM-compatible assemblers.
4504 \b You don't need to define a stack segment.
4506 \b All your segments should be in the same group, so that every time
4507 your code or data references a symbol offset, all offsets are
4508 relative to the same segment base. This is because, when a \c{.COM}
4509 file is loaded, all the segment registers contain the same value.
4512 \H{sysfiles} Producing \i\c{.SYS} Files
4514 \i{MS-DOS device drivers} - \c{.SYS} files - are pure binary files,
4515 similar to \c{.COM} files, except that they start at origin zero
4516 rather than \c{100h}. Therefore, if you are writing a device driver
4517 using the \c{bin} format, you do not need the \c{ORG} directive,
4518 since the default origin for \c{bin} is zero. Similarly, if you are
4519 using \c{obj}, you do not need the \c{RESB 100h} at the start of
4522 \c{.SYS} files start with a header structure, containing pointers to
4523 the various routines inside the driver which do the work. This
4524 structure should be defined at the start of the code segment, even
4525 though it is not actually code.
4527 For more information on the format of \c{.SYS} files, and the data
4528 which has to go in the header structure, a list of books is given in
4529 the Frequently Asked Questions list for the newsgroup
4530 \W{news:comp.os.msdos.programmer}\i\c{comp.os.msdos.programmer}.
4533 \H{16c} Interfacing to 16-bit C Programs
4535 This section covers the basics of writing assembly routines that
4536 call, or are called from, C programs. To do this, you would
4537 typically write an assembly module as a \c{.OBJ} file, and link it
4538 with your C modules to produce a \i{mixed-language program}.
4541 \S{16cunder} External Symbol Names
4543 \I{C symbol names}\I{underscore, in C symbols}C compilers have the
4544 convention that the names of all global symbols (functions or data)
4545 they define are formed by prefixing an underscore to the name as it
4546 appears in the C program. So, for example, the function a C
4547 programmer thinks of as \c{printf} appears to an assembly language
4548 programmer as \c{_printf}. This means that in your assembly
4549 programs, you can define symbols without a leading underscore, and
4550 not have to worry about name clashes with C symbols.
4552 If you find the underscores inconvenient, you can define macros to
4553 replace the \c{GLOBAL} and \c{EXTERN} directives as follows:
4569 (These forms of the macros only take one argument at a time; a
4570 \c{%rep} construct could solve this.)
4572 If you then declare an external like this:
4576 then the macro will expand it as
4579 \c %define printf _printf
4581 Thereafter, you can reference \c{printf} as if it was a symbol, and
4582 the preprocessor will put the leading underscore on where necessary.
4584 The \c{cglobal} macro works similarly. You must use \c{cglobal}
4585 before defining the symbol in question, but you would have had to do
4586 that anyway if you used \c{GLOBAL}.
4589 \S{16cmodels} \i{Memory Models}
4591 NASM contains no mechanism to support the various C memory models
4592 directly; you have to keep track yourself of which one you are
4593 writing for. This means you have to keep track of the following
4596 \b In models using a single code segment (tiny, small and compact),
4597 functions are near. This means that function pointers, when stored
4598 in data segments or pushed on the stack as function arguments, are
4599 16 bits long and contain only an offset field (the \c{CS} register
4600 never changes its value, and always gives the segment part of the
4601 full function address), and that functions are called using ordinary
4602 near \c{CALL} instructions and return using \c{RETN} (which, in
4603 NASM, is synonymous with \c{RET} anyway). This means both that you
4604 should write your own routines to return with \c{RETN}, and that you
4605 should call external C routines with near \c{CALL} instructions.
4607 \b In models using more than one code segment (medium, large and
4608 huge), functions are far. This means that function pointers are 32
4609 bits long (consisting of a 16-bit offset followed by a 16-bit
4610 segment), and that functions are called using \c{CALL FAR} (or
4611 \c{CALL seg:offset}) and return using \c{RETF}. Again, you should
4612 therefore write your own routines to return with \c{RETF} and use
4613 \c{CALL FAR} to call external routines.
4615 \b In models using a single data segment (tiny, small and medium),
4616 data pointers are 16 bits long, containing only an offset field (the
4617 \c{DS} register doesn't change its value, and always gives the
4618 segment part of the full data item address).
4620 \b In models using more than one data segment (compact, large and
4621 huge), data pointers are 32 bits long, consisting of a 16-bit offset
4622 followed by a 16-bit segment. You should still be careful not to
4623 modify \c{DS} in your routines without restoring it afterwards, but
4624 \c{ES} is free for you to use to access the contents of 32-bit data
4625 pointers you are passed.
4627 \b The huge memory model allows single data items to exceed 64K in
4628 size. In all other memory models, you can access the whole of a data
4629 item just by doing arithmetic on the offset field of the pointer you
4630 are given, whether a segment field is present or not; in huge model,
4631 you have to be more careful of your pointer arithmetic.
4633 \b In most memory models, there is a \e{default} data segment, whose
4634 segment address is kept in \c{DS} throughout the program. This data
4635 segment is typically the same segment as the stack, kept in \c{SS},
4636 so that functions' local variables (which are stored on the stack)
4637 and global data items can both be accessed easily without changing
4638 \c{DS}. Particularly large data items are typically stored in other
4639 segments. However, some memory models (though not the standard
4640 ones, usually) allow the assumption that \c{SS} and \c{DS} hold the
4641 same value to be removed. Be careful about functions' local
4642 variables in this latter case.
4644 In models with a single code segment, the segment is called
4645 \i\c{_TEXT}, so your code segment must also go by this name in order
4646 to be linked into the same place as the main code segment. In models
4647 with a single data segment, or with a default data segment, it is
4651 \S{16cfunc} Function Definitions and Function Calls
4653 \I{functions, C calling convention}The \i{C calling convention} in
4654 16-bit programs is as follows. In the following description, the
4655 words \e{caller} and \e{callee} are used to denote the function
4656 doing the calling and the function which gets called.
4658 \b The caller pushes the function's parameters on the stack, one
4659 after another, in reverse order (right to left, so that the first
4660 argument specified to the function is pushed last).
4662 \b The caller then executes a \c{CALL} instruction to pass control
4663 to the callee. This \c{CALL} is either near or far depending on the
4666 \b The callee receives control, and typically (although this is not
4667 actually necessary, in functions which do not need to access their
4668 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
4669 be able to use \c{BP} as a base pointer to find its parameters on
4670 the stack. However, the caller was probably doing this too, so part
4671 of the calling convention states that \c{BP} must be preserved by
4672 any C function. Hence the callee, if it is going to set up \c{BP} as
4673 a \i\e{frame pointer}, must push the previous value first.
4675 \b The callee may then access its parameters relative to \c{BP}.
4676 The word at \c{[BP]} holds the previous value of \c{BP} as it was
4677 pushed; the next word, at \c{[BP+2]}, holds the offset part of the
4678 return address, pushed implicitly by \c{CALL}. In a small-model
4679 (near) function, the parameters start after that, at \c{[BP+4]}; in
4680 a large-model (far) function, the segment part of the return address
4681 lives at \c{[BP+4]}, and the parameters begin at \c{[BP+6]}. The
4682 leftmost parameter of the function, since it was pushed last, is
4683 accessible at this offset from \c{BP}; the others follow, at
4684 successively greater offsets. Thus, in a function such as \c{printf}
4685 which takes a variable number of parameters, the pushing of the
4686 parameters in reverse order means that the function knows where to
4687 find its first parameter, which tells it the number and type of the
4690 \b The callee may also wish to decrease \c{SP} further, so as to
4691 allocate space on the stack for local variables, which will then be
4692 accessible at negative offsets from \c{BP}.
4694 \b The callee, if it wishes to return a value to the caller, should
4695 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
4696 of the value. Floating-point results are sometimes (depending on the
4697 compiler) returned in \c{ST0}.
4699 \b Once the callee has finished processing, it restores \c{SP} from
4700 \c{BP} if it had allocated local stack space, then pops the previous
4701 value of \c{BP}, and returns via \c{RETN} or \c{RETF} depending on
4704 \b When the caller regains control from the callee, the function
4705 parameters are still on the stack, so it typically adds an immediate
4706 constant to \c{SP} to remove them (instead of executing a number of
4707 slow \c{POP} instructions). Thus, if a function is accidentally
4708 called with the wrong number of parameters due to a prototype
4709 mismatch, the stack will still be returned to a sensible state since
4710 the caller, which \e{knows} how many parameters it pushed, does the
4713 It is instructive to compare this calling convention with that for
4714 Pascal programs (described in \k{16bpfunc}). Pascal has a simpler
4715 convention, since no functions have variable numbers of parameters.
4716 Therefore the callee knows how many parameters it should have been
4717 passed, and is able to deallocate them from the stack itself by
4718 passing an immediate argument to the \c{RET} or \c{RETF}
4719 instruction, so the caller does not have to do it. Also, the
4720 parameters are pushed in left-to-right order, not right-to-left,
4721 which means that a compiler can give better guarantees about
4722 sequence points without performance suffering.
4724 Thus, you would define a function in C style in the following way.
4725 The following example is for small model:
4732 \c sub sp,0x40 ; 64 bytes of local stack space
4733 \c mov bx,[bp+4] ; first parameter to function
4737 \c mov sp,bp ; undo "sub sp,0x40" above
4741 For a large-model function, you would replace \c{RET} by \c{RETF},
4742 and look for the first parameter at \c{[BP+6]} instead of
4743 \c{[BP+4]}. Of course, if one of the parameters is a pointer, then
4744 the offsets of \e{subsequent} parameters will change depending on
4745 the memory model as well: far pointers take up four bytes on the
4746 stack when passed as a parameter, whereas near pointers take up two.
4748 At the other end of the process, to call a C function from your
4749 assembly code, you would do something like this:
4753 \c ; and then, further down...
4755 \c push word [myint] ; one of my integer variables
4756 \c push word mystring ; pointer into my data segment
4758 \c add sp,byte 4 ; `byte' saves space
4760 \c ; then those data items...
4765 \c mystring db 'This number -> %d <- should be 1234',10,0
4767 This piece of code is the small-model assembly equivalent of the C
4770 \c int myint = 1234;
4771 \c printf("This number -> %d <- should be 1234\n", myint);
4773 In large model, the function-call code might look more like this. In
4774 this example, it is assumed that \c{DS} already holds the segment
4775 base of the segment \c{_DATA}. If not, you would have to initialise
4778 \c push word [myint]
4779 \c push word seg mystring ; Now push the segment, and...
4780 \c push word mystring ; ... offset of "mystring"
4784 The integer value still takes up one word on the stack, since large
4785 model does not affect the size of the \c{int} data type. The first
4786 argument (pushed last) to \c{printf}, however, is a data pointer,
4787 and therefore has to contain a segment and offset part. The segment
4788 should be stored second in memory, and therefore must be pushed
4789 first. (Of course, \c{PUSH DS} would have been a shorter instruction
4790 than \c{PUSH WORD SEG mystring}, if \c{DS} was set up as the above
4791 example assumed.) Then the actual call becomes a far call, since
4792 functions expect far calls in large model; and \c{SP} has to be
4793 increased by 6 rather than 4 afterwards to make up for the extra
4797 \S{16cdata} Accessing Data Items
4799 To get at the contents of C variables, or to declare variables which
4800 C can access, you need only declare the names as \c{GLOBAL} or
4801 \c{EXTERN}. (Again, the names require leading underscores, as stated
4802 in \k{16cunder}.) Thus, a C variable declared as \c{int i} can be
4803 accessed from assembler as
4809 And to declare your own integer variable which C programs can access
4810 as \c{extern int j}, you do this (making sure you are assembling in
4811 the \c{_DATA} segment, if necessary):
4817 To access a C array, you need to know the size of the components of
4818 the array. For example, \c{int} variables are two bytes long, so if
4819 a C program declares an array as \c{int a[10]}, you can access
4820 \c{a[3]} by coding \c{mov ax,[_a+6]}. (The byte offset 6 is obtained
4821 by multiplying the desired array index, 3, by the size of the array
4822 element, 2.) The sizes of the C base types in 16-bit compilers are:
4823 1 for \c{char}, 2 for \c{short} and \c{int}, 4 for \c{long} and
4824 \c{float}, and 8 for \c{double}.
4826 To access a C \i{data structure}, you need to know the offset from
4827 the base of the structure to the field you are interested in. You
4828 can either do this by converting the C structure definition into a
4829 NASM structure definition (using \i\c{STRUC}), or by calculating the
4830 one offset and using just that.
4832 To do either of these, you should read your C compiler's manual to
4833 find out how it organises data structures. NASM gives no special
4834 alignment to structure members in its own \c{STRUC} macro, so you
4835 have to specify alignment yourself if the C compiler generates it.
4836 Typically, you might find that a structure like
4843 might be four bytes long rather than three, since the \c{int} field
4844 would be aligned to a two-byte boundary. However, this sort of
4845 feature tends to be a configurable option in the C compiler, either
4846 using command-line options or \c{#pragma} lines, so you have to find
4847 out how your own compiler does it.
4850 \S{16cmacro} \i\c{c16.mac}: Helper Macros for the 16-bit C Interface
4852 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4853 directory, is a file \c{c16.mac} of macros. It defines three macros:
4854 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
4855 used for C-style procedure definitions, and they automate a lot of
4856 the work involved in keeping track of the calling convention.
4858 (An alternative, TASM compatible form of \c{arg} is also now built
4859 into NASM's preprocessor. See \k{tasmcompat} for details.)
4861 An example of an assembly function using the macro set is given
4868 \c mov ax,[bp + %$i]
4869 \c mov bx,[bp + %$j]
4874 This defines \c{_nearproc} to be a procedure taking two arguments,
4875 the first (\c{i}) an integer and the second (\c{j}) a pointer to an
4876 integer. It returns \c{i + *j}.
4878 Note that the \c{arg} macro has an \c{EQU} as the first line of its
4879 expansion, and since the label before the macro call gets prepended
4880 to the first line of the expanded macro, the \c{EQU} works, defining
4881 \c{%$i} to be an offset from \c{BP}. A context-local variable is
4882 used, local to the context pushed by the \c{proc} macro and popped
4883 by the \c{endproc} macro, so that the same argument name can be used
4884 in later procedures. Of course, you don't \e{have} to do that.
4886 The macro set produces code for near functions (tiny, small and
4887 compact-model code) by default. You can have it generate far
4888 functions (medium, large and huge-model code) by means of coding
4889 \I\c{FARCODE}\c{%define FARCODE}. This changes the kind of return
4890 instruction generated by \c{endproc}, and also changes the starting
4891 point for the argument offsets. The macro set contains no intrinsic
4892 dependency on whether data pointers are far or not.
4894 \c{arg} can take an optional parameter, giving the size of the
4895 argument. If no size is given, 2 is assumed, since it is likely that
4896 many function parameters will be of type \c{int}.
4898 The large-model equivalent of the above function would look like this:
4906 \c mov ax,[bp + %$i]
4907 \c mov bx,[bp + %$j]
4908 \c mov es,[bp + %$j + 2]
4913 This makes use of the argument to the \c{arg} macro to define a
4914 parameter of size 4, because \c{j} is now a far pointer. When we
4915 load from \c{j}, we must load a segment and an offset.
4918 \H{16bp} Interfacing to \i{Borland Pascal} Programs
4920 Interfacing to Borland Pascal programs is similar in concept to
4921 interfacing to 16-bit C programs. The differences are:
4923 \b The leading underscore required for interfacing to C programs is
4924 not required for Pascal.
4926 \b The memory model is always large: functions are far, data
4927 pointers are far, and no data item can be more than 64K long.
4928 (Actually, some functions are near, but only those functions that
4929 are local to a Pascal unit and never called from outside it. All
4930 assembly functions that Pascal calls, and all Pascal functions that
4931 assembly routines are able to call, are far.) However, all static
4932 data declared in a Pascal program goes into the default data
4933 segment, which is the one whose segment address will be in \c{DS}
4934 when control is passed to your assembly code. The only things that
4935 do not live in the default data segment are local variables (they
4936 live in the stack segment) and dynamically allocated variables. All
4937 data \e{pointers}, however, are far.
4939 \b The function calling convention is different - described below.
4941 \b Some data types, such as strings, are stored differently.
4943 \b There are restrictions on the segment names you are allowed to
4944 use - Borland Pascal will ignore code or data declared in a segment
4945 it doesn't like the name of. The restrictions are described below.
4948 \S{16bpfunc} The Pascal Calling Convention
4950 \I{functions, Pascal calling convention}\I{Pascal calling
4951 convention}The 16-bit Pascal calling convention is as follows. In
4952 the following description, the words \e{caller} and \e{callee} are
4953 used to denote the function doing the calling and the function which
4956 \b The caller pushes the function's parameters on the stack, one
4957 after another, in normal order (left to right, so that the first
4958 argument specified to the function is pushed first).
4960 \b The caller then executes a far \c{CALL} instruction to pass
4961 control to the callee.
4963 \b The callee receives control, and typically (although this is not
4964 actually necessary, in functions which do not need to access their
4965 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
4966 be able to use \c{BP} as a base pointer to find its parameters on
4967 the stack. However, the caller was probably doing this too, so part
4968 of the calling convention states that \c{BP} must be preserved by
4969 any function. Hence the callee, if it is going to set up \c{BP} as a
4970 \i{frame pointer}, must push the previous value first.
4972 \b The callee may then access its parameters relative to \c{BP}.
4973 The word at \c{[BP]} holds the previous value of \c{BP} as it was
4974 pushed. The next word, at \c{[BP+2]}, holds the offset part of the
4975 return address, and the next one at \c{[BP+4]} the segment part. The
4976 parameters begin at \c{[BP+6]}. The rightmost parameter of the
4977 function, since it was pushed last, is accessible at this offset
4978 from \c{BP}; the others follow, at successively greater offsets.
4980 \b The callee may also wish to decrease \c{SP} further, so as to
4981 allocate space on the stack for local variables, which will then be
4982 accessible at negative offsets from \c{BP}.
4984 \b The callee, if it wishes to return a value to the caller, should
4985 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
4986 of the value. Floating-point results are returned in \c{ST0}.
4987 Results of type \c{Real} (Borland's own custom floating-point data
4988 type, not handled directly by the FPU) are returned in \c{DX:BX:AX}.
4989 To return a result of type \c{String}, the caller pushes a pointer
4990 to a temporary string before pushing the parameters, and the callee
4991 places the returned string value at that location. The pointer is
4992 not a parameter, and should not be removed from the stack by the
4993 \c{RETF} instruction.
4995 \b Once the callee has finished processing, it restores \c{SP} from
4996 \c{BP} if it had allocated local stack space, then pops the previous
4997 value of \c{BP}, and returns via \c{RETF}. It uses the form of
4998 \c{RETF} with an immediate parameter, giving the number of bytes
4999 taken up by the parameters on the stack. This causes the parameters
5000 to be removed from the stack as a side effect of the return
5003 \b When the caller regains control from the callee, the function
5004 parameters have already been removed from the stack, so it needs to
5007 Thus, you would define a function in Pascal style, taking two
5008 \c{Integer}-type parameters, in the following way:
5014 \c sub sp,0x40 ; 64 bytes of local stack space
5015 \c mov bx,[bp+8] ; first parameter to function
5016 \c mov bx,[bp+6] ; second parameter to function
5020 \c mov sp,bp ; undo "sub sp,0x40" above
5022 \c retf 4 ; total size of params is 4
5024 At the other end of the process, to call a Pascal function from your
5025 assembly code, you would do something like this:
5029 \c ; and then, further down...
5031 \c push word seg mystring ; Now push the segment, and...
5032 \c push word mystring ; ... offset of "mystring"
5033 \c push word [myint] ; one of my variables
5034 \c call far SomeFunc
5036 This is equivalent to the Pascal code
5038 \c procedure SomeFunc(String: PChar; Int: Integer);
5039 \c SomeFunc(@mystring, myint);
5042 \S{16bpseg} Borland Pascal \I{segment names, Borland Pascal}Segment
5045 Since Borland Pascal's internal unit file format is completely
5046 different from \c{OBJ}, it only makes a very sketchy job of actually
5047 reading and understanding the various information contained in a
5048 real \c{OBJ} file when it links that in. Therefore an object file
5049 intended to be linked to a Pascal program must obey a number of
5052 \b Procedures and functions must be in a segment whose name is
5053 either \c{CODE}, \c{CSEG}, or something ending in \c{_TEXT}.
5055 \b Initialised data must be in a segment whose name is either
5056 \c{CONST} or something ending in \c{_DATA}.
5058 \b Uninitialised data must be in a segment whose name is either
5059 \c{DATA}, \c{DSEG}, or something ending in \c{_BSS}.
5061 \b Any other segments in the object file are completely ignored.
5062 \c{GROUP} directives and segment attributes are also ignored.
5065 \S{16bpmacro} Using \i\c{c16.mac} With Pascal Programs
5067 The \c{c16.mac} macro package, described in \k{16cmacro}, can also
5068 be used to simplify writing functions to be called from Pascal
5069 programs, if you code \I\c{PASCAL}\c{%define PASCAL}. This
5070 definition ensures that functions are far (it implies
5071 \i\c{FARCODE}), and also causes procedure return instructions to be
5072 generated with an operand.
5074 Defining \c{PASCAL} does not change the code which calculates the
5075 argument offsets; you must declare your function's arguments in
5076 reverse order. For example:
5084 \c mov ax,[bp + %$i]
5085 \c mov bx,[bp + %$j]
5086 \c mov es,[bp + %$j + 2]
5091 This defines the same routine, conceptually, as the example in
5092 \k{16cmacro}: it defines a function taking two arguments, an integer
5093 and a pointer to an integer, which returns the sum of the integer
5094 and the contents of the pointer. The only difference between this
5095 code and the large-model C version is that \c{PASCAL} is defined
5096 instead of \c{FARCODE}, and that the arguments are declared in
5100 \C{32bit} Writing 32-bit Code (Unix, Win32, DJGPP)
5102 This chapter attempts to cover some of the common issues involved
5103 when writing 32-bit code, to run under \i{Win32} or Unix, or to be
5104 linked with C code generated by a Unix-style C compiler such as
5105 \i{DJGPP}. It covers how to write assembly code to interface with
5106 32-bit C routines, and how to write position-independent code for
5109 Almost all 32-bit code, and in particular all code running under
5110 \c{Win32}, \c{DJGPP} or any of the PC Unix variants, runs in \I{flat
5111 memory model}\e{flat} memory model. This means that the segment registers
5112 and paging have already been set up to give you the same 32-bit 4Gb
5113 address space no matter what segment you work relative to, and that
5114 you should ignore all segment registers completely. When writing
5115 flat-model application code, you never need to use a segment
5116 override or modify any segment register, and the code-section
5117 addresses you pass to \c{CALL} and \c{JMP} live in the same address
5118 space as the data-section addresses you access your variables by and
5119 the stack-section addresses you access local variables and procedure
5120 parameters by. Every address is 32 bits long and contains only an
5124 \H{32c} Interfacing to 32-bit C Programs
5126 A lot of the discussion in \k{16c}, about interfacing to 16-bit C
5127 programs, still applies when working in 32 bits. The absence of
5128 memory models or segmentation worries simplifies things a lot.
5131 \S{32cunder} External Symbol Names
5133 Most 32-bit C compilers share the convention used by 16-bit
5134 compilers, that the names of all global symbols (functions or data)
5135 they define are formed by prefixing an underscore to the name as it
5136 appears in the C program. However, not all of them do: the \c{ELF}
5137 specification states that C symbols do \e{not} have a leading
5138 underscore on their assembly-language names.
5140 The older Linux \c{a.out} C compiler, all \c{Win32} compilers,
5141 \c{DJGPP}, and \c{NetBSD} and \c{FreeBSD}, all use the leading
5142 underscore; for these compilers, the macros \c{cextern} and
5143 \c{cglobal}, as given in \k{16cunder}, will still work. For \c{ELF},
5144 though, the leading underscore should not be used.
5147 \S{32cfunc} Function Definitions and Function Calls
5149 \I{functions, C calling convention}The \i{C calling convention}The C
5150 calling convention in 32-bit programs is as follows. In the
5151 following description, the words \e{caller} and \e{callee} are used
5152 to denote the function doing the calling and the function which gets
5155 \b The caller pushes the function's parameters on the stack, one
5156 after another, in reverse order (right to left, so that the first
5157 argument specified to the function is pushed last).
5159 \b The caller then executes a near \c{CALL} instruction to pass
5160 control to the callee.
5162 \b The callee receives control, and typically (although this is not
5163 actually necessary, in functions which do not need to access their
5164 parameters) starts by saving the value of \c{ESP} in \c{EBP} so as
5165 to be able to use \c{EBP} as a base pointer to find its parameters
5166 on the stack. However, the caller was probably doing this too, so
5167 part of the calling convention states that \c{EBP} must be preserved
5168 by any C function. Hence the callee, if it is going to set up
5169 \c{EBP} as a \i{frame pointer}, must push the previous value first.
5171 \b The callee may then access its parameters relative to \c{EBP}.
5172 The doubleword at \c{[EBP]} holds the previous value of \c{EBP} as
5173 it was pushed; the next doubleword, at \c{[EBP+4]}, holds the return
5174 address, pushed implicitly by \c{CALL}. The parameters start after
5175 that, at \c{[EBP+8]}. The leftmost parameter of the function, since
5176 it was pushed last, is accessible at this offset from \c{EBP}; the
5177 others follow, at successively greater offsets. Thus, in a function
5178 such as \c{printf} which takes a variable number of parameters, the
5179 pushing of the parameters in reverse order means that the function
5180 knows where to find its first parameter, which tells it the number
5181 and type of the remaining ones.
5183 \b The callee may also wish to decrease \c{ESP} further, so as to
5184 allocate space on the stack for local variables, which will then be
5185 accessible at negative offsets from \c{EBP}.
5187 \b The callee, if it wishes to return a value to the caller, should
5188 leave the value in \c{AL}, \c{AX} or \c{EAX} depending on the size
5189 of the value. Floating-point results are typically returned in
5192 \b Once the callee has finished processing, it restores \c{ESP} from
5193 \c{EBP} if it had allocated local stack space, then pops the previous
5194 value of \c{EBP}, and returns via \c{RET} (equivalently, \c{RETN}).
5196 \b When the caller regains control from the callee, the function
5197 parameters are still on the stack, so it typically adds an immediate
5198 constant to \c{ESP} to remove them (instead of executing a number of
5199 slow \c{POP} instructions). Thus, if a function is accidentally
5200 called with the wrong number of parameters due to a prototype
5201 mismatch, the stack will still be returned to a sensible state since
5202 the caller, which \e{knows} how many parameters it pushed, does the
5205 There is an alternative calling convention used by Win32 programs
5206 for Windows API calls, and also for functions called \e{by} the
5207 Windows API such as window procedures: they follow what Microsoft
5208 calls the \c{__stdcall} convention. This is slightly closer to the
5209 Pascal convention, in that the callee clears the stack by passing a
5210 parameter to the \c{RET} instruction. However, the parameters are
5211 still pushed in right-to-left order.
5213 Thus, you would define a function in C style in the following way:
5220 \c sub esp,0x40 ; 64 bytes of local stack space
5221 \c mov ebx,[ebp+8] ; first parameter to function
5225 \c leave ; mov esp,ebp / pop ebp
5228 At the other end of the process, to call a C function from your
5229 assembly code, you would do something like this:
5233 \c ; and then, further down...
5235 \c push dword [myint] ; one of my integer variables
5236 \c push dword mystring ; pointer into my data segment
5238 \c add esp,byte 8 ; `byte' saves space
5240 \c ; then those data items...
5245 \c mystring db 'This number -> %d <- should be 1234',10,0
5247 This piece of code is the assembly equivalent of the C code
5249 \c int myint = 1234;
5250 \c printf("This number -> %d <- should be 1234\n", myint);
5253 \S{32cdata} Accessing Data Items
5255 To get at the contents of C variables, or to declare variables which
5256 C can access, you need only declare the names as \c{GLOBAL} or
5257 \c{EXTERN}. (Again, the names require leading underscores, as stated
5258 in \k{32cunder}.) Thus, a C variable declared as \c{int i} can be
5259 accessed from assembler as
5264 And to declare your own integer variable which C programs can access
5265 as \c{extern int j}, you do this (making sure you are assembling in
5266 the \c{_DATA} segment, if necessary):
5271 To access a C array, you need to know the size of the components of
5272 the array. For example, \c{int} variables are four bytes long, so if
5273 a C program declares an array as \c{int a[10]}, you can access
5274 \c{a[3]} by coding \c{mov ax,[_a+12]}. (The byte offset 12 is obtained
5275 by multiplying the desired array index, 3, by the size of the array
5276 element, 4.) The sizes of the C base types in 32-bit compilers are:
5277 1 for \c{char}, 2 for \c{short}, 4 for \c{int}, \c{long} and
5278 \c{float}, and 8 for \c{double}. Pointers, being 32-bit addresses,
5279 are also 4 bytes long.
5281 To access a C \i{data structure}, you need to know the offset from
5282 the base of the structure to the field you are interested in. You
5283 can either do this by converting the C structure definition into a
5284 NASM structure definition (using \c{STRUC}), or by calculating the
5285 one offset and using just that.
5287 To do either of these, you should read your C compiler's manual to
5288 find out how it organises data structures. NASM gives no special
5289 alignment to structure members in its own \i\c{STRUC} macro, so you
5290 have to specify alignment yourself if the C compiler generates it.
5291 Typically, you might find that a structure like
5298 might be eight bytes long rather than five, since the \c{int} field
5299 would be aligned to a four-byte boundary. However, this sort of
5300 feature is sometimes a configurable option in the C compiler, either
5301 using command-line options or \c{#pragma} lines, so you have to find
5302 out how your own compiler does it.
5305 \S{32cmacro} \i\c{c32.mac}: Helper Macros for the 32-bit C Interface
5307 Included in the NASM archives, in the \I{misc directory}\c{misc}
5308 directory, is a file \c{c32.mac} of macros. It defines three macros:
5309 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
5310 used for C-style procedure definitions, and they automate a lot of
5311 the work involved in keeping track of the calling convention.
5313 An example of an assembly function using the macro set is given
5320 \c mov eax,[ebp + %$i]
5321 \c mov ebx,[ebp + %$j]
5326 This defines \c{_proc32} to be a procedure taking two arguments, the
5327 first (\c{i}) an integer and the second (\c{j}) a pointer to an
5328 integer. It returns \c{i + *j}.
5330 Note that the \c{arg} macro has an \c{EQU} as the first line of its
5331 expansion, and since the label before the macro call gets prepended
5332 to the first line of the expanded macro, the \c{EQU} works, defining
5333 \c{%$i} to be an offset from \c{BP}. A context-local variable is
5334 used, local to the context pushed by the \c{proc} macro and popped
5335 by the \c{endproc} macro, so that the same argument name can be used
5336 in later procedures. Of course, you don't \e{have} to do that.
5338 \c{arg} can take an optional parameter, giving the size of the
5339 argument. If no size is given, 4 is assumed, since it is likely that
5340 many function parameters will be of type \c{int} or pointers.
5343 \H{picdll} Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF \i{Shared
5346 \c{ELF} replaced the older \c{a.out} object file format under Linux
5347 because it contains support for \i{position-independent code}
5348 (\i{PIC}), which makes writing shared libraries much easier. NASM
5349 supports the \c{ELF} position-independent code features, so you can
5350 write Linux \c{ELF} shared libraries in NASM.
5352 \i{NetBSD}, and its close cousins \i{FreeBSD} and \i{OpenBSD}, take
5353 a different approach by hacking PIC support into the \c{a.out}
5354 format. NASM supports this as the \i\c{aoutb} output format, so you
5355 can write \i{BSD} shared libraries in NASM too.
5357 The operating system loads a PIC shared library by memory-mapping
5358 the library file at an arbitrarily chosen point in the address space
5359 of the running process. The contents of the library's code section
5360 must therefore not depend on where it is loaded in memory.
5362 Therefore, you cannot get at your variables by writing code like
5365 \c mov eax,[myvar] ; WRONG
5367 Instead, the linker provides an area of memory called the
5368 \i\e{global offset table}, or \i{GOT}; the GOT is situated at a
5369 constant distance from your library's code, so if you can find out
5370 where your library is loaded (which is typically done using a
5371 \c{CALL} and \c{POP} combination), you can obtain the address of the
5372 GOT, and you can then load the addresses of your variables out of
5373 linker-generated entries in the GOT.
5375 The \e{data} section of a PIC shared library does not have these
5376 restrictions: since the data section is writable, it has to be
5377 copied into memory anyway rather than just paged in from the library
5378 file, so as long as it's being copied it can be relocated too. So
5379 you can put ordinary types of relocation in the data section without
5380 too much worry (but see \k{picglobal} for a caveat).
5383 \S{picgot} Obtaining the Address of the GOT
5385 Each code module in your shared library should define the GOT as an
5388 \c extern _GLOBAL_OFFSET_TABLE_ ; in ELF
5389 \c extern __GLOBAL_OFFSET_TABLE_ ; in BSD a.out
5391 At the beginning of any function in your shared library which plans
5392 to access your data or BSS sections, you must first calculate the
5393 address of the GOT. This is typically done by writing the function
5402 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-.get_GOT wrt ..gotpc
5404 \c ; the function body comes here
5411 (For BSD, again, the symbol \c{_GLOBAL_OFFSET_TABLE} requires a
5412 second leading underscore.)
5414 The first two lines of this function are simply the standard C
5415 prologue to set up a stack frame, and the last three lines are
5416 standard C function epilogue. The third line, and the fourth to last
5417 line, save and restore the \c{EBX} register, because PIC shared
5418 libraries use this register to store the address of the GOT.
5420 The interesting bit is the \c{CALL} instruction and the following
5421 two lines. The \c{CALL} and \c{POP} combination obtains the address
5422 of the label \c{.get_GOT}, without having to know in advance where
5423 the program was loaded (since the \c{CALL} instruction is encoded
5424 relative to the current position). The \c{ADD} instruction makes use
5425 of one of the special PIC relocation types: \i{GOTPC relocation}.
5426 With the \i\c{WRT ..gotpc} qualifier specified, the symbol
5427 referenced (here \c{_GLOBAL_OFFSET_TABLE_}, the special symbol
5428 assigned to the GOT) is given as an offset from the beginning of the
5429 section. (Actually, \c{ELF} encodes it as the offset from the operand
5430 field of the \c{ADD} instruction, but NASM simplifies this
5431 deliberately, so you do things the same way for both \c{ELF} and
5432 \c{BSD}.) So the instruction then \e{adds} the beginning of the section,
5433 to get the real address of the GOT, and subtracts the value of
5434 \c{.get_GOT} which it knows is in \c{EBX}. Therefore, by the time
5435 that instruction has finished, \c{EBX} contains the address of the GOT.
5437 If you didn't follow that, don't worry: it's never necessary to
5438 obtain the address of the GOT by any other means, so you can put
5439 those three instructions into a macro and safely ignore them:
5446 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc
5450 \S{piclocal} Finding Your Local Data Items
5452 Having got the GOT, you can then use it to obtain the addresses of
5453 your data items. Most variables will reside in the sections you have
5454 declared; they can be accessed using the \I{GOTOFF
5455 relocation}\c{..gotoff} special \I\c{WRT ..gotoff}\c{WRT} type. The
5456 way this works is like this:
5458 \c lea eax,[ebx+myvar wrt ..gotoff]
5460 The expression \c{myvar wrt ..gotoff} is calculated, when the shared
5461 library is linked, to be the offset to the local variable \c{myvar}
5462 from the beginning of the GOT. Therefore, adding it to \c{EBX} as
5463 above will place the real address of \c{myvar} in \c{EAX}.
5465 If you declare variables as \c{GLOBAL} without specifying a size for
5466 them, they are shared between code modules in the library, but do
5467 not get exported from the library to the program that loaded it.
5468 They will still be in your ordinary data and BSS sections, so you
5469 can access them in the same way as local variables, using the above
5470 \c{..gotoff} mechanism.
5472 Note that due to a peculiarity of the way BSD \c{a.out} format
5473 handles this relocation type, there must be at least one non-local
5474 symbol in the same section as the address you're trying to access.
5477 \S{picextern} Finding External and Common Data Items
5479 If your library needs to get at an external variable (external to
5480 the \e{library}, not just to one of the modules within it), you must
5481 use the \I{GOT relocations}\I\c{WRT ..got}\c{..got} type to get at
5482 it. The \c{..got} type, instead of giving you the offset from the
5483 GOT base to the variable, gives you the offset from the GOT base to
5484 a GOT \e{entry} containing the address of the variable. The linker
5485 will set up this GOT entry when it builds the library, and the
5486 dynamic linker will place the correct address in it at load time. So
5487 to obtain the address of an external variable \c{extvar} in \c{EAX},
5490 \c mov eax,[ebx+extvar wrt ..got]
5492 This loads the address of \c{extvar} out of an entry in the GOT. The
5493 linker, when it builds the shared library, collects together every
5494 relocation of type \c{..got}, and builds the GOT so as to ensure it
5495 has every necessary entry present.
5497 Common variables must also be accessed in this way.
5500 \S{picglobal} Exporting Symbols to the Library User
5502 If you want to export symbols to the user of the library, you have
5503 to declare whether they are functions or data, and if they are data,
5504 you have to give the size of the data item. This is because the
5505 dynamic linker has to build \I{PLT}\i{procedure linkage table}
5506 entries for any exported functions, and also moves exported data
5507 items away from the library's data section in which they were
5510 So to export a function to users of the library, you must use
5512 \c global func:function ; declare it as a function
5518 And to export a data item such as an array, you would have to code
5520 \c global array:data array.end-array ; give the size too
5525 Be careful: If you export a variable to the library user, by
5526 declaring it as \c{GLOBAL} and supplying a size, the variable will
5527 end up living in the data section of the main program, rather than
5528 in your library's data section, where you declared it. So you will
5529 have to access your own global variable with the \c{..got} mechanism
5530 rather than \c{..gotoff}, as if it were external (which,
5531 effectively, it has become).
5533 Equally, if you need to store the address of an exported global in
5534 one of your data sections, you can't do it by means of the standard
5537 \c dataptr: dd global_data_item ; WRONG
5539 NASM will interpret this code as an ordinary relocation, in which
5540 \c{global_data_item} is merely an offset from the beginning of the
5541 \c{.data} section (or whatever); so this reference will end up
5542 pointing at your data section instead of at the exported global
5543 which resides elsewhere.
5545 Instead of the above code, then, you must write
5547 \c dataptr: dd global_data_item wrt ..sym
5549 which makes use of the special \c{WRT} type \I\c{WRT ..sym}\c{..sym}
5550 to instruct NASM to search the symbol table for a particular symbol
5551 at that address, rather than just relocating by section base.
5553 Either method will work for functions: referring to one of your
5554 functions by means of
5556 \c funcptr: dd my_function
5558 will give the user the address of the code you wrote, whereas
5560 \c funcptr: dd my_function wrt .sym
5562 will give the address of the procedure linkage table for the
5563 function, which is where the calling program will \e{believe} the
5564 function lives. Either address is a valid way to call the function.
5567 \S{picproc} Calling Procedures Outside the Library
5569 Calling procedures outside your shared library has to be done by
5570 means of a \i\e{procedure linkage table}, or \i{PLT}. The PLT is
5571 placed at a known offset from where the library is loaded, so the
5572 library code can make calls to the PLT in a position-independent
5573 way. Within the PLT there is code to jump to offsets contained in
5574 the GOT, so function calls to other shared libraries or to routines
5575 in the main program can be transparently passed off to their real
5578 To call an external routine, you must use another special PIC
5579 relocation type, \I{PLT relocations}\i\c{WRT ..plt}. This is much
5580 easier than the GOT-based ones: you simply replace calls such as
5581 \c{CALL printf} with the PLT-relative version \c{CALL printf WRT
5585 \S{link} Generating the Library File
5587 Having written some code modules and assembled them to \c{.o} files,
5588 you then generate your shared library with a command such as
5590 \c ld -shared -o library.so module1.o module2.o # for ELF
5591 \c ld -Bshareable -o library.so module1.o module2.o # for BSD
5593 For ELF, if your shared library is going to reside in system
5594 directories such as \c{/usr/lib} or \c{/lib}, it is usually worth
5595 using the \i\c{-soname} flag to the linker, to store the final
5596 library file name, with a version number, into the library:
5598 \c ld -shared -soname library.so.1 -o library.so.1.2 *.o
5600 You would then copy \c{library.so.1.2} into the library directory,
5601 and create \c{library.so.1} as a symbolic link to it.
5604 \C{mixsize} Mixing 16 and 32 Bit Code
5606 This chapter tries to cover some of the issues, largely related to
5607 unusual forms of addressing and jump instructions, encountered when
5608 writing operating system code such as protected-mode initialisation
5609 routines, which require code that operates in mixed segment sizes,
5610 such as code in a 16-bit segment trying to modify data in a 32-bit
5611 one, or jumps between different-size segments.
5614 \H{mixjump} Mixed-Size Jumps\I{jumps, mixed-size}
5616 \I{operating system, writing}\I{writing operating systems}The most
5617 common form of \i{mixed-size instruction} is the one used when
5618 writing a 32-bit OS: having done your setup in 16-bit mode, such as
5619 loading the kernel, you then have to boot it by switching into
5620 protected mode and jumping to the 32-bit kernel start address. In a
5621 fully 32-bit OS, this tends to be the \e{only} mixed-size
5622 instruction you need, since everything before it can be done in pure
5623 16-bit code, and everything after it can be pure 32-bit.
5625 This jump must specify a 48-bit far address, since the target
5626 segment is a 32-bit one. However, it must be assembled in a 16-bit
5627 segment, so just coding, for example,
5629 \c jmp 0x1234:0x56789ABC ; wrong!
5631 will not work, since the offset part of the address will be
5632 truncated to \c{0x9ABC} and the jump will be an ordinary 16-bit far
5635 The Linux kernel setup code gets round the inability of \c{as86} to
5636 generate the required instruction by coding it manually, using
5637 \c{DB} instructions. NASM can go one better than that, by actually
5638 generating the right instruction itself. Here's how to do it right:
5640 \c jmp dword 0x1234:0x56789ABC ; right
5642 \I\c{JMP DWORD}The \c{DWORD} prefix (strictly speaking, it should
5643 come \e{after} the colon, since it is declaring the \e{offset} field
5644 to be a doubleword; but NASM will accept either form, since both are
5645 unambiguous) forces the offset part to be treated as far, in the
5646 assumption that you are deliberately writing a jump from a 16-bit
5647 segment to a 32-bit one.
5649 You can do the reverse operation, jumping from a 32-bit segment to a
5650 16-bit one, by means of the \c{WORD} prefix:
5652 \c jmp word 0x8765:0x4321 ; 32 to 16 bit
5654 If the \c{WORD} prefix is specified in 16-bit mode, or the \c{DWORD}
5655 prefix in 32-bit mode, they will be ignored, since each is
5656 explicitly forcing NASM into a mode it was in anyway.
5659 \H{mixaddr} Addressing Between Different-Size Segments\I{addressing,
5660 mixed-size}\I{mixed-size addressing}
5662 If your OS is mixed 16 and 32-bit, or if you are writing a DOS
5663 extender, you are likely to have to deal with some 16-bit segments
5664 and some 32-bit ones. At some point, you will probably end up
5665 writing code in a 16-bit segment which has to access data in a
5666 32-bit segment, or vice versa.
5668 If the data you are trying to access in a 32-bit segment lies within
5669 the first 64K of the segment, you may be able to get away with using
5670 an ordinary 16-bit addressing operation for the purpose; but sooner
5671 or later, you will want to do 32-bit addressing from 16-bit mode.
5673 The easiest way to do this is to make sure you use a register for
5674 the address, since any effective address containing a 32-bit
5675 register is forced to be a 32-bit address. So you can do
5677 \c mov eax,offset_into_32_bit_segment_specified_by_fs
5678 \c mov dword [fs:eax],0x11223344
5680 This is fine, but slightly cumbersome (since it wastes an
5681 instruction and a register) if you already know the precise offset
5682 you are aiming at. The x86 architecture does allow 32-bit effective
5683 addresses to specify nothing but a 4-byte offset, so why shouldn't
5684 NASM be able to generate the best instruction for the purpose?
5686 It can. As in \k{mixjump}, you need only prefix the address with the
5687 \c{DWORD} keyword, and it will be forced to be a 32-bit address:
5689 \c mov dword [fs:dword my_offset],0x11223344
5691 Also as in \k{mixjump}, NASM is not fussy about whether the
5692 \c{DWORD} prefix comes before or after the segment override, so
5693 arguably a nicer-looking way to code the above instruction is
5695 \c mov dword [dword fs:my_offset],0x11223344
5697 Don't confuse the \c{DWORD} prefix \e{outside} the square brackets,
5698 which controls the size of the data stored at the address, with the
5699 one \c{inside} the square brackets which controls the length of the
5700 address itself. The two can quite easily be different:
5702 \c mov word [dword 0x12345678],0x9ABC
5704 This moves 16 bits of data to an address specified by a 32-bit
5707 You can also specify \c{WORD} or \c{DWORD} prefixes along with the
5708 \c{FAR} prefix to indirect far jumps or calls. For example:
5710 \c call dword far [fs:word 0x4321]
5712 This instruction contains an address specified by a 16-bit offset;
5713 it loads a 48-bit far pointer from that (16-bit segment and 32-bit
5714 offset), and calls that address.
5717 \H{mixother} Other Mixed-Size Instructions
5719 The other way you might want to access data might be using the
5720 string instructions (\c{LODSx}, \c{STOSx} and so on) or the
5721 \c{XLATB} instruction. These instructions, since they take no
5722 parameters, might seem to have no easy way to make them perform
5723 32-bit addressing when assembled in a 16-bit segment.
5725 This is the purpose of NASM's \i\c{a16} and \i\c{a32} prefixes. If
5726 you are coding \c{LODSB} in a 16-bit segment but it is supposed to
5727 be accessing a string in a 32-bit segment, you should load the
5728 desired address into \c{ESI} and then code
5732 The prefix forces the addressing size to 32 bits, meaning that
5733 \c{LODSB} loads from \c{[DS:ESI]} instead of \c{[DS:SI]}. To access
5734 a string in a 16-bit segment when coding in a 32-bit one, the
5735 corresponding \c{a16} prefix can be used.
5737 The \c{a16} and \c{a32} prefixes can be applied to any instruction
5738 in NASM's instruction table, but most of them can generate all the
5739 useful forms without them. The prefixes are necessary only for
5740 instructions with implicit addressing: \c{CMPSx} (\k{insCMPSB}),
5741 \c{SCASx} (\k{insSCASB}), \c{LODSx} (\k{insLODSB}), \c{STOSx}
5742 (\k{insSTOSB}), \c{MOVSx} (\k{insMOVSB}), \c{INSx} (\k{insINSB}),
5743 \c{OUTSx} (\k{insOUTSB}), and \c{XLATB} (\k{insXLATB}). Also, the
5744 various push and pop instructions (\c{PUSHA} and \c{POPF} as well as
5745 the more usual \c{PUSH} and \c{POP}) can accept \c{a16} or \c{a32}
5746 prefixes to force a particular one of \c{SP} or \c{ESP} to be used
5747 as a stack pointer, in case the stack segment in use is a different
5748 size from the code segment.
5750 \c{PUSH} and \c{POP}, when applied to segment registers in 32-bit
5751 mode, also have the slightly odd behaviour that they push and pop 4
5752 bytes at a time, of which the top two are ignored and the bottom two
5753 give the value of the segment register being manipulated. To force
5754 the 16-bit behaviour of segment-register push and pop instructions,
5755 you can use the operand-size prefix \i\c{o16}:
5760 This code saves a doubleword of stack space by fitting two segment
5761 registers into the space which would normally be consumed by pushing
5764 (You can also use the \i\c{o32} prefix to force the 32-bit behaviour
5765 when in 16-bit mode, but this seems less useful.)
5768 \C{trouble} Troubleshooting
5770 This chapter describes some of the common problems that users have
5771 been known to encounter with NASM, and answers them. It also gives
5772 instructions for reporting bugs in NASM if you find a difficulty
5773 that isn't listed here.
5776 \H{problems} Common Problems
5778 \S{inefficient} NASM Generates \i{Inefficient Code}
5780 I get a lot of `bug' reports about NASM generating inefficient, or
5781 even `wrong', code on instructions such as \c{ADD ESP,8}. This is a
5782 deliberate design feature, connected to predictability of output:
5783 NASM, on seeing \c{ADD ESP,8}, will generate the form of the
5784 instruction which leaves room for a 32-bit offset. You need to code
5785 \I\c{BYTE}\c{ADD ESP,BYTE 8} if you want the space-efficient
5786 form of the instruction. This isn't a bug: at worst it's a
5787 misfeature, and that's a matter of opinion only.
5790 \S{jmprange} My Jumps are Out of Range\I{out of range, jumps}
5792 Similarly, people complain that when they issue \i{conditional
5793 jumps} (which are \c{SHORT} by default) that try to jump too far,
5794 NASM reports `short jump out of range' instead of making the jumps
5797 This, again, is partly a predictability issue, but in fact has a
5798 more practical reason as well. NASM has no means of being told what
5799 type of processor the code it is generating will be run on; so it
5800 cannot decide for itself that it should generate \i\c{Jcc NEAR} type
5801 instructions, because it doesn't know that it's working for a 386 or
5802 above. Alternatively, it could replace the out-of-range short
5803 \c{JNE} instruction with a very short \c{JE} instruction that jumps
5804 over a \c{JMP NEAR}; this is a sensible solution for processors
5805 below a 386, but hardly efficient on processors which have good
5806 branch prediction \e{and} could have used \c{JNE NEAR} instead. So,
5807 once again, it's up to the user, not the assembler, to decide what
5808 instructions should be generated.
5811 \S{proborg} \i\c{ORG} Doesn't Work
5813 People writing \i{boot sector} programs in the \c{bin} format often
5814 complain that \c{ORG} doesn't work the way they'd like: in order to
5815 place the \c{0xAA55} signature word at the end of a 512-byte boot
5816 sector, people who are used to MASM tend to code
5820 \c ; some boot sector code
5825 This is not the intended use of the \c{ORG} directive in NASM, and
5826 will not work. The correct way to solve this problem in NASM is to
5827 use the \i\c{TIMES} directive, like this:
5831 \c ; some boot sector code
5833 \c TIMES 510-($-$$) DB 0
5836 The \c{TIMES} directive will insert exactly enough zero bytes into
5837 the output to move the assembly point up to 510. This method also
5838 has the advantage that if you accidentally fill your boot sector too
5839 full, NASM will catch the problem at assembly time and report it, so
5840 you won't end up with a boot sector that you have to disassemble to
5841 find out what's wrong with it.
5844 \S{probtimes} \i\c{TIMES} Doesn't Work
5846 The other common problem with the above code is people who write the
5851 by reasoning that \c{$} should be a pure number, just like 510, so
5852 the difference between them is also a pure number and can happily be
5855 NASM is a \e{modular} assembler: the various component parts are
5856 designed to be easily separable for re-use, so they don't exchange
5857 information unnecessarily. In consequence, the \c{bin} output
5858 format, even though it has been told by the \c{ORG} directive that
5859 the \c{.text} section should start at 0, does not pass that
5860 information back to the expression evaluator. So from the
5861 evaluator's point of view, \c{$} isn't a pure number: it's an offset
5862 from a section base. Therefore the difference between \c{$} and 510
5863 is also not a pure number, but involves a section base. Values
5864 involving section bases cannot be passed as arguments to \c{TIMES}.
5866 The solution, as in the previous section, is to code the \c{TIMES}
5869 \c TIMES 510-($-$$) DB 0
5871 in which \c{$} and \c{$$} are offsets from the same section base,
5872 and so their difference is a pure number. This will solve the
5873 problem and generate sensible code.
5876 \H{bugs} \i{Bugs}\I{reporting bugs}
5878 We have never yet released a version of NASM with any \e{known}
5879 bugs. That doesn't usually stop there being plenty we didn't know
5880 about, though. Any that you find should be reported firstly via the
5882 \W{https://sourceforge.net/projects/nasm/}\c{https://sourceforge.net/projects/nasm/}
5883 (click on "Bugs"), or if that fails then through one of the
5884 contacts in \k{contact}.
5886 Please read \k{qstart} first, and don't report the bug if it's
5887 listed in there as a deliberate feature. (If you think the feature
5888 is badly thought out, feel free to send us reasons why you think it
5889 should be changed, but don't just send us mail saying `This is a
5890 bug' if the documentation says we did it on purpose.) Then read
5891 \k{problems}, and don't bother reporting the bug if it's listed
5894 If you do report a bug, \e{please} give us all of the following
5897 \b What operating system you're running NASM under. DOS, Linux,
5898 NetBSD, Win16, Win32, VMS (I'd be impressed), whatever.
5900 \b If you're running NASM under DOS or Win32, tell us whether you've
5901 compiled your own executable from the DOS source archive, or whether
5902 you were using the standard distribution binaries out of the
5903 archive. If you were using a locally built executable, try to
5904 reproduce the problem using one of the standard binaries, as this
5905 will make it easier for us to reproduce your problem prior to fixing
5908 \b Which version of NASM you're using, and exactly how you invoked
5909 it. Give us the precise command line, and the contents of the
5910 \c{NASMENV} environment variable if any.
5912 \b Which versions of any supplementary programs you're using, and
5913 how you invoked them. If the problem only becomes visible at link
5914 time, tell us what linker you're using, what version of it you've
5915 got, and the exact linker command line. If the problem involves
5916 linking against object files generated by a compiler, tell us what
5917 compiler, what version, and what command line or options you used.
5918 (If you're compiling in an IDE, please try to reproduce the problem
5919 with the command-line version of the compiler.)
5921 \b If at all possible, send us a NASM source file which exhibits the
5922 problem. If this causes copyright problems (e.g. you can only
5923 reproduce the bug in restricted-distribution code) then bear in mind
5924 the following two points: firstly, we guarantee that any source code
5925 sent to us for the purposes of debugging NASM will be used \e{only}
5926 for the purposes of debugging NASM, and that we will delete all our
5927 copies of it as soon as we have found and fixed the bug or bugs in
5928 question; and secondly, we would prefer \e{not} to be mailed large
5929 chunks of code anyway. The smaller the file, the better. A
5930 three-line sample file that does nothing useful \e{except}
5931 demonstrate the problem is much easier to work with than a
5932 fully fledged ten-thousand-line program. (Of course, some errors
5933 \e{do} only crop up in large files, so this may not be possible.)
5935 \b A description of what the problem actually \e{is}. `It doesn't
5936 work' is \e{not} a helpful description! Please describe exactly what
5937 is happening that shouldn't be, or what isn't happening that should.
5938 Examples might be: `NASM generates an error message saying Line 3
5939 for an error that's actually on Line 5'; `NASM generates an error
5940 message that I believe it shouldn't be generating at all'; `NASM
5941 fails to generate an error message that I believe it \e{should} be
5942 generating'; `the object file produced from this source code crashes
5943 my linker'; `the ninth byte of the output file is 66 and I think it
5944 should be 77 instead'.
5946 \b If you believe the output file from NASM to be faulty, send it to
5947 us. That allows us to determine whether our own copy of NASM
5948 generates the same file, or whether the problem is related to
5949 portability issues between our development platforms and yours. We
5950 can handle binary files mailed to us as MIME attachments, uuencoded,
5951 and even BinHex. Alternatively, we may be able to provide an FTP
5952 site you can upload the suspect files to; but mailing them is easier
5955 \b Any other information or data files that might be helpful. If,
5956 for example, the problem involves NASM failing to generate an object
5957 file while TASM can generate an equivalent file without trouble,
5958 then send us \e{both} object files, so we can see what TASM is doing
5959 differently from us.
5962 \A{ndisasm} \i{Ndisasm}
5964 The Netwide Disassembler, NDISASM
5966 \H{ndisintro} Introduction
5969 The Netwide Disassembler is a small companion program to the Netwide
5970 Assembler, NASM. It seemed a shame to have an x86 assembler,
5971 complete with a full instruction table, and not make as much use of
5972 it as possible, so here's a disassembler which shares the
5973 instruction table (and some other bits of code) with NASM.
5975 The Netwide Disassembler does nothing except to produce
5976 disassemblies of \e{binary} source files. NDISASM does not have any
5977 understanding of object file formats, like \c{objdump}, and it will
5978 not understand \c{DOS .EXE} files like \c{debug} will. It just
5982 \H{ndisstart} Getting Started: Installation
5984 See \k{install} for installation instructions. NDISASM, like NASM,
5985 has a \c{man page} which you may want to put somewhere useful, if you
5986 are on a Unix system.
5989 \H{ndisrun} Running NDISASM
5991 To disassemble a file, you will typically use a command of the form
5993 \c ndisasm [-b16 | -b32] filename
5995 NDISASM can disassemble 16-bit code or 32-bit code equally easily,
5996 provided of course that you remember to specify which it is to work
5997 with. If no \i\c{-b} switch is present, NDISASM works in 16-bit mode by
5998 default. The \i\c{-u} switch (for USE32) also invokes 32-bit mode.
6000 Two more command line options are \i\c{-r} which reports the version
6001 number of NDISASM you are running, and \i\c{-h} which gives a short
6002 summary of command line options.
6005 \S{ndiscom} COM Files: Specifying an Origin
6007 To disassemble a \c{DOS .COM} file correctly, a disassembler must assume
6008 that the first instruction in the file is loaded at address \c{0x100},
6009 rather than at zero. NDISASM, which assumes by default that any file
6010 you give it is loaded at zero, will therefore need to be informed of
6013 The \i\c{-o} option allows you to declare a different origin for the
6014 file you are disassembling. Its argument may be expressed in any of
6015 the NASM numeric formats: decimal by default, if it begins with `\c{$}'
6016 or `\c{0x}' or ends in `\c{H}' it's \c{hex}, if it ends in `\c{Q}' it's
6017 \c{octal}, and if it ends in `\c{B}' it's \c{binary}.
6019 Hence, to disassemble a \c{.COM} file:
6021 \c ndisasm -o100h filename.com
6026 \S{ndissync} Code Following Data: Synchronisation
6028 Suppose you are disassembling a file which contains some data which
6029 isn't machine code, and \e{then} contains some machine code. NDISASM
6030 will faithfully plough through the data section, producing machine
6031 instructions wherever it can (although most of them will look
6032 bizarre, and some may have unusual prefixes, e.g. `\c{FS OR AX,0x240A}'),
6033 and generating `DB' instructions ever so often if it's totally stumped.
6034 Then it will reach the code section.
6036 Supposing NDISASM has just finished generating a strange machine
6037 instruction from part of the data section, and its file position is
6038 now one byte \e{before} the beginning of the code section. It's
6039 entirely possible that another spurious instruction will get
6040 generated, starting with the final byte of the data section, and
6041 then the correct first instruction in the code section will not be
6042 seen because the starting point skipped over it. This isn't really
6045 To avoid this, you can specify a `\i\c{synchronisation}' point, or indeed
6046 as many synchronisation points as you like (although NDISASM can
6047 only handle 8192 sync points internally). The definition of a sync
6048 point is this: NDISASM guarantees to hit sync points exactly during
6049 disassembly. If it is thinking about generating an instruction which
6050 would cause it to jump over a sync point, it will discard that
6051 instruction and output a `\c{db}' instead. So it \e{will} start
6052 disassembly exactly from the sync point, and so you \e{will} see all
6053 the instructions in your code section.
6055 Sync points are specified using the \i\c{-s} option: they are measured
6056 in terms of the program origin, not the file position. So if you
6057 want to synchronise after 32 bytes of a \c{.COM} file, you would have to
6060 \c ndisasm -o100h -s120h file.com
6064 \c ndisasm -o100h -s20h file.com
6066 As stated above, you can specify multiple sync markers if you need
6067 to, just by repeating the \c{-s} option.
6070 \S{ndisisync} Mixed Code and Data: Automatic (Intelligent) Synchronisation
6073 Suppose you are disassembling the boot sector of a \c{DOS} floppy (maybe
6074 it has a virus, and you need to understand the virus so that you
6075 know what kinds of damage it might have done you). Typically, this
6076 will contain a \c{JMP} instruction, then some data, then the rest of the
6077 code. So there is a very good chance of NDISASM being \e{misaligned}
6078 when the data ends and the code begins. Hence a sync point is
6081 On the other hand, why should you have to specify the sync point
6082 manually? What you'd do in order to find where the sync point would
6083 be, surely, would be to read the \c{JMP} instruction, and then to use
6084 its target address as a sync point. So can NDISASM do that for you?
6086 The answer, of course, is yes: using either of the synonymous
6087 switches \i\c{-a} (for automatic sync) or \i\c{-i} (for intelligent
6088 sync) will enable \c{auto-sync} mode. Auto-sync mode automatically
6089 generates a sync point for any forward-referring PC-relative jump or
6090 call instruction that NDISASM encounters. (Since NDISASM is one-pass,
6091 if it encounters a PC-relative jump whose target has already been
6092 processed, there isn't much it can do about it...)
6094 Only PC-relative jumps are processed, since an absolute jump is
6095 either through a register (in which case NDISASM doesn't know what
6096 the register contains) or involves a segment address (in which case
6097 the target code isn't in the same segment that NDISASM is working
6098 in, and so the sync point can't be placed anywhere useful).
6100 For some kinds of file, this mechanism will automatically put sync
6101 points in all the right places, and save you from having to place
6102 any sync points manually. However, it should be stressed that
6103 auto-sync mode is \e{not} guaranteed to catch all the sync points, and
6104 you may still have to place some manually.
6106 Auto-sync mode doesn't prevent you from declaring manual sync
6107 points: it just adds automatically generated ones to the ones you
6108 provide. It's perfectly feasible to specify \c{-i} \e{and} some \c{-s}
6111 Another caveat with auto-sync mode is that if, by some unpleasant
6112 fluke, something in your data section should disassemble to a
6113 PC-relative call or jump instruction, NDISASM may obediently place a
6114 sync point in a totally random place, for example in the middle of
6115 one of the instructions in your code section. So you may end up with
6116 a wrong disassembly even if you use auto-sync. Again, there isn't
6117 much I can do about this. If you have problems, you'll have to use
6118 manual sync points, or use the \c{-k} option (documented below) to
6119 suppress disassembly of the data area.
6122 \S{ndisother} Other Options
6124 The \i\c{-e} option skips a header on the file, by ignoring the first N
6125 bytes. This means that the header is \e{not} counted towards the
6126 disassembly offset: if you give \c{-e10 -o10}, disassembly will start
6127 at byte 10 in the file, and this will be given offset 10, not 20.
6129 The \i\c{-k} option is provided with two comma-separated numeric
6130 arguments, the first of which is an assembly offset and the second
6131 is a number of bytes to skip. This \e{will} count the skipped bytes
6132 towards the assembly offset: its use is to suppress disassembly of a
6133 data section which wouldn't contain anything you wanted to see
6137 \H{ndisbugs} Bugs and Improvements
6139 There are no known bugs. However, any you find, with patches if
6140 possible, should be sent to \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk}
6141 or \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}, or to the
6142 developer's site \W{http://nasm.2y.net/}\c{http://nasm.2y.net/}
6143 and we'll try to fix them. Feel free to send contributions and
6144 new features as well.
6146 Future plans include awareness of which processors certain
6147 instructions will run on, and marking of instructions that are too
6148 advanced for some processor (or are \c{FPU} instructions, or are
6149 undocumented opcodes, or are privileged protected-mode instructions,
6154 I hope NDISASM is of some use to somebody. Including me. :-)
6156 I don't recommend taking NDISASM apart to see how an efficient
6157 disassembler works, because as far as I know, it isn't an efficient
6158 one anyway. You have been warned.
6161 \A{iref} x86 Instruction Reference
6163 This appendix provides a complete list of the machine instructions
6164 which NASM will assemble, and a short description of the function of
6167 It is not intended to be exhaustive documentation on the fine
6168 details of the instructions' function, such as which exceptions they
6169 can trigger: for such documentation, you should go to Intel's Web
6170 site, \W{http://developer.intel.com/design/Pentium4/manuals/}\c{http://developer.intel.com/design/Pentium4/manuals/}.
6172 Instead, this appendix is intended primarily to provide
6173 documentation on the way the instructions may be used within NASM.
6174 For example, looking up \c{LOOP} will tell you that NASM allows
6175 \c{CX} or \c{ECX} to be specified as an optional second argument to
6176 the \c{LOOP} instruction, to enforce which of the two possible
6177 counter registers should be used if the default is not the one
6180 The instructions are not quite listed in alphabetical order, since
6181 groups of instructions with similar functions are lumped together in
6182 the same entry. Most of them don't move very far from their
6183 alphabetic position because of this.
6186 \H{iref-opr} Key to Operand Specifications
6188 The instruction descriptions in this appendix specify their operands
6189 using the following notation:
6191 \b Registers: \c{reg8} denotes an 8-bit \i{general purpose
6192 register}, \c{reg16} denotes a 16-bit general purpose register, and
6193 \c{reg32} a 32-bit one. \c{fpureg} denotes one of the eight FPU
6194 stack registers, \c{mmxreg} denotes one of the eight 64-bit MMX
6195 registers, and \c{segreg} denotes a segment register. In addition,
6196 some registers (such as \c{AL}, \c{DX} or
6197 \c{ECX}) may be specified explicitly.
6199 \b Immediate operands: \c{imm} denotes a generic \i{immediate operand}.
6200 \c{imm8}, \c{imm16} and \c{imm32} are used when the operand is
6201 intended to be a specific size. For some of these instructions, NASM
6202 needs an explicit specifier: for example, \c{ADD ESP,16} could be
6203 interpreted as either \c{ADD r/m32,imm32} or \c{ADD r/m32,imm8}.
6204 NASM chooses the former by default, and so you must specify \c{ADD
6205 ESP,BYTE 16} for the latter.
6207 \b Memory references: \c{mem} denotes a generic \i{memory reference};
6208 \c{mem8}, \c{mem16}, \c{mem32}, \c{mem64} and \c{mem80} are used
6209 when the operand needs to be a specific size. Again, a specifier is
6210 needed in some cases: \c{DEC [address]} is ambiguous and will be
6211 rejected by NASM. You must specify \c{DEC BYTE [address]}, \c{DEC
6212 WORD [address]} or \c{DEC DWORD [address]} instead.
6214 \b \i{Restricted memory references}: one form of the \c{MOV}
6215 instruction allows a memory address to be specified \e{without}
6216 allowing the normal range of register combinations and effective
6217 address processing. This is denoted by \c{memoffs8}, \c{memoffs16}
6220 \b Register or memory choices: many instructions can accept either a
6221 register \e{or} a memory reference as an operand. \c{r/m8} is a
6222 shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}.
6223 \c{r/m64} is MMX-related, and is a shorthand for \c{mmxreg/mem64}.
6226 \H{iref-opc} Key to Opcode Descriptions
6228 This appendix also provides the opcodes which NASM will generate for
6229 each form of each instruction. The opcodes are listed in the
6232 \b A hex number, such as \c{3F}, indicates a fixed byte containing
6235 \b A hex number followed by \c{+r}, such as \c{C8+r}, indicates that
6236 one of the operands to the instruction is a register, and the
6237 `register value' of that register should be added to the hex number
6238 to produce the generated byte. For example, EDX has register value
6239 2, so the code \c{C8+r}, when the register operand is EDX, generates
6240 the hex byte \c{CA}. Register values for specific registers are
6241 given in \k{iref-rv}.
6243 \b A hex number followed by \c{+cc}, such as \c{40+cc}, indicates
6244 that the instruction name has a condition code suffix, and the
6245 numeric representation of the condition code should be added to the
6246 hex number to produce the generated byte. For example, the code
6247 \c{40+cc}, when the instruction contains the \c{NE} condition,
6248 generates the hex byte \c{45}. Condition codes and their numeric
6249 representations are given in \k{iref-cc}.
6251 \b A slash followed by a digit, such as \c{/2}, indicates that one
6252 of the operands to the instruction is a memory address or register
6253 (denoted \c{mem} or \c{r/m}, with an optional size). This is to be
6254 encoded as an effective address, with a \i{ModR/M byte}, an optional
6255 \i{SIB byte}, and an optional displacement, and the spare (register)
6256 field of the ModR/M byte should be the digit given (which will be
6257 from 0 to 7, so it fits in three bits). The encoding of effective
6258 addresses is given in \k{iref-ea}.
6260 \b The code \c{/r} combines the above two: it indicates that one of
6261 the operands is a memory address or \c{r/m}, and another is a
6262 register, and that an effective address should be generated with the
6263 spare (register) field in the ModR/M byte being equal to the
6264 `register value' of the register operand. The encoding of effective
6265 addresses is given in \k{iref-ea}; register values are given in
6268 \b The codes \c{ib}, \c{iw} and \c{id} indicate that one of the
6269 operands to the instruction is an immediate value, and that this is
6270 to be encoded as a byte, little-endian word or little-endian
6271 doubleword respectively.
6273 \b The codes \c{rb}, \c{rw} and \c{rd} indicate that one of the
6274 operands to the instruction is an immediate value, and that the
6275 \e{difference} between this value and the address of the end of the
6276 instruction is to be encoded as a byte, word or doubleword
6277 respectively. Where the form \c{rw/rd} appears, it indicates that
6278 either \c{rw} or \c{rd} should be used according to whether assembly
6279 is being performed in \c{BITS 16} or \c{BITS 32} state respectively.
6281 \b The codes \c{ow} and \c{od} indicate that one of the operands to
6282 the instruction is a reference to the contents of a memory address
6283 specified as an immediate value: this encoding is used in some forms
6284 of the \c{MOV} instruction in place of the standard
6285 effective-address mechanism. The displacement is encoded as a word
6286 or doubleword. Again, \c{ow/od} denotes that \c{ow} or \c{od} should
6287 be chosen according to the \c{BITS} setting.
6289 \b The codes \c{o16} and \c{o32} indicate that the given form of the
6290 instruction should be assembled with operand size 16 or 32 bits. In
6291 other words, \c{o16} indicates a \c{66} prefix in \c{BITS 32} state,
6292 but generates no code in \c{BITS 16} state; and \c{o32} indicates a
6293 \c{66} prefix in \c{BITS 16} state but generates nothing in \c{BITS
6296 \b The codes \c{a16} and \c{a32}, similarly to \c{o16} and \c{o32},
6297 indicate the address size of the given form of the instruction.
6298 Where this does not match the \c{BITS} setting, a \c{67} prefix is
6302 \S{iref-rv} Register Values
6304 Where an instruction requires a register value, it is already
6305 implicit in the encoding of the rest of the instruction what type of
6306 register is intended: an 8-bit general-purpose register, a segment
6307 register, a debug register, an MMX register, or whatever. Therefore
6308 there is no problem with registers of different types sharing an
6311 The encodings for the various classes of register are:
6313 \b 8-bit general registers: \c{AL} is 0, \c{CL} is 1, \c{DL} is 2,
6314 \c{BL} is 3, \c{AH} is 4, \c{CH} is 5, \c{DH} is 6, and \c{BH} is
6317 \b 16-bit general registers: \c{AX} is 0, \c{CX} is 1, \c{DX} is 2,
6318 \c{BX} is 3, \c{SP} is 4, \c{BP} is 5, \c{SI} is 6, and \c{DI} is 7.
6320 \b 32-bit general registers: \c{EAX} is 0, \c{ECX} is 1, \c{EDX} is
6321 2, \c{EBX} is 3, \c{ESP} is 4, \c{EBP} is 5, \c{ESI} is 6, and
6324 \b \i{Segment registers}: \c{ES} is 0, \c{CS} is 1, \c{SS} is 2, \c{DS}
6325 is 3, \c{FS} is 4, and \c{GS} is 5.
6327 \b \I{floating-point, registers}Floating-point registers: \c{ST0}
6328 is 0, \c{ST1} is 1, \c{ST2} is 2, \c{ST3} is 3, \c{ST4} is 4,
6329 \c{ST5} is 5, \c{ST6} is 6, and \c{ST7} is 7.
6331 \b 64-bit \i{MMX registers}: \c{MM0} is 0, \c{MM1} is 1, \c{MM2} is 2,
6332 \c{MM3} is 3, \c{MM4} is 4, \c{MM5} is 5, \c{MM6} is 6, and \c{MM7}
6335 \b \i{Control registers}: \c{CR0} is 0, \c{CR2} is 2, \c{CR3} is 3,
6338 \b \i{Debug registers}: \c{DR0} is 0, \c{DR1} is 1, \c{DR2} is 2,
6339 \c{DR3} is 3, \c{DR6} is 6, and \c{DR7} is 7.
6341 \b \i{Test registers}: \c{TR3} is 3, \c{TR4} is 4, \c{TR5} is 5,
6342 \c{TR6} is 6, and \c{TR7} is 7.
6344 (Note that wherever a register name contains a number, that number
6345 is also the register value for that register.)
6348 \S{iref-cc} \i{Condition Codes}
6350 The available condition codes are given here, along with their
6351 numeric representations as part of opcodes. Many of these condition
6352 codes have synonyms, so several will be listed at a time.
6354 In the following descriptions, the word `either', when applied to two
6355 possible trigger conditions, is used to mean `either or both'. If
6356 `either but not both' is meant, the phrase `exactly one of' is used.
6358 \b \c{O} is 0 (trigger if the overflow flag is set); \c{NO} is 1.
6360 \b \c{B}, \c{C} and \c{NAE} are 2 (trigger if the carry flag is
6361 set); \c{AE}, \c{NB} and \c{NC} are 3.
6363 \b \c{E} and \c{Z} are 4 (trigger if the zero flag is set); \c{NE}
6366 \b \c{BE} and \c{NA} are 6 (trigger if either of the carry or zero
6367 flags is set); \c{A} and \c{NBE} are 7.
6369 \b \c{S} is 8 (trigger if the sign flag is set); \c{NS} is 9.
6371 \b \c{P} and \c{PE} are 10 (trigger if the parity flag is set);
6372 \c{NP} and \c{PO} are 11.
6374 \b \c{L} and \c{NGE} are 12 (trigger if exactly one of the sign and
6375 overflow flags is set); \c{GE} and \c{NL} are 13.
6377 \b \c{LE} and \c{NG} are 14 (trigger if either the zero flag is set,
6378 or exactly one of the sign and overflow flags is set); \c{G} and
6381 Note that in all cases, the sense of a condition code may be
6382 reversed by changing the low bit of the numeric representation.
6384 For details of when an instruction sets each of the status flags,
6385 see the individual instruction, plus the Status Flags reference
6389 \S{iref-SSE-cc} \i{SSE Condition Predicates}
6391 The condition predicates for SSE comparison instructions are the
6392 codes used as part of the opcode, to determine what form of
6393 comparison is being carried out. In each case, the imm8 value is
6394 the final byte of the opcode encoding, and the predicate is the
6395 code used as part of the mnemonic for the instruction (equivalent
6396 to the "cc" in an integer instruction that used a condition code).
6397 The instructions that use this will give details of what the various
6398 mnemonics are, this table is used to help you work out details of what
6401 \c Predi- imm8 Description Relation where: Emula- Result QNaN
6402 \c cate Encod- A Is 1st Operand tion if NaN Signal
6403 \c ing B Is 2nd Operand Operand Invalid
6405 \c EQ 000B equal A = B False No
6407 \c LT 001B less-than A < B False Yes
6409 \c LE 010B less-than- A <= B False Yes
6412 \c --- ---- greater A > B Swap False Yes
6416 \c --- ---- greater- A >= B Swap False Yes
6417 \c than-or-equal Operands,
6420 \c UNORD 011B unordered A, B = Unordered True No
6422 \c NEQ 100B not-equal A != B True No
6424 \c NLT 101B not-less- NOT(A < B) True Yes
6427 \c NLE 110B not-less- NOT(A <= B) True Yes
6431 \c --- ---- not-greater NOT(A > B) Swap True Yes
6435 \c --- ---- not-greater NOT(A >= B) Swap True Yes
6439 \c ORD 111B ordered A , B = Ordered False No
6441 The unordered relationship is true when at least one of the two
6442 values being compared is a NaN or in an unsupported format.
6444 Note that the comparisons which are listed as not having a predicate
6445 or encoding can only be achieved through software emulation, as
6446 described in the "emulation" column. Note in particular that an
6447 instruction such as \c{greater-than} is not the same as \c{NLE}, as,
6448 unlike with the \c{CMP} instruction, it has to take into account the
6449 possibility of one operand containing a NaN or an unsupported numeric
6453 \S{iref-Flags} \i{Status Flags}
6455 The status flags provide some information about the result of the
6456 arithmetic instructions. This information can be used by conditional
6457 instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of
6458 the other instructions (such as \c{ADC} and \c{INTO}).
6460 There are 6 status flags:
6464 Set if an arithmetic operation generates a
6465 carry or a borrow out of the most-significant bit of the result;
6466 cleared otherwise. This flag indicates an overflow condition for
6467 unsigned-integer arithmetic. It is also used in multiple-precision
6470 \c PF - Parity flag.
6472 Set if the least-significant byte of the result contains an even
6473 number of 1 bits; cleared otherwise.
6475 \c AF - Adjust flag.
6477 Set if an arithmetic operation generates a carry or a borrow
6478 out of bit 3 of the result; cleared otherwise. This flag is used
6479 in binary-coded decimal (BCD) arithmetic.
6483 Set if the result is zero; cleared otherwise.
6487 Set equal to the most-significant bit of the result, which is the
6488 sign bit of a signed integer. (0 indicates a positive value and 1
6489 indicates a negative value.)
6491 \c OF - Overflow flag.
6493 Set if the integer result is too large a positive number or too
6494 small a negative number (excluding the sign-bit) to fit in the
6495 destination operand; cleared otherwise. This flag indicates an
6496 overflow condition for signed-integer (two's complement) arithmetic.
6499 \S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB}
6501 An \i{effective address} is encoded in up to three parts: a ModR/M
6502 byte, an optional SIB byte, and an optional byte, word or doubleword
6505 The ModR/M byte consists of three fields: the \c{mod} field, ranging
6506 from 0 to 3, in the upper two bits of the byte, the \c{r/m} field,
6507 ranging from 0 to 7, in the lower three bits, and the spare
6508 (register) field in the middle (bit 3 to bit 5). The spare field is
6509 not relevant to the effective address being encoded, and either
6510 contains an extension to the instruction opcode or the register
6511 value of another operand.
6513 The ModR/M system can be used to encode a direct register reference
6514 rather than a memory access. This is always done by setting the
6515 \c{mod} field to 3 and the \c{r/m} field to the register value of
6516 the register in question (it must be a general-purpose register, and
6517 the size of the register must already be implicit in the encoding of
6518 the rest of the instruction). In this case, the SIB byte and
6519 displacement field are both absent.
6521 In 16-bit addressing mode (either \c{BITS 16} with no \c{67} prefix,
6522 or \c{BITS 32} with a \c{67} prefix), the SIB byte is never used.
6523 The general rules for \c{mod} and \c{r/m} (there is an exception,
6526 \b The \c{mod} field gives the length of the displacement field: 0
6527 means no displacement, 1 means one byte, and 2 means two bytes.
6529 \b The \c{r/m} field encodes the combination of registers to be
6530 added to the displacement to give the accessed address: 0 means
6531 \c{BX+SI}, 1 means \c{BX+DI}, 2 means \c{BP+SI}, 3 means \c{BP+DI},
6532 4 means \c{SI} only, 5 means \c{DI} only, 6 means \c{BP} only, and 7
6535 However, there is a special case:
6537 \b If \c{mod} is 0 and \c{r/m} is 6, the effective address encoded
6538 is not \c{[BP]} as the above rules would suggest, but instead
6539 \c{[disp16]}: the displacement field is present and is two bytes
6540 long, and no registers are added to the displacement.
6542 Therefore the effective address \c{[BP]} cannot be encoded as
6543 efficiently as \c{[BX]}; so if you code \c{[BP]} in a program, NASM
6544 adds a notional 8-bit zero displacement, and sets \c{mod} to 1,
6545 \c{r/m} to 6, and the one-byte displacement field to 0.
6547 In 32-bit addressing mode (either \c{BITS 16} with a \c{67} prefix,
6548 or \c{BITS 32} with no \c{67} prefix) the general rules (again,
6549 there are exceptions) for \c{mod} and \c{r/m} are:
6551 \b The \c{mod} field gives the length of the displacement field: 0
6552 means no displacement, 1 means one byte, and 2 means four bytes.
6554 \b If only one register is to be added to the displacement, and it
6555 is not \c{ESP}, the \c{r/m} field gives its register value, and the
6556 SIB byte is absent. If the \c{r/m} field is 4 (which would encode
6557 \c{ESP}), the SIB byte is present and gives the combination and
6558 scaling of registers to be added to the displacement.
6560 If the SIB byte is present, it describes the combination of
6561 registers (an optional base register, and an optional index register
6562 scaled by multiplication by 1, 2, 4 or 8) to be added to the
6563 displacement. The SIB byte is divided into the \c{scale} field, in
6564 the top two bits, the \c{index} field in the next three, and the
6565 \c{base} field in the bottom three. The general rules are:
6567 \b The \c{base} field encodes the register value of the base
6570 \b The \c{index} field encodes the register value of the index
6571 register, unless it is 4, in which case no index register is used
6572 (so \c{ESP} cannot be used as an index register).
6574 \b The \c{scale} field encodes the multiplier by which the index
6575 register is scaled before adding it to the base and displacement: 0
6576 encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.
6578 The exceptions to the 32-bit encoding rules are:
6580 \b If \c{mod} is 0 and \c{r/m} is 5, the effective address encoded
6581 is not \c{[EBP]} as the above rules would suggest, but instead
6582 \c{[disp32]}: the displacement field is present and is four bytes
6583 long, and no registers are added to the displacement.
6585 \b If \c{mod} is 0, \c{r/m} is 4 (meaning the SIB byte is present)
6586 and \c{base} is 4, the effective address encoded is not
6587 \c{[EBP+index]} as the above rules would suggest, but instead
6588 \c{[disp32+index]}: the displacement field is present and is four
6589 bytes long, and there is no base register (but the index register is
6590 still processed in the normal way).
6593 \H{iref-flg} Key to Instruction Flags
6595 Given along with each instruction in this appendix is a set of
6596 flags, denoting the type of the instruction. The types are as follows:
6598 \b \c{8086}, \c{186}, \c{286}, \c{386}, \c{486}, \c{PENT} and \c{P6}
6599 denote the lowest processor type that supports the instruction. Most
6600 instructions run on all processors above the given type; those that
6601 do not are documented. The Pentium II contains no additional
6602 instructions beyond the P6 (Pentium Pro); from the point of view of
6603 its instruction set, it can be thought of as a P6 with MMX
6606 \b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will
6607 run on the AMD K6-2 and later processors. ATHLON extensions to the
6608 3DNow! instruction set are documented as such.
6610 \b \c{CYRIX} indicates that the instruction is specific to Cyrix
6611 processors, for example the extra MMX instructions in the Cyrix
6612 extended MMX instruction set.
6614 \b \c{FPU} indicates that the instruction is a floating-point one,
6615 and will only run on machines with a coprocessor (automatically
6616 including 486DX, Pentium and above).
6618 \b \c{KATMAI} indicates that the instruction was introduced as part
6619 of the Katmai New Instruction set. These instructions are available
6620 on the Pentium III and later processors. Those which are not
6621 specifically SSE instructions are also available on the AMD Athlon.
6623 \b \c{MMX} indicates that the instruction is an MMX one, and will
6624 run on MMX-capable Pentium processors and the Pentium II.
6626 \b \c{PRIV} indicates that the instruction is a protected-mode
6627 management instruction. Many of these may only be used in protected
6628 mode, or only at privilege level zero.
6630 \b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming
6631 SIMD Extension instruction. These instructions operate on multiple
6632 values in a single operation. SSE was introduced with the Pentium III
6633 and SSE2 was introduced with the Pentium 4.
6635 \b \c{UNDOC} indicates that the instruction is an undocumented one,
6636 and not part of the official Intel Architecture; it may or may not
6637 be supported on any given machine.
6639 \b \c{WILLAMETTE} indicates that the instruction was introduced as
6640 part of the new instruction set in the Pentium 4 and Intel Xeon
6641 processors. These instructions are also known as SSE2 instructions.
6644 \H{iref-inst} x86 Instruction Set
6647 \S{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII
6654 \c AAD ; D5 0A [8086]
6655 \c AAD imm ; D5 ib [8086]
6657 \c AAM ; D4 0A [8086]
6658 \c AAM imm ; D4 ib [8086]
6660 These instructions are used in conjunction with the add, subtract,
6661 multiply and divide instructions to perform binary-coded decimal
6662 arithmetic in \e{unpacked} (one BCD digit per byte - easy to
6663 translate to and from \c{ASCII}, hence the instruction names) form.
6664 There are also packed BCD instructions \c{DAA} and \c{DAS}: see
6667 \b \c{AAA} (ASCII Adjust After Addition) should be used after a
6668 one-byte \c{ADD} instruction whose destination was the \c{AL}
6669 register: by means of examining the value in the low nibble of
6670 \c{AL} and also the auxiliary carry flag \c{AF}, it determines
6671 whether the addition has overflowed, and adjusts it (and sets
6672 the carry flag) if so. You can add long BCD strings together
6673 by doing \c{ADD}/\c{AAA} on the low digits, then doing
6674 \c{ADC}/\c{AAA} on each subsequent digit.
6676 \b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to
6677 \c{AAA}, but is for use after \c{SUB} instructions rather than
6680 \b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you
6681 have multiplied two decimal digits together and left the result
6682 in \c{AL}: it divides \c{AL} by ten and stores the quotient in
6683 \c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be
6684 changed by specifying an operand to the instruction: a particularly
6685 handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL}
6686 to be separated into \c{AH} and \c{AL}.
6688 \b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse
6689 operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to
6690 \c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can
6694 \S{insADC} \i\c{ADC}: Add with Carry
6696 \c ADC r/m8,reg8 ; 10 /r [8086]
6697 \c ADC r/m16,reg16 ; o16 11 /r [8086]
6698 \c ADC r/m32,reg32 ; o32 11 /r [386]
6700 \c ADC reg8,r/m8 ; 12 /r [8086]
6701 \c ADC reg16,r/m16 ; o16 13 /r [8086]
6702 \c ADC reg32,r/m32 ; o32 13 /r [386]
6704 \c ADC r/m8,imm8 ; 80 /2 ib [8086]
6705 \c ADC r/m16,imm16 ; o16 81 /2 iw [8086]
6706 \c ADC r/m32,imm32 ; o32 81 /2 id [386]
6708 \c ADC r/m16,imm8 ; o16 83 /2 ib [8086]
6709 \c ADC r/m32,imm8 ; o32 83 /2 ib [386]
6711 \c ADC AL,imm8 ; 14 ib [8086]
6712 \c ADC AX,imm16 ; o16 15 iw [8086]
6713 \c ADC EAX,imm32 ; o32 15 id [386]
6715 \c{ADC} performs integer addition: it adds its two operands
6716 together, plus the value of the carry flag, and leaves the result in
6717 its destination (first) operand. The destination operand can be a
6718 register or a memory location. The source operand can be a register,
6719 a memory location or an immediate value.
6721 The flags are set according to the result of the operation: in
6722 particular, the carry flag is affected and can be used by a
6723 subsequent \c{ADC} instruction.
6725 In the forms with an 8-bit immediate second operand and a longer
6726 first operand, the second operand is considered to be signed, and is
6727 sign-extended to the length of the first operand. In these cases,
6728 the \c{BYTE} qualifier is necessary to force NASM to generate this
6729 form of the instruction.
6731 To add two numbers without also adding the contents of the carry
6732 flag, use \c{ADD} (\k{insADD}).
6735 \S{insADD} \i\c{ADD}: Add Integers
6737 \c ADD r/m8,reg8 ; 00 /r [8086]
6738 \c ADD r/m16,reg16 ; o16 01 /r [8086]
6739 \c ADD r/m32,reg32 ; o32 01 /r [386]
6741 \c ADD reg8,r/m8 ; 02 /r [8086]
6742 \c ADD reg16,r/m16 ; o16 03 /r [8086]
6743 \c ADD reg32,r/m32 ; o32 03 /r [386]
6745 \c ADD r/m8,imm8 ; 80 /0 ib [8086]
6746 \c ADD r/m16,imm16 ; o16 81 /0 iw [8086]
6747 \c ADD r/m32,imm32 ; o32 81 /0 id [386]
6749 \c ADD r/m16,imm8 ; o16 83 /0 ib [8086]
6750 \c ADD r/m32,imm8 ; o32 83 /0 ib [386]
6752 \c ADD AL,imm8 ; 04 ib [8086]
6753 \c ADD AX,imm16 ; o16 05 iw [8086]
6754 \c ADD EAX,imm32 ; o32 05 id [386]
6756 \c{ADD} performs integer addition: it adds its two operands
6757 together, and leaves the result in its destination (first) operand.
6758 The destination operand can be a register or a memory location.
6759 The source operand can be a register, a memory location or an
6762 The flags are set according to the result of the operation: in
6763 particular, the carry flag is affected and can be used by a
6764 subsequent \c{ADC} instruction.
6766 In the forms with an 8-bit immediate second operand and a longer
6767 first operand, the second operand is considered to be signed, and is
6768 sign-extended to the length of the first operand. In these cases,
6769 the \c{BYTE} qualifier is necessary to force NASM to generate this
6770 form of the instruction.
6773 \S{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values
6775 \c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2]
6777 \c{ADDPD} performs addition on each of two packed double-precision
6780 \c dst[0-63] := dst[0-63] + src[0-63],
6781 \c dst[64-127] := dst[64-127] + src[64-127].
6783 The destination is an \c{XMM} register. The source operand can be
6784 either an \c{XMM} register or a 128-bit memory location.
6787 \S{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values
6789 \c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE]
6791 \c{ADDPS} performs addition on each of four packed single-precision
6794 \c dst[0-31] := dst[0-31] + src[0-31],
6795 \c dst[32-63] := dst[32-63] + src[32-63],
6796 \c dst[64-95] := dst[64-95] + src[64-95],
6797 \c dst[96-127] := dst[96-127] + src[96-127].
6799 The destination is an \c{XMM} register. The source operand can be
6800 either an \c{XMM} register or a 128-bit memory location.
6803 \S{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values
6805 \c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE]
6807 \c{ADDSD} adds the low double-precision FP values from the source
6808 and destination operands and stores the double-precision FP result
6809 in the destination operand.
6811 \c dst[0-63] := dst[0-63] + src[0-63],
6812 \c dst[64-127) remains unchanged.
6814 The destination is an \c{XMM} register. The source operand can be
6815 either an \c{XMM} register or a 64-bit memory location.
6818 \S{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values
6820 \c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2]
6822 \c{ADDSS} adds the low single-precision FP values from the source
6823 and destination operands and stores the single-precision FP result
6824 in the destination operand.
6826 \c dst[0-31] := dst[0-31] + src[0-31],
6827 \c dst[32-127] remains unchanged.
6829 The destination is an \c{XMM} register. The source operand can be
6830 either an \c{XMM} register or a 32-bit memory location.
6833 \S{insAND} \i\c{AND}: Bitwise AND
6835 \c AND r/m8,reg8 ; 20 /r [8086]
6836 \c AND r/m16,reg16 ; o16 21 /r [8086]
6837 \c AND r/m32,reg32 ; o32 21 /r [386]
6839 \c AND reg8,r/m8 ; 22 /r [8086]
6840 \c AND reg16,r/m16 ; o16 23 /r [8086]
6841 \c AND reg32,r/m32 ; o32 23 /r [386]
6843 \c AND r/m8,imm8 ; 80 /4 ib [8086]
6844 \c AND r/m16,imm16 ; o16 81 /4 iw [8086]
6845 \c AND r/m32,imm32 ; o32 81 /4 id [386]
6847 \c AND r/m16,imm8 ; o16 83 /4 ib [8086]
6848 \c AND r/m32,imm8 ; o32 83 /4 ib [386]
6850 \c AND AL,imm8 ; 24 ib [8086]
6851 \c AND AX,imm16 ; o16 25 iw [8086]
6852 \c AND EAX,imm32 ; o32 25 id [386]
6854 \c{AND} performs a bitwise AND operation between its two operands
6855 (i.e. each bit of the result is 1 if and only if the corresponding
6856 bits of the two inputs were both 1), and stores the result in the
6857 destination (first) operand. The destination operand can be a
6858 register or a memory location. The source operand can be a register,
6859 a memory location or an immediate value.
6861 In the forms with an 8-bit immediate second operand and a longer
6862 first operand, the second operand is considered to be signed, and is
6863 sign-extended to the length of the first operand. In these cases,
6864 the \c{BYTE} qualifier is necessary to force NASM to generate this
6865 form of the instruction.
6867 The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same
6868 operation on the 64-bit \c{MMX} registers.
6871 \S{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of
6872 Packed Double-Precision FP Values
6874 \c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2]
6876 \c{ANDNPD} inverts the bits of the two double-precision
6877 floating-point values in the destination register, and then
6878 performs a logical AND between the two double-precision
6879 floating-point values in the source operand and the temporary
6880 inverted result, storing the result in the destination register.
6882 \c dst[0-63] := src[0-63] AND NOT dst[0-63],
6883 \c dst[64-127] := src[64-127] AND NOT dst[64-127].
6885 The destination is an \c{XMM} register. The source operand can be
6886 either an \c{XMM} register or a 128-bit memory location.
6889 \S{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of
6890 Packed Single-Precision FP Values
6892 \c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE]
6894 \c{ANDNPS} inverts the bits of the four single-precision
6895 floating-point values in the destination register, and then
6896 performs a logical AND between the four single-precision
6897 floating-point values in the source operand and the temporary
6898 inverted result, storing the result in the destination register.
6900 \c dst[0-31] := src[0-31] AND NOT dst[0-31],
6901 \c dst[32-63] := src[32-63] AND NOT dst[32-63],
6902 \c dst[64-95] := src[64-95] AND NOT dst[64-95],
6903 \c dst[96-127] := src[96-127] AND NOT dst[96-127].
6905 The destination is an \c{XMM} register. The source operand can be
6906 either an \c{XMM} register or a 128-bit memory location.
6909 \S{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP
6911 \c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2]
6913 \c{ANDPD} performs a bitwise logical AND of the two double-precision
6914 floating point values in the source and destination operand, and
6915 stores the result in the destination register.
6917 \c dst[0-63] := src[0-63] AND dst[0-63],
6918 \c dst[64-127] := src[64-127] AND dst[64-127].
6920 The destination is an \c{XMM} register. The source operand can be
6921 either an \c{XMM} register or a 128-bit memory location.
6924 \S{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP
6926 \c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE]
6928 \c{ANDPS} performs a bitwise logical AND of the four single-precision
6929 floating point values in the source and destination operand, and
6930 stores the result in the destination register.
6932 \c dst[0-31] := src[0-31] AND dst[0-31],
6933 \c dst[32-63] := src[32-63] AND dst[32-63],
6934 \c dst[64-95] := src[64-95] AND dst[64-95],
6935 \c dst[96-127] := src[96-127] AND dst[96-127].
6937 The destination is an \c{XMM} register. The source operand can be
6938 either an \c{XMM} register or a 128-bit memory location.
6941 \S{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector
6943 \c ARPL r/m16,reg16 ; 63 /r [286,PRIV]
6945 \c{ARPL} expects its two word operands to be segment selectors. It
6946 adjusts the \i\c{RPL} (requested privilege level - stored in the bottom
6947 two bits of the selector) field of the destination (first) operand
6948 to ensure that it is no less (i.e. no more privileged than) the \c{RPL}
6949 field of the source operand. The zero flag is set if and only if a
6950 change had to be made.
6953 \S{insBOUND} \i\c{BOUND}: Check Array Index against Bounds
6955 \c BOUND reg16,mem ; o16 62 /r [186]
6956 \c BOUND reg32,mem ; o32 62 /r [386]
6958 \c{BOUND} expects its second operand to point to an area of memory
6959 containing two signed values of the same size as its first operand
6960 (i.e. two words for the 16-bit form; two doublewords for the 32-bit
6961 form). It performs two signed comparisons: if the value in the
6962 register passed as its first operand is less than the first of the
6963 in-memory values, or is greater than or equal to the second, it
6964 throws a \c{BR} exception. Otherwise, it does nothing.
6967 \S{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan
6969 \c BSF reg16,r/m16 ; o16 0F BC /r [386]
6970 \c BSF reg32,r/m32 ; o32 0F BC /r [386]
6972 \c BSR reg16,r/m16 ; o16 0F BD /r [386]
6973 \c BSR reg32,r/m32 ; o32 0F BD /r [386]
6975 \b \c{BSF} searches for the least significant set bit in its source
6976 (second) operand, and if it finds one, stores the index in
6977 its destination (first) operand. If no set bit is found, the
6978 contents of the destination operand are undefined. If the source
6979 operand is zero, the zero flag is set.
6981 \b \c{BSR} performs the same function, but searches from the top
6982 instead, so it finds the most significant set bit.
6984 Bit indices are from 0 (least significant) to 15 or 31 (most
6985 significant). The destination operand can only be a register.
6986 The source operand can be a register or a memory location.
6989 \S{insBSWAP} \i\c{BSWAP}: Byte Swap
6991 \c BSWAP reg32 ; o32 0F C8+r [486]
6993 \c{BSWAP} swaps the order of the four bytes of a 32-bit register:
6994 bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with
6995 bits 16-23. There is no explicit 16-bit equivalent: to byte-swap
6996 \c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP}
6997 is used with a 16-bit register, the result is undefined.
7000 \S{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test
7002 \c BT r/m16,reg16 ; o16 0F A3 /r [386]
7003 \c BT r/m32,reg32 ; o32 0F A3 /r [386]
7004 \c BT r/m16,imm8 ; o16 0F BA /4 ib [386]
7005 \c BT r/m32,imm8 ; o32 0F BA /4 ib [386]
7007 \c BTC r/m16,reg16 ; o16 0F BB /r [386]
7008 \c BTC r/m32,reg32 ; o32 0F BB /r [386]
7009 \c BTC r/m16,imm8 ; o16 0F BA /7 ib [386]
7010 \c BTC r/m32,imm8 ; o32 0F BA /7 ib [386]
7012 \c BTR r/m16,reg16 ; o16 0F B3 /r [386]
7013 \c BTR r/m32,reg32 ; o32 0F B3 /r [386]
7014 \c BTR r/m16,imm8 ; o16 0F BA /6 ib [386]
7015 \c BTR r/m32,imm8 ; o32 0F BA /6 ib [386]
7017 \c BTS r/m16,reg16 ; o16 0F AB /r [386]
7018 \c BTS r/m32,reg32 ; o32 0F AB /r [386]
7019 \c BTS r/m16,imm ; o16 0F BA /5 ib [386]
7020 \c BTS r/m32,imm ; o32 0F BA /5 ib [386]
7022 These instructions all test one bit of their first operand, whose
7023 index is given by the second operand, and store the value of that
7024 bit into the carry flag. Bit indices are from 0 (least significant)
7025 to 15 or 31 (most significant).
7027 In addition to storing the original value of the bit into the carry
7028 flag, \c{BTR} also resets (clears) the bit in the operand itself.
7029 \c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does
7030 not modify its operands.
7032 The destination can be a register or a memory location. The source can
7033 be a register or an immediate value.
7035 If the destination operand is a register, the bit offset should be
7036 in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands).
7037 An immediate value outside these ranges will be taken modulo 16/32
7040 If the destination operand is a memory location, then an immediate
7041 bit offset follows the same rules as for a register. If the bit offset
7042 is in a register, then it can be anything within the signed range of
7043 the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1)
7046 \S{insCALL} \i\c{CALL}: Call Subroutine
7048 \c CALL imm ; E8 rw/rd [8086]
7049 \c CALL imm:imm16 ; o16 9A iw iw [8086]
7050 \c CALL imm:imm32 ; o32 9A id iw [386]
7051 \c CALL FAR mem16 ; o16 FF /3 [8086]
7052 \c CALL FAR mem32 ; o32 FF /3 [386]
7053 \c CALL r/m16 ; o16 FF /2 [8086]
7054 \c CALL r/m32 ; o32 FF /2 [386]
7056 \c{CALL} calls a subroutine, by means of pushing the current
7057 instruction pointer (\c{IP}) and optionally \c{CS} as well on the
7058 stack, and then jumping to a given address.
7060 \c{CS} is pushed as well as \c{IP} if and only if the call is a far
7061 call, i.e. a destination segment address is specified in the
7062 instruction. The forms involving two colon-separated arguments are
7063 far calls; so are the \c{CALL FAR mem} forms.
7065 The immediate \i{near call} takes one of two forms (\c{call imm16/imm32},
7066 determined by the current segment size limit. For 16-bit operands,
7067 you would use \c{CALL 0x1234}, and for 32-bit operands you would use
7068 \c{CALL 0x12345678}. The value passed as an operand is a relative offset.
7070 You can choose between the two immediate \i{far call} forms
7071 (\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords:
7072 \c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}.
7074 The \c{CALL FAR mem} forms execute a far call by loading the
7075 destination address out of memory. The address loaded consists of 16
7076 or 32 bits of offset (depending on the operand size), and 16 bits of
7077 segment. The operand size may be overridden using \c{CALL WORD FAR
7078 mem} or \c{CALL DWORD FAR mem}.
7080 The \c{CALL r/m} forms execute a \i{near call} (within the same
7081 segment), loading the destination address out of memory or out of a
7082 register. The keyword \c{NEAR} may be specified, for clarity, in
7083 these forms, but is not necessary. Again, operand size can be
7084 overridden using \c{CALL WORD mem} or \c{CALL DWORD mem}.
7086 As a convenience, NASM does not require you to call a far procedure
7087 symbol by coding the cumbersome \c{CALL SEG routine:routine}, but
7088 instead allows the easier synonym \c{CALL FAR routine}.
7090 The \c{CALL r/m} forms given above are near calls; NASM will accept
7091 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
7092 is not strictly necessary.
7095 \S{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions
7097 \c CBW ; o16 98 [8086]
7098 \c CWDE ; o32 98 [386]
7100 \c CWD ; o16 99 [8086]
7101 \c CDQ ; o32 99 [386]
7103 All these instructions sign-extend a short value into a longer one,
7104 by replicating the top bit of the original value to fill the
7107 \c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of
7108 \c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into
7109 \c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating
7110 the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends
7111 \c{EAX} into \c{EDX:EAX}.
7114 \S{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags
7119 \c CLTS ; 0F 06 [286,PRIV]
7121 These instructions clear various flags. \c{CLC} clears the carry
7122 flag; \c{CLD} clears the direction flag; \c{CLI} clears the
7123 interrupt flag (thus disabling interrupts); and \c{CLTS} clears the
7124 task-switched (\c{TS}) flag in \c{CR0}.
7126 To set the carry, direction, or interrupt flags, use the \c{STC},
7127 \c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry
7128 flag, use \c{CMC} (\k{insCMC}).
7131 \S{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line
7133 \c CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2]
7135 \c{CLFLUSH} invalidates the cache line that contains the linear address
7136 specified by the source operand from all levels of the processor cache
7137 hierarchy (data and instruction). If, at any level of the cache
7138 hierarchy, the line is inconsistent with memory (dirty) it is written
7139 to memory before invalidation. The source operand points to a
7140 byte-sized memory location.
7142 Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be
7143 present on all processors which have \c{SSE2} support, and it may be
7144 supported on other processors; the \c{CPUID} instruction (\k{insCPUID})
7145 will return a bit which indicates support for the \c{CLFLUSH} instruction.
7148 \S{insCMC} \i\c{CMC}: Complement Carry Flag
7152 \c{CMC} changes the value of the carry flag: if it was 0, it sets it
7153 to 1, and vice versa.
7156 \S{insCMOVcc} \i\c{CMOVcc}: Conditional Move
7158 \c CMOVcc reg16,r/m16 ; o16 0F 40+cc /r [P6]
7159 \c CMOVcc reg32,r/m32 ; o32 0F 40+cc /r [P6]
7161 \c{CMOV} moves its source (second) operand into its destination
7162 (first) operand if the given condition code is satisfied; otherwise
7165 For a list of condition codes, see \k{iref-cc}.
7167 Although the \c{CMOV} instructions are flagged \c{P6} and above, they
7168 may not be supported by all Pentium Pro processors; the \c{CPUID}
7169 instruction (\k{insCPUID}) will return a bit which indicates whether
7170 conditional moves are supported.
7173 \S{insCMP} \i\c{CMP}: Compare Integers
7175 \c CMP r/m8,reg8 ; 38 /r [8086]
7176 \c CMP r/m16,reg16 ; o16 39 /r [8086]
7177 \c CMP r/m32,reg32 ; o32 39 /r [386]
7179 \c CMP reg8,r/m8 ; 3A /r [8086]
7180 \c CMP reg16,r/m16 ; o16 3B /r [8086]
7181 \c CMP reg32,r/m32 ; o32 3B /r [386]
7183 \c CMP r/m8,imm8 ; 80 /0 ib [8086]
7184 \c CMP r/m16,imm16 ; o16 81 /0 iw [8086]
7185 \c CMP r/m32,imm32 ; o32 81 /0 id [386]
7187 \c CMP r/m16,imm8 ; o16 83 /0 ib [8086]
7188 \c CMP r/m32,imm8 ; o32 83 /0 ib [386]
7190 \c CMP AL,imm8 ; 3C ib [8086]
7191 \c CMP AX,imm16 ; o16 3D iw [8086]
7192 \c CMP EAX,imm32 ; o32 3D id [386]
7194 \c{CMP} performs a `mental' subtraction of its second operand from
7195 its first operand, and affects the flags as if the subtraction had
7196 taken place, but does not store the result of the subtraction
7199 In the forms with an 8-bit immediate second operand and a longer
7200 first operand, the second operand is considered to be signed, and is
7201 sign-extended to the length of the first operand. In these cases,
7202 the \c{BYTE} qualifier is necessary to force NASM to generate this
7203 form of the instruction.
7205 The destination operand can be a register or a memory location. The
7206 source can be a register, memory location or an immediate value of
7207 the same size as the destination.
7210 \S{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare
7211 \I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD}
7212 \I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD}
7214 \c CMPPD xmm1,xmm2/mem128,imm8 ; 66 0F C2 /r ib [WILLAMETTE,SSE2]
7216 \c CMPEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 00 [WILLAMETTE,SSE2]
7217 \c CMPLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 01 [WILLAMETTE,SSE2]
7218 \c CMPLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 02 [WILLAMETTE,SSE2]
7219 \c CMPUNORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 03 [WILLAMETTE,SSE2]
7220 \c CMPNEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 04 [WILLAMETTE,SSE2]
7221 \c CMPNLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 05 [WILLAMETTE,SSE2]
7222 \c CMPNLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 06 [WILLAMETTE,SSE2]
7223 \c CMPORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 07 [WILLAMETTE,SSE2]
7225 The \c{CMPccPD} instructions compare the two packed double-precision
7226 FP values in the source and destination operands, and returns the
7227 result of the comparison in the destination register. The result of
7228 each comparison is a quadword mask of all 1s (comparison true) or
7229 all 0s (comparison false).
7231 The destination is an \c{XMM} register. The source can be either an
7232 \c{XMM} register or a 128-bit memory location.
7234 The third operand is an 8-bit immediate value, of which the low 3
7235 bits define the type of comparison. For ease of programming, the
7236 8 two-operand pseudo-instructions are provided, with the third
7237 operand already filled in. The \I{Condition Predicates}
7238 \c{Condition Predicates} are:
7242 \c LE 2 Less-than-or-equal
7243 \c UNORD 3 Unordered
7245 \c NLT 5 Not-less-than
7246 \c NLE 6 Not-less-than-or-equal
7249 For more details of the comparison predicates, and details of how
7250 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7253 \S{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare
7254 \I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS}
7255 \I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS}
7257 \c CMPPS xmm1,xmm2/mem128,imm8 ; 0F C2 /r ib [KATMAI,SSE]
7259 \c CMPEQPS xmm1,xmm2/mem128 ; 0F C2 /r 00 [KATMAI,SSE]
7260 \c CMPLTPS xmm1,xmm2/mem128 ; 0F C2 /r 01 [KATMAI,SSE]
7261 \c CMPLEPS xmm1,xmm2/mem128 ; 0F C2 /r 02 [KATMAI,SSE]
7262 \c CMPUNORDPS xmm1,xmm2/mem128 ; 0F C2 /r 03 [KATMAI,SSE]
7263 \c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE]
7264 \c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE]
7265 \c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE]
7266 \c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE]
7268 The \c{CMPccPS} instructions compare the two packed single-precision
7269 FP values in the source and destination operands, and returns the
7270 result of the comparison in the destination register. The result of
7271 each comparison is a doubleword mask of all 1s (comparison true) or
7272 all 0s (comparison false).
7274 The destination is an \c{XMM} register. The source can be either an
7275 \c{XMM} register or a 128-bit memory location.
7277 The third operand is an 8-bit immediate value, of which the low 3
7278 bits define the type of comparison. For ease of programming, the
7279 8 two-operand pseudo-instructions are provided, with the third
7280 operand already filled in. The \I{Condition Predicates}
7281 \c{Condition Predicates} are:
7285 \c LE 2 Less-than-or-equal
7286 \c UNORD 3 Unordered
7288 \c NLT 5 Not-less-than
7289 \c NLE 6 Not-less-than-or-equal
7292 For more details of the comparison predicates, and details of how
7293 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7296 \S{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings
7298 \c CMPSB ; A6 [8086]
7299 \c CMPSW ; o16 A7 [8086]
7300 \c CMPSD ; o32 A7 [386]
7302 \c{CMPSB} compares the byte at \c{[DS:SI]} or \c{[DS:ESI]} with the
7303 byte at \c{[ES:DI]} or \c{[ES:EDI]}, and sets the flags accordingly.
7304 It then increments or decrements (depending on the direction flag:
7305 increments if the flag is clear, decrements if it is set) \c{SI} and
7306 \c{DI} (or \c{ESI} and \c{EDI}).
7308 The registers used are \c{SI} and \c{DI} if the address size is 16
7309 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
7310 an address size not equal to the current \c{BITS} setting, you can
7311 use an explicit \i\c{a16} or \i\c{a32} prefix.
7313 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
7314 overridden by using a segment register name as a prefix (for
7315 example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]}
7316 or \c{[EDI]} cannot be overridden.
7318 \c{CMPSW} and \c{CMPSD} work in the same way, but they compare a
7319 word or a doubleword instead of a byte, and increment or decrement
7320 the addressing registers by 2 or 4 instead of 1.
7322 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
7323 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
7324 \c{ECX} - again, the address size chooses which) times until the
7325 first unequal or equal byte is found.
7328 \S{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare
7329 \I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD}
7330 \I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD}
7332 \c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2]
7334 \c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2]
7335 \c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2]
7336 \c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2]
7337 \c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2]
7338 \c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2]
7339 \c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2]
7340 \c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2]
7341 \c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2]
7343 The \c{CMPccSD} instructions compare the low-order double-precision
7344 FP values in the source and destination operands, and returns the
7345 result of the comparison in the destination register. The result of
7346 each comparison is a quadword mask of all 1s (comparison true) or
7347 all 0s (comparison false).
7349 The destination is an \c{XMM} register. The source can be either an
7350 \c{XMM} register or a 128-bit memory location.
7352 The third operand is an 8-bit immediate value, of which the low 3
7353 bits define the type of comparison. For ease of programming, the
7354 8 two-operand pseudo-instructions are provided, with the third
7355 operand already filled in. The \I{Condition Predicates}
7356 \c{Condition Predicates} are:
7360 \c LE 2 Less-than-or-equal
7361 \c UNORD 3 Unordered
7363 \c NLT 5 Not-less-than
7364 \c NLE 6 Not-less-than-or-equal
7367 For more details of the comparison predicates, and details of how
7368 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7371 \S{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare
7372 \I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS}
7373 \I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS}
7375 \c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE]
7377 \c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE]
7378 \c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE]
7379 \c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE]
7380 \c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE]
7381 \c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE]
7382 \c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE]
7383 \c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE]
7384 \c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE]
7386 The \c{CMPccSS} instructions compare the low-order single-precision
7387 FP values in the source and destination operands, and returns the
7388 result of the comparison in the destination register. The result of
7389 each comparison is a doubleword mask of all 1s (comparison true) or
7390 all 0s (comparison false).
7392 The destination is an \c{XMM} register. The source can be either an
7393 \c{XMM} register or a 128-bit memory location.
7395 The third operand is an 8-bit immediate value, of which the low 3
7396 bits define the type of comparison. For ease of programming, the
7397 8 two-operand pseudo-instructions are provided, with the third
7398 operand already filled in. The \I{Condition Predicates}
7399 \c{Condition Predicates} are:
7403 \c LE 2 Less-than-or-equal
7404 \c UNORD 3 Unordered
7406 \c NLT 5 Not-less-than
7407 \c NLE 6 Not-less-than-or-equal
7410 For more details of the comparison predicates, and details of how
7411 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7414 \S{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange
7416 \c CMPXCHG r/m8,reg8 ; 0F B0 /r [PENT]
7417 \c CMPXCHG r/m16,reg16 ; o16 0F B1 /r [PENT]
7418 \c CMPXCHG r/m32,reg32 ; o32 0F B1 /r [PENT]
7420 \c CMPXCHG486 r/m8,reg8 ; 0F A6 /r [486,UNDOC]
7421 \c CMPXCHG486 r/m16,reg16 ; o16 0F A7 /r [486,UNDOC]
7422 \c CMPXCHG486 r/m32,reg32 ; o32 0F A7 /r [486,UNDOC]
7424 These two instructions perform exactly the same operation; however,
7425 apparently some (not all) 486 processors support it under a
7426 non-standard opcode, so NASM provides the undocumented
7427 \c{CMPXCHG486} form to generate the non-standard opcode.
7429 \c{CMPXCHG} compares its destination (first) operand to the value in
7430 \c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the
7431 instruction). If they are equal, it copies its source (second)
7432 operand into the destination and sets the zero flag. Otherwise, it
7433 clears the zero flag and leaves the destination alone.
7435 The destination can be either a register or a memory location. The
7436 source is a register.
7438 \c{CMPXCHG} is intended to be used for atomic operations in
7439 multitasking or multiprocessor environments. To safely update a
7440 value in shared memory, for example, you might load the value into
7441 \c{EAX}, load the updated value into \c{EBX}, and then execute the
7442 instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not
7443 changed since being loaded, it is updated with your desired new
7444 value, and the zero flag is set to let you know it has worked. (The
7445 \c{LOCK} prefix prevents another processor doing anything in the
7446 middle of this operation: it guarantees atomicity.) However, if
7447 another processor has modified the value in between your load and
7448 your attempted store, the store does not happen, and you are
7449 notified of the failure by a cleared zero flag, so you can go round
7453 \S{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes
7455 \c CMPXCHG8B mem ; 0F C7 /1 [PENT]
7457 This is a larger and more unwieldy version of \c{CMPXCHG}: it
7458 compares the 64-bit (eight-byte) value stored at \c{[mem]} with the
7459 value in \c{EDX:EAX}. If they are equal, it sets the zero flag and
7460 stores \c{ECX:EBX} into the memory area. If they are unequal, it
7461 clears the zero flag and stores the memory contents into \c{EDX:EAX}.
7463 \c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic
7464 execution. This is useful in multi-processor and multi-tasking
7468 \S{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
7470 \c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2]
7472 \c{COMISD} compares the low-order double-precision FP value in the
7473 two source operands. ZF, PF and CF are set according to the result.
7474 OF, AF and AF are cleared. The unordered result is returned if either
7475 source is a NaN (QNaN or SNaN).
7477 The destination operand is an \c{XMM} register. The source can be either
7478 an \c{XMM} register or a memory location.
7480 The flags are set according to the following rules:
7482 \c Result Flags Values
7484 \c UNORDERED: ZF,PF,CF <-- 111;
7485 \c GREATER_THAN: ZF,PF,CF <-- 000;
7486 \c LESS_THAN: ZF,PF,CF <-- 001;
7487 \c EQUAL: ZF,PF,CF <-- 100;
7490 \S{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
7492 \c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE]
7494 \c{COMISS} compares the low-order single-precision FP value in the
7495 two source operands. ZF, PF and CF are set according to the result.
7496 OF, AF and AF are cleared. The unordered result is returned if either
7497 source is a NaN (QNaN or SNaN).
7499 The destination operand is an \c{XMM} register. The source can be either
7500 an \c{XMM} register or a memory location.
7502 The flags are set according to the following rules:
7504 \c Result Flags Values
7506 \c UNORDERED: ZF,PF,CF <-- 111;
7507 \c GREATER_THAN: ZF,PF,CF <-- 000;
7508 \c LESS_THAN: ZF,PF,CF <-- 001;
7509 \c EQUAL: ZF,PF,CF <-- 100;
7512 \S{insCPUID} \i\c{CPUID}: Get CPU Identification Code
7514 \c CPUID ; 0F A2 [PENT]
7516 \c{CPUID} returns various information about the processor it is
7517 being executed on. It fills the four registers \c{EAX}, \c{EBX},
7518 \c{ECX} and \c{EDX} with information, which varies depending on the
7519 input contents of \c{EAX}.
7521 \c{CPUID} also acts as a barrier to serialise instruction execution:
7522 executing the \c{CPUID} instruction guarantees that all the effects
7523 (memory modification, flag modification, register modification) of
7524 previous instructions have been completed before the next
7525 instruction gets fetched.
7527 The information returned is as follows:
7529 \b If \c{EAX} is zero on input, \c{EAX} on output holds the maximum
7530 acceptable input value of \c{EAX}, and \c{EBX:EDX:ECX} contain the
7531 string \c{"GenuineIntel"} (or not, if you have a clone processor).
7532 That is to say, \c{EBX} contains \c{"Genu"} (in NASM's own sense of
7533 character constants, described in \k{chrconst}), \c{EDX} contains
7534 \c{"ineI"} and \c{ECX} contains \c{"ntel"}.
7536 \b If \c{EAX} is one on input, \c{EAX} on output contains version
7537 information about the processor, and \c{EDX} contains a set of
7538 feature flags, showing the presence and absence of various features.
7539 For example, bit 8 is set if the \c{CMPXCHG8B} instruction
7540 (\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional
7541 move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported,
7542 and bit 23 is set if \c{MMX} instructions are supported.
7544 \b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX}
7545 all contain information about caches and TLBs (Translation Lookahead
7548 For more information on the data returned from \c{CPUID}, see the
7549 documentation from Intel and other processor manufacturers.
7552 \S{insCVTDQ2PD} \i\c{CVTDQ2PD}:
7553 Packed Signed INT32 to Packed Double-Precision FP Conversion
7555 \c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2]
7557 \c{CVTDQ2PD} converts two packed signed doublewords from the source
7558 operand to two packed double-precision FP values in the destination
7561 The destination operand is an \c{XMM} register. The source can be
7562 either an \c{XMM} register or a 64-bit memory location. If the
7563 source is a register, the packed integers are in the low quadword.
7566 \S{insCVTDQ2PS} \i\c{CVTDQ2PS}:
7567 Packed Signed INT32 to Packed Single-Precision FP Conversion
7569 \c CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2]
7571 \c{CVTDQ2PS} converts four packed signed doublewords from the source
7572 operand to four packed single-precision FP values in the destination
7575 The destination operand is an \c{XMM} register. The source can be
7576 either an \c{XMM} register or a 128-bit memory location.
7578 For more details of this instruction, see the Intel Processor manuals.
7581 \S{insCVTPD2DQ} \i\c{CVTPD2DQ}:
7582 Packed Double-Precision FP to Packed Signed INT32 Conversion
7584 \c CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2]
7586 \c{CVTPD2DQ} converts two packed double-precision FP values from the
7587 source operand to two packed signed doublewords in the low quadword
7588 of the destination operand. The high quadword of the destination is
7591 The destination operand is an \c{XMM} register. The source can be
7592 either an \c{XMM} register or a 128-bit memory location.
7594 For more details of this instruction, see the Intel Processor manuals.
7597 \S{insCVTPD2PI} \i\c{CVTPD2PI}:
7598 Packed Double-Precision FP to Packed Signed INT32 Conversion
7600 \c CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2]
7602 \c{CVTPD2PI} converts two packed double-precision FP values from the
7603 source operand to two packed signed doublewords in the destination
7606 The destination operand is an \c{MMX} register. The source can be
7607 either an \c{XMM} register or a 128-bit memory location.
7609 For more details of this instruction, see the Intel Processor manuals.
7612 \S{insCVTPD2PS} \i\c{CVTPD2PS}:
7613 Packed Double-Precision FP to Packed Single-Precision FP Conversion
7615 \c CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2]
7617 \c{CVTPD2PS} converts two packed double-precision FP values from the
7618 source operand to two packed single-precision FP values in the low
7619 quadword of the destination operand. The high quadword of the
7620 destination is set to all 0s.
7622 The destination operand is an \c{XMM} register. The source can be
7623 either an \c{XMM} register or a 128-bit memory location.
7625 For more details of this instruction, see the Intel Processor manuals.
7628 \S{insCVTPI2PD} \i\c{CVTPI2PD}:
7629 Packed Signed INT32 to Packed Double-Precision FP Conversion
7631 \c CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2]
7633 \c{CVTPI2PD} converts two packed signed doublewords from the source
7634 operand to two packed double-precision FP values in the destination
7637 The destination operand is an \c{XMM} register. The source can be
7638 either an \c{MMX} register or a 64-bit memory location.
7640 For more details of this instruction, see the Intel Processor manuals.
7643 \S{insCVTPI2PS} \i\c{CVTPI2PS}:
7644 Packed Signed INT32 to Packed Single-FP Conversion
7646 \c CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE]
7648 \c{CVTPI2PS} converts two packed signed doublewords from the source
7649 operand to two packed single-precision FP values in the low quadword
7650 of the destination operand. The high quadword of the destination
7653 The destination operand is an \c{XMM} register. The source can be
7654 either an \c{MMX} register or a 64-bit memory location.
7656 For more details of this instruction, see the Intel Processor manuals.
7659 \S{insCVTPS2DQ} \i\c{CVTPS2DQ}:
7660 Packed Single-Precision FP to Packed Signed INT32 Conversion
7662 \c CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2]
7664 \c{CVTPS2DQ} converts four packed single-precision FP values from the
7665 source operand to four packed signed doublewords in the destination operand.
7667 The destination operand is an \c{XMM} register. The source can be
7668 either an \c{XMM} register or a 128-bit memory location.
7670 For more details of this instruction, see the Intel Processor manuals.
7673 \S{insCVTPS2PD} \i\c{CVTPS2PD}:
7674 Packed Single-Precision FP to Packed Double-Precision FP Conversion
7676 \c CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2]
7678 \c{CVTPS2PD} converts two packed single-precision FP values from the
7679 source operand to two packed double-precision FP values in the destination
7682 The destination operand is an \c{XMM} register. The source can be
7683 either an \c{XMM} register or a 64-bit memory location. If the source
7684 is a register, the input values are in the low quadword.
7686 For more details of this instruction, see the Intel Processor manuals.
7689 \S{insCVTPS2PI} \i\c{CVTPS2PI}:
7690 Packed Single-Precision FP to Packed Signed INT32 Conversion
7692 \c CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE]
7694 \c{CVTPS2PI} converts two packed single-precision FP values from
7695 the source operand to two packed signed doublewords in the destination
7698 The destination operand is an \c{MMX} register. The source can be
7699 either an \c{XMM} register or a 64-bit memory location. If the
7700 source is a register, the input values are in the low quadword.
7702 For more details of this instruction, see the Intel Processor manuals.
7705 \S{insCVTSD2SI} \i\c{CVTSD2SI}:
7706 Scalar Double-Precision FP to Signed INT32 Conversion
7708 \c CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2]
7710 \c{CVTSD2SI} converts a double-precision FP value from the source
7711 operand to a signed doubleword in the destination operand.
7713 The destination operand is a general purpose register. The source can be
7714 either an \c{XMM} register or a 64-bit memory location. If the
7715 source is a register, the input value is in the low quadword.
7717 For more details of this instruction, see the Intel Processor manuals.
7720 \S{insCVTSD2SS} \i\c{CVTSD2SS}:
7721 Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
7723 \c CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE]
7725 \c{CVTSD2SS} converts a double-precision FP value from the source
7726 operand to a single-precision FP value in the low doubleword of the
7727 destination operand. The upper 3 doublewords are left unchanged.
7729 The destination operand is an \c{XMM} register. The source can be
7730 either an \c{XMM} register or a 64-bit memory location. If the
7731 source is a register, the input value is in the low quadword.
7733 For more details of this instruction, see the Intel Processor manuals.
7736 \S{insCVTSI2SD} \i\c{CVTSI2SD}:
7737 Signed INT32 to Scalar Double-Precision FP Conversion
7739 \c CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2]
7741 \c{CVTSI2SD} converts a signed doubleword from the source operand to
7742 a double-precision FP value in the low quadword of the destination
7743 operand. The high quadword is left unchanged.
7745 The destination operand is an \c{XMM} register. The source can be either
7746 a general purpose register or a 32-bit memory location.
7748 For more details of this instruction, see the Intel Processor manuals.
7751 \S{insCVTSI2SS} \i\c{CVTSI2SS}:
7752 Signed INT32 to Scalar Single-Precision FP Conversion
7754 \c CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE]
7756 \c{CVTSI2SS} converts a signed doubleword from the source operand to a
7757 single-precision FP value in the low doubleword of the destination operand.
7758 The upper 3 doublewords are left unchanged.
7760 The destination operand is an \c{XMM} register. The source can be either
7761 a general purpose register or a 32-bit memory location.
7763 For more details of this instruction, see the Intel Processor manuals.
7766 \S{insCVTSS2SD} \i\c{CVTSS2SD}:
7767 Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
7769 \c CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2]
7771 \c{CVTSS2SD} converts a single-precision FP value from the source operand
7772 to a double-precision FP value in the low quadword of the destination
7773 operand. The upper quadword is left unchanged.
7775 The destination operand is an \c{XMM} register. The source can be either
7776 an \c{XMM} register or a 32-bit memory location. If the source is a
7777 register, the input value is contained in the low doubleword.
7779 For more details of this instruction, see the Intel Processor manuals.
7782 \S{insCVTSS2SI} \i\c{CVTSS2SI}:
7783 Scalar Single-Precision FP to Signed INT32 Conversion
7785 \c CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE]
7787 \c{CVTSS2SI} converts a single-precision FP value from the source
7788 operand to a signed doubleword in the destination operand.
7790 The destination operand is a general purpose register. The source can be
7791 either an \c{XMM} register or a 32-bit memory location. If the
7792 source is a register, the input value is in the low doubleword.
7794 For more details of this instruction, see the Intel Processor manuals.
7797 \S{insCVTTPD2DQ} \i\c{CVTTPD2DQ}:
7798 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7800 \c CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2]
7802 \c{CVTTPD2DQ} converts two packed double-precision FP values in the source
7803 operand to two packed single-precision FP values in the destination operand.
7804 If the result is inexact, it is truncated (rounded toward zero). The high
7805 quadword is set to all 0s.
7807 The destination operand is an \c{XMM} register. The source can be
7808 either an \c{XMM} register or a 128-bit memory location.
7810 For more details of this instruction, see the Intel Processor manuals.
7813 \S{insCVTTPD2PI} \i\c{CVTTPD2PI}:
7814 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7816 \c CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2]
7818 \c{CVTTPD2PI} converts two packed double-precision FP values in the source
7819 operand to two packed single-precision FP values in the destination operand.
7820 If the result is inexact, it is truncated (rounded toward zero).
7822 The destination operand is an \c{MMX} register. The source can be
7823 either an \c{XMM} register or a 128-bit memory location.
7825 For more details of this instruction, see the Intel Processor manuals.
7828 \S{insCVTTPS2DQ} \i\c{CVTTPS2DQ}:
7829 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7831 \c CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2]
7833 \c{CVTTPS2DQ} converts four packed single-precision FP values in the source
7834 operand to four packed signed doublewords in the destination operand.
7835 If the result is inexact, it is truncated (rounded toward zero).
7837 The destination operand is an \c{XMM} register. The source can be
7838 either an \c{XMM} register or a 128-bit memory location.
7840 For more details of this instruction, see the Intel Processor manuals.
7843 \S{insCVTTPS2PI} \i\c{CVTTPS2PI}:
7844 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7846 \c CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE]
7848 \c{CVTTPS2PI} converts two packed single-precision FP values in the source
7849 operand to two packed signed doublewords in the destination operand.
7850 If the result is inexact, it is truncated (rounded toward zero). If
7851 the source is a register, the input values are in the low quadword.
7853 The destination operand is an \c{MMX} register. The source can be
7854 either an \c{XMM} register or a 64-bit memory location. If the source
7855 is a register, the input value is in the low quadword.
7857 For more details of this instruction, see the Intel Processor manuals.
7860 \S{insCVTTSD2SI} \i\c{CVTTSD2SI}:
7861 Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
7863 \c CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2]
7865 \c{CVTTSD2SI} converts a double-precision FP value in the source operand
7866 to a signed doubleword in the destination operand. If the result is
7867 inexact, it is truncated (rounded toward zero).
7869 The destination operand is a general purpose register. The source can be
7870 either an \c{XMM} register or a 64-bit memory location. If the source is a
7871 register, the input value is in the low quadword.
7873 For more details of this instruction, see the Intel Processor manuals.
7876 \S{insCVTTSS2SI} \i\c{CVTTSS2SI}:
7877 Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
7879 \c CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE]
7881 \c{CVTTSS2SI} converts a single-precision FP value in the source operand
7882 to a signed doubleword in the destination operand. If the result is
7883 inexact, it is truncated (rounded toward zero).
7885 The destination operand is a general purpose register. The source can be
7886 either an \c{XMM} register or a 32-bit memory location. If the source is a
7887 register, the input value is in the low doubleword.
7889 For more details of this instruction, see the Intel Processor manuals.
7892 \S{insDAA} \i\c{DAA}, \i\c{DAS}: Decimal Adjustments
7897 These instructions are used in conjunction with the add and subtract
7898 instructions to perform binary-coded decimal arithmetic in
7899 \e{packed} (one BCD digit per nibble) form. For the unpacked
7900 equivalents, see \k{insAAA}.
7902 \c{DAA} should be used after a one-byte \c{ADD} instruction whose
7903 destination was the \c{AL} register: by means of examining the value
7904 in the \c{AL} and also the auxiliary carry flag \c{AF}, it
7905 determines whether either digit of the addition has overflowed, and
7906 adjusts it (and sets the carry and auxiliary-carry flags) if so. You
7907 can add long BCD strings together by doing \c{ADD}/\c{DAA} on the
7908 low two digits, then doing \c{ADC}/\c{DAA} on each subsequent pair
7911 \c{DAS} works similarly to \c{DAA}, but is for use after \c{SUB}
7912 instructions rather than \c{ADD}.
7915 \S{insDEC} \i\c{DEC}: Decrement Integer
7917 \c DEC reg16 ; o16 48+r [8086]
7918 \c DEC reg32 ; o32 48+r [386]
7919 \c DEC r/m8 ; FE /1 [8086]
7920 \c DEC r/m16 ; o16 FF /1 [8086]
7921 \c DEC r/m32 ; o32 FF /1 [386]
7923 \c{DEC} subtracts 1 from its operand. It does \e{not} affect the
7924 carry flag: to affect the carry flag, use \c{SUB something,1} (see
7925 \k{insSUB}). \c{DEC} affects all the other flags according to the result.
7927 This instruction can be used with a \c{LOCK} prefix to allow atomic
7930 See also \c{INC} (\k{insINC}).
7933 \S{insDIV} \i\c{DIV}: Unsigned Integer Divide
7935 \c DIV r/m8 ; F6 /6 [8086]
7936 \c DIV r/m16 ; o16 F7 /6 [8086]
7937 \c DIV r/m32 ; o32 F7 /6 [386]
7939 \c{DIV} performs unsigned integer division. The explicit operand
7940 provided is the divisor; the dividend and destination operands are
7941 implicit, in the following way:
7943 \b For \c{DIV r/m8}, \c{AX} is divided by the given operand; the
7944 quotient is stored in \c{AL} and the remainder in \c{AH}.
7946 \b For \c{DIV r/m16}, \c{DX:AX} is divided by the given operand; the
7947 quotient is stored in \c{AX} and the remainder in \c{DX}.
7949 \b For \c{DIV r/m32}, \c{EDX:EAX} is divided by the given operand;
7950 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
7952 Signed integer division is performed by the \c{IDIV} instruction:
7956 \S{insDIVPD} \i\c{DIVPD}: Packed Double-Precision FP Divide
7958 \c DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2]
7960 \c{DIVPD} divides the two packed double-precision FP values in
7961 the destination operand by the two packed double-precision FP
7962 values in the source operand, and stores the packed double-precision
7963 results in the destination register.
7965 The destination is an \c{XMM} register. The source operand can be
7966 either an \c{XMM} register or a 128-bit memory location.
7968 \c dst[0-63] := dst[0-63] / src[0-63],
7969 \c dst[64-127] := dst[64-127] / src[64-127].
7972 \S{insDIVPS} \i\c{DIVPS}: Packed Single-Precision FP Divide
7974 \c DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE]
7976 \c{DIVPS} divides the four packed single-precision FP values in
7977 the destination operand by the four packed single-precision FP
7978 values in the source operand, and stores the packed single-precision
7979 results in the destination register.
7981 The destination is an \c{XMM} register. The source operand can be
7982 either an \c{XMM} register or a 128-bit memory location.
7984 \c dst[0-31] := dst[0-31] / src[0-31],
7985 \c dst[32-63] := dst[32-63] / src[32-63],
7986 \c dst[64-95] := dst[64-95] / src[64-95],
7987 \c dst[96-127] := dst[96-127] / src[96-127].
7990 \S{insDIVSD} \i\c{DIVSD}: Scalar Double-Precision FP Divide
7992 \c DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2]
7994 \c{DIVSD} divides the low-order double-precision FP value in the
7995 destination operand by the low-order double-precision FP value in
7996 the source operand, and stores the double-precision result in the
7997 destination register.
7999 The destination is an \c{XMM} register. The source operand can be
8000 either an \c{XMM} register or a 64-bit memory location.
8002 \c dst[0-63] := dst[0-63] / src[0-63],
8003 \c dst[64-127] remains unchanged.
8006 \S{insDIVSS} \i\c{DIVSS}: Scalar Single-Precision FP Divide
8008 \c DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE]
8010 \c{DIVSS} divides the low-order single-precision FP value in the
8011 destination operand by the low-order single-precision FP value in
8012 the source operand, and stores the single-precision result in the
8013 destination register.
8015 The destination is an \c{XMM} register. The source operand can be
8016 either an \c{XMM} register or a 32-bit memory location.
8018 \c dst[0-31] := dst[0-31] / src[0-31],
8019 \c dst[32-127] remains unchanged.
8022 \S{insEMMS} \i\c{EMMS}: Empty MMX State
8024 \c EMMS ; 0F 77 [PENT,MMX]
8026 \c{EMMS} sets the FPU tag word (marking which floating-point registers
8027 are available) to all ones, meaning all registers are available for
8028 the FPU to use. It should be used after executing \c{MMX} instructions
8029 and before executing any subsequent floating-point operations.
8032 \S{insENTER} \i\c{ENTER}: Create Stack Frame
8034 \c ENTER imm,imm ; C8 iw ib [186]
8036 \c{ENTER} constructs a \i\c{stack frame} for a high-level language
8037 procedure call. The first operand (the \c{iw} in the opcode
8038 definition above refers to the first operand) gives the amount of
8039 stack space to allocate for local variables; the second (the \c{ib}
8040 above) gives the nesting level of the procedure (for languages like
8041 Pascal, with nested procedures).
8043 The function of \c{ENTER}, with a nesting level of zero, is
8046 \c PUSH EBP ; or PUSH BP in 16 bits
8047 \c MOV EBP,ESP ; or MOV BP,SP in 16 bits
8048 \c SUB ESP,operand1 ; or SUB SP,operand1 in 16 bits
8050 This creates a stack frame with the procedure parameters accessible
8051 upwards from \c{EBP}, and local variables accessible downwards from
8054 With a nesting level of one, the stack frame created is 4 (or 2)
8055 bytes bigger, and the value of the final frame pointer \c{EBP} is
8056 accessible in memory at \c{[EBP-4]}.
8058 This allows \c{ENTER}, when called with a nesting level of two, to
8059 look at the stack frame described by the \e{previous} value of
8060 \c{EBP}, find the frame pointer at offset -4 from that, and push it
8061 along with its new frame pointer, so that when a level-two procedure
8062 is called from within a level-one procedure, \c{[EBP-4]} holds the
8063 frame pointer of the most recent level-one procedure call and
8064 \c{[EBP-8]} holds that of the most recent level-two call. And so on,
8065 for nesting levels up to 31.
8067 Stack frames created by \c{ENTER} can be destroyed by the \c{LEAVE}
8068 instruction: see \k{insLEAVE}.
8071 \S{insF2XM1} \i\c{F2XM1}: Calculate 2**X-1
8073 \c F2XM1 ; D9 F0 [8086,FPU]
8075 \c{F2XM1} raises 2 to the power of \c{ST0}, subtracts one, and
8076 stores the result back into \c{ST0}. The initial contents of \c{ST0}
8077 must be a number in the range -1.0 to +1.0.
8080 \S{insFABS} \i\c{FABS}: Floating-Point Absolute Value
8082 \c FABS ; D9 E1 [8086,FPU]
8084 \c{FABS} computes the absolute value of \c{ST0},by clearing the sign
8085 bit, and stores the result back in \c{ST0}.
8088 \S{insFADD} \i\c{FADD}, \i\c{FADDP}: Floating-Point Addition
8090 \c FADD mem32 ; D8 /0 [8086,FPU]
8091 \c FADD mem64 ; DC /0 [8086,FPU]
8093 \c FADD fpureg ; D8 C0+r [8086,FPU]
8094 \c FADD ST0,fpureg ; D8 C0+r [8086,FPU]
8096 \c FADD TO fpureg ; DC C0+r [8086,FPU]
8097 \c FADD fpureg,ST0 ; DC C0+r [8086,FPU]
8099 \c FADDP fpureg ; DE C0+r [8086,FPU]
8100 \c FADDP fpureg,ST0 ; DE C0+r [8086,FPU]
8102 \b \c{FADD}, given one operand, adds the operand to \c{ST0} and stores
8103 the result back in \c{ST0}. If the operand has the \c{TO} modifier,
8104 the result is stored in the register given rather than in \c{ST0}.
8106 \b \c{FADDP} performs the same function as \c{FADD TO}, but pops the
8107 register stack after storing the result.
8109 The given two-operand forms are synonyms for the one-operand forms.
8111 To add an integer value to \c{ST0}, use the c{FIADD} instruction
8115 \S{insFBLD} \i\c{FBLD}, \i\c{FBSTP}: BCD Floating-Point Load and Store
8117 \c FBLD mem80 ; DF /4 [8086,FPU]
8118 \c FBSTP mem80 ; DF /6 [8086,FPU]
8120 \c{FBLD} loads an 80-bit (ten-byte) packed binary-coded decimal
8121 number from the given memory address, converts it to a real, and
8122 pushes it on the register stack. \c{FBSTP} stores the value of
8123 \c{ST0}, in packed BCD, at the given address and then pops the
8127 \S{insFCHS} \i\c{FCHS}: Floating-Point Change Sign
8129 \c FCHS ; D9 E0 [8086,FPU]
8131 \c{FCHS} negates the number in \c{ST0}, by inverting the sign bit:
8132 negative numbers become positive, and vice versa.
8135 \S{insFCLEX} \i\c{FCLEX}, \c{FNCLEX}: Clear Floating-Point Exceptions
8137 \c FCLEX ; 9B DB E2 [8086,FPU]
8138 \c FNCLEX ; DB E2 [8086,FPU]
8140 \c{FCLEX} clears any floating-point exceptions which may be pending.
8141 \c{FNCLEX} does the same thing but doesn't wait for previous
8142 floating-point operations (including the \e{handling} of pending
8143 exceptions) to finish first.
8146 \S{insFCMOVB} \i\c{FCMOVcc}: Floating-Point Conditional Move
8148 \c FCMOVB fpureg ; DA C0+r [P6,FPU]
8149 \c FCMOVB ST0,fpureg ; DA C0+r [P6,FPU]
8151 \c FCMOVE fpureg ; DA C8+r [P6,FPU]
8152 \c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU]
8154 \c FCMOVBE fpureg ; DA D0+r [P6,FPU]
8155 \c FCMOVBE ST0,fpureg ; DA D0+r [P6,FPU]
8157 \c FCMOVU fpureg ; DA D8+r [P6,FPU]
8158 \c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU]
8160 \c FCMOVNB fpureg ; DB C0+r [P6,FPU]
8161 \c FCMOVNB ST0,fpureg ; DB C0+r [P6,FPU]
8163 \c FCMOVNE fpureg ; DB C8+r [P6,FPU]
8164 \c FCMOVNE ST0,fpureg ; DB C8+r [P6,FPU]
8166 \c FCMOVNBE fpureg ; DB D0+r [P6,FPU]
8167 \c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU]
8169 \c FCMOVNU fpureg ; DB D8+r [P6,FPU]
8170 \c FCMOVNU ST0,fpureg ; DB D8+r [P6,FPU]
8172 The \c{FCMOV} instructions perform conditional move operations: each
8173 of them moves the contents of the given register into \c{ST0} if its
8174 condition is satisfied, and does nothing if not.
8176 The conditions are not the same as the standard condition codes used
8177 with conditional jump instructions. The conditions \c{B}, \c{BE},
8178 \c{NB}, \c{NBE}, \c{E} and \c{NE} are exactly as normal, but none of
8179 the other standard ones are supported. Instead, the condition \c{U}
8180 and its counterpart \c{NU} are provided; the \c{U} condition is
8181 satisfied if the last two floating-point numbers compared were
8182 \e{unordered}, i.e. they were not equal but neither one could be
8183 said to be greater than the other, for example if they were NaNs.
8184 (The flag state which signals this is the setting of the parity
8185 flag: so the \c{U} condition is notionally equivalent to \c{PE}, and
8186 \c{NU} is equivalent to \c{PO}.)
8188 The \c{FCMOV} conditions test the main processor's status flags, not
8189 the FPU status flags, so using \c{FCMOV} directly after \c{FCOM}
8190 will not work. Instead, you should either use \c{FCOMI} which writes
8191 directly to the main CPU flags word, or use \c{FSTSW} to extract the
8194 Although the \c{FCMOV} instructions are flagged \c{P6} above, they
8195 may not be supported by all Pentium Pro processors; the \c{CPUID}
8196 instruction (\k{insCPUID}) will return a bit which indicates whether
8197 conditional moves are supported.
8200 \S{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI},
8201 \i\c{FCOMIP}: Floating-Point Compare
8203 \c FCOM mem32 ; D8 /2 [8086,FPU]
8204 \c FCOM mem64 ; DC /2 [8086,FPU]
8205 \c FCOM fpureg ; D8 D0+r [8086,FPU]
8206 \c FCOM ST0,fpureg ; D8 D0+r [8086,FPU]
8208 \c FCOMP mem32 ; D8 /3 [8086,FPU]
8209 \c FCOMP mem64 ; DC /3 [8086,FPU]
8210 \c FCOMP fpureg ; D8 D8+r [8086,FPU]
8211 \c FCOMP ST0,fpureg ; D8 D8+r [8086,FPU]
8213 \c FCOMPP ; DE D9 [8086,FPU]
8215 \c FCOMI fpureg ; DB F0+r [P6,FPU]
8216 \c FCOMI ST0,fpureg ; DB F0+r [P6,FPU]
8218 \c FCOMIP fpureg ; DF F0+r [P6,FPU]
8219 \c FCOMIP ST0,fpureg ; DF F0+r [P6,FPU]
8221 \c{FCOM} compares \c{ST0} with the given operand, and sets the FPU
8222 flags accordingly. \c{ST0} is treated as the left-hand side of the
8223 comparison, so that the carry flag is set (for a `less-than' result)
8224 if \c{ST0} is less than the given operand.
8226 \c{FCOMP} does the same as \c{FCOM}, but pops the register stack
8227 afterwards. \c{FCOMPP} compares \c{ST0} with \c{ST1} and then pops
8228 the register stack twice.
8230 \c{FCOMI} and \c{FCOMIP} work like the corresponding forms of
8231 \c{FCOM} and \c{FCOMP}, but write their results directly to the CPU
8232 flags register rather than the FPU status word, so they can be
8233 immediately followed by conditional jump or conditional move
8236 The \c{FCOM} instructions differ from the \c{FUCOM} instructions
8237 (\k{insFUCOM}) only in the way they handle quiet NaNs: \c{FUCOM}
8238 will handle them silently and set the condition code flags to an
8239 `unordered' result, whereas \c{FCOM} will generate an exception.
8242 \S{insFCOS} \i\c{FCOS}: Cosine
8244 \c FCOS ; D9 FF [386,FPU]
8246 \c{FCOS} computes the cosine of \c{ST0} (in radians), and stores the
8247 result in \c{ST0}. The absolute value of \c{ST0} must be less than 2**63.
8249 See also \c{FSINCOS} (\k{insFSIN}).
8252 \S{insFDECSTP} \i\c{FDECSTP}: Decrement Floating-Point Stack Pointer
8254 \c FDECSTP ; D9 F6 [8086,FPU]
8256 \c{FDECSTP} decrements the `top' field in the floating-point status
8257 word. This has the effect of rotating the FPU register stack by one,
8258 as if the contents of \c{ST7} had been pushed on the stack. See also
8259 \c{FINCSTP} (\k{insFINCSTP}).
8262 \S{insFDISI} \i\c{FxDISI}, \i\c{FxENI}: Disable and Enable Floating-Point Interrupts
8264 \c FDISI ; 9B DB E1 [8086,FPU]
8265 \c FNDISI ; DB E1 [8086,FPU]
8267 \c FENI ; 9B DB E0 [8086,FPU]
8268 \c FNENI ; DB E0 [8086,FPU]
8270 \c{FDISI} and \c{FENI} disable and enable floating-point interrupts.
8271 These instructions are only meaningful on original 8087 processors:
8272 the 287 and above treat them as no-operation instructions.
8274 \c{FNDISI} and \c{FNENI} do the same thing as \c{FDISI} and \c{FENI}
8275 respectively, but without waiting for the floating-point processor
8276 to finish what it was doing first.
8279 \S{insFDIV} \i\c{FDIV}, \i\c{FDIVP}, \i\c{FDIVR}, \i\c{FDIVRP}: Floating-Point Division
8281 \c FDIV mem32 ; D8 /6 [8086,FPU]
8282 \c FDIV mem64 ; DC /6 [8086,FPU]
8284 \c FDIV fpureg ; D8 F0+r [8086,FPU]
8285 \c FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
8287 \c FDIV TO fpureg ; DC F8+r [8086,FPU]
8288 \c FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
8290 \c FDIVR mem32 ; D8 /0 [8086,FPU]
8291 \c FDIVR mem64 ; DC /0 [8086,FPU]
8293 \c FDIVR fpureg ; D8 F8+r [8086,FPU]
8294 \c FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
8296 \c FDIVR TO fpureg ; DC F0+r [8086,FPU]
8297 \c FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
8299 \c FDIVP fpureg ; DE F8+r [8086,FPU]
8300 \c FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
8302 \c FDIVRP fpureg ; DE F0+r [8086,FPU]
8303 \c FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
8305 \b \c{FDIV} divides \c{ST0} by the given operand and stores the result
8306 back in \c{ST0}, unless the \c{TO} qualifier is given, in which case
8307 it divides the given operand by \c{ST0} and stores the result in the
8310 \b \c{FDIVR} does the same thing, but does the division the other way
8311 up: so if \c{TO} is not given, it divides the given operand by
8312 \c{ST0} and stores the result in \c{ST0}, whereas if \c{TO} is given
8313 it divides \c{ST0} by its operand and stores the result in the
8316 \b \c{FDIVP} operates like \c{FDIV TO}, but pops the register stack
8317 once it has finished.
8319 \b \c{FDIVRP} operates like \c{FDIVR TO}, but pops the register stack
8320 once it has finished.
8322 For FP/Integer divisions, see \c{FIDIV} (\k{insFIDIV}).
8325 \S{insFEMMS} \i\c{FEMMS}: Faster Enter/Exit of the MMX or floating-point state
8327 \c FEMMS ; 0F 0E [PENT,3DNOW]
8329 \c{FEMMS} can be used in place of the \c{EMMS} instruction on
8330 processors which support the 3DNow! instruction set. Following
8331 execution of \c{FEMMS}, the state of the \c{MMX/FP} registers
8332 is undefined, and this allows a faster context switch between
8333 \c{FP} and \c{MMX} instructions. The \c{FEMMS} instruction can
8334 also be used \e{before} executing \c{MMX} instructions
8337 \S{insFFREE} \i\c{FFREE}: Flag Floating-Point Register as Unused
8339 \c FFREE fpureg ; DD C0+r [8086,FPU]
8340 \c FFREEP fpureg ; DF C0+r [286,FPU,UNDOC]
8342 \c{FFREE} marks the given register as being empty.
8344 \c{FFREEP} marks the given register as being empty, and then
8345 pops the register stack.
8348 \S{insFIADD} \i\c{FIADD}: Floating-Point/Integer Addition
8350 \c FIADD mem16 ; DE /0 [8086,FPU]
8351 \c FIADD mem32 ; DA /0 [8086,FPU]
8353 \c{FIADD} adds the 16-bit or 32-bit integer stored in the given
8354 memory location to \c{ST0}, storing the result in \c{ST0}.
8357 \S{insFICOM} \i\c{FICOM}, \i\c{FICOMP}: Floating-Point/Integer Compare
8359 \c FICOM mem16 ; DE /2 [8086,FPU]
8360 \c FICOM mem32 ; DA /2 [8086,FPU]
8362 \c FICOMP mem16 ; DE /3 [8086,FPU]
8363 \c FICOMP mem32 ; DA /3 [8086,FPU]
8365 \c{FICOM} compares \c{ST0} with the 16-bit or 32-bit integer stored
8366 in the given memory location, and sets the FPU flags accordingly.
8367 \c{FICOMP} does the same, but pops the register stack afterwards.
8370 \S{insFIDIV} \i\c{FIDIV}, \i\c{FIDIVR}: Floating-Point/Integer Division
8372 \c FIDIV mem16 ; DE /6 [8086,FPU]
8373 \c FIDIV mem32 ; DA /6 [8086,FPU]
8375 \c FIDIVR mem16 ; DE /7 [8086,FPU]
8376 \c FIDIVR mem32 ; DA /7 [8086,FPU]
8378 \c{FIDIV} divides \c{ST0} by the 16-bit or 32-bit integer stored in
8379 the given memory location, and stores the result in \c{ST0}.
8380 \c{FIDIVR} does the division the other way up: it divides the
8381 integer by \c{ST0}, but still stores the result in \c{ST0}.
8384 \S{insFILD} \i\c{FILD}, \i\c{FIST}, \i\c{FISTP}: Floating-Point/Integer Conversion
8386 \c FILD mem16 ; DF /0 [8086,FPU]
8387 \c FILD mem32 ; DB /0 [8086,FPU]
8388 \c FILD mem64 ; DF /5 [8086,FPU]
8390 \c FIST mem16 ; DF /2 [8086,FPU]
8391 \c FIST mem32 ; DB /2 [8086,FPU]
8393 \c FISTP mem16 ; DF /3 [8086,FPU]
8394 \c FISTP mem32 ; DB /3 [8086,FPU]
8395 \c FISTP mem64 ; DF /7 [8086,FPU]
8397 \c{FILD} loads an integer out of a memory location, converts it to a
8398 real, and pushes it on the FPU register stack. \c{FIST} converts
8399 \c{ST0} to an integer and stores that in memory; \c{FISTP} does the
8400 same as \c{FIST}, but pops the register stack afterwards.
8403 \S{insFIMUL} \i\c{FIMUL}: Floating-Point/Integer Multiplication
8405 \c FIMUL mem16 ; DE /1 [8086,FPU]
8406 \c FIMUL mem32 ; DA /1 [8086,FPU]
8408 \c{FIMUL} multiplies \c{ST0} by the 16-bit or 32-bit integer stored
8409 in the given memory location, and stores the result in \c{ST0}.
8412 \S{insFINCSTP} \i\c{FINCSTP}: Increment Floating-Point Stack Pointer
8414 \c FINCSTP ; D9 F7 [8086,FPU]
8416 \c{FINCSTP} increments the `top' field in the floating-point status
8417 word. This has the effect of rotating the FPU register stack by one,
8418 as if the register stack had been popped; however, unlike the
8419 popping of the stack performed by many FPU instructions, it does not
8420 flag the new \c{ST7} (previously \c{ST0}) as empty. See also
8421 \c{FDECSTP} (\k{insFDECSTP}).
8424 \S{insFINIT} \i\c{FINIT}, \i\c{FNINIT}: Initialise Floating-Point Unit
8426 \c FINIT ; 9B DB E3 [8086,FPU]
8427 \c FNINIT ; DB E3 [8086,FPU]
8429 \c{FINIT} initialises the FPU to its default state. It flags all
8430 registers as empty, without actually change their values, clears
8431 the top of stack pointer. \c{FNINIT} does the same, without first
8432 waiting for pending exceptions to clear.
8435 \S{insFISUB} \i\c{FISUB}: Floating-Point/Integer Subtraction
8437 \c FISUB mem16 ; DE /4 [8086,FPU]
8438 \c FISUB mem32 ; DA /4 [8086,FPU]
8440 \c FISUBR mem16 ; DE /5 [8086,FPU]
8441 \c FISUBR mem32 ; DA /5 [8086,FPU]
8443 \c{FISUB} subtracts the 16-bit or 32-bit integer stored in the given
8444 memory location from \c{ST0}, and stores the result in \c{ST0}.
8445 \c{FISUBR} does the subtraction the other way round, i.e. it
8446 subtracts \c{ST0} from the given integer, but still stores the
8450 \S{insFLD} \i\c{FLD}: Floating-Point Load
8452 \c FLD mem32 ; D9 /0 [8086,FPU]
8453 \c FLD mem64 ; DD /0 [8086,FPU]
8454 \c FLD mem80 ; DB /5 [8086,FPU]
8455 \c FLD fpureg ; D9 C0+r [8086,FPU]
8457 \c{FLD} loads a floating-point value out of the given register or
8458 memory location, and pushes it on the FPU register stack.
8461 \S{insFLD1} \i\c{FLDxx}: Floating-Point Load Constants
8463 \c FLD1 ; D9 E8 [8086,FPU]
8464 \c FLDL2E ; D9 EA [8086,FPU]
8465 \c FLDL2T ; D9 E9 [8086,FPU]
8466 \c FLDLG2 ; D9 EC [8086,FPU]
8467 \c FLDLN2 ; D9 ED [8086,FPU]
8468 \c FLDPI ; D9 EB [8086,FPU]
8469 \c FLDZ ; D9 EE [8086,FPU]
8471 These instructions push specific standard constants on the FPU
8474 \c Instruction Constant pushed
8477 \c FLDL2E base-2 logarithm of e
8478 \c FLDL2T base-2 log of 10
8479 \c FLDLG2 base-10 log of 2
8480 \c FLDLN2 base-e log of 2
8485 \S{insFLDCW} \i\c{FLDCW}: Load Floating-Point Control Word
8487 \c FLDCW mem16 ; D9 /5 [8086,FPU]
8489 \c{FLDCW} loads a 16-bit value out of memory and stores it into the
8490 FPU control word (governing things like the rounding mode, the
8491 precision, and the exception masks). See also \c{FSTCW}
8492 (\k{insFSTCW}). If exceptions are enabled and you don't want to
8493 generate one, use \c{FCLEX} or \c{FNCLEX} (\k{insFCLEX}) before
8494 loading the new control word.
8497 \S{insFLDENV} \i\c{FLDENV}: Load Floating-Point Environment
8499 \c FLDENV mem ; D9 /4 [8086,FPU]
8501 \c{FLDENV} loads the FPU operating environment (control word, status
8502 word, tag word, instruction pointer, data pointer and last opcode)
8503 from memory. The memory area is 14 or 28 bytes long, depending on
8504 the CPU mode at the time. See also \c{FSTENV} (\k{insFSTENV}).
8507 \S{insFMUL} \i\c{FMUL}, \i\c{FMULP}: Floating-Point Multiply
8509 \c FMUL mem32 ; D8 /1 [8086,FPU]
8510 \c FMUL mem64 ; DC /1 [8086,FPU]
8512 \c FMUL fpureg ; D8 C8+r [8086,FPU]
8513 \c FMUL ST0,fpureg ; D8 C8+r [8086,FPU]
8515 \c FMUL TO fpureg ; DC C8+r [8086,FPU]
8516 \c FMUL fpureg,ST0 ; DC C8+r [8086,FPU]
8518 \c FMULP fpureg ; DE C8+r [8086,FPU]
8519 \c FMULP fpureg,ST0 ; DE C8+r [8086,FPU]
8521 \c{FMUL} multiplies \c{ST0} by the given operand, and stores the
8522 result in \c{ST0}, unless the \c{TO} qualifier is used in which case
8523 it stores the result in the operand. \c{FMULP} performs the same
8524 operation as \c{FMUL TO}, and then pops the register stack.
8527 \S{insFNOP} \i\c{FNOP}: Floating-Point No Operation
8529 \c FNOP ; D9 D0 [8086,FPU]
8531 \c{FNOP} does nothing.
8534 \S{insFPATAN} \i\c{FPATAN}, \i\c{FPTAN}: Arctangent and Tangent
8536 \c FPATAN ; D9 F3 [8086,FPU]
8537 \c FPTAN ; D9 F2 [8086,FPU]
8539 \c{FPATAN} computes the arctangent, in radians, of the result of
8540 dividing \c{ST1} by \c{ST0}, stores the result in \c{ST1}, and pops
8541 the register stack. It works like the C \c{atan2} function, in that
8542 changing the sign of both \c{ST0} and \c{ST1} changes the output
8543 value by pi (so it performs true rectangular-to-polar coordinate
8544 conversion, with \c{ST1} being the Y coordinate and \c{ST0} being
8545 the X coordinate, not merely an arctangent).
8547 \c{FPTAN} computes the tangent of the value in \c{ST0} (in radians),
8548 and stores the result back into \c{ST0}.
8550 The absolute value of \c{ST0} must be less than 2**63.
8553 \S{insFPREM} \i\c{FPREM}, \i\c{FPREM1}: Floating-Point Partial Remainder
8555 \c FPREM ; D9 F8 [8086,FPU]
8556 \c FPREM1 ; D9 F5 [386,FPU]
8558 These instructions both produce the remainder obtained by dividing
8559 \c{ST0} by \c{ST1}. This is calculated, notionally, by dividing
8560 \c{ST0} by \c{ST1}, rounding the result to an integer, multiplying
8561 by \c{ST1} again, and computing the value which would need to be
8562 added back on to the result to get back to the original value in
8565 The two instructions differ in the way the notional round-to-integer
8566 operation is performed. \c{FPREM} does it by rounding towards zero,
8567 so that the remainder it returns always has the same sign as the
8568 original value in \c{ST0}; \c{FPREM1} does it by rounding to the
8569 nearest integer, so that the remainder always has at most half the
8570 magnitude of \c{ST1}.
8572 Both instructions calculate \e{partial} remainders, meaning that
8573 they may not manage to provide the final result, but might leave
8574 intermediate results in \c{ST0} instead. If this happens, they will
8575 set the C2 flag in the FPU status word; therefore, to calculate a
8576 remainder, you should repeatedly execute \c{FPREM} or \c{FPREM1}
8577 until C2 becomes clear.
8580 \S{insFRNDINT} \i\c{FRNDINT}: Floating-Point Round to Integer
8582 \c FRNDINT ; D9 FC [8086,FPU]
8584 \c{FRNDINT} rounds the contents of \c{ST0} to an integer, according
8585 to the current rounding mode set in the FPU control word, and stores
8586 the result back in \c{ST0}.
8589 \S{insFRSTOR} \i\c{FSAVE}, \i\c{FRSTOR}: Save/Restore Floating-Point State
8591 \c FSAVE mem ; 9B DD /6 [8086,FPU]
8592 \c FNSAVE mem ; DD /6 [8086,FPU]
8594 \c FRSTOR mem ; DD /4 [8086,FPU]
8596 \c{FSAVE} saves the entire floating-point unit state, including all
8597 the information saved by \c{FSTENV} (\k{insFSTENV}) plus the
8598 contents of all the registers, to a 94 or 108 byte area of memory
8599 (depending on the CPU mode). \c{FRSTOR} restores the floating-point
8600 state from the same area of memory.
8602 \c{FNSAVE} does the same as \c{FSAVE}, without first waiting for
8603 pending floating-point exceptions to clear.
8606 \S{insFSCALE} \i\c{FSCALE}: Scale Floating-Point Value by Power of Two
8608 \c FSCALE ; D9 FD [8086,FPU]
8610 \c{FSCALE} scales a number by a power of two: it rounds \c{ST1}
8611 towards zero to obtain an integer, then multiplies \c{ST0} by two to
8612 the power of that integer, and stores the result in \c{ST0}.
8615 \S{insFSETPM} \i\c{FSETPM}: Set Protected Mode
8617 \c FSETPM ; DB E4 [286,FPU]
8619 This instruction initialises protected mode on the 287 floating-point
8620 coprocessor. It is only meaningful on that processor: the 387 and
8621 above treat the instruction as a no-operation.
8624 \S{insFSIN} \i\c{FSIN}, \i\c{FSINCOS}: Sine and Cosine
8626 \c FSIN ; D9 FE [386,FPU]
8627 \c FSINCOS ; D9 FB [386,FPU]
8629 \c{FSIN} calculates the sine of \c{ST0} (in radians) and stores the
8630 result in \c{ST0}. \c{FSINCOS} does the same, but then pushes the
8631 cosine of the same value on the register stack, so that the sine
8632 ends up in \c{ST1} and the cosine in \c{ST0}. \c{FSINCOS} is faster
8633 than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in succession.
8635 The absolute value of \c{ST0} must be less than 2**63.
8638 \S{insFSQRT} \i\c{FSQRT}: Floating-Point Square Root
8640 \c FSQRT ; D9 FA [8086,FPU]
8642 \c{FSQRT} calculates the square root of \c{ST0} and stores the
8646 \S{insFST} \i\c{FST}, \i\c{FSTP}: Floating-Point Store
8648 \c FST mem32 ; D9 /2 [8086,FPU]
8649 \c FST mem64 ; DD /2 [8086,FPU]
8650 \c FST fpureg ; DD D0+r [8086,FPU]
8652 \c FSTP mem32 ; D9 /3 [8086,FPU]
8653 \c FSTP mem64 ; DD /3 [8086,FPU]
8654 \c FSTP mem80 ; DB /7 [8086,FPU]
8655 \c FSTP fpureg ; DD D8+r [8086,FPU]
8657 \c{FST} stores the value in \c{ST0} into the given memory location
8658 or other FPU register. \c{FSTP} does the same, but then pops the
8662 \S{insFSTCW} \i\c{FSTCW}: Store Floating-Point Control Word
8664 \c FSTCW mem16 ; 9B D9 /7 [8086,FPU]
8665 \c FNSTCW mem16 ; D9 /7 [8086,FPU]
8667 \c{FSTCW} stores the \c{FPU} control word (governing things like the
8668 rounding mode, the precision, and the exception masks) into a 2-byte
8669 memory area. See also \c{FLDCW} (\k{insFLDCW}).
8671 \c{FNSTCW} does the same thing as \c{FSTCW}, without first waiting
8672 for pending floating-point exceptions to clear.
8675 \S{insFSTENV} \i\c{FSTENV}: Store Floating-Point Environment
8677 \c FSTENV mem ; 9B D9 /6 [8086,FPU]
8678 \c FNSTENV mem ; D9 /6 [8086,FPU]
8680 \c{FSTENV} stores the \c{FPU} operating environment (control word,
8681 status word, tag word, instruction pointer, data pointer and last
8682 opcode) into memory. The memory area is 14 or 28 bytes long,
8683 depending on the CPU mode at the time. See also \c{FLDENV}
8686 \c{FNSTENV} does the same thing as \c{FSTENV}, without first waiting
8687 for pending floating-point exceptions to clear.
8690 \S{insFSTSW} \i\c{FSTSW}: Store Floating-Point Status Word
8692 \c FSTSW mem16 ; 9B DD /7 [8086,FPU]
8693 \c FSTSW AX ; 9B DF E0 [286,FPU]
8695 \c FNSTSW mem16 ; DD /7 [8086,FPU]
8696 \c FNSTSW AX ; DF E0 [286,FPU]
8698 \c{FSTSW} stores the \c{FPU} status word into \c{AX} or into a 2-byte
8701 \c{FNSTSW} does the same thing as \c{FSTSW}, without first waiting
8702 for pending floating-point exceptions to clear.
8705 \S{insFSUB} \i\c{FSUB}, \i\c{FSUBP}, \i\c{FSUBR}, \i\c{FSUBRP}: Floating-Point Subtract
8707 \c FSUB mem32 ; D8 /4 [8086,FPU]
8708 \c FSUB mem64 ; DC /4 [8086,FPU]
8710 \c FSUB fpureg ; D8 E0+r [8086,FPU]
8711 \c FSUB ST0,fpureg ; D8 E0+r [8086,FPU]
8713 \c FSUB TO fpureg ; DC E8+r [8086,FPU]
8714 \c FSUB fpureg,ST0 ; DC E8+r [8086,FPU]
8716 \c FSUBR mem32 ; D8 /5 [8086,FPU]
8717 \c FSUBR mem64 ; DC /5 [8086,FPU]
8719 \c FSUBR fpureg ; D8 E8+r [8086,FPU]
8720 \c FSUBR ST0,fpureg ; D8 E8+r [8086,FPU]
8722 \c FSUBR TO fpureg ; DC E0+r [8086,FPU]
8723 \c FSUBR fpureg,ST0 ; DC E0+r [8086,FPU]
8725 \c FSUBP fpureg ; DE E8+r [8086,FPU]
8726 \c FSUBP fpureg,ST0 ; DE E8+r [8086,FPU]
8728 \c FSUBRP fpureg ; DE E0+r [8086,FPU]
8729 \c FSUBRP fpureg,ST0 ; DE E0+r [8086,FPU]
8731 \b \c{FSUB} subtracts the given operand from \c{ST0} and stores the
8732 result back in \c{ST0}, unless the \c{TO} qualifier is given, in
8733 which case it subtracts \c{ST0} from the given operand and stores
8734 the result in the operand.
8736 \b \c{FSUBR} does the same thing, but does the subtraction the other
8737 way up: so if \c{TO} is not given, it subtracts \c{ST0} from the given
8738 operand and stores the result in \c{ST0}, whereas if \c{TO} is given
8739 it subtracts its operand from \c{ST0} and stores the result in the
8742 \b \c{FSUBP} operates like \c{FSUB TO}, but pops the register stack
8743 once it has finished.
8745 \b \c{FSUBRP} operates like \c{FSUBR TO}, but pops the register stack
8746 once it has finished.
8749 \S{insFTST} \i\c{FTST}: Test \c{ST0} Against Zero
8751 \c FTST ; D9 E4 [8086,FPU]
8753 \c{FTST} compares \c{ST0} with zero and sets the FPU flags
8754 accordingly. \c{ST0} is treated as the left-hand side of the
8755 comparison, so that a `less-than' result is generated if \c{ST0} is
8759 \S{insFUCOM} \i\c{FUCOMxx}: Floating-Point Unordered Compare
8761 \c FUCOM fpureg ; DD E0+r [386,FPU]
8762 \c FUCOM ST0,fpureg ; DD E0+r [386,FPU]
8764 \c FUCOMP fpureg ; DD E8+r [386,FPU]
8765 \c FUCOMP ST0,fpureg ; DD E8+r [386,FPU]
8767 \c FUCOMPP ; DA E9 [386,FPU]
8769 \c FUCOMI fpureg ; DB E8+r [P6,FPU]
8770 \c FUCOMI ST0,fpureg ; DB E8+r [P6,FPU]
8772 \c FUCOMIP fpureg ; DF E8+r [P6,FPU]
8773 \c FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU]
8775 \b \c{FUCOM} compares \c{ST0} with the given operand, and sets the
8776 FPU flags accordingly. \c{ST0} is treated as the left-hand side of
8777 the comparison, so that the carry flag is set (for a `less-than'
8778 result) if \c{ST0} is less than the given operand.
8780 \b \c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack
8781 afterwards. \c{FUCOMPP} compares \c{ST0} with \c{ST1} and then pops
8782 the register stack twice.
8784 \b \c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of
8785 \c{FUCOM} and \c{FUCOMP}, but write their results directly to the CPU
8786 flags register rather than the FPU status word, so they can be
8787 immediately followed by conditional jump or conditional move
8790 The \c{FUCOM} instructions differ from the \c{FCOM} instructions
8791 (\k{insFCOM}) only in the way they handle quiet NaNs: \c{FUCOM} will
8792 handle them silently and set the condition code flags to an
8793 `unordered' result, whereas \c{FCOM} will generate an exception.
8796 \S{insFXAM} \i\c{FXAM}: Examine Class of Value in \c{ST0}
8798 \c FXAM ; D9 E5 [8086,FPU]
8800 \c{FXAM} sets the FPU flags \c{C3}, \c{C2} and \c{C0} depending on
8801 the type of value stored in \c{ST0}:
8803 \c Register contents Flags
8805 \c Unsupported format 000
8807 \c Finite number 010
8810 \c Empty register 101
8813 Additionally, the \c{C1} flag is set to the sign of the number.
8816 \S{insFXCH} \i\c{FXCH}: Floating-Point Exchange
8818 \c FXCH ; D9 C9 [8086,FPU]
8819 \c FXCH fpureg ; D9 C8+r [8086,FPU]
8820 \c FXCH fpureg,ST0 ; D9 C8+r [8086,FPU]
8821 \c FXCH ST0,fpureg ; D9 C8+r [8086,FPU]
8823 \c{FXCH} exchanges \c{ST0} with a given FPU register. The no-operand
8824 form exchanges \c{ST0} with \c{ST1}.
8827 \S{insFXRSTOR} \i\c{FXRSTOR}: Restore \c{FP}, \c{MMX} and \c{SSE} State
8829 \c FXRSTOR memory ; 0F AE /1 [P6,SSE,FPU]
8831 The \c{FXRSTOR} instruction reloads the \c{FPU}, \c{MMX} and \c{SSE}
8832 state (environment and registers), from the 512 byte memory area defined
8833 by the source operand. This data should have been written by a previous
8837 \S{insFXSAVE} \i\c{FXSAVE}: Store \c{FP}, \c{MMX} and \c{SSE} State
8839 \c FXSAVE memory ; 0F AE /0 [P6,SSE,FPU]
8841 \c{FXSAVE}The FXSAVE instruction writes the current \c{FPU}, \c{MMX}
8842 and \c{SSE} technology states (environment and registers), to the
8843 512 byte memory area defined by the destination operand. It does this
8844 without checking for pending unmasked floating-point exceptions
8845 (similar to the operation of \c{FNSAVE}).
8847 Unlike the \c{FSAVE/FNSAVE} instructions, the processor retains the
8848 contents of the \c{FPU}, \c{MMX} and \c{SSE} state in the processor
8849 after the state has been saved. This instruction has been optimised
8850 to maximize floating-point save performance.
8853 \S{insFXTRACT} \i\c{FXTRACT}: Extract Exponent and Significand
8855 \c FXTRACT ; D9 F4 [8086,FPU]
8857 \c{FXTRACT} separates the number in \c{ST0} into its exponent and
8858 significand (mantissa), stores the exponent back into \c{ST0}, and
8859 then pushes the significand on the register stack (so that the
8860 significand ends up in \c{ST0}, and the exponent in \c{ST1}).
8863 \S{insFYL2X} \i\c{FYL2X}, \i\c{FYL2XP1}: Compute Y times Log2(X) or Log2(X+1)
8865 \c FYL2X ; D9 F1 [8086,FPU]
8866 \c FYL2XP1 ; D9 F9 [8086,FPU]
8868 \c{FYL2X} multiplies \c{ST1} by the base-2 logarithm of \c{ST0},
8869 stores the result in \c{ST1}, and pops the register stack (so that
8870 the result ends up in \c{ST0}). \c{ST0} must be non-zero and
8873 \c{FYL2XP1} works the same way, but replacing the base-2 log of
8874 \c{ST0} with that of \c{ST0} plus one. This time, \c{ST0} must have
8875 magnitude no greater than 1 minus half the square root of two.
8878 \S{insHLT} \i\c{HLT}: Halt Processor
8880 \c HLT ; F4 [8086,PRIV]
8882 \c{HLT} puts the processor into a halted state, where it will
8883 perform no more operations until restarted by an interrupt or a
8886 On the 286 and later processors, this is a privileged instruction.
8889 \S{insIBTS} \i\c{IBTS}: Insert Bit String
8891 \c IBTS r/m16,reg16 ; o16 0F A7 /r [386,UNDOC]
8892 \c IBTS r/m32,reg32 ; o32 0F A7 /r [386,UNDOC]
8894 The implied operation of this instruction is:
8896 \c IBTS r/m16,AX,CL,reg16
8897 \c IBTS r/m32,EAX,CL,reg32
8899 Writes a bit string from the source operand to the destination.
8900 \c{CL} indicates the number of bits to be copied, from the low bits
8901 of the source. \c{(E)AX} indicates the low order bit offset in the
8902 destination that is written to. For example, if \c{CL} is set to 4
8903 and \c{AX} (for 16-bit code) is set to 5, bits 0-3 of \c{src} will
8904 be copied to bits 5-8 of \c{dst}. This instruction is very poorly
8905 documented, and I have been unable to find any official source of
8906 documentation on it.
8908 \c{IBTS} is supported only on the early Intel 386s, and conflicts
8909 with the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM
8910 supports it only for completeness. Its counterpart is \c{XBTS}
8914 \S{insIDIV} \i\c{IDIV}: Signed Integer Divide
8916 \c IDIV r/m8 ; F6 /7 [8086]
8917 \c IDIV r/m16 ; o16 F7 /7 [8086]
8918 \c IDIV r/m32 ; o32 F7 /7 [386]
8920 \c{IDIV} performs signed integer division. The explicit operand
8921 provided is the divisor; the dividend and destination operands
8922 are implicit, in the following way:
8924 \b For \c{IDIV r/m8}, \c{AX} is divided by the given operand;
8925 the quotient is stored in \c{AL} and the remainder in \c{AH}.
8927 \b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand;
8928 the quotient is stored in \c{AX} and the remainder in \c{DX}.
8930 \b For \c{IDIV r/m32}, \c{EDX:EAX} is divided by the given operand;
8931 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
8933 Unsigned integer division is performed by the \c{DIV} instruction:
8937 \S{insIMUL} \i\c{IMUL}: Signed Integer Multiply
8939 \c IMUL r/m8 ; F6 /5 [8086]
8940 \c IMUL r/m16 ; o16 F7 /5 [8086]
8941 \c IMUL r/m32 ; o32 F7 /5 [386]
8943 \c IMUL reg16,r/m16 ; o16 0F AF /r [386]
8944 \c IMUL reg32,r/m32 ; o32 0F AF /r [386]
8946 \c IMUL reg16,imm8 ; o16 6B /r ib [286]
8947 \c IMUL reg16,imm16 ; o16 69 /r iw [286]
8948 \c IMUL reg32,imm8 ; o32 6B /r ib [386]
8949 \c IMUL reg32,imm32 ; o32 69 /r id [386]
8951 \c IMUL reg16,r/m16,imm8 ; o16 6B /r ib [286]
8952 \c IMUL reg16,r/m16,imm16 ; o16 69 /r iw [286]
8953 \c IMUL reg32,r/m32,imm8 ; o32 6B /r ib [386]
8954 \c IMUL reg32,r/m32,imm32 ; o32 69 /r id [386]
8956 \c{IMUL} performs signed integer multiplication. For the
8957 single-operand form, the other operand and destination are
8958 implicit, in the following way:
8960 \b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand;
8961 the product is stored in \c{AX}.
8963 \b For \c{IMUL r/m16}, \c{AX} is multiplied by the given operand;
8964 the product is stored in \c{DX:AX}.
8966 \b For \c{IMUL r/m32}, \c{EAX} is multiplied by the given operand;
8967 the product is stored in \c{EDX:EAX}.
8969 The two-operand form multiplies its two operands and stores the
8970 result in the destination (first) operand. The three-operand
8971 form multiplies its last two operands and stores the result in
8974 The two-operand form with an immediate second operand is in
8975 fact a shorthand for the three-operand form, as can be seen by
8976 examining the opcode descriptions: in the two-operand form, the
8977 code \c{/r} takes both its register and \c{r/m} parts from the
8978 same operand (the first one).
8980 In the forms with an 8-bit immediate operand and another longer
8981 source operand, the immediate operand is considered to be signed,
8982 and is sign-extended to the length of the other source operand.
8983 In these cases, the \c{BYTE} qualifier is necessary to force
8984 NASM to generate this form of the instruction.
8986 Unsigned integer multiplication is performed by the \c{MUL}
8987 instruction: see \k{insMUL}.
8990 \S{insIN} \i\c{IN}: Input from I/O Port
8992 \c IN AL,imm8 ; E4 ib [8086]
8993 \c IN AX,imm8 ; o16 E5 ib [8086]
8994 \c IN EAX,imm8 ; o32 E5 ib [386]
8995 \c IN AL,DX ; EC [8086]
8996 \c IN AX,DX ; o16 ED [8086]
8997 \c IN EAX,DX ; o32 ED [386]
8999 \c{IN} reads a byte, word or doubleword from the specified I/O port,
9000 and stores it in the given destination register. The port number may
9001 be specified as an immediate value if it is between 0 and 255, and
9002 otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}).
9005 \S{insINC} \i\c{INC}: Increment Integer
9007 \c INC reg16 ; o16 40+r [8086]
9008 \c INC reg32 ; o32 40+r [386]
9009 \c INC r/m8 ; FE /0 [8086]
9010 \c INC r/m16 ; o16 FF /0 [8086]
9011 \c INC r/m32 ; o32 FF /0 [386]
9013 \c{INC} adds 1 to its operand. It does \e{not} affect the carry
9014 flag: to affect the carry flag, use \c{ADD something,1} (see
9015 \k{insADD}). \c{INC} affects all the other flags according to the result.
9017 This instruction can be used with a \c{LOCK} prefix to allow atomic execution.
9019 See also \c{DEC} (\k{insDEC}).
9022 \S{insINSB} \i\c{INSB}, \i\c{INSW}, \i\c{INSD}: Input String from I/O Port
9025 \c INSW ; o16 6D [186]
9026 \c INSD ; o32 6D [386]
9028 \c{INSB} inputs a byte from the I/O port specified in \c{DX} and
9029 stores it at \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or
9030 decrements (depending on the direction flag: increments if the flag
9031 is clear, decrements if it is set) \c{DI} or \c{EDI}.
9033 The register used is \c{DI} if the address size is 16 bits, and
9034 \c{EDI} if it is 32 bits. If you need to use an address size not
9035 equal to the current \c{BITS} setting, you can use an explicit
9036 \i\c{a16} or \i\c{a32} prefix.
9038 Segment override prefixes have no effect for this instruction: the
9039 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
9042 \c{INSW} and \c{INSD} work in the same way, but they input a word or
9043 a doubleword instead of a byte, and increment or decrement the
9044 addressing register by 2 or 4 instead of 1.
9046 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
9047 \c{ECX} - again, the address size chooses which) times.
9049 See also \c{OUTSB}, \c{OUTSW} and \c{OUTSD} (\k{insOUTSB}).
9052 \S{insINT} \i\c{INT}: Software Interrupt
9054 \c INT imm8 ; CD ib [8086]
9056 \c{INT} causes a software interrupt through a specified vector
9057 number from 0 to 255.
9059 The code generated by the \c{INT} instruction is always two bytes
9060 long: although there are short forms for some \c{INT} instructions,
9061 NASM does not generate them when it sees the \c{INT} mnemonic. In
9062 order to generate single-byte breakpoint instructions, use the
9063 \c{INT3} or \c{INT1} instructions (see \k{insINT1}) instead.
9066 \S{insINT1} \i\c{INT3}, \i\c{INT1}, \i\c{ICEBP}, \i\c{INT01}: Breakpoints
9073 \c INT03 ; CC [8086]
9075 \c{INT1} and \c{INT3} are short one-byte forms of the instructions
9076 \c{INT 1} and \c{INT 3} (see \k{insINT}). They perform a similar
9077 function to their longer counterparts, but take up less code space.
9078 They are used as breakpoints by debuggers.
9080 \b \c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is
9081 an instruction used by in-circuit emulators (ICEs). It is present,
9082 though not documented, on some processors down to the 286, but is
9083 only documented for the Pentium Pro. \c{INT3} is the instruction
9084 normally used as a breakpoint by debuggers.
9086 \b \c{INT3}, and its synonym \c{INT03}, is not precisely equivalent to
9087 \c{INT 3}: the short form, since it is designed to be used as a
9088 breakpoint, bypasses the normal \c{IOPL} checks in virtual-8086 mode,
9089 and also does not go through interrupt redirection.
9092 \S{insINTO} \i\c{INTO}: Interrupt if Overflow
9096 \c{INTO} performs an \c{INT 4} software interrupt (see \k{insINT})
9097 if and only if the overflow flag is set.
9100 \S{insINVD} \i\c{INVD}: Invalidate Internal Caches
9102 \c INVD ; 0F 08 [486]
9104 \c{INVD} invalidates and empties the processor's internal caches,
9105 and causes the processor to instruct external caches to do the same.
9106 It does not write the contents of the caches back to memory first:
9107 any modified data held in the caches will be lost. To write the data
9108 back first, use \c{WBINVD} (\k{insWBINVD}).
9111 \S{insINVLPG} \i\c{INVLPG}: Invalidate TLB Entry
9113 \c INVLPG mem ; 0F 01 /7 [486]
9115 \c{INVLPG} invalidates the translation lookahead buffer (TLB) entry
9116 associated with the supplied memory address.
9119 \S{insIRET} \i\c{IRET}, \i\c{IRETW}, \i\c{IRETD}: Return from Interrupt
9122 \c IRETW ; o16 CF [8086]
9123 \c IRETD ; o32 CF [386]
9125 \c{IRET} returns from an interrupt (hardware or software) by means
9126 of popping \c{IP} (or \c{EIP}), \c{CS} and the flags off the stack
9127 and then continuing execution from the new \c{CS:IP}.
9129 \c{IRETW} pops \c{IP}, \c{CS} and the flags as 2 bytes each, taking
9130 6 bytes off the stack in total. \c{IRETD} pops \c{EIP} as 4 bytes,
9131 pops a further 4 bytes of which the top two are discarded and the
9132 bottom two go into \c{CS}, and pops the flags as 4 bytes as well,
9133 taking 12 bytes off the stack.
9135 \c{IRET} is a shorthand for either \c{IRETW} or \c{IRETD}, depending
9136 on the default \c{BITS} setting at the time.
9139 \S{insJcc} \i\c{Jcc}: Conditional Branch
9141 \c Jcc imm ; 70+cc rb [8086]
9142 \c Jcc NEAR imm ; 0F 80+cc rw/rd [386]
9144 The \i{conditional jump} instructions execute a near (same segment)
9145 jump if and only if their conditions are satisfied. For example,
9146 \c{JNZ} jumps only if the zero flag is not set.
9148 The ordinary form of the instructions has only a 128-byte range; the
9149 \c{NEAR} form is a 386 extension to the instruction set, and can
9150 span the full size of a segment. NASM will not override your choice
9151 of jump instruction: if you want \c{Jcc NEAR}, you have to use the
9154 The \c{SHORT} keyword is allowed on the first form of the
9155 instruction, for clarity, but is not necessary.
9157 For details of the condition codes, see \k{iref-cc}.
9160 \S{insJCXZ} \i\c{JCXZ}, \i\c{JECXZ}: Jump if CX/ECX Zero
9162 \c JCXZ imm ; a16 E3 rb [8086]
9163 \c JECXZ imm ; a32 E3 rb [386]
9165 \c{JCXZ} performs a short jump (with maximum range 128 bytes) if and
9166 only if the contents of the \c{CX} register is 0. \c{JECXZ} does the
9167 same thing, but with \c{ECX}.
9170 \S{insJMP} \i\c{JMP}: Jump
9172 \c JMP imm ; E9 rw/rd [8086]
9173 \c JMP SHORT imm ; EB rb [8086]
9174 \c JMP imm:imm16 ; o16 EA iw iw [8086]
9175 \c JMP imm:imm32 ; o32 EA id iw [386]
9176 \c JMP FAR mem ; o16 FF /5 [8086]
9177 \c JMP FAR mem32 ; o32 FF /5 [386]
9178 \c JMP r/m16 ; o16 FF /4 [8086]
9179 \c JMP r/m32 ; o32 FF /4 [386]
9181 \c{JMP} jumps to a given address. The address may be specified as an
9182 absolute segment and offset, or as a relative jump within the
9185 \c{JMP SHORT imm} has a maximum range of 128 bytes, since the
9186 displacement is specified as only 8 bits, but takes up less code
9187 space. NASM does not choose when to generate \c{JMP SHORT} for you:
9188 you must explicitly code \c{SHORT} every time you want a short jump.
9190 You can choose between the two immediate \i{far jump} forms (\c{JMP
9191 imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: \c{JMP
9192 WORD 0x1234:0x5678}) or \c{JMP DWORD 0x1234:0x56789abc}.
9194 The \c{JMP FAR mem} forms execute a far jump by loading the
9195 destination address out of memory. The address loaded consists of 16
9196 or 32 bits of offset (depending on the operand size), and 16 bits of
9197 segment. The operand size may be overridden using \c{JMP WORD FAR
9198 mem} or \c{JMP DWORD FAR mem}.
9200 The \c{JMP r/m} forms execute a \i{near jump} (within the same
9201 segment), loading the destination address out of memory or out of a
9202 register. The keyword \c{NEAR} may be specified, for clarity, in
9203 these forms, but is not necessary. Again, operand size can be
9204 overridden using \c{JMP WORD mem} or \c{JMP DWORD mem}.
9206 As a convenience, NASM does not require you to jump to a far symbol
9207 by coding the cumbersome \c{JMP SEG routine:routine}, but instead
9208 allows the easier synonym \c{JMP FAR routine}.
9210 The \c{CALL r/m} forms given above are near calls; NASM will accept
9211 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
9212 is not strictly necessary.
9215 \S{insLAHF} \i\c{LAHF}: Load AH from Flags
9219 \c{LAHF} sets the \c{AH} register according to the contents of the
9220 low byte of the flags word.
9222 The operation of \c{LAHF} is:
9224 \c AH <-- SF:ZF:0:AF:0:PF:1:CF
9226 See also \c{SAHF} (\k{insSAHF}).
9229 \S{insLAR} \i\c{LAR}: Load Access Rights
9231 \c LAR reg16,r/m16 ; o16 0F 02 /r [286,PRIV]
9232 \c LAR reg32,r/m32 ; o32 0F 02 /r [286,PRIV]
9234 \c{LAR} takes the segment selector specified by its source (second)
9235 operand, finds the corresponding segment descriptor in the GDT or
9236 LDT, and loads the access-rights byte of the descriptor into its
9237 destination (first) operand.
9240 \S{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension
9243 \c LDMXCSR mem32 ; 0F AE /2 [KATMAI,SSE]
9245 \c{LDMXCSR} loads 32-bits of data from the specified memory location
9246 into the \c{MXCSR} control/status register. \c{MXCSR} is used to
9247 enable masked/unmasked exception handling, to set rounding modes,
9248 to set flush-to-zero mode, and to view exception status flags.
9250 For details of the \c{MXCSR} register, see the Intel processor docs.
9252 See also \c{STMXCSR} (\k{insSTMXCSR}
9255 \S{insLDS} \i\c{LDS}, \i\c{LES}, \i\c{LFS}, \i\c{LGS}, \i\c{LSS}: Load Far Pointer
9257 \c LDS reg16,mem ; o16 C5 /r [8086]
9258 \c LDS reg32,mem ; o32 C5 /r [386]
9260 \c LES reg16,mem ; o16 C4 /r [8086]
9261 \c LES reg32,mem ; o32 C4 /r [386]
9263 \c LFS reg16,mem ; o16 0F B4 /r [386]
9264 \c LFS reg32,mem ; o32 0F B4 /r [386]
9266 \c LGS reg16,mem ; o16 0F B5 /r [386]
9267 \c LGS reg32,mem ; o32 0F B5 /r [386]
9269 \c LSS reg16,mem ; o16 0F B2 /r [386]
9270 \c LSS reg32,mem ; o32 0F B2 /r [386]
9272 These instructions load an entire far pointer (16 or 32 bits of
9273 offset, plus 16 bits of segment) out of memory in one go. \c{LDS},
9274 for example, loads 16 or 32 bits from the given memory address into
9275 the given register (depending on the size of the register), then
9276 loads the \e{next} 16 bits from memory into \c{DS}. \c{LES},
9277 \c{LFS}, \c{LGS} and \c{LSS} work in the same way but use the other
9281 \S{insLEA} \i\c{LEA}: Load Effective Address
9283 \c LEA reg16,mem ; o16 8D /r [8086]
9284 \c LEA reg32,mem ; o32 8D /r [386]
9286 \c{LEA}, despite its syntax, does not access memory. It calculates
9287 the effective address specified by its second operand as if it were
9288 going to load or store data from it, but instead it stores the
9289 calculated address into the register specified by its first operand.
9290 This can be used to perform quite complex calculations (e.g. \c{LEA
9291 EAX,[EBX+ECX*4+100]}) in one instruction.
9293 \c{LEA}, despite being a purely arithmetic instruction which
9294 accesses no memory, still requires square brackets around its second
9295 operand, as if it were a memory reference.
9297 The size of the calculation is the current \e{address} size, and the
9298 size that the result is stored as is the current \e{operand} size.
9299 If the address and operand size are not the same, then if the
9300 addressing mode was 32-bits, the low 16-bits are stored, and if the
9301 address was 16-bits, it is zero-extended to 32-bits before storing.
9304 \S{insLEAVE} \i\c{LEAVE}: Destroy Stack Frame
9308 \c{LEAVE} destroys a stack frame of the form created by the
9309 \c{ENTER} instruction (see \k{insENTER}). It is functionally
9310 equivalent to \c{MOV ESP,EBP} followed by \c{POP EBP} (or \c{MOV
9311 SP,BP} followed by \c{POP BP} in 16-bit mode).
9314 \S{insLFENCE} \i\c{LFENCE}: Load Fence
9316 \c LFENCE ; 0F AE /5 [WILLAMETTE,SSE2]
9318 \c{LFENCE} performs a serialising operation on all loads from memory
9319 that were issued before the \c{LFENCE} instruction. This guarantees that
9320 all memory reads before the \c{LFENCE} instruction are visible before any
9321 reads after the \c{LFENCE} instruction.
9323 \c{LFENCE} is ordered respective to other \c{LFENCE} instruction, \c{MFENCE},
9324 any memory read and any other serialising instruction (such as \c{CPUID}).
9326 Weakly ordered memory types can be used to achieve higher processor
9327 performance through such techniques as out-of-order issue and
9328 speculative reads. The degree to which a consumer of data recognizes
9329 or knows that the data is weakly ordered varies among applications
9330 and may be unknown to the producer of this data. The \c{LFENCE}
9331 instruction provides a performance-efficient way of ensuring load
9332 ordering between routines that produce weakly-ordered results and
9333 routines that consume that data.
9335 \c{LFENCE} uses the following ModRM encoding:
9338 \c Reg/Opcode (5:3) = 101B
9341 All other ModRM encodings are defined to be reserved, and use
9342 of these encodings risks incompatibility with future processors.
9344 See also \c{SFENCE} (\k{insSFENCE}) and \c{MFENCE} (\k{insMFENCE}).
9347 \S{insLGDT} \i\c{LGDT}, \i\c{LIDT}, \i\c{LLDT}: Load Descriptor Tables
9349 \c LGDT mem ; 0F 01 /2 [286,PRIV]
9350 \c LIDT mem ; 0F 01 /3 [286,PRIV]
9351 \c LLDT r/m16 ; 0F 00 /2 [286,PRIV]
9353 \c{LGDT} and \c{LIDT} both take a 6-byte memory area as an operand:
9354 they load a 32-bit linear address and a 16-bit size limit from that
9355 area (in the opposite order) into the \c{GDTR} (global descriptor table
9356 register) or \c{IDTR} (interrupt descriptor table register). These are
9357 the only instructions which directly use \e{linear} addresses, rather
9358 than segment/offset pairs.
9360 \c{LLDT} takes a segment selector as an operand. The processor looks
9361 up that selector in the GDT and stores the limit and base address
9362 given there into the \c{LDTR} (local descriptor table register).
9364 See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}).
9367 \S{insLMSW} \i\c{LMSW}: Load/Store Machine Status Word
9369 \c LMSW r/m16 ; 0F 01 /6 [286,PRIV]
9371 \c{LMSW} loads the bottom four bits of the source operand into the
9372 bottom four bits of the \c{CR0} control register (or the Machine
9373 Status Word, on 286 processors). See also \c{SMSW} (\k{insSMSW}).
9376 \S{insLOADALL} \i\c{LOADALL}, \i\c{LOADALL286}: Load Processor State
9378 \c LOADALL ; 0F 07 [386,UNDOC]
9379 \c LOADALL286 ; 0F 05 [286,UNDOC]
9381 This instruction, in its two different-opcode forms, is apparently
9382 supported on most 286 processors, some 386 and possibly some 486.
9383 The opcode differs between the 286 and the 386.
9385 The function of the instruction is to load all information relating
9386 to the state of the processor out of a block of memory: on the 286,
9387 this block is located implicitly at absolute address \c{0x800}, and
9388 on the 386 and 486 it is at \c{[ES:EDI]}.
9391 \S{insLODSB} \i\c{LODSB}, \i\c{LODSW}, \i\c{LODSD}: Load from String
9393 \c LODSB ; AC [8086]
9394 \c LODSW ; o16 AD [8086]
9395 \c LODSD ; o32 AD [386]
9397 \c{LODSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} into \c{AL}.
9398 It then increments or decrements (depending on the direction flag:
9399 increments if the flag is clear, decrements if it is set) \c{SI} or
9402 The register used is \c{SI} if the address size is 16 bits, and
9403 \c{ESI} if it is 32 bits. If you need to use an address size not
9404 equal to the current \c{BITS} setting, you can use an explicit
9405 \i\c{a16} or \i\c{a32} prefix.
9407 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
9408 overridden by using a segment register name as a prefix (for
9409 example, \c{ES LODSB}).
9411 \c{LODSW} and \c{LODSD} work in the same way, but they load a
9412 word or a doubleword instead of a byte, and increment or decrement
9413 the addressing registers by 2 or 4 instead of 1.
9416 \S{insLOOP} \i\c{LOOP}, \i\c{LOOPE}, \i\c{LOOPZ}, \i\c{LOOPNE}, \i\c{LOOPNZ}: Loop with Counter
9418 \c LOOP imm ; E2 rb [8086]
9419 \c LOOP imm,CX ; a16 E2 rb [8086]
9420 \c LOOP imm,ECX ; a32 E2 rb [386]
9422 \c LOOPE imm ; E1 rb [8086]
9423 \c LOOPE imm,CX ; a16 E1 rb [8086]
9424 \c LOOPE imm,ECX ; a32 E1 rb [386]
9425 \c LOOPZ imm ; E1 rb [8086]
9426 \c LOOPZ imm,CX ; a16 E1 rb [8086]
9427 \c LOOPZ imm,ECX ; a32 E1 rb [386]
9429 \c LOOPNE imm ; E0 rb [8086]
9430 \c LOOPNE imm,CX ; a16 E0 rb [8086]
9431 \c LOOPNE imm,ECX ; a32 E0 rb [386]
9432 \c LOOPNZ imm ; E0 rb [8086]
9433 \c LOOPNZ imm,CX ; a16 E0 rb [8086]
9434 \c LOOPNZ imm,ECX ; a32 E0 rb [386]
9436 \c{LOOP} decrements its counter register (either \c{CX} or \c{ECX} -
9437 if one is not specified explicitly, the \c{BITS} setting dictates
9438 which is used) by one, and if the counter does not become zero as a
9439 result of this operation, it jumps to the given label. The jump has
9440 a range of 128 bytes.
9442 \c{LOOPE} (or its synonym \c{LOOPZ}) adds the additional condition
9443 that it only jumps if the counter is nonzero \e{and} the zero flag
9444 is set. Similarly, \c{LOOPNE} (and \c{LOOPNZ}) jumps only if the
9445 counter is nonzero and the zero flag is clear.
9448 \S{insLSL} \i\c{LSL}: Load Segment Limit
9450 \c LSL reg16,r/m16 ; o16 0F 03 /r [286,PRIV]
9451 \c LSL reg32,r/m32 ; o32 0F 03 /r [286,PRIV]
9453 \c{LSL} is given a segment selector in its source (second) operand;
9454 it computes the segment limit value by loading the segment limit
9455 field from the associated segment descriptor in the \c{GDT} or \c{LDT}.
9456 (This involves shifting left by 12 bits if the segment limit is
9457 page-granular, and not if it is byte-granular; so you end up with a
9458 byte limit in either case.) The segment limit obtained is then
9459 loaded into the destination (first) operand.
9462 \S{insLTR} \i\c{LTR}: Load Task Register
9464 \c LTR r/m16 ; 0F 00 /3 [286,PRIV]
9466 \c{LTR} looks up the segment base and limit in the GDT or LDT
9467 descriptor specified by the segment selector given as its operand,
9468 and loads them into the Task Register.
9471 \S{insMASKMOVDQU} \i\c{MASKMOVDQU}: Byte Mask Write
9473 \c MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2]
9475 \c{MASKMOVDQU} stores data from xmm1 to the location specified by
9476 \c{ES:(E)DI}. The size of the store depends on the address-size
9477 attribute. The most significant bit in each byte of the mask
9478 register xmm2 is used to selectively write the data (0 = no write,
9479 1 = write) on a per-byte basis.
9482 \S{insMASKMOVQ} \i\c{MASKMOVQ}: Byte Mask Write
9484 \c MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX]
9486 \c{MASKMOVQ} stores data from mm1 to the location specified by
9487 \c{ES:(E)DI}. The size of the store depends on the address-size
9488 attribute. The most significant bit in each byte of the mask
9489 register mm2 is used to selectively write the data (0 = no write,
9490 1 = write) on a per-byte basis.
9493 \S{insMAXPD} \i\c{MAXPD}: Return Packed Double-Precision FP Maximum
9495 \c MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2]
9497 \c{MAXPD} performs a SIMD compare of the packed double-precision
9498 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9499 of each pair of values in xmm1. If the values being compared are
9500 both zeroes, source2 (xmm2/m128) would be returned. If source2
9501 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9502 destination (i.e., a QNaN version of the SNaN is not returned).
9505 \S{insMAXPS} \i\c{MAXPS}: Return Packed Single-Precision FP Maximum
9507 \c MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE]
9509 \c{MAXPS} performs a SIMD compare of the packed single-precision
9510 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9511 of each pair of values in xmm1. If the values being compared are
9512 both zeroes, source2 (xmm2/m128) would be returned. If source2
9513 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9514 destination (i.e., a QNaN version of the SNaN is not returned).
9517 \S{insMAXSD} \i\c{MAXSD}: Return Scalar Double-Precision FP Maximum
9519 \c MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2]
9521 \c{MAXSD} compares the low-order double-precision FP numbers from
9522 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9523 values being compared are both zeroes, source2 (xmm2/m64) would
9524 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9525 forwarded unchanged to the destination (i.e., a QNaN version of
9526 the SNaN is not returned). The high quadword of the destination
9530 \S{insMAXSS} \i\c{MAXSS}: Return Scalar Single-Precision FP Maximum
9532 \c MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE]
9534 \c{MAXSS} compares the low-order single-precision FP numbers from
9535 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9536 values being compared are both zeroes, source2 (xmm2/m32) would
9537 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9538 forwarded unchanged to the destination (i.e., a QNaN version of
9539 the SNaN is not returned). The high three doublewords of the
9540 destination are left unchanged.
9543 \S{insMFENCE} \i\c{MFENCE}: Memory Fence
9545 \c MFENCE ; 0F AE /6 [WILLAMETTE,SSE2]
9547 \c{MFENCE} performs a serialising operation on all loads from memory
9548 and writes to memory that were issued before the \c{MFENCE} instruction.
9549 This guarantees that all memory reads and writes before the \c{MFENCE}
9550 instruction are completed before any reads and writes after the
9551 \c{MFENCE} instruction.
9553 \c{MFENCE} is ordered respective to other \c{MFENCE} instructions,
9554 \c{LFENCE}, \c{SFENCE}, any memory read and any other serialising
9555 instruction (such as \c{CPUID}).
9557 Weakly ordered memory types can be used to achieve higher processor
9558 performance through such techniques as out-of-order issue, speculative
9559 reads, write-combining, and write-collapsing. The degree to which a
9560 consumer of data recognizes or knows that the data is weakly ordered
9561 varies among applications and may be unknown to the producer of this
9562 data. The \c{MFENCE} instruction provides a performance-efficient way
9563 of ensuring load and store ordering between routines that produce
9564 weakly-ordered results and routines that consume that data.
9566 \c{MFENCE} uses the following ModRM encoding:
9569 \c Reg/Opcode (5:3) = 110B
9572 All other ModRM encodings are defined to be reserved, and use
9573 of these encodings risks incompatibility with future processors.
9575 See also \c{LFENCE} (\k{insLFENCE}) and \c{SFENCE} (\k{insSFENCE}).
9578 \S{insMINPD} \i\c{MINPD}: Return Packed Double-Precision FP Minimum
9580 \c MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2]
9582 \c{MINPD} performs a SIMD compare of the packed double-precision
9583 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9584 of each pair of values in xmm1. If the values being compared are
9585 both zeroes, source2 (xmm2/m128) would be returned. If source2
9586 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9587 destination (i.e., a QNaN version of the SNaN is not returned).
9590 \S{insMINPS} \i\c{MINPS}: Return Packed Single-Precision FP Minimum
9592 \c MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE]
9594 \c{MINPS} performs a SIMD compare of the packed single-precision
9595 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9596 of each pair of values in xmm1. If the values being compared are
9597 both zeroes, source2 (xmm2/m128) would be returned. If source2
9598 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9599 destination (i.e., a QNaN version of the SNaN is not returned).
9602 \S{insMINSD} \i\c{MINSD}: Return Scalar Double-Precision FP Minimum
9604 \c MINSD xmm1,xmm2/m64 ; F2 0F 5D /r [WILLAMETTE,SSE2]
9606 \c{MINSD} compares the low-order double-precision FP numbers from
9607 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9608 values being compared are both zeroes, source2 (xmm2/m64) would
9609 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9610 forwarded unchanged to the destination (i.e., a QNaN version of
9611 the SNaN is not returned). The high quadword of the destination
9615 \S{insMINSS} \i\c{MINSS}: Return Scalar Single-Precision FP Minimum
9617 \c MINSS xmm1,xmm2/m32 ; F3 0F 5D /r [KATMAI,SSE]
9619 \c{MINSS} compares the low-order single-precision FP numbers from
9620 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9621 values being compared are both zeroes, source2 (xmm2/m32) would
9622 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9623 forwarded unchanged to the destination (i.e., a QNaN version of
9624 the SNaN is not returned). The high three doublewords of the
9625 destination are left unchanged.
9628 \S{insMOV} \i\c{MOV}: Move Data
9630 \c MOV r/m8,reg8 ; 88 /r [8086]
9631 \c MOV r/m16,reg16 ; o16 89 /r [8086]
9632 \c MOV r/m32,reg32 ; o32 89 /r [386]
9633 \c MOV reg8,r/m8 ; 8A /r [8086]
9634 \c MOV reg16,r/m16 ; o16 8B /r [8086]
9635 \c MOV reg32,r/m32 ; o32 8B /r [386]
9637 \c MOV reg8,imm8 ; B0+r ib [8086]
9638 \c MOV reg16,imm16 ; o16 B8+r iw [8086]
9639 \c MOV reg32,imm32 ; o32 B8+r id [386]
9640 \c MOV r/m8,imm8 ; C6 /0 ib [8086]
9641 \c MOV r/m16,imm16 ; o16 C7 /0 iw [8086]
9642 \c MOV r/m32,imm32 ; o32 C7 /0 id [386]
9644 \c MOV AL,memoffs8 ; A0 ow/od [8086]
9645 \c MOV AX,memoffs16 ; o16 A1 ow/od [8086]
9646 \c MOV EAX,memoffs32 ; o32 A1 ow/od [386]
9647 \c MOV memoffs8,AL ; A2 ow/od [8086]
9648 \c MOV memoffs16,AX ; o16 A3 ow/od [8086]
9649 \c MOV memoffs32,EAX ; o32 A3 ow/od [386]
9651 \c MOV r/m16,segreg ; o16 8C /r [8086]
9652 \c MOV r/m32,segreg ; o32 8C /r [386]
9653 \c MOV segreg,r/m16 ; o16 8E /r [8086]
9654 \c MOV segreg,r/m32 ; o32 8E /r [386]
9656 \c MOV reg32,CR0/2/3/4 ; 0F 20 /r [386]
9657 \c MOV reg32,DR0/1/2/3/6/7 ; 0F 21 /r [386]
9658 \c MOV reg32,TR3/4/5/6/7 ; 0F 24 /r [386]
9659 \c MOV CR0/2/3/4,reg32 ; 0F 22 /r [386]
9660 \c MOV DR0/1/2/3/6/7,reg32 ; 0F 23 /r [386]
9661 \c MOV TR3/4/5/6/7,reg32 ; 0F 26 /r [386]
9663 \c{MOV} copies the contents of its source (second) operand into its
9664 destination (first) operand.
9666 In all forms of the \c{MOV} instruction, the two operands are the
9667 same size, except for moving between a segment register and an
9668 \c{r/m32} operand. These instructions are treated exactly like the
9669 corresponding 16-bit equivalent (so that, for example, \c{MOV
9670 DS,EAX} functions identically to \c{MOV DS,AX} but saves a prefix
9671 when in 32-bit mode), except that when a segment register is moved
9672 into a 32-bit destination, the top two bytes of the result are
9675 \c{MOV} may not use \c{CS} as a destination.
9677 \c{CR4} is only a supported register on the Pentium and above.
9679 Test registers are supported on 386/486 processors and on some
9680 non-Intel Pentium class processors.
9683 \S{insMOVAPD} \i\c{MOVAPD}: Move Aligned Packed Double-Precision FP Values
9685 \c MOVAPD xmm1,xmm2/mem128 ; 66 0F 28 /r [WILLAMETTE,SSE2]
9686 \c MOVAPD xmm1/mem128,xmm2 ; 66 0F 29 /r [WILLAMETTE,SSE2]
9688 \c{MOVAPD} moves a double quadword containing 2 packed double-precision
9689 FP values from the source operand to the destination. When the source
9690 or destination operand is a memory location, it must be aligned on a
9693 To move data in and out of memory locations that are not known to be on
9694 16-byte boundaries, use the \c{MOVUPD} instruction (\k{insMOVUPD}).
9697 \S{insMOVAPS} \i\c{MOVAPS}: Move Aligned Packed Single-Precision FP Values
9699 \c MOVAPS xmm1,xmm2/mem128 ; 0F 28 /r [KATMAI,SSE]
9700 \c MOVAPS xmm1/mem128,xmm2 ; 0F 29 /r [KATMAI,SSE]
9702 \c{MOVAPS} moves a double quadword containing 4 packed single-precision
9703 FP values from the source operand to the destination. When the source
9704 or destination operand is a memory location, it must be aligned on a
9707 To move data in and out of memory locations that are not known to be on
9708 16-byte boundaries, use the \c{MOVUPS} instruction (\k{insMOVUPS}).
9711 \S{insMOVD} \i\c{MOVD}: Move Doubleword to/from MMX Register
9713 \c MOVD mm,r/m32 ; 0F 6E /r [PENT,MMX]
9714 \c MOVD r/m32,mm ; 0F 7E /r [PENT,MMX]
9715 \c MOVD xmm,r/m32 ; 66 0F 6E /r [WILLAMETTE,SSE2]
9716 \c MOVD r/m32,xmm ; 66 0F 7E /r [WILLAMETTE,SSE2]
9718 \c{MOVD} copies 32 bits from its source (second) operand into its
9719 destination (first) operand. When the destination is a 64-bit \c{MMX}
9720 register or a 128-bit \c{XMM} register, the input value is zero-extended
9721 to fill the destination register.
9724 \S{insMOVDQ2Q} \i\c{MOVDQ2Q}: Move Quadword from XMM to MMX register.
9726 \c MOVDQ2Q mm,xmm ; F2 OF D6 /r [WILLAMETTE,SSE2]
9728 \c{MOVDQ2Q} moves the low quadword from the source operand to the
9729 destination operand.
9732 \S{insMOVDQA} \i\c{MOVDQA}: Move Aligned Double Quadword
9734 \c MOVDQA xmm1,xmm2/m128 ; 66 OF 6F /r [WILLAMETTE,SSE2]
9735 \c MOVDQA xmm1/m128,xmm2 ; 66 OF 7F /r [WILLAMETTE,SSE2]
9737 \c{MOVDQA} moves a double quadword from the source operand to the
9738 destination operand. When the source or destination operand is a
9739 memory location, it must be aligned to a 16-byte boundary.
9741 To move a double quadword to or from unaligned memory locations,
9742 use the \c{MOVDQU} instruction (\k{insMOVDQU}).
9745 \S{insMOVDQU} \i\c{MOVDQU}: Move Unaligned Double Quadword
9747 \c MOVDQU xmm1,xmm2/m128 ; F3 OF 6F /r [WILLAMETTE,SSE2]
9748 \c MOVDQU xmm1/m128,xmm2 ; F3 OF 7F /r [WILLAMETTE,SSE2]
9750 \c{MOVDQU} moves a double quadword from the source operand to the
9751 destination operand. When the source or destination operand is a
9752 memory location, the memory may be unaligned.
9754 To move a double quadword to or from known aligned memory locations,
9755 use the \c{MOVDQA} instruction (\k{insMOVDQA}).
9758 \S{insMOVHLPS} \i\c{MOVHLPS}: Move Packed Single-Precision FP High to Low
9760 \c MOVHLPS xmm1,xmm2 ; OF 12 /r [KATMAI,SSE]
9762 \c{MOVHLPS} moves the two packed single-precision FP values from the
9763 high quadword of the source register xmm2 to the low quadword of the
9764 destination register, xmm2. The upper quadword of xmm1 is left unchanged.
9766 The operation of this instruction is:
9768 \c dst[0-63] := src[64-127],
9769 \c dst[64-127] remains unchanged.
9772 \S{insMOVHPD} \i\c{MOVHPD}: Move High Packed Double-Precision FP
9774 \c MOVHPD xmm,m64 ; 66 OF 16 /r [WILLAMETTE,SSE2]
9775 \c MOVHPD m64,xmm ; 66 OF 17 /r [WILLAMETTE,SSE2]
9777 \c{MOVHPD} moves a double-precision FP value between the source and
9778 destination operands. One of the operands is a 64-bit memory location,
9779 the other is the high quadword of an \c{XMM} register.
9781 The operation of this instruction is:
9783 \c mem[0-63] := xmm[64-127];
9787 \c xmm[0-63] remains unchanged;
9788 \c xmm[64-127] := mem[0-63].
9791 \S{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-Precision FP
9793 \c MOVHPS xmm,m64 ; 0F 16 /r [KATMAI,SSE]
9794 \c MOVHPS m64,xmm ; 0F 17 /r [KATMAI,SSE]
9796 \c{MOVHPS} moves two packed single-precision FP values between the source
9797 and destination operands. One of the operands is a 64-bit memory location,
9798 the other is the high quadword of an \c{XMM} register.
9800 The operation of this instruction is:
9802 \c mem[0-63] := xmm[64-127];
9806 \c xmm[0-63] remains unchanged;
9807 \c xmm[64-127] := mem[0-63].
9810 \S{insMOVLHPS} \i\c{MOVLHPS}: Move Packed Single-Precision FP Low to High
9812 \c MOVLHPS xmm1,xmm2 ; OF 16 /r [KATMAI,SSE]
9814 \c{MOVLHPS} moves the two packed single-precision FP values from the
9815 low quadword of the source register xmm2 to the high quadword of the
9816 destination register, xmm2. The low quadword of xmm1 is left unchanged.
9818 The operation of this instruction is:
9820 \c dst[0-63] remains unchanged;
9821 \c dst[64-127] := src[0-63].
9823 \S{insMOVLPD} \i\c{MOVLPD}: Move Low Packed Double-Precision FP
9825 \c MOVLPD xmm,m64 ; 66 OF 12 /r [WILLAMETTE,SSE2]
9826 \c MOVLPD m64,xmm ; 66 OF 13 /r [WILLAMETTE,SSE2]
9828 \c{MOVLPD} moves a double-precision FP value between the source and
9829 destination operands. One of the operands is a 64-bit memory location,
9830 the other is the low quadword of an \c{XMM} register.
9832 The operation of this instruction is:
9834 \c mem(0-63) := xmm(0-63);
9838 \c xmm(0-63) := mem(0-63);
9839 \c xmm(64-127) remains unchanged.
9841 \S{insMOVLPS} \i\c{MOVLPS}: Move Low Packed Single-Precision FP
9843 \c MOVLPS xmm,m64 ; OF 12 /r [KATMAI,SSE]
9844 \c MOVLPS m64,xmm ; OF 13 /r [KATMAI,SSE]
9846 \c{MOVLPS} moves two packed single-precision FP values between the source
9847 and destination operands. One of the operands is a 64-bit memory location,
9848 the other is the low quadword of an \c{XMM} register.
9850 The operation of this instruction is:
9852 \c mem(0-63) := xmm(0-63);
9856 \c xmm(0-63) := mem(0-63);
9857 \c xmm(64-127) remains unchanged.
9860 \S{insMOVMSKPD} \i\c{MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask
9862 \c MOVMSKPD reg32,xmm ; 66 0F 50 /r [WILLAMETTE,SSE2]
9864 \c{MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant
9865 bits of each double-precision FP number of the source operand.
9868 \S{insMOVMSKPS} \i\c{MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask
9870 \c MOVMSKPS reg32,xmm ; 0F 50 /r [KATMAI,SSE]
9872 \c{MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant
9873 bits of each single-precision FP number of the source operand.
9876 \S{insMOVNTDQ} \i\c{MOVNTDQ}: Move Double Quadword Non Temporal
9878 \c MOVNTDQ m128,xmm ; 66 0F E7 /r [WILLAMETTE,SSE2]
9880 \c{MOVNTDQ} moves the double quadword from the \c{XMM} source
9881 register to the destination memory location, using a non-temporal
9882 hint. This store instruction minimizes cache pollution.
9885 \S{insMOVNTI} \i\c{MOVNTI}: Move Doubleword Non Temporal
9887 \c MOVNTI m32,reg32 ; 0F C3 /r [WILLAMETTE,SSE2]
9889 \c{MOVNTI} moves the doubleword in the source register
9890 to the destination memory location, using a non-temporal
9891 hint. This store instruction minimizes cache pollution.
9894 \S{insMOVNTPD} \i\c{MOVNTPD}: Move Aligned Four Packed Single-Precision
9895 FP Values Non Temporal
9897 \c MOVNTPD m128,xmm ; 66 0F 2B /r [WILLAMETTE,SSE2]
9899 \c{MOVNTPD} moves the double quadword from the \c{XMM} source
9900 register to the destination memory location, using a non-temporal
9901 hint. This store instruction minimizes cache pollution. The memory
9902 location must be aligned to a 16-byte boundary.
9905 \S{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-Precision
9906 FP Values Non Temporal
9908 \c MOVNTPS m128,xmm ; 0F 2B /r [KATMAI,SSE]
9910 \c{MOVNTPS} moves the double quadword from the \c{XMM} source
9911 register to the destination memory location, using a non-temporal
9912 hint. This store instruction minimizes cache pollution. The memory
9913 location must be aligned to a 16-byte boundary.
9916 \S{insMOVNTQ} \i\c{MOVNTQ}: Move Quadword Non Temporal
9918 \c MOVNTQ m64,mm ; 0F E7 /r [KATMAI,MMX]
9920 \c{MOVNTQ} moves the quadword in the \c{MMX} source register
9921 to the destination memory location, using a non-temporal
9922 hint. This store instruction minimizes cache pollution.
9925 \S{insMOVQ} \i\c{MOVQ}: Move Quadword to/from MMX Register
9927 \c MOVQ mm1,mm2/m64 ; 0F 6F /r [PENT,MMX]
9928 \c MOVQ mm1/m64,mm2 ; 0F 7F /r [PENT,MMX]
9930 \c MOVQ xmm1,xmm2/m64 ; F3 0F 7E /r [WILLAMETTE,SSE2]
9931 \c MOVQ xmm1/m64,xmm2 ; 66 0F D6 /r [WILLAMETTE,SSE2]
9933 \c{MOVQ} copies 64 bits from its source (second) operand into its
9934 destination (first) operand. When the source is an \c{XMM} register,
9935 the low quadword is moved. When the destination is an \c{XMM} register,
9936 the destination is the low quadword, and the high quadword is cleared.
9939 \S{insMOVQ2DQ} \i\c{MOVQ2DQ}: Move Quadword from MMX to XMM register.
9941 \c MOVQ2DQ xmm,mm ; F3 OF D6 /r [WILLAMETTE,SSE2]
9943 \c{MOVQ2DQ} moves the quadword from the source operand to the low
9944 quadword of the destination operand, and clears the high quadword.
9947 \S{insMOVSB} \i\c{MOVSB}, \i\c{MOVSW}, \i\c{MOVSD}: Move String
9949 \c MOVSB ; A4 [8086]
9950 \c MOVSW ; o16 A5 [8086]
9951 \c MOVSD ; o32 A5 [386]
9953 \c{MOVSB} copies the byte at \c{[DS:SI]} or \c{[DS:ESI]} to
9954 \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or decrements
9955 (depending on the direction flag: increments if the flag is clear,
9956 decrements if it is set) \c{SI} and \c{DI} (or \c{ESI} and \c{EDI}).
9958 The registers used are \c{SI} and \c{DI} if the address size is 16
9959 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
9960 an address size not equal to the current \c{BITS} setting, you can
9961 use an explicit \i\c{a16} or \i\c{a32} prefix.
9963 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
9964 overridden by using a segment register name as a prefix (for
9965 example, \c{es movsb}). The use of \c{ES} for the store to \c{[DI]}
9966 or \c{[EDI]} cannot be overridden.
9968 \c{MOVSW} and \c{MOVSD} work in the same way, but they copy a word
9969 or a doubleword instead of a byte, and increment or decrement the
9970 addressing registers by 2 or 4 instead of 1.
9972 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
9973 \c{ECX} - again, the address size chooses which) times.
9976 \S{insMOVSD} \i\c{MOVSD}: Move Scalar Double-Precision FP Value
9978 \c MOVSD xmm1,xmm2/m64 ; F2 0F 10 /r [WILLAMETTE,SSE2]
9979 \c MOVSD xmm1/m64,xmm2 ; F2 0F 11 /r [WILLAMETTE,SSE2]
9981 \c{MOVSD} moves a double-precision FP value from the source operand
9982 to the destination operand. When the source or destination is a
9983 register, the low-order FP value is read or written.
9986 \S{insMOVSS} \i\c{MOVSS}: Move Scalar Single-Precision FP Value
9988 \c MOVSS xmm1,xmm2/m32 ; F3 0F 10 /r [KATMAI,SSE]
9989 \c MOVSS xmm1/m32,xmm2 ; F3 0F 11 /r [KATMAI,SSE]
9991 \c{MOVSS} moves a single-precision FP value from the source operand
9992 to the destination operand. When the source or destination is a
9993 register, the low-order FP value is read or written.
9996 \S{insMOVSX} \i\c{MOVSX}, \i\c{MOVZX}: Move Data with Sign or Zero Extend
9998 \c MOVSX reg16,r/m8 ; o16 0F BE /r [386]
9999 \c MOVSX reg32,r/m8 ; o32 0F BE /r [386]
10000 \c MOVSX reg32,r/m16 ; o32 0F BF /r [386]
10002 \c MOVZX reg16,r/m8 ; o16 0F B6 /r [386]
10003 \c MOVZX reg32,r/m8 ; o32 0F B6 /r [386]
10004 \c MOVZX reg32,r/m16 ; o32 0F B7 /r [386]
10006 \c{MOVSX} sign-extends its source (second) operand to the length of
10007 its destination (first) operand, and copies the result into the
10008 destination operand. \c{MOVZX} does the same, but zero-extends
10009 rather than sign-extending.
10012 \S{insMOVUPD} \i\c{MOVUPD}: Move Unaligned Packed Double-Precision FP Values
10014 \c MOVUPD xmm1,xmm2/mem128 ; 66 0F 10 /r [WILLAMETTE,SSE2]
10015 \c MOVUPD xmm1/mem128,xmm2 ; 66 0F 11 /r [WILLAMETTE,SSE2]
10017 \c{MOVUPD} moves a double quadword containing 2 packed double-precision
10018 FP values from the source operand to the destination. This instruction
10019 makes no assumptions about alignment of memory operands.
10021 To move data in and out of memory locations that are known to be on 16-byte
10022 boundaries, use the \c{MOVAPD} instruction (\k{insMOVAPD}).
10025 \S{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Packed Single-Precision FP Values
10027 \c MOVUPS xmm1,xmm2/mem128 ; 0F 10 /r [KATMAI,SSE]
10028 \c MOVUPS xmm1/mem128,xmm2 ; 0F 11 /r [KATMAI,SSE]
10030 \c{MOVUPS} moves a double quadword containing 4 packed single-precision
10031 FP values from the source operand to the destination. This instruction
10032 makes no assumptions about alignment of memory operands.
10034 To move data in and out of memory locations that are known to be on 16-byte
10035 boundaries, use the \c{MOVAPS} instruction (\k{insMOVAPS}).
10038 \S{insMUL} \i\c{MUL}: Unsigned Integer Multiply
10040 \c MUL r/m8 ; F6 /4 [8086]
10041 \c MUL r/m16 ; o16 F7 /4 [8086]
10042 \c MUL r/m32 ; o32 F7 /4 [386]
10044 \c{MUL} performs unsigned integer multiplication. The other operand
10045 to the multiplication, and the destination operand, are implicit, in
10048 \b For \c{MUL r/m8}, \c{AL} is multiplied by the given operand; the
10049 product is stored in \c{AX}.
10051 \b For \c{MUL r/m16}, \c{AX} is multiplied by the given operand;
10052 the product is stored in \c{DX:AX}.
10054 \b For \c{MUL r/m32}, \c{EAX} is multiplied by the given operand;
10055 the product is stored in \c{EDX:EAX}.
10057 Signed integer multiplication is performed by the \c{IMUL}
10058 instruction: see \k{insIMUL}.
10061 \S{insMULPD} \i\c{MULPD}: Packed Single-FP Multiply
10063 \c MULPD xmm1,xmm2/mem128 ; 66 0F 59 /r [WILLAMETTE,SSE2]
10065 \c{MULPD} performs a SIMD multiply of the packed double-precision FP
10066 values in both operands, and stores the results in the destination register.
10069 \S{insMULPS} \i\c{MULPS}: Packed Single-FP Multiply
10071 \c MULPS xmm1,xmm2/mem128 ; 0F 59 /r [KATMAI,SSE]
10073 \c{MULPS} performs a SIMD multiply of the packed single-precision FP
10074 values in both operands, and stores the results in the destination register.
10077 \S{insMULSD} \i\c{MULSD}: Scalar Single-FP Multiply
10079 \c MULSD xmm1,xmm2/mem32 ; F2 0F 59 /r [WILLAMETTE,SSE2]
10081 \c{MULSD} multiplies the lowest double-precision FP values of both
10082 operands, and stores the result in the low quadword of xmm1.
10085 \S{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply
10087 \c MULSS xmm1,xmm2/mem32 ; F3 0F 59 /r [KATMAI,SSE]
10089 \c{MULSS} multiplies the lowest single-precision FP values of both
10090 operands, and stores the result in the low doubleword of xmm1.
10093 \S{insNEG} \i\c{NEG}, \i\c{NOT}: Two's and One's Complement
10095 \c NEG r/m8 ; F6 /3 [8086]
10096 \c NEG r/m16 ; o16 F7 /3 [8086]
10097 \c NEG r/m32 ; o32 F7 /3 [386]
10099 \c NOT r/m8 ; F6 /2 [8086]
10100 \c NOT r/m16 ; o16 F7 /2 [8086]
10101 \c NOT r/m32 ; o32 F7 /2 [386]
10103 \c{NEG} replaces the contents of its operand by the two's complement
10104 negation (invert all the bits and then add one) of the original
10105 value. \c{NOT}, similarly, performs one's complement (inverts all
10109 \S{insNOP} \i\c{NOP}: No Operation
10113 \c{NOP} performs no operation. Its opcode is the same as that
10114 generated by \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the
10115 processor mode; see \k{insXCHG}).
10118 \S{insOR} \i\c{OR}: Bitwise OR
10120 \c OR r/m8,reg8 ; 08 /r [8086]
10121 \c OR r/m16,reg16 ; o16 09 /r [8086]
10122 \c OR r/m32,reg32 ; o32 09 /r [386]
10124 \c OR reg8,r/m8 ; 0A /r [8086]
10125 \c OR reg16,r/m16 ; o16 0B /r [8086]
10126 \c OR reg32,r/m32 ; o32 0B /r [386]
10128 \c OR r/m8,imm8 ; 80 /1 ib [8086]
10129 \c OR r/m16,imm16 ; o16 81 /1 iw [8086]
10130 \c OR r/m32,imm32 ; o32 81 /1 id [386]
10132 \c OR r/m16,imm8 ; o16 83 /1 ib [8086]
10133 \c OR r/m32,imm8 ; o32 83 /1 ib [386]
10135 \c OR AL,imm8 ; 0C ib [8086]
10136 \c OR AX,imm16 ; o16 0D iw [8086]
10137 \c OR EAX,imm32 ; o32 0D id [386]
10139 \c{OR} performs a bitwise OR operation between its two operands
10140 (i.e. each bit of the result is 1 if and only if at least one of the
10141 corresponding bits of the two inputs was 1), and stores the result
10142 in the destination (first) operand.
10144 In the forms with an 8-bit immediate second operand and a longer
10145 first operand, the second operand is considered to be signed, and is
10146 sign-extended to the length of the first operand. In these cases,
10147 the \c{BYTE} qualifier is necessary to force NASM to generate this
10148 form of the instruction.
10150 The MMX instruction \c{POR} (see \k{insPOR}) performs the same
10151 operation on the 64-bit MMX registers.
10154 \S{insORPD} \i\c{ORPD}: Bit-wise Logical OR of Double-Precision FP Data
10156 \c ORPD xmm1,xmm2/m128 ; 66 0F 56 /r [WILLAMETTE,SSE2]
10158 \c{ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem,
10159 and stores the result in xmm1. If the source operand is a memory
10160 location, it must be aligned to a 16-byte boundary.
10163 \S{insORPS} \i\c{ORPS}: Bit-wise Logical OR of Single-Precision FP Data
10165 \c ORPS xmm1,xmm2/m128 ; 0F 56 /r [KATMAI,SSE]
10167 \c{ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem,
10168 and stores the result in xmm1. If the source operand is a memory
10169 location, it must be aligned to a 16-byte boundary.
10172 \S{insOUT} \i\c{OUT}: Output Data to I/O Port
10174 \c OUT imm8,AL ; E6 ib [8086]
10175 \c OUT imm8,AX ; o16 E7 ib [8086]
10176 \c OUT imm8,EAX ; o32 E7 ib [386]
10177 \c OUT DX,AL ; EE [8086]
10178 \c OUT DX,AX ; o16 EF [8086]
10179 \c OUT DX,EAX ; o32 EF [386]
10181 \c{OUT} writes the contents of the given source register to the
10182 specified I/O port. The port number may be specified as an immediate
10183 value if it is between 0 and 255, and otherwise must be stored in
10184 \c{DX}. See also \c{IN} (\k{insIN}).
10187 \S{insOUTSB} \i\c{OUTSB}, \i\c{OUTSW}, \i\c{OUTSD}: Output String to I/O Port
10189 \c OUTSB ; 6E [186]
10190 \c OUTSW ; o16 6F [186]
10191 \c OUTSD ; o32 6F [386]
10193 \c{OUTSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} and writes
10194 it to the I/O port specified in \c{DX}. It then increments or
10195 decrements (depending on the direction flag: increments if the flag
10196 is clear, decrements if it is set) \c{SI} or \c{ESI}.
10198 The register used is \c{SI} if the address size is 16 bits, and
10199 \c{ESI} if it is 32 bits. If you need to use an address size not
10200 equal to the current \c{BITS} setting, you can use an explicit
10201 \i\c{a16} or \i\c{a32} prefix.
10203 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
10204 overridden by using a segment register name as a prefix (for
10205 example, \c{es outsb}).
10207 \c{OUTSW} and \c{OUTSD} work in the same way, but they output a
10208 word or a doubleword instead of a byte, and increment or decrement
10209 the addressing registers by 2 or 4 instead of 1.
10211 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
10212 \c{ECX} - again, the address size chooses which) times.
10215 \S{insPACKSSDW} \i\c{PACKSSDW}, \i\c{PACKSSWB}, \i\c{PACKUSWB}: Pack Data
10217 \c PACKSSDW mm1,mm2/m64 ; 0F 6B /r [PENT,MMX]
10218 \c PACKSSWB mm1,mm2/m64 ; 0F 63 /r [PENT,MMX]
10219 \c PACKUSWB mm1,mm2/m64 ; 0F 67 /r [PENT,MMX]
10221 \c PACKSSDW xmm1,xmm2/m128 ; 66 0F 6B /r [WILLAMETTE,SSE2]
10222 \c PACKSSWB xmm1,xmm2/m128 ; 66 0F 63 /r [WILLAMETTE,SSE2]
10223 \c PACKUSWB xmm1,xmm2/m128 ; 66 0F 67 /r [WILLAMETTE,SSE2]
10225 All these instructions start by combining the source and destination
10226 operands, and then splitting the result in smaller sections which it
10227 then packs into the destination register. The \c{MMX} versions pack
10228 two 64-bit operands into one 64-bit register, while the \c{SSE}
10229 versions pack two 128-bit operands into one 128-bit register.
10231 \b \c{PACKSSWB} splits the combined value into words, and then reduces
10232 the words to bytes, using signed saturation. It then packs the bytes
10233 into the destination register in the same order the words were in.
10235 \b \c{PACKSSDW} performs the same operation as \c{PACKSSWB}, except that
10236 it reduces doublewords to words, then packs them into the destination
10239 \b \c{PACKUSWB} performs the same operation as \c{PACKSSWB}, except that
10240 it uses unsigned saturation when reducing the size of the elements.
10242 To perform signed saturation on a number, it is replaced by the largest
10243 signed number (\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too
10244 small it is replaced by the smallest signed number (\c{8000h} or
10245 \c{80h}) that will fit. To perform unsigned saturation, the input is
10246 treated as unsigned, and the input is replaced by the largest unsigned
10247 number that will fit.
10250 \S{insPADDB} \i\c{PADDB}, \i\c{PADDW}, \i\c{PADDD}: Add Packed Integers
10252 \c PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX]
10253 \c PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX]
10254 \c PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX]
10256 \c PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2]
10257 \c PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2]
10258 \c PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2]
10260 \c{PADDx} performs packed addition of the two operands, storing the
10261 result in the destination (first) operand.
10263 \b \c{PADDB} treats the operands as packed bytes, and adds each byte
10266 \b \c{PADDW} treats the operands as packed words;
10268 \b \c{PADDD} treats its operands as packed doublewords.
10270 When an individual result is too large to fit in its destination, it
10271 is wrapped around and the low bits are stored, with the carry bit
10275 \S{insPADDQ} \i\c{PADDQ}: Add Packed Quadword Integers
10277 \c PADDQ mm1,mm2/m64 ; 0F D4 /r [PENT,MMX]
10279 \c PADDQ xmm1,xmm2/m128 ; 66 0F D4 /r [WILLAMETTE,SSE2]
10281 \c{PADDQ} adds the quadwords in the source and destination operands, and
10282 stores the result in the destination register.
10284 When an individual result is too large to fit in its destination, it
10285 is wrapped around and the low bits are stored, with the carry bit
10289 \S{insPADDSB} \i\c{PADDSB}, \i\c{PADDSW}: Add Packed Signed Integers With Saturation
10291 \c PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX]
10292 \c PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX]
10294 \c PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2]
10295 \c PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2]
10297 \c{PADDSx} performs packed addition of the two operands, storing the
10298 result in the destination (first) operand.
10299 \c{PADDSB} treats the operands as packed bytes, and adds each byte
10300 individually; and \c{PADDSW} treats the operands as packed words.
10302 When an individual result is too large to fit in its destination, a
10303 saturated value is stored. The resulting value is the value with the
10304 largest magnitude of the same sign as the result which will fit in
10305 the available space.
10308 \S{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit Destination
10310 \c PADDSIW mmxreg,r/m64 ; 0F 51 /r [CYRIX,MMX]
10312 \c{PADDSIW}, specific to the Cyrix extensions to the MMX instruction
10313 set, performs the same function as \c{PADDSW}, except that the result
10314 is placed in an implied register.
10316 To work out the implied register, invert the lowest bit in the register
10317 number. So \c{PADDSIW MM0,MM2} would put the result in \c{MM1}, but
10318 \c{PADDSIW MM1,MM2} would put the result in \c{MM0}.
10321 \S{insPADDUSB} \i\c{PADDUSB}, \i\c{PADDUSW}: Add Packed Unsigned Integers With Saturation
10323 \c PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX]
10324 \c PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX]
10326 \c PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2]
10327 \c PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2]
10329 \c{PADDUSx} performs packed addition of the two operands, storing the
10330 result in the destination (first) operand.
10331 \c{PADDUSB} treats the operands as packed bytes, and adds each byte
10332 individually; and \c{PADDUSW} treats the operands as packed words.
10334 When an individual result is too large to fit in its destination, a
10335 saturated value is stored. The resulting value is the maximum value
10336 that will fit in the available space.
10339 \S{insPAND} \i\c{PAND}, \i\c{PANDN}: MMX Bitwise AND and AND-NOT
10341 \c PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX]
10342 \c PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX]
10344 \c PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2]
10345 \c PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2]
10348 \c{PAND} performs a bitwise AND operation between its two operands
10349 (i.e. each bit of the result is 1 if and only if the corresponding
10350 bits of the two inputs were both 1), and stores the result in the
10351 destination (first) operand.
10353 \c{PANDN} performs the same operation, but performs a one's
10354 complement operation on the destination (first) operand first.
10357 \S{insPAUSE} \i\c{PAUSE}: Spin Loop Hint
10359 \c PAUSE ; F3 90 [WILLAMETTE,SSE2]
10361 \c{PAUSE} provides a hint to the processor that the following code
10362 is a spin loop. This improves processor performance by bypassing
10363 possible memory order violations. On older processors, this instruction
10364 operates as a \c{NOP}.
10367 \S{insPAVEB} \i\c{PAVEB}: MMX Packed Average
10369 \c PAVEB mmxreg,r/m64 ; 0F 50 /r [CYRIX,MMX]
10371 \c{PAVEB}, specific to the Cyrix MMX extensions, treats its two
10372 operands as vectors of eight unsigned bytes, and calculates the
10373 average of the corresponding bytes in the operands. The resulting
10374 vector of eight averages is stored in the first operand.
10376 This opcode maps to \c{MOVMSKPS r32, xmm} on processors that support
10377 the SSE instruction set.
10380 \S{insPAVGB} \i\c{PAVGB} \i\c{PAVGW}: Average Packed Integers
10382 \c PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX]
10383 \c PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM]
10385 \c PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2]
10386 \c PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2]
10388 \c{PAVGB} and \c{PAVGW} add the unsigned data elements of the source
10389 operand to the unsigned data elements of the destination register,
10390 then adds 1 to the temporary results. The results of the add are then
10391 each independently right-shifted by one bit position. The high order
10392 bits of each element are filled with the carry bits of the corresponding
10395 \b \c{PAVGB} operates on packed unsigned bytes, and
10397 \b \c{PAVGW} operates on packed unsigned words.
10400 \S{insPAVGUSB} \i\c{PAVGUSB}: Average of unsigned packed 8-bit values
10402 \c PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW]
10404 \c{PAVGUSB} adds the unsigned data elements of the source operand to
10405 the unsigned data elements of the destination register, then adds 1
10406 to the temporary results. The results of the add are then each
10407 independently right-shifted by one bit position. The high order bits
10408 of each element are filled with the carry bits of the corresponding
10411 This instruction performs exactly the same operations as the \c{PAVGB}
10412 \c{MMX} instruction (\k{insPAVGB}).
10415 \S{insPCMPEQB} \i\c{PCMPxx}: Compare Packed Integers.
10417 \c PCMPEQB mm1,mm2/m64 ; 0F 74 /r [PENT,MMX]
10418 \c PCMPEQW mm1,mm2/m64 ; 0F 75 /r [PENT,MMX]
10419 \c PCMPEQD mm1,mm2/m64 ; 0F 76 /r [PENT,MMX]
10421 \c PCMPGTB mm1,mm2/m64 ; 0F 64 /r [PENT,MMX]
10422 \c PCMPGTW mm1,mm2/m64 ; 0F 65 /r [PENT,MMX]
10423 \c PCMPGTD mm1,mm2/m64 ; 0F 66 /r [PENT,MMX]
10425 \c PCMPEQB xmm1,xmm2/m128 ; 66 0F 74 /r [WILLAMETTE,SSE2]
10426 \c PCMPEQW xmm1,xmm2/m128 ; 66 0F 75 /r [WILLAMETTE,SSE2]
10427 \c PCMPEQD xmm1,xmm2/m128 ; 66 0F 76 /r [WILLAMETTE,SSE2]
10429 \c PCMPGTB xmm1,xmm2/m128 ; 66 0F 64 /r [WILLAMETTE,SSE2]
10430 \c PCMPGTW xmm1,xmm2/m128 ; 66 0F 65 /r [WILLAMETTE,SSE2]
10431 \c PCMPGTD xmm1,xmm2/m128 ; 66 0F 66 /r [WILLAMETTE,SSE2]
10433 The \c{PCMPxx} instructions all treat their operands as vectors of
10434 bytes, words, or doublewords; corresponding elements of the source
10435 and destination are compared, and the corresponding element of the
10436 destination (first) operand is set to all zeros or all ones
10437 depending on the result of the comparison.
10439 \b \c{PCMPxxB} treats the operands as vectors of bytes;
10441 \b \c{PCMPxxW} treats the operands as vectors of words;
10443 \b \c{PCMPxxD} treats the operands as vectors of doublewords;
10445 \b \c{PCMPEQx} sets the corresponding element of the destination
10446 operand to all ones if the two elements compared are equal;
10448 \b \c{PCMPGTx} sets the destination element to all ones if the element
10449 of the first (destination) operand is greater (treated as a signed
10450 integer) than that of the second (source) operand.
10453 \S{insPDISTIB} \i\c{PDISTIB}: MMX Packed Distance and Accumulate
10454 with Implied Register
10456 \c PDISTIB mm,m64 ; 0F 54 /r [CYRIX,MMX]
10458 \c{PDISTIB}, specific to the Cyrix MMX extensions, treats its two
10459 input operands as vectors of eight unsigned bytes. For each byte
10460 position, it finds the absolute difference between the bytes in that
10461 position in the two input operands, and adds that value to the byte
10462 in the same position in the implied output register. The addition is
10463 saturated to an unsigned byte in the same way as \c{PADDUSB}.
10465 To work out the implied register, invert the lowest bit in the register
10466 number. So \c{PDISTIB MM0,M64} would put the result in \c{MM1}, but
10467 \c{PDISTIB MM1,M64} would put the result in \c{MM0}.
10469 Note that \c{PDISTIB} cannot take a register as its second source
10474 \c dstI[0-7] := dstI[0-7] + ABS(src0[0-7] - src1[0-7]),
10475 \c dstI[8-15] := dstI[8-15] + ABS(src0[8-15] - src1[8-15]),
10478 \c dstI[56-63] := dstI[56-63] + ABS(src0[56-63] - src1[56-63]).
10481 \S{insPEXTRW} \i\c{PEXTRW}: Extract Word
10483 \c PEXTRW reg32,mm,imm8 ; 0F C5 /r ib [KATMAI,MMX]
10484 \c PEXTRW reg32,xmm,imm8 ; 66 0F C5 /r ib [WILLAMETTE,SSE2]
10486 \c{PEXTRW} moves the word in the source register (second operand)
10487 that is pointed to by the count operand (third operand), into the
10488 lower half of a 32-bit general purpose register. The upper half of
10489 the register is cleared to all 0s.
10491 When the source operand is an \c{MMX} register, the two least
10492 significant bits of the count specify the source word. When it is
10493 an \c{SSE} register, the three least significant bits specify the
10497 \S{insPF2ID} \i\c{PF2ID}: Packed Single-Precision FP to Integer Convert
10499 \c PF2ID mm1,mm2/m64 ; 0F 0F /r 1D [PENT,3DNOW]
10501 \c{PF2ID} converts two single-precision FP values in the source operand
10502 to signed 32-bit integers, using truncation, and stores them in the
10503 destination operand. Source values that are outside the range supported
10504 by the destination are saturated to the largest absolute value of the
10508 \S{insPF2IW} \i\c{PF2IW}: Packed Single-Precision FP to Integer Word Convert
10510 \c PF2IW mm1,mm2/m64 ; 0F 0F /r 1C [PENT,3DNOW]
10512 \c{PF2IW} converts two single-precision FP values in the source operand
10513 to signed 16-bit integers, using truncation, and stores them in the
10514 destination operand. Source values that are outside the range supported
10515 by the destination are saturated to the largest absolute value of the
10518 \b In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits
10521 \b In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended
10522 to 32-bits before storing.
10525 \S{insPFACC} \i\c{PFACC}: Packed Single-Precision FP Accumulate
10527 \c PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW]
10529 \c{PFACC} adds the two single-precision FP values from the destination
10530 operand together, then adds the two single-precision FP values from the
10531 source operand, and places the results in the low and high doublewords
10532 of the destination operand.
10536 \c dst[0-31] := dst[0-31] + dst[32-63],
10537 \c dst[32-63] := src[0-31] + src[32-63].
10540 \S{insPFADD} \i\c{PFADD}: Packed Single-Precision FP Addition
10542 \c PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW]
10544 \c{PFADD} performs addition on each of two packed single-precision
10547 \c dst[0-31] := dst[0-31] + src[0-31],
10548 \c dst[32-63] := dst[32-63] + src[32-63].
10551 \S{insPFCMP} \i\c{PFCMPxx}: Packed Single-Precision FP Compare
10552 \I\c{PFCMPEQ} \I\c{PFCMPGE} \I\c{PFCMPGT}
10554 \c PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW]
10555 \c PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW]
10556 \c PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW]
10558 The \c{PFCMPxx} instructions compare the packed single-point FP values
10559 in the source and destination operands, and set the destination
10560 according to the result. If the condition is true, the destination is
10561 set to all 1s, otherwise it's set to all 0s.
10563 \b \c{PFCMPEQ} tests whether dst == src;
10565 \b \c{PFCMPGE} tests whether dst >= src;
10567 \b \c{PFCMPGT} tests whether dst > src.
10570 \S{insPFMAX} \i\c{PFMAX}: Packed Single-Precision FP Maximum
10572 \c PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW]
10574 \c{PFMAX} returns the higher of each pair of single-precision FP values.
10575 If the higher value is zero, it is returned as positive zero.
10578 \S{insPFMIN} \i\c{PFMIN}: Packed Single-Precision FP Minimum
10580 \c PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW]
10582 \c{PFMIN} returns the lower of each pair of single-precision FP values.
10583 If the lower value is zero, it is returned as positive zero.
10586 \S{insPFMUL} \i\c{PFMUL}: Packed Single-Precision FP Multiply
10588 \c PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW]
10590 \c{PFMUL} returns the product of each pair of single-precision FP values.
10592 \c dst[0-31] := dst[0-31] * src[0-31],
10593 \c dst[32-63] := dst[32-63] * src[32-63].
10596 \S{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Negative Accumulate
10598 \c PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW]
10600 \c{PFNACC} performs a negative accumulate of the two single-precision
10601 FP values in the source and destination registers. The result of the
10602 accumulate from the destination register is stored in the low doubleword
10603 of the destination, and the result of the source accumulate is stored in
10604 the high doubleword of the destination register.
10608 \c dst[0-31] := dst[0-31] - dst[32-63],
10609 \c dst[32-63] := src[0-31] - src[32-63].
10612 \S{insPFPNACC} \i\c{PFPNACC}: Packed Single-Precision FP Mixed Accumulate
10614 \c PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW]
10616 \c{PFPNACC} performs a positive accumulate of the two single-precision
10617 FP values in the source register and a negative accumulate of the
10618 destination register. The result of the accumulate from the destination
10619 register is stored in the low doubleword of the destination, and the
10620 result of the source accumulate is stored in the high doubleword of the
10621 destination register.
10625 \c dst[0-31] := dst[0-31] - dst[32-63],
10626 \c dst[32-63] := src[0-31] + src[32-63].
10629 \S{insPFRCP} \i\c{PFRCP}: Packed Single-Precision FP Reciprocal Approximation
10631 \c PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW]
10633 \c{PFRCP} performs a low precision estimate of the reciprocal of the
10634 low-order single-precision FP value in the source operand, storing the
10635 result in both halves of the destination register. The result is accurate
10638 For higher precision reciprocals, this instruction should be followed by
10639 two more instructions: \c{PFRCPIT1} (\k{insPFRCPIT1}) and \c{PFRCPIT2}
10640 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10641 see the AMD 3DNow! technology manual.
10644 \S{insPFRCPIT1} \i\c{PFRCPIT1}: Packed Single-Precision FP Reciprocal,
10645 First Iteration Step
10647 \c PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW]
10649 \c{PFRCPIT1} performs the first intermediate step in the calculation of
10650 the reciprocal of a single-precision FP value. The first source value
10651 (\c{mm1} is the original value, and the second source value (\c{mm2/m64}
10652 is the result of a \c{PFRCP} instruction.
10654 For the final step in a reciprocal, returning the full 24-bit accuracy
10655 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10656 more details, see the AMD 3DNow! technology manual.
10659 \S{insPFRCPIT2} \i\c{PFRCPIT2}: Packed Single-Precision FP
10660 Reciprocal/ Reciprocal Square Root, Second Iteration Step
10662 \c PFRCPIT2 mm1,mm2/m64 ; 0F 0F /r B6 [PENT,3DNOW]
10664 \c{PFRCPIT2} performs the second and final intermediate step in the
10665 calculation of a reciprocal or reciprocal square root, refining the
10666 values returned by the \c{PFRCP} and \c{PFRSQRT} instructions,
10669 The first source value (\c{mm1}) is the output of either a \c{PFRCPIT1}
10670 or a \c{PFRSQIT1} instruction, and the second source is the output of
10671 either the \c{PFRCP} or the \c{PFRSQRT} instruction. For more details,
10672 see the AMD 3DNow! technology manual.
10675 \S{insPFRSQIT1} \i\c{PFRSQIT1}: Packed Single-Precision FP Reciprocal
10676 Square Root, First Iteration Step
10678 \c PFRSQIT1 mm1,mm2/m64 ; 0F 0F /r A7 [PENT,3DNOW]
10680 \c{PFRSQIT1} performs the first intermediate step in the calculation of
10681 the reciprocal square root of a single-precision FP value. The first
10682 source value (\c{mm1} is the square of the result of a \c{PFRSQRT}
10683 instruction, and the second source value (\c{mm2/m64} is the original
10686 For the final step in a calculation, returning the full 24-bit accuracy
10687 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10688 more details, see the AMD 3DNow! technology manual.
10691 \S{insPFRSQRT} \i\c{PFRSQRT}: Packed Single-Precision FP Reciprocal
10692 Square Root Approximation
10694 \c PFRSQRT mm1,mm2/m64 ; 0F 0F /r 97 [PENT,3DNOW]
10696 \c{PFRSQRT} performs a low precision estimate of the reciprocal square
10697 root of the low-order single-precision FP value in the source operand,
10698 storing the result in both halves of the destination register. The result
10699 is accurate to 15 bits.
10701 For higher precision reciprocals, this instruction should be followed by
10702 two more instructions: \c{PFRSQIT1} (\k{insPFRSQIT1}) and \c{PFRCPIT2}
10703 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10704 see the AMD 3DNow! technology manual.
10707 \S{insPFSUB} \i\c{PFSUB}: Packed Single-Precision FP Subtract
10709 \c PFSUB mm1,mm2/m64 ; 0F 0F /r 9A [PENT,3DNOW]
10711 \c{PFSUB} subtracts the single-precision FP values in the source from
10712 those in the destination, and stores the result in the destination
10715 \c dst[0-31] := dst[0-31] - src[0-31],
10716 \c dst[32-63] := dst[32-63] - src[32-63].
10719 \S{insPFSUBR} \i\c{PFSUBR}: Packed Single-Precision FP Reverse Subtract
10721 \c PFSUBR mm1,mm2/m64 ; 0F 0F /r AA [PENT,3DNOW]
10723 \c{PFSUBR} subtracts the single-precision FP values in the destination
10724 from those in the source, and stores the result in the destination
10727 \c dst[0-31] := src[0-31] - dst[0-31],
10728 \c dst[32-63] := src[32-63] - dst[32-63].
10731 \S{insPI2FD} \i\c{PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert
10733 \c PI2FD mm1,mm2/m64 ; 0F 0F /r 0D [PENT,3DNOW]
10735 \c{PF2ID} converts two signed 32-bit integers in the source operand
10736 to single-precision FP values, using truncation of significant digits,
10737 and stores them in the destination operand.
10740 \S{insPF2IW} \i\c{PF2IW}: Packed Word Integer to Single-Precision FP Convert
10742 \c PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW]
10744 \c{PF2IW} converts two signed 16-bit integers in the source operand
10745 to single-precision FP values, and stores them in the destination
10746 operand. The input values are in the low word of each doubleword.
10749 \S{insPINSRW} \i\c{PINSRW}: Insert Word
10751 \c PINSRW mm,r16/r32/m16,imm8 ;0F C4 /r ib [KATMAI,MMX]
10752 \c PINSRW xmm,r16/r32/m16,imm8 ;66 0F C4 /r ib [WILLAMETTE,SSE2]
10754 \c{PINSRW} loads a word from a 16-bit register (or the low half of a
10755 32-bit register), or from memory, and loads it to the word position
10756 in the destination register, pointed at by the count operand (third
10757 operand). If the destination is an \c{MMX} register, the low two bits
10758 of the count byte are used, if it is an \c{XMM} register the low 3
10759 bits are used. The insertion is done in such a way that the other
10760 words from the destination register are left untouched.
10763 \S{insPMACHRIW} \i\c{PMACHRIW}: Packed Multiply and Accumulate with Rounding
10765 \c PMACHRIW mm,m64 ; 0F 5E /r [CYRIX,MMX]
10767 \c{PMACHRIW} takes two packed 16-bit integer inputs, multiplies the
10768 values in the inputs, rounds on bit 15 of each result, then adds bits
10769 15-30 of each result to the corresponding position of the \e{implied}
10770 destination register.
10772 The operation of this instruction is:
10774 \c dstI[0-15] := dstI[0-15] + (mm[0-15] *m64[0-15]
10775 \c + 0x00004000)[15-30],
10776 \c dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31]
10777 \c + 0x00004000)[15-30],
10778 \c dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47]
10779 \c + 0x00004000)[15-30],
10780 \c dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63]
10781 \c + 0x00004000)[15-30].
10783 Note that \c{PMACHRIW} cannot take a register as its second source
10787 \S{insPMADDWD} \i\c{PMADDWD}: MMX Packed Multiply and Add
10789 \c PMADDWD mm1,mm2/m64 ; 0F F5 /r [PENT,MMX]
10790 \c PMADDWD xmm1,xmm2/m128 ; 66 0F F5 /r [WILLAMETTE,SSE2]
10792 \c{PMADDWD} treats its two inputs as vectors of signed words. It
10793 multiplies corresponding elements of the two operands, giving doubleword
10794 results. These are then added together in pairs and stored in the
10795 destination operand.
10797 The operation of this instruction is:
10799 \c dst[0-31] := (dst[0-15] * src[0-15])
10800 \c + (dst[16-31] * src[16-31]);
10801 \c dst[32-63] := (dst[32-47] * src[32-47])
10802 \c + (dst[48-63] * src[48-63]);
10804 The following apply to the \c{SSE} version of the instruction:
10806 \c dst[64-95] := (dst[64-79] * src[64-79])
10807 \c + (dst[80-95] * src[80-95]);
10808 \c dst[96-127] := (dst[96-111] * src[96-111])
10809 \c + (dst[112-127] * src[112-127]).
10812 \S{insPMAGW} \i\c{PMAGW}: MMX Packed Magnitude
10814 \c PMAGW mm1,mm2/m64 ; 0F 52 /r [CYRIX,MMX]
10816 \c{PMAGW}, specific to the Cyrix MMX extensions, treats both its
10817 operands as vectors of four signed words. It compares the absolute
10818 values of the words in corresponding positions, and sets each word
10819 of the destination (first) operand to whichever of the two words in
10820 that position had the larger absolute value.
10823 \S{insPMAXSW} \i\c{PMAXSW}: Packed Signed Integer Word Maximum
10825 \c PMAXSW mm1,mm2/m64 ; 0F EE /r [KATMAI,MMX]
10826 \c PMAXSW xmm1,xmm2/m128 ; 66 0F EE /r [WILLAMETTE,SSE2]
10828 \c{PMAXSW} compares each pair of words in the two source operands, and
10829 for each pair it stores the maximum value in the destination register.
10832 \S{insPMAXUB} \i\c{PMAXUB}: Packed Unsigned Integer Byte Maximum
10834 \c PMAXUB mm1,mm2/m64 ; 0F DE /r [KATMAI,MMX]
10835 \c PMAXUB xmm1,xmm2/m128 ; 66 0F DE /r [WILLAMETTE,SSE2]
10837 \c{PMAXUB} compares each pair of bytes in the two source operands, and
10838 for each pair it stores the maximum value in the destination register.
10841 \S{insPMINSW} \i\c{PMINSW}: Packed Signed Integer Word Minimum
10843 \c PMINSW mm1,mm2/m64 ; 0F EA /r [KATMAI,MMX]
10844 \c PMINSW xmm1,xmm2/m128 ; 66 0F EA /r [WILLAMETTE,SSE2]
10846 \c{PMINSW} compares each pair of words in the two source operands, and
10847 for each pair it stores the minimum value in the destination register.
10850 \S{insPMINUB} \i\c{PMINUB}: Packed Unsigned Integer Byte Minimum
10852 \c PMINUB mm1,mm2/m64 ; 0F DA /r [KATMAI,MMX]
10853 \c PMINUB xmm1,xmm2/m128 ; 66 0F DA /r [WILLAMETTE,SSE2]
10855 \c{PMINUB} compares each pair of bytes in the two source operands, and
10856 for each pair it stores the minimum value in the destination register.
10859 \S{insPMOVMSKB} \i\c{PMOVMSKB}: Move Byte Mask To Integer
10861 \c PMOVMSKB reg32,mm ; 0F D7 /r [KATMAI,MMX]
10862 \c PMOVMSKB reg32,xmm ; 66 0F D7 /r [WILLAMETTE,SSE2]
10864 \c{PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most
10865 significant bits of each byte of source operand (8-bits for an
10866 \c{MMX} register, 16-bits for an \c{XMM} register).
10869 \S{insPMULHRW} \i\c{PMULHRWC}, \i\c{PMULHRIW}: Multiply Packed 16-bit Integers
10870 With Rounding, and Store High Word
10872 \c PMULHRWC mm1,mm2/m64 ; 0F 59 /r [CYRIX,MMX]
10873 \c PMULHRIW mm1,mm2/m64 ; 0F 5D /r [CYRIX,MMX]
10875 These instructions take two packed 16-bit integer inputs, multiply the
10876 values in the inputs, round on bit 15 of each result, then store bits
10877 15-30 of each result to the corresponding position of the destination
10880 \b For \c{PMULHRWC}, the destination is the first source operand.
10882 \b For \c{PMULHRIW}, the destination is an implied register (worked out
10883 as described for \c{PADDSIW} (\k{insPADDSIW})).
10885 The operation of this instruction is:
10887 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00004000)[15-30]
10888 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30]
10889 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30]
10890 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30]
10892 See also \c{PMULHRWA} (\k{insPMULHRWA}) for a 3DNow! version of this
10896 \S{insPMULHRWA} \i\c{PMULHRWA}: Multiply Packed 16-bit Integers
10897 With Rounding, and Store High Word
10899 \c PMULHRWA mm1,mm2/m64 ; 0F 0F /r B7 [PENT,3DNOW]
10901 \c{PMULHRWA} takes two packed 16-bit integer inputs, multiplies
10902 the values in the inputs, rounds on bit 16 of each result, then
10903 stores bits 16-31 of each result to the corresponding position
10904 of the destination register.
10906 The operation of this instruction is:
10908 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00008000)[16-31];
10909 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31];
10910 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31];
10911 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31].
10913 See also \c{PMULHRWC} (\k{insPMULHRW}) for a Cyrix version of this
10917 \S{insPMULHUW} \i\c{PMULHUW}: Multiply Packed 16-bit Integers,
10918 and Store High Word
10920 \c PMULHUW mm1,mm2/m64 ; 0F E4 /r [KATMAI,MMX]
10921 \c PMULHUW xmm1,xmm2/m128 ; 66 0F E4 /r [WILLAMETTE,SSE2]
10923 \c{PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies
10924 the values in the inputs, then stores bits 16-31 of each result to the
10925 corresponding position of the destination register.
10928 \S{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: Multiply Packed 16-bit Integers,
10931 \c PMULHW mm1,mm2/m64 ; 0F E5 /r [PENT,MMX]
10932 \c PMULLW mm1,mm2/m64 ; 0F D5 /r [PENT,MMX]
10934 \c PMULHW xmm1,xmm2/m128 ; 66 0F E5 /r [WILLAMETTE,SSE2]
10935 \c PMULLW xmm1,xmm2/m128 ; 66 0F D5 /r [WILLAMETTE,SSE2]
10937 \c{PMULxW} takes two packed unsigned 16-bit integer inputs, and
10938 multiplies the values in the inputs, forming doubleword results.
10940 \b \c{PMULHW} then stores the top 16 bits of each doubleword in the
10941 destination (first) operand;
10943 \b \c{PMULLW} stores the bottom 16 bits of each doubleword in the
10944 destination operand.
10947 \S{insPMULUDQ} \i\c{PMULUDQ}: Multiply Packed Unsigned
10948 32-bit Integers, and Store.
10950 \c PMULUDQ mm1,mm2/m64 ; 0F F4 /r [WILLAMETTE,SSE2]
10951 \c PMULUDQ xmm1,xmm2/m128 ; 66 0F F4 /r [WILLAMETTE,SSE2]
10953 \c{PMULUDQ} takes two packed unsigned 32-bit integer inputs, and
10954 multiplies the values in the inputs, forming quadword results. The
10955 source is either an unsigned doubleword in the low doubleword of a
10956 64-bit operand, or it's two unsigned doublewords in the first and
10957 third doublewords of a 128-bit operand. This produces either one or
10958 two 64-bit results, which are stored in the respective quadword
10959 locations of the destination register.
10963 \c dst[0-63] := dst[0-31] * src[0-31];
10964 \c dst[64-127] := dst[64-95] * src[64-95].
10967 \S{insPMVccZB} \i\c{PMVccZB}: MMX Packed Conditional Move
10969 \c PMVZB mmxreg,mem64 ; 0F 58 /r [CYRIX,MMX]
10970 \c PMVNZB mmxreg,mem64 ; 0F 5A /r [CYRIX,MMX]
10971 \c PMVLZB mmxreg,mem64 ; 0F 5B /r [CYRIX,MMX]
10972 \c PMVGEZB mmxreg,mem64 ; 0F 5C /r [CYRIX,MMX]
10974 These instructions, specific to the Cyrix MMX extensions, perform
10975 parallel conditional moves. The two input operands are treated as
10976 vectors of eight bytes. Each byte of the destination (first) operand
10977 is either written from the corresponding byte of the source (second)
10978 operand, or left alone, depending on the value of the byte in the
10979 \e{implied} operand (specified in the same way as \c{PADDSIW}, in
10982 \b \c{PMVZB} performs each move if the corresponding byte in the
10983 implied operand is zero;
10985 \b \c{PMVNZB} moves if the byte is non-zero;
10987 \b \c{PMVLZB} moves if the byte is less than zero;
10989 \b \c{PMVGEZB} moves if the byte is greater than or equal to zero.
10991 Note that these instructions cannot take a register as their second
10995 \S{insPOP} \i\c{POP}: Pop Data from Stack
10997 \c POP reg16 ; o16 58+r [8086]
10998 \c POP reg32 ; o32 58+r [386]
11000 \c POP r/m16 ; o16 8F /0 [8086]
11001 \c POP r/m32 ; o32 8F /0 [386]
11003 \c POP CS ; 0F [8086,UNDOC]
11004 \c POP DS ; 1F [8086]
11005 \c POP ES ; 07 [8086]
11006 \c POP SS ; 17 [8086]
11007 \c POP FS ; 0F A1 [386]
11008 \c POP GS ; 0F A9 [386]
11010 \c{POP} loads a value from the stack (from \c{[SS:SP]} or
11011 \c{[SS:ESP]}) and then increments the stack pointer.
11013 The address-size attribute of the instruction determines whether
11014 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11015 override the default given by the \c{BITS} setting, you can use an
11016 \i\c{a16} or \i\c{a32} prefix.
11018 The operand-size attribute of the instruction determines whether the
11019 stack pointer is incremented by 2 or 4: this means that segment
11020 register pops in \c{BITS 32} mode will pop 4 bytes off the stack and
11021 discard the upper two of them. If you need to override that, you can
11022 use an \i\c{o16} or \i\c{o32} prefix.
11024 The above opcode listings give two forms for general-purpose
11025 register pop instructions: for example, \c{POP BX} has the two forms
11026 \c{5B} and \c{8F C3}. NASM will always generate the shorter form
11027 when given \c{POP BX}. NDISASM will disassemble both.
11029 \c{POP CS} is not a documented instruction, and is not supported on
11030 any processor above the 8086 (since they use \c{0Fh} as an opcode
11031 prefix for instruction set extensions). However, at least some 8086
11032 processors do support it, and so NASM generates it for completeness.
11035 \S{insPOPA} \i\c{POPAx}: Pop All General-Purpose Registers
11038 \c POPAW ; o16 61 [186]
11039 \c POPAD ; o32 61 [386]
11041 \b \c{POPAW} pops a word from the stack into each of, successively,
11042 \c{DI}, \c{SI}, \c{BP}, nothing (it discards a word from the stack
11043 which was a placeholder for \c{SP}), \c{BX}, \c{DX}, \c{CX} and
11044 \c{AX}. It is intended to reverse the operation of \c{PUSHAW} (see
11045 \k{insPUSHA}), but it ignores the value for \c{SP} that was pushed
11046 on the stack by \c{PUSHAW}.
11048 \b \c{POPAD} pops twice as much data, and places the results in
11049 \c{EDI}, \c{ESI}, \c{EBP}, nothing (placeholder for \c{ESP}),
11050 \c{EBX}, \c{EDX}, \c{ECX} and \c{EAX}. It reverses the operation of
11053 \c{POPA} is an alias mnemonic for either \c{POPAW} or \c{POPAD},
11054 depending on the current \c{BITS} setting.
11056 Note that the registers are popped in reverse order of their numeric
11057 values in opcodes (see \k{iref-rv}).
11060 \S{insPOPF} \i\c{POPFx}: Pop Flags Register
11062 \c POPF ; 9D [8086]
11063 \c POPFW ; o16 9D [8086]
11064 \c POPFD ; o32 9D [386]
11066 \b \c{POPFW} pops a word from the stack and stores it in the bottom 16
11067 bits of the flags register (or the whole flags register, on
11068 processors below a 386).
11070 \b \c{POPFD} pops a doubleword and stores it in the entire flags register.
11072 \c{POPF} is an alias mnemonic for either \c{POPFW} or \c{POPFD},
11073 depending on the current \c{BITS} setting.
11075 See also \c{PUSHF} (\k{insPUSHF}).
11078 \S{insPOR} \i\c{POR}: MMX Bitwise OR
11080 \c POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX]
11081 \c POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2]
11083 \c{POR} performs a bitwise OR operation between its two operands
11084 (i.e. each bit of the result is 1 if and only if at least one of the
11085 corresponding bits of the two inputs was 1), and stores the result
11086 in the destination (first) operand.
11089 \S{insPREFETCH} \i\c{PREFETCH}: Prefetch Data Into Caches
11091 \c PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW]
11092 \c PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW]
11094 \c{PREFETCH} and \c{PREFETCHW} fetch the line of data from memory that
11095 contains the specified byte. \c{PREFETCHW} performs differently on the
11096 Athlon to earlier processors.
11098 For more details, see the 3DNow! Technology Manual.
11101 \S{insPREFETCHh} \i\c{PREFETCHh}: Prefetch Data Into Caches
11102 \I\c{PREFETCHNTA} \I\c{PREFETCHT0} \I\c{PREFETCHT1} \I\c{PREFETCHT2}
11104 \c PREFETCHNTA m8 ; 0F 18 /0 [KATMAI]
11105 \c PREFETCHT0 m8 ; 0F 18 /1 [KATMAI]
11106 \c PREFETCHT1 m8 ; 0F 18 /2 [KATMAI]
11107 \c PREFETCHT2 m8 ; 0F 18 /3 [KATMAI]
11109 The \c{PREFETCHh} instructions fetch the line of data from memory
11110 that contains the specified byte. It is placed in the cache
11111 according to rules specified by locality hints \c{h}:
11115 \b \c{T0} (temporal data) - prefetch data into all levels of the
11118 \b \c{T1} (temporal data with respect to first level cache) -
11119 prefetch data into level 2 cache and higher.
11121 \b \c{T2} (temporal data with respect to second level cache) -
11122 prefetch data into level 2 cache and higher.
11124 \b \c{NTA} (non-temporal data with respect to all cache levels) -
11125 prefetch data into non-temporal cache structure and into a
11126 location close to the processor, minimizing cache pollution.
11128 Note that this group of instructions doesn't provide a guarantee
11129 that the data will be in the cache when it is needed. For more
11130 details, see the Intel IA32 Software Developer Manual, Volume 2.
11133 \S{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences
11135 \c PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX]
11136 \c PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2]
11138 \c{PSADBW} The PSADBW instruction computes the absolute value of the
11139 difference of the packed unsigned bytes in the two source operands.
11140 These differences are then summed to produce a word result in the lower
11141 16-bit field of the destination register; the rest of the register is
11142 cleared. The destination operand is an \c{MMX} or an \c{XMM} register.
11143 The source operand can either be a register or a memory operand.
11146 \S{insPSHUFD} \i\c{PSHUFD}: Shuffle Packed Doublewords
11148 \c PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2]
11150 \c{PSHUFD} shuffles the doublewords in the source (second) operand
11151 according to the encoding specified by imm8, and stores the result
11152 in the destination (first) operand.
11154 Bits 0 and 1 of imm8 encode the source position of the doubleword to
11155 be copied to position 0 in the destination operand. Bits 2 and 3
11156 encode for position 1, bits 4 and 5 encode for position 2, and bits
11157 6 and 7 encode for position 3. For example, an encoding of 10 in
11158 bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of
11159 the source operand will be copied to bits 0-31 of the destination.
11162 \S{insPSHUFHW} \i\c{PSHUFHW}: Shuffle Packed High Words
11164 \c PSHUFHW xmm1,xmm2/m128,imm8 ; F3 0F 70 /r ib [WILLAMETTE,SSE2]
11166 \c{PSHUFW} shuffles the words in the high quadword of the source
11167 (second) operand according to the encoding specified by imm8, and
11168 stores the result in the high quadword of the destination (first)
11171 The operation of this instruction is similar to the \c{PSHUFW}
11172 instruction, except that the source and destination are the top
11173 quadword of a 128-bit operand, instead of being 64-bit operands.
11174 The low quadword is copied from the source to the destination
11175 without any changes.
11178 \S{insPSHUFLW} \i\c{PSHUFLW}: Shuffle Packed Low Words
11180 \c PSHUFLW xmm1,xmm2/m128,imm8 ; F2 0F 70 /r ib [WILLAMETTE,SSE2]
11182 \c{PSHUFLW} shuffles the words in the low quadword of the source
11183 (second) operand according to the encoding specified by imm8, and
11184 stores the result in the low quadword of the destination (first)
11187 The operation of this instruction is similar to the \c{PSHUFW}
11188 instruction, except that the source and destination are the low
11189 quadword of a 128-bit operand, instead of being 64-bit operands.
11190 The high quadword is copied from the source to the destination
11191 without any changes.
11194 \S{insPSHUFW} \i\c{PSHUFW}: Shuffle Packed Words
11196 \c PSHUFW mm1,mm2/m64,imm8 ; 0F 70 /r ib [KATMAI,MMX]
11198 \c{PSHUFW} shuffles the words in the source (second) operand
11199 according to the encoding specified by imm8, and stores the result
11200 in the destination (first) operand.
11202 Bits 0 and 1 of imm8 encode the source position of the word to be
11203 copied to position 0 in the destination operand. Bits 2 and 3 encode
11204 for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7
11205 encode for position 3. For example, an encoding of 10 in bits 0 and 1
11206 of imm8 indicates that the word at bits 32-47 of the source operand
11207 will be copied to bits 0-15 of the destination.
11210 \S{insPSLLD} \i\c{PSLLx}: Packed Data Bit Shift Left Logical
11212 \c PSLLW mm1,mm2/m64 ; 0F F1 /r [PENT,MMX]
11213 \c PSLLW mm,imm8 ; 0F 71 /6 ib [PENT,MMX]
11215 \c PSLLW xmm1,xmm2/m128 ; 66 0F F1 /r [WILLAMETTE,SSE2]
11216 \c PSLLW xmm,imm8 ; 66 0F 71 /6 ib [WILLAMETTE,SSE2]
11218 \c PSLLD mm1,mm2/m64 ; 0F F2 /r [PENT,MMX]
11219 \c PSLLD mm,imm8 ; 0F 72 /6 ib [PENT,MMX]
11221 \c PSLLD xmm1,xmm2/m128 ; 66 0F F2 /r [WILLAMETTE,SSE2]
11222 \c PSLLD xmm,imm8 ; 66 0F 72 /6 ib [WILLAMETTE,SSE2]
11224 \c PSLLQ mm1,mm2/m64 ; 0F F3 /r [PENT,MMX]
11225 \c PSLLQ mm,imm8 ; 0F 73 /6 ib [PENT,MMX]
11227 \c PSLLQ xmm1,xmm2/m128 ; 66 0F F3 /r [WILLAMETTE,SSE2]
11228 \c PSLLQ xmm,imm8 ; 66 0F 73 /6 ib [WILLAMETTE,SSE2]
11230 \c PSLLDQ xmm1,imm8 ; 66 0F 73 /7 ib [PENT,MMX]
11232 \c{PSLLx} performs logical left shifts of the data elements in the
11233 destination (first) operand, moving each bit in the separate elements
11234 left by the number of bits specified in the source (second) operand,
11235 clearing the low-order bits as they are vacated.
11237 \b \c{PSLLW} shifts word sized elements.
11239 \b \c{PSLLD} shifts doubleword sized elements.
11241 \b \c{PSLLQ} shifts quadword sized elements.
11243 \b \c{PSLLDQ} shifts double quadword sized elements.
11246 \S{insPSRAD} \i\c{PSRAx}: Packed Data Bit Shift Right Arithmetic
11248 \c PSRAW mm1,mm2/m64 ; 0F E1 /r [PENT,MMX]
11249 \c PSRAW mm,imm8 ; 0F 71 /4 ib [PENT,MMX]
11251 \c PSRAW xmm1,xmm2/m128 ; 66 0F E1 /r [WILLAMETTE,SSE2]
11252 \c PSRAW xmm,imm8 ; 66 0F 71 /4 ib [WILLAMETTE,SSE2]
11254 \c PSRAD mm1,mm2/m64 ; 0F E2 /r [PENT,MMX]
11255 \c PSRAD mm,imm8 ; 0F 72 /4 ib [PENT,MMX]
11257 \c PSRAD xmm1,xmm2/m128 ; 66 0F E2 /r [WILLAMETTE,SSE2]
11258 \c PSRAD xmm,imm8 ; 66 0F 72 /4 ib [WILLAMETTE,SSE2]
11260 \c{PSRAx} performs arithmetic right shifts of the data elements in the
11261 destination (first) operand, moving each bit in the separate elements
11262 right by the number of bits specified in the source (second) operand,
11263 setting the high-order bits to the value of the original sign bit.
11265 \b \c{PSRAW} shifts word sized elements.
11267 \b \c{PSRAD} shifts doubleword sized elements.
11270 \S{insPSRLD} \i\c{PSRLx}: Packed Data Bit Shift Right Logical
11272 \c PSRLW mm1,mm2/m64 ; 0F D1 /r [PENT,MMX]
11273 \c PSRLW mm,imm8 ; 0F 71 /2 ib [PENT,MMX]
11275 \c PSRLW xmm1,xmm2/m128 ; 66 0F D1 /r [WILLAMETTE,SSE2]
11276 \c PSRLW xmm,imm8 ; 66 0F 71 /2 ib [WILLAMETTE,SSE2]
11278 \c PSRLD mm1,mm2/m64 ; 0F D2 /r [PENT,MMX]
11279 \c PSRLD mm,imm8 ; 0F 72 /2 ib [PENT,MMX]
11281 \c PSRLD xmm1,xmm2/m128 ; 66 0F D2 /r [WILLAMETTE,SSE2]
11282 \c PSRLD xmm,imm8 ; 66 0F 72 /2 ib [WILLAMETTE,SSE2]
11284 \c PSRLQ mm1,mm2/m64 ; 0F D3 /r [PENT,MMX]
11285 \c PSRLQ mm,imm8 ; 0F 73 /2 ib [PENT,MMX]
11287 \c PSRLQ xmm1,xmm2/m128 ; 66 0F D3 /r [WILLAMETTE,SSE2]
11288 \c PSRLQ xmm,imm8 ; 66 0F 73 /2 ib [WILLAMETTE,SSE2]
11290 \c PSRLDQ xmm1,imm8 ; 66 0F 73 /3 ib [WILLAMETTE,SSE2]
11292 \c{PSRLx} performs logical right shifts of the data elements in the
11293 destination (first) operand, moving each bit in the separate elements
11294 right by the number of bits specified in the source (second) operand,
11295 clearing the high-order bits as they are vacated.
11297 \b \c{PSRLW} shifts word sized elements.
11299 \b \c{PSRLD} shifts doubleword sized elements.
11301 \b \c{PSRLQ} shifts quadword sized elements.
11303 \b \c{PSRLDQ} shifts double quadword sized elements.
11306 \S{insPSUBB} \i\c{PSUBx}: Subtract Packed Integers
11308 \c PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX]
11309 \c PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX]
11310 \c PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX]
11311 \c PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2]
11313 \c PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2]
11314 \c PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2]
11315 \c PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2]
11316 \c PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2]
11318 \c{PSUBx} subtracts packed integers in the source operand from those
11319 in the destination operand. It doesn't differentiate between signed
11320 and unsigned integers, and doesn't set any of the flags.
11322 \b \c{PSUBB} operates on byte sized elements.
11324 \b \c{PSUBW} operates on word sized elements.
11326 \b \c{PSUBD} operates on doubleword sized elements.
11328 \b \c{PSUBQ} operates on quadword sized elements.
11331 \S{insPSUBSB} \i\c{PSUBSxx}, \i\c{PSUBUSx}: Subtract Packed Integers With Saturation
11333 \c PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX]
11334 \c PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX]
11336 \c PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2]
11337 \c PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2]
11339 \c PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX]
11340 \c PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX]
11342 \c PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2]
11343 \c PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2]
11345 \c{PSUBSx} and \c{PSUBUSx} subtracts packed integers in the source
11346 operand from those in the destination operand, and use saturation for
11347 results that are outside the range supported by the destination operand.
11349 \b \c{PSUBSB} operates on signed bytes, and uses signed saturation on the
11352 \b \c{PSUBSW} operates on signed words, and uses signed saturation on the
11355 \b \c{PSUBUSB} operates on unsigned bytes, and uses signed saturation on
11358 \b \c{PSUBUSW} operates on unsigned words, and uses signed saturation on
11362 \S{insPSUBSIW} \i\c{PSUBSIW}: MMX Packed Subtract with Saturation to
11363 Implied Destination
11365 \c PSUBSIW mm1,mm2/m64 ; 0F 55 /r [CYRIX,MMX]
11367 \c{PSUBSIW}, specific to the Cyrix extensions to the MMX instruction
11368 set, performs the same function as \c{PSUBSW}, except that the
11369 result is not placed in the register specified by the first operand,
11370 but instead in the implied destination register, specified as for
11371 \c{PADDSIW} (\k{insPADDSIW}).
11374 \S{insPSWAPD} \i\c{PSWAPD}: Swap Packed Data
11377 \c PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW]
11379 \c{PSWAPD} swaps the packed doublewords in the source operand, and
11380 stores the result in the destination operand.
11382 In the \c{K6-2} and \c{K6-III} processors, this opcode uses the
11383 mnemonic \c{PSWAPW}, and it swaps the order of words when copying
11384 from the source to the destination.
11386 The operation in the \c{K6-2} and \c{K6-III} processors is
11388 \c dst[0-15] = src[48-63];
11389 \c dst[16-31] = src[32-47];
11390 \c dst[32-47] = src[16-31];
11391 \c dst[48-63] = src[0-15].
11393 The operation in the \c{K6-x+}, \c{ATHLON} and later processors is:
11395 \c dst[0-31] = src[32-63];
11396 \c dst[32-63] = src[0-31].
11399 \S{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack and Interleave Data
11401 \c PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX]
11402 \c PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX]
11403 \c PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX]
11405 \c PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2]
11406 \c PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2]
11407 \c PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2]
11408 \c PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2]
11410 \c PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX]
11411 \c PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX]
11412 \c PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX]
11414 \c PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2]
11415 \c PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2]
11416 \c PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2]
11417 \c PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2]
11419 \c{PUNPCKxx} all treat their operands as vectors, and produce a new
11420 vector generated by interleaving elements from the two inputs. The
11421 \c{PUNPCKHxx} instructions start by throwing away the bottom half of
11422 each input operand, and the \c{PUNPCKLxx} instructions throw away
11425 The remaining elements, are then interleaved into the destination,
11426 alternating elements from the second (source) operand and the first
11427 (destination) operand: so the leftmost part of each element in the
11428 result always comes from the second operand, and the rightmost from
11431 \b \c{PUNPCKxBW} works a byte at a time, producing word sized output
11434 \b \c{PUNPCKxWD} works a word at a time, producing doubleword sized
11437 \b \c{PUNPCKxDQ} works a doubleword at a time, producing quadword sized
11440 \b \c{PUNPCKxQDQ} works a quadword at a time, producing double quadword
11441 sized output elements.
11443 So, for example, for \c{MMX} operands, if the first operand held
11444 \c{0x7A6A5A4A3A2A1A0A} and the second held \c{0x7B6B5B4B3B2B1B0B},
11447 \b \c{PUNPCKHBW} would return \c{0x7B7A6B6A5B5A4B4A}.
11449 \b \c{PUNPCKHWD} would return \c{0x7B6B7A6A5B4B5A4A}.
11451 \b \c{PUNPCKHDQ} would return \c{0x7B6B5B4B7A6A5A4A}.
11453 \b \c{PUNPCKLBW} would return \c{0x3B3A2B2A1B1A0B0A}.
11455 \b \c{PUNPCKLWD} would return \c{0x3B2B3A2A1B0B1A0A}.
11457 \b \c{PUNPCKLDQ} would return \c{0x3B2B1B0B3A2A1A0A}.
11460 \S{insPUSH} \i\c{PUSH}: Push Data on Stack
11462 \c PUSH reg16 ; o16 50+r [8086]
11463 \c PUSH reg32 ; o32 50+r [386]
11465 \c PUSH r/m16 ; o16 FF /6 [8086]
11466 \c PUSH r/m32 ; o32 FF /6 [386]
11468 \c PUSH CS ; 0E [8086]
11469 \c PUSH DS ; 1E [8086]
11470 \c PUSH ES ; 06 [8086]
11471 \c PUSH SS ; 16 [8086]
11472 \c PUSH FS ; 0F A0 [386]
11473 \c PUSH GS ; 0F A8 [386]
11475 \c PUSH imm8 ; 6A ib [286]
11476 \c PUSH imm16 ; o16 68 iw [286]
11477 \c PUSH imm32 ; o32 68 id [386]
11479 \c{PUSH} decrements the stack pointer (\c{SP} or \c{ESP}) by 2 or 4,
11480 and then stores the given value at \c{[SS:SP]} or \c{[SS:ESP]}.
11482 The address-size attribute of the instruction determines whether
11483 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11484 override the default given by the \c{BITS} setting, you can use an
11485 \i\c{a16} or \i\c{a32} prefix.
11487 The operand-size attribute of the instruction determines whether the
11488 stack pointer is decremented by 2 or 4: this means that segment
11489 register pushes in \c{BITS 32} mode will push 4 bytes on the stack,
11490 of which the upper two are undefined. If you need to override that,
11491 you can use an \i\c{o16} or \i\c{o32} prefix.
11493 The above opcode listings give two forms for general-purpose
11494 \i{register push} instructions: for example, \c{PUSH BX} has the two
11495 forms \c{53} and \c{FF F3}. NASM will always generate the shorter
11496 form when given \c{PUSH BX}. NDISASM will disassemble both.
11498 Unlike the undocumented and barely supported \c{POP CS}, \c{PUSH CS}
11499 is a perfectly valid and sensible instruction, supported on all
11502 The instruction \c{PUSH SP} may be used to distinguish an 8086 from
11503 later processors: on an 8086, the value of \c{SP} stored is the
11504 value it has \e{after} the push instruction, whereas on later
11505 processors it is the value \e{before} the push instruction.
11508 \S{insPUSHA} \i\c{PUSHAx}: Push All General-Purpose Registers
11510 \c PUSHA ; 60 [186]
11511 \c PUSHAD ; o32 60 [386]
11512 \c PUSHAW ; o16 60 [186]
11514 \c{PUSHAW} pushes, in succession, \c{AX}, \c{CX}, \c{DX}, \c{BX},
11515 \c{SP}, \c{BP}, \c{SI} and \c{DI} on the stack, decrementing the
11516 stack pointer by a total of 16.
11518 \c{PUSHAD} pushes, in succession, \c{EAX}, \c{ECX}, \c{EDX},
11519 \c{EBX}, \c{ESP}, \c{EBP}, \c{ESI} and \c{EDI} on the stack,
11520 decrementing the stack pointer by a total of 32.
11522 In both cases, the value of \c{SP} or \c{ESP} pushed is its
11523 \e{original} value, as it had before the instruction was executed.
11525 \c{PUSHA} is an alias mnemonic for either \c{PUSHAW} or \c{PUSHAD},
11526 depending on the current \c{BITS} setting.
11528 Note that the registers are pushed in order of their numeric values
11529 in opcodes (see \k{iref-rv}).
11531 See also \c{POPA} (\k{insPOPA}).
11534 \S{insPUSHF} \i\c{PUSHFx}: Push Flags Register
11536 \c PUSHF ; 9C [8086]
11537 \c PUSHFD ; o32 9C [386]
11538 \c PUSHFW ; o16 9C [8086]
11540 \b \c{PUSHFW} pops a word from the stack and stores it in the
11541 bottom 16 bits of the flags register (or the whole flags register,
11542 on processors below a 386).
11544 \b \c{PUSHFD} pops a doubleword and stores it in the entire flags
11547 \c{PUSHF} is an alias mnemonic for either \c{PUSHFW} or \c{PUSHFD},
11548 depending on the current \c{BITS} setting.
11550 See also \c{POPF} (\k{insPOPF}).
11553 \S{insPXOR} \i\c{PXOR}: MMX Bitwise XOR
11555 \c PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX]
11556 \c PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2]
11558 \c{PXOR} performs a bitwise XOR operation between its two operands
11559 (i.e. each bit of the result is 1 if and only if exactly one of the
11560 corresponding bits of the two inputs was 1), and stores the result
11561 in the destination (first) operand.
11564 \S{insRCL} \i\c{RCL}, \i\c{RCR}: Bitwise Rotate through Carry Bit
11566 \c RCL r/m8,1 ; D0 /2 [8086]
11567 \c RCL r/m8,CL ; D2 /2 [8086]
11568 \c RCL r/m8,imm8 ; C0 /2 ib [286]
11569 \c RCL r/m16,1 ; o16 D1 /2 [8086]
11570 \c RCL r/m16,CL ; o16 D3 /2 [8086]
11571 \c RCL r/m16,imm8 ; o16 C1 /2 ib [286]
11572 \c RCL r/m32,1 ; o32 D1 /2 [386]
11573 \c RCL r/m32,CL ; o32 D3 /2 [386]
11574 \c RCL r/m32,imm8 ; o32 C1 /2 ib [386]
11576 \c RCR r/m8,1 ; D0 /3 [8086]
11577 \c RCR r/m8,CL ; D2 /3 [8086]
11578 \c RCR r/m8,imm8 ; C0 /3 ib [286]
11579 \c RCR r/m16,1 ; o16 D1 /3 [8086]
11580 \c RCR r/m16,CL ; o16 D3 /3 [8086]
11581 \c RCR r/m16,imm8 ; o16 C1 /3 ib [286]
11582 \c RCR r/m32,1 ; o32 D1 /3 [386]
11583 \c RCR r/m32,CL ; o32 D3 /3 [386]
11584 \c RCR r/m32,imm8 ; o32 C1 /3 ib [386]
11586 \c{RCL} and \c{RCR} perform a 9-bit, 17-bit or 33-bit bitwise
11587 rotation operation, involving the given source/destination (first)
11588 operand and the carry bit. Thus, for example, in the operation
11589 \c{RCL AL,1}, a 9-bit rotation is performed in which \c{AL} is
11590 shifted left by 1, the top bit of \c{AL} moves into the carry flag,
11591 and the original value of the carry flag is placed in the low bit of
11594 The number of bits to rotate by is given by the second operand. Only
11595 the bottom five bits of the rotation count are considered by
11596 processors above the 8086.
11598 You can force the longer (286 and upwards, beginning with a \c{C1}
11599 byte) form of \c{RCL foo,1} by using a \c{BYTE} prefix: \c{RCL
11600 foo,BYTE 1}. Similarly with \c{RCR}.
11603 \S{insRCPPS} \i\c{RCPPS}: Packed Single-Precision FP Reciprocal
11605 \c RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE]
11607 \c{RCPPS} returns an approximation of the reciprocal of the packed
11608 single-precision FP values from xmm2/m128. The maximum error for this
11609 approximation is: |Error| <= 1.5 x 2^-12
11612 \S{insRCPSS} \i\c{RCPSS}: Scalar Single-Precision FP Reciprocal
11614 \c RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE]
11616 \c{RCPSS} returns an approximation of the reciprocal of the lower
11617 single-precision FP value from xmm2/m32; the upper three fields are
11618 passed through from xmm1. The maximum error for this approximation is:
11619 |Error| <= 1.5 x 2^-12
11622 \S{insRDMSR} \i\c{RDMSR}: Read Model-Specific Registers
11624 \c RDMSR ; 0F 32 [PENT,PRIV]
11626 \c{RDMSR} reads the processor Model-Specific Register (MSR) whose
11627 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11628 See also \c{WRMSR} (\k{insWRMSR}).
11631 \S{insRDPMC} \i\c{RDPMC}: Read Performance-Monitoring Counters
11633 \c RDPMC ; 0F 33 [P6]
11635 \c{RDPMC} reads the processor performance-monitoring counter whose
11636 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11638 This instruction is available on P6 and later processors and on MMX
11642 \S{insRDSHR} \i\c{RDSHR}: Read SMM Header Pointer Register
11644 \c RDSHR r/m32 ; 0F 36 /0 [386,CYRIX,SMM]
11646 \c{RDSHR} reads the contents of the SMM header pointer register and
11647 saves it to the destination operand, which can be either a 32 bit
11648 memory location or a 32 bit register.
11650 See also \c{WRSHR} (\k{insWRSHR}).
11653 \S{insRDTSC} \i\c{RDTSC}: Read Time-Stamp Counter
11655 \c RDTSC ; 0F 31 [PENT]
11657 \c{RDTSC} reads the processor's time-stamp counter into \c{EDX:EAX}.
11660 \S{insRET} \i\c{RET}, \i\c{RETF}, \i\c{RETN}: Return from Procedure Call
11663 \c RET imm16 ; C2 iw [8086]
11665 \c RETF ; CB [8086]
11666 \c RETF imm16 ; CA iw [8086]
11668 \c RETN ; C3 [8086]
11669 \c RETN imm16 ; C2 iw [8086]
11671 \b \c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from
11672 the stack and transfer control to the new address. Optionally, if a
11673 numeric second operand is provided, they increment the stack pointer
11674 by a further \c{imm16} bytes after popping the return address.
11676 \b \c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it
11677 then pops \c{CS}, and \e{then} increments the stack pointer by the
11678 optional argument if present.
11681 \S{insROL} \i\c{ROL}, \i\c{ROR}: Bitwise Rotate
11683 \c ROL r/m8,1 ; D0 /0 [8086]
11684 \c ROL r/m8,CL ; D2 /0 [8086]
11685 \c ROL r/m8,imm8 ; C0 /0 ib [286]
11686 \c ROL r/m16,1 ; o16 D1 /0 [8086]
11687 \c ROL r/m16,CL ; o16 D3 /0 [8086]
11688 \c ROL r/m16,imm8 ; o16 C1 /0 ib [286]
11689 \c ROL r/m32,1 ; o32 D1 /0 [386]
11690 \c ROL r/m32,CL ; o32 D3 /0 [386]
11691 \c ROL r/m32,imm8 ; o32 C1 /0 ib [386]
11693 \c ROR r/m8,1 ; D0 /1 [8086]
11694 \c ROR r/m8,CL ; D2 /1 [8086]
11695 \c ROR r/m8,imm8 ; C0 /1 ib [286]
11696 \c ROR r/m16,1 ; o16 D1 /1 [8086]
11697 \c ROR r/m16,CL ; o16 D3 /1 [8086]
11698 \c ROR r/m16,imm8 ; o16 C1 /1 ib [286]
11699 \c ROR r/m32,1 ; o32 D1 /1 [386]
11700 \c ROR r/m32,CL ; o32 D3 /1 [386]
11701 \c ROR r/m32,imm8 ; o32 C1 /1 ib [386]
11703 \c{ROL} and \c{ROR} perform a bitwise rotation operation on the given
11704 source/destination (first) operand. Thus, for example, in the
11705 operation \c{ROL AL,1}, an 8-bit rotation is performed in which
11706 \c{AL} is shifted left by 1 and the original top bit of \c{AL} moves
11707 round into the low bit.
11709 The number of bits to rotate by is given by the second operand. Only
11710 the bottom five bits of the rotation count are considered by processors
11713 You can force the longer (286 and upwards, beginning with a \c{C1}
11714 byte) form of \c{ROL foo,1} by using a \c{BYTE} prefix: \c{ROL
11715 foo,BYTE 1}. Similarly with \c{ROR}.
11718 \S{insRSDC} \i\c{RSDC}: Restore Segment Register and Descriptor
11720 \c RSDC segreg,m80 ; 0F 79 /r [486,CYRIX,SMM]
11722 \c{RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80,
11723 and sets up its descriptor.
11726 \S{insRSLDT} \i\c{RSLDT}: Restore Segment Register and Descriptor
11728 \c RSLDT m80 ; 0F 7B /0 [486,CYRIX,SMM]
11730 \c{RSLDT} restores the Local Descriptor Table (LDTR) from mem80.
11733 \S{insRSM} \i\c{RSM}: Resume from System-Management Mode
11735 \c RSM ; 0F AA [PENT]
11737 \c{RSM} returns the processor to its normal operating mode when it
11738 was in System-Management Mode.
11741 \S{insRSQRTPS} \i\c{RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal
11743 \c RSQRTPS xmm1,xmm2/m128 ; 0F 52 /r [KATMAI,SSE]
11745 \c{RSQRTPS} computes the approximate reciprocals of the square
11746 roots of the packed single-precision floating-point values in the
11747 source and stores the results in xmm1. The maximum error for this
11748 approximation is: |Error| <= 1.5 x 2^-12
11751 \S{insRSQRTSS} \i\c{RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal
11753 \c RSQRTSS xmm1,xmm2/m128 ; F3 0F 52 /r [KATMAI,SSE]
11755 \c{RSQRTSS} returns an approximation of the reciprocal of the
11756 square root of the lowest order single-precision FP value from
11757 the source, and stores it in the low doubleword of the destination
11758 register. The upper three fields of xmm1 are preserved. The maximum
11759 error for this approximation is: |Error| <= 1.5 x 2^-12
11762 \S{insRSTS} \i\c{RSTS}: Restore TSR and Descriptor
11764 \c RSTS m80 ; 0F 7D /0 [486,CYRIX,SMM]
11766 \c{RSTS} restores Task State Register (TSR) from mem80.
11769 \S{insSAHF} \i\c{SAHF}: Store AH to Flags
11771 \c SAHF ; 9E [8086]
11773 \c{SAHF} sets the low byte of the flags word according to the
11774 contents of the \c{AH} register.
11776 The operation of \c{SAHF} is:
11778 \c AH --> SF:ZF:0:AF:0:PF:1:CF
11780 See also \c{LAHF} (\k{insLAHF}).
11783 \S{insSAL} \i\c{SAL}, \i\c{SAR}: Bitwise Arithmetic Shifts
11785 \c SAL r/m8,1 ; D0 /4 [8086]
11786 \c SAL r/m8,CL ; D2 /4 [8086]
11787 \c SAL r/m8,imm8 ; C0 /4 ib [286]
11788 \c SAL r/m16,1 ; o16 D1 /4 [8086]
11789 \c SAL r/m16,CL ; o16 D3 /4 [8086]
11790 \c SAL r/m16,imm8 ; o16 C1 /4 ib [286]
11791 \c SAL r/m32,1 ; o32 D1 /4 [386]
11792 \c SAL r/m32,CL ; o32 D3 /4 [386]
11793 \c SAL r/m32,imm8 ; o32 C1 /4 ib [386]
11795 \c SAR r/m8,1 ; D0 /7 [8086]
11796 \c SAR r/m8,CL ; D2 /7 [8086]
11797 \c SAR r/m8,imm8 ; C0 /7 ib [286]
11798 \c SAR r/m16,1 ; o16 D1 /7 [8086]
11799 \c SAR r/m16,CL ; o16 D3 /7 [8086]
11800 \c SAR r/m16,imm8 ; o16 C1 /7 ib [286]
11801 \c SAR r/m32,1 ; o32 D1 /7 [386]
11802 \c SAR r/m32,CL ; o32 D3 /7 [386]
11803 \c SAR r/m32,imm8 ; o32 C1 /7 ib [386]
11805 \c{SAL} and \c{SAR} perform an arithmetic shift operation on the given
11806 source/destination (first) operand. The vacated bits are filled with
11807 zero for \c{SAL}, and with copies of the original high bit of the
11808 source operand for \c{SAR}.
11810 \c{SAL} is a synonym for \c{SHL} (see \k{insSHL}). NASM will
11811 assemble either one to the same code, but NDISASM will always
11812 disassemble that code as \c{SHL}.
11814 The number of bits to shift by is given by the second operand. Only
11815 the bottom five bits of the shift count are considered by processors
11818 You can force the longer (286 and upwards, beginning with a \c{C1}
11819 byte) form of \c{SAL foo,1} by using a \c{BYTE} prefix: \c{SAL
11820 foo,BYTE 1}. Similarly with \c{SAR}.
11823 \S{insSALC} \i\c{SALC}: Set AL from Carry Flag
11825 \c SALC ; D6 [8086,UNDOC]
11827 \c{SALC} is an early undocumented instruction similar in concept to
11828 \c{SETcc} (\k{insSETcc}). Its function is to set \c{AL} to zero if
11829 the carry flag is clear, or to \c{0xFF} if it is set.
11832 \S{insSBB} \i\c{SBB}: Subtract with Borrow
11834 \c SBB r/m8,reg8 ; 18 /r [8086]
11835 \c SBB r/m16,reg16 ; o16 19 /r [8086]
11836 \c SBB r/m32,reg32 ; o32 19 /r [386]
11838 \c SBB reg8,r/m8 ; 1A /r [8086]
11839 \c SBB reg16,r/m16 ; o16 1B /r [8086]
11840 \c SBB reg32,r/m32 ; o32 1B /r [386]
11842 \c SBB r/m8,imm8 ; 80 /3 ib [8086]
11843 \c SBB r/m16,imm16 ; o16 81 /3 iw [8086]
11844 \c SBB r/m32,imm32 ; o32 81 /3 id [386]
11846 \c SBB r/m16,imm8 ; o16 83 /3 ib [8086]
11847 \c SBB r/m32,imm8 ; o32 83 /3 ib [386]
11849 \c SBB AL,imm8 ; 1C ib [8086]
11850 \c SBB AX,imm16 ; o16 1D iw [8086]
11851 \c SBB EAX,imm32 ; o32 1D id [386]
11853 \c{SBB} performs integer subtraction: it subtracts its second
11854 operand, plus the value of the carry flag, from its first, and
11855 leaves the result in its destination (first) operand. The flags are
11856 set according to the result of the operation: in particular, the
11857 carry flag is affected and can be used by a subsequent \c{SBB}
11860 In the forms with an 8-bit immediate second operand and a longer
11861 first operand, the second operand is considered to be signed, and is
11862 sign-extended to the length of the first operand. In these cases,
11863 the \c{BYTE} qualifier is necessary to force NASM to generate this
11864 form of the instruction.
11866 To subtract one number from another without also subtracting the
11867 contents of the carry flag, use \c{SUB} (\k{insSUB}).
11870 \S{insSCASB} \i\c{SCASB}, \i\c{SCASW}, \i\c{SCASD}: Scan String
11872 \c SCASB ; AE [8086]
11873 \c SCASW ; o16 AF [8086]
11874 \c SCASD ; o32 AF [386]
11876 \c{SCASB} compares the byte in \c{AL} with the byte at \c{[ES:DI]}
11877 or \c{[ES:EDI]}, and sets the flags accordingly. It then increments
11878 or decrements (depending on the direction flag: increments if the
11879 flag is clear, decrements if it is set) \c{DI} (or \c{EDI}).
11881 The register used is \c{DI} if the address size is 16 bits, and
11882 \c{EDI} if it is 32 bits. If you need to use an address size not
11883 equal to the current \c{BITS} setting, you can use an explicit
11884 \i\c{a16} or \i\c{a32} prefix.
11886 Segment override prefixes have no effect for this instruction: the
11887 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
11890 \c{SCASW} and \c{SCASD} work in the same way, but they compare a
11891 word to \c{AX} or a doubleword to \c{EAX} instead of a byte to
11892 \c{AL}, and increment or decrement the addressing registers by 2 or
11895 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
11896 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
11897 \c{ECX} - again, the address size chooses which) times until the
11898 first unequal or equal byte is found.
11901 \S{insSETcc} \i\c{SETcc}: Set Register from Condition
11903 \c SETcc r/m8 ; 0F 90+cc /2 [386]
11905 \c{SETcc} sets the given 8-bit operand to zero if its condition is
11906 not satisfied, and to 1 if it is.
11909 \S{insSFENCE} \i\c{SFENCE}: Store Fence
11911 \c SFENCE ; 0F AE /7 [KATMAI]
11913 \c{SFENCE} performs a serialising operation on all writes to memory
11914 that were issued before the \c{SFENCE} instruction. This guarantees that
11915 all memory writes before the \c{SFENCE} instruction are visible before any
11916 writes after the \c{SFENCE} instruction.
11918 \c{SFENCE} is ordered respective to other \c{SFENCE} instruction, \c{MFENCE},
11919 any memory write and any other serialising instruction (such as \c{CPUID}).
11921 Weakly ordered memory types can be used to achieve higher processor
11922 performance through such techniques as out-of-order issue,
11923 write-combining, and write-collapsing. The degree to which a consumer
11924 of data recognizes or knows that the data is weakly ordered varies
11925 among applications and may be unknown to the producer of this data.
11926 The \c{SFENCE} instruction provides a performance-efficient way of
11927 insuring store ordering between routines that produce weakly-ordered
11928 results and routines that consume this data.
11930 \c{SFENCE} uses the following ModRM encoding:
11933 \c Reg/Opcode (5:3) = 111B
11934 \c R/M (2:0) = 000B
11936 All other ModRM encodings are defined to be reserved, and use
11937 of these encodings risks incompatibility with future processors.
11939 See also \c{LFENCE} (\k{insLFENCE}) and \c{MFENCE} (\k{insMFENCE}).
11942 \S{insSGDT} \i\c{SGDT}, \i\c{SIDT}, \i\c{SLDT}: Store Descriptor Table Pointers
11944 \c SGDT mem ; 0F 01 /0 [286,PRIV]
11945 \c SIDT mem ; 0F 01 /1 [286,PRIV]
11946 \c SLDT r/m16 ; 0F 00 /0 [286,PRIV]
11948 \c{SGDT} and \c{SIDT} both take a 6-byte memory area as an operand:
11949 they store the contents of the GDTR (global descriptor table
11950 register) or IDTR (interrupt descriptor table register) into that
11951 area as a 32-bit linear address and a 16-bit size limit from that
11952 area (in that order). These are the only instructions which directly
11953 use \e{linear} addresses, rather than segment/offset pairs.
11955 \c{SLDT} stores the segment selector corresponding to the LDT (local
11956 descriptor table) into the given operand.
11958 See also \c{LGDT}, \c{LIDT} and \c{LLDT} (\k{insLGDT}).
11961 \S{insSHL} \i\c{SHL}, \i\c{SHR}: Bitwise Logical Shifts
11963 \c SHL r/m8,1 ; D0 /4 [8086]
11964 \c SHL r/m8,CL ; D2 /4 [8086]
11965 \c SHL r/m8,imm8 ; C0 /4 ib [286]
11966 \c SHL r/m16,1 ; o16 D1 /4 [8086]
11967 \c SHL r/m16,CL ; o16 D3 /4 [8086]
11968 \c SHL r/m16,imm8 ; o16 C1 /4 ib [286]
11969 \c SHL r/m32,1 ; o32 D1 /4 [386]
11970 \c SHL r/m32,CL ; o32 D3 /4 [386]
11971 \c SHL r/m32,imm8 ; o32 C1 /4 ib [386]
11973 \c SHR r/m8,1 ; D0 /5 [8086]
11974 \c SHR r/m8,CL ; D2 /5 [8086]
11975 \c SHR r/m8,imm8 ; C0 /5 ib [286]
11976 \c SHR r/m16,1 ; o16 D1 /5 [8086]
11977 \c SHR r/m16,CL ; o16 D3 /5 [8086]
11978 \c SHR r/m16,imm8 ; o16 C1 /5 ib [286]
11979 \c SHR r/m32,1 ; o32 D1 /5 [386]
11980 \c SHR r/m32,CL ; o32 D3 /5 [386]
11981 \c SHR r/m32,imm8 ; o32 C1 /5 ib [386]
11983 \c{SHL} and \c{SHR} perform a logical shift operation on the given
11984 source/destination (first) operand. The vacated bits are filled with
11987 A synonym for \c{SHL} is \c{SAL} (see \k{insSAL}). NASM will
11988 assemble either one to the same code, but NDISASM will always
11989 disassemble that code as \c{SHL}.
11991 The number of bits to shift by is given by the second operand. Only
11992 the bottom five bits of the shift count are considered by processors
11995 You can force the longer (286 and upwards, beginning with a \c{C1}
11996 byte) form of \c{SHL foo,1} by using a \c{BYTE} prefix: \c{SHL
11997 foo,BYTE 1}. Similarly with \c{SHR}.
12000 \S{insSHLD} \i\c{SHLD}, \i\c{SHRD}: Bitwise Double-Precision Shifts
12002 \c SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386]
12003 \c SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386]
12004 \c SHLD r/m16,reg16,CL ; o16 0F A5 /r [386]
12005 \c SHLD r/m16,reg32,CL ; o32 0F A5 /r [386]
12007 \c SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386]
12008 \c SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386]
12009 \c SHRD r/m16,reg16,CL ; o16 0F AD /r [386]
12010 \c SHRD r/m32,reg32,CL ; o32 0F AD /r [386]
12012 \b \c{SHLD} performs a double-precision left shift. It notionally
12013 places its second operand to the right of its first, then shifts
12014 the entire bit string thus generated to the left by a number of
12015 bits specified in the third operand. It then updates only the
12016 \e{first} operand according to the result of this. The second
12017 operand is not modified.
12019 \b \c{SHRD} performs the corresponding right shift: it notionally
12020 places the second operand to the \e{left} of the first, shifts the
12021 whole bit string right, and updates only the first operand.
12023 For example, if \c{EAX} holds \c{0x01234567} and \c{EBX} holds
12024 \c{0x89ABCDEF}, then the instruction \c{SHLD EAX,EBX,4} would update
12025 \c{EAX} to hold \c{0x12345678}. Under the same conditions, \c{SHRD
12026 EAX,EBX,4} would update \c{EAX} to hold \c{0xF0123456}.
12028 The number of bits to shift by is given by the third operand. Only
12029 the bottom five bits of the shift count are considered.
12032 \S{insSHUFPD} \i\c{SHUFPD}: Shuffle Packed Double-Precision FP Values
12034 \c SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2]
12036 \c{SHUFPD} moves one of the packed double-precision FP values from
12037 the destination operand into the low quadword of the destination
12038 operand; the upper quadword is generated by moving one of the
12039 double-precision FP values from the source operand into the
12040 destination. The select (third) operand selects which of the values
12041 are moved to the destination register.
12043 The select operand is an 8-bit immediate: bit 0 selects which value
12044 is moved from the destination operand to the result (where 0 selects
12045 the low quadword and 1 selects the high quadword) and bit 1 selects
12046 which value is moved from the source operand to the result.
12047 Bits 2 through 7 of the shuffle operand are reserved.
12050 \S{insSHUFPS} \i\c{SHUFPS}: Shuffle Packed Single-Precision FP Values
12052 \c SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE]
12054 \c{SHUFPS} moves two of the packed single-precision FP values from
12055 the destination operand into the low quadword of the destination
12056 operand; the upper quadword is generated by moving two of the
12057 single-precision FP values from the source operand into the
12058 destination. The select (third) operand selects which of the
12059 values are moved to the destination register.
12061 The select operand is an 8-bit immediate: bits 0 and 1 select the
12062 value to be moved from the destination operand the low doubleword of
12063 the result, bits 2 and 3 select the value to be moved from the
12064 destination operand the second doubleword of the result, bits 4 and
12065 5 select the value to be moved from the source operand the third
12066 doubleword of the result, and bits 6 and 7 select the value to be
12067 moved from the source operand to the high doubleword of the result.
12070 \S{insSMI} \i\c{SMI}: System Management Interrupt
12072 \c SMI ; F1 [386,UNDOC]
12074 \c{SMI} puts some AMD processors into SMM mode. It is available on some
12075 386 and 486 processors, and is only available when DR7 bit 12 is set,
12076 otherwise it generates an Int 1.
12079 \S{insSMINT} \i\c{SMINT}, \i\c{SMINTOLD}: Software SMM Entry (CYRIX)
12081 \c SMINT ; 0F 38 [PENT,CYRIX]
12082 \c SMINTOLD ; 0F 7E [486,CYRIX]
12084 \c{SMINT} puts the processor into SMM mode. The CPU state information is
12085 saved in the SMM memory header, and then execution begins at the SMM base
12088 \c{SMINTOLD} is the same as \c{SMINT}, but was the opcode used on the 486.
12090 This pair of opcodes are specific to the Cyrix and compatible range of
12091 processors (Cyrix, IBM, Via).
12094 \S{insSMSW} \i\c{SMSW}: Store Machine Status Word
12096 \c SMSW r/m16 ; 0F 01 /4 [286,PRIV]
12098 \c{SMSW} stores the bottom half of the \c{CR0} control register (or
12099 the Machine Status Word, on 286 processors) into the destination
12100 operand. See also \c{LMSW} (\k{insLMSW}).
12102 For 32-bit code, this would use the low 16-bits of the specified
12103 register (or a 16bit memory location), without needing an operand
12104 size override byte.
12107 \S{insSQRTPD} \i\c{SQRTPD}: Packed Double-Precision FP Square Root
12109 \c SQRTPD xmm1,xmm2/m128 ; 66 0F 51 /r [WILLAMETTE,SSE2]
12111 \c{SQRTPD} calculates the square root of the packed double-precision
12112 FP value from the source operand, and stores the double-precision
12113 results in the destination register.
12116 \S{insSQRTPS} \i\c{SQRTPS}: Packed Single-Precision FP Square Root
12118 \c SQRTPS xmm1,xmm2/m128 ; 0F 51 /r [KATMAI,SSE]
12120 \c{SQRTPS} calculates the square root of the packed single-precision
12121 FP value from the source operand, and stores the single-precision
12122 results in the destination register.
12125 \S{insSQRTSD} \i\c{SQRTSD}: Scalar Double-Precision FP Square Root
12127 \c SQRTSD xmm1,xmm2/m128 ; F2 0F 51 /r [WILLAMETTE,SSE2]
12129 \c{SQRTSD} calculates the square root of the low-order double-precision
12130 FP value from the source operand, and stores the double-precision
12131 result in the destination register. The high-quadword remains unchanged.
12134 \S{insSQRTSS} \i\c{SQRTSS}: Scalar Single-Precision FP Square Root
12136 \c SQRTSS xmm1,xmm2/m128 ; F3 0F 51 /r [KATMAI,SSE]
12138 \c{SQRTSS} calculates the square root of the low-order single-precision
12139 FP value from the source operand, and stores the single-precision
12140 result in the destination register. The three high doublewords remain
12144 \S{insSTC} \i\c{STC}, \i\c{STD}, \i\c{STI}: Set Flags
12150 These instructions set various flags. \c{STC} sets the carry flag;
12151 \c{STD} sets the direction flag; and \c{STI} sets the interrupt flag
12152 (thus enabling interrupts).
12154 To clear the carry, direction, or interrupt flags, use the \c{CLC},
12155 \c{CLD} and \c{CLI} instructions (\k{insCLC}). To invert the carry
12156 flag, use \c{CMC} (\k{insCMC}).
12159 \S{insSTMXCSR} \i\c{STMXCSR}: Store Streaming SIMD Extension
12162 \c STMXCSR m32 ; 0F AE /3 [KATMAI,SSE]
12164 \c{STMXCSR} stores the contents of the \c{MXCSR} control/status
12165 register to the specified memory location. \c{MXCSR} is used to
12166 enable masked/unmasked exception handling, to set rounding modes,
12167 to set flush-to-zero mode, and to view exception status flags.
12168 The reserved bits in the \c{MXCSR} register are stored as 0s.
12170 For details of the \c{MXCSR} register, see the Intel processor docs.
12172 See also \c{LDMXCSR} (\k{insLDMXCSR}).
12175 \S{insSTOSB} \i\c{STOSB}, \i\c{STOSW}, \i\c{STOSD}: Store Byte to String
12177 \c STOSB ; AA [8086]
12178 \c STOSW ; o16 AB [8086]
12179 \c STOSD ; o32 AB [386]
12181 \c{STOSB} stores the byte in \c{AL} at \c{[ES:DI]} or \c{[ES:EDI]},
12182 and sets the flags accordingly. It then increments or decrements
12183 (depending on the direction flag: increments if the flag is clear,
12184 decrements if it is set) \c{DI} (or \c{EDI}).
12186 The register used is \c{DI} if the address size is 16 bits, and
12187 \c{EDI} if it is 32 bits. If you need to use an address size not
12188 equal to the current \c{BITS} setting, you can use an explicit
12189 \i\c{a16} or \i\c{a32} prefix.
12191 Segment override prefixes have no effect for this instruction: the
12192 use of \c{ES} for the store to \c{[DI]} or \c{[EDI]} cannot be
12195 \c{STOSW} and \c{STOSD} work in the same way, but they store the
12196 word in \c{AX} or the doubleword in \c{EAX} instead of the byte in
12197 \c{AL}, and increment or decrement the addressing registers by 2 or
12200 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
12201 \c{ECX} - again, the address size chooses which) times.
12204 \S{insSTR} \i\c{STR}: Store Task Register
12206 \c STR r/m16 ; 0F 00 /1 [286,PRIV]
12208 \c{STR} stores the segment selector corresponding to the contents of
12209 the Task Register into its operand. When the operand size is a 16-bit
12210 register, the upper 16-bits are cleared to 0s. When the destination
12211 operand is a memory location, 16 bits are written regardless of the
12215 \S{insSUB} \i\c{SUB}: Subtract Integers
12217 \c SUB r/m8,reg8 ; 28 /r [8086]
12218 \c SUB r/m16,reg16 ; o16 29 /r [8086]
12219 \c SUB r/m32,reg32 ; o32 29 /r [386]
12221 \c SUB reg8,r/m8 ; 2A /r [8086]
12222 \c SUB reg16,r/m16 ; o16 2B /r [8086]
12223 \c SUB reg32,r/m32 ; o32 2B /r [386]
12225 \c SUB r/m8,imm8 ; 80 /5 ib [8086]
12226 \c SUB r/m16,imm16 ; o16 81 /5 iw [8086]
12227 \c SUB r/m32,imm32 ; o32 81 /5 id [386]
12229 \c SUB r/m16,imm8 ; o16 83 /5 ib [8086]
12230 \c SUB r/m32,imm8 ; o32 83 /5 ib [386]
12232 \c SUB AL,imm8 ; 2C ib [8086]
12233 \c SUB AX,imm16 ; o16 2D iw [8086]
12234 \c SUB EAX,imm32 ; o32 2D id [386]
12236 \c{SUB} performs integer subtraction: it subtracts its second
12237 operand from its first, and leaves the result in its destination
12238 (first) operand. The flags are set according to the result of the
12239 operation: in particular, the carry flag is affected and can be used
12240 by a subsequent \c{SBB} instruction (\k{insSBB}).
12242 In the forms with an 8-bit immediate second operand and a longer
12243 first operand, the second operand is considered to be signed, and is
12244 sign-extended to the length of the first operand. In these cases,
12245 the \c{BYTE} qualifier is necessary to force NASM to generate this
12246 form of the instruction.
12249 \S{insSUBPD} \i\c{SUBPD}: Packed Double-Precision FP Subtract
12251 \c SUBPD xmm1,xmm2/m128 ; 66 0F 5C /r [WILLAMETTE,SSE2]
12253 \c{SUBPD} subtracts the packed double-precision FP values of
12254 the source operand from those of the destination operand, and
12255 stores the result in the destination operation.
12258 \S{insSUBPS} \i\c{SUBPS}: Packed Single-Precision FP Subtract
12260 \c SUBPS xmm1,xmm2/m128 ; 0F 5C /r [KATMAI,SSE]
12262 \c{SUBPS} subtracts the packed single-precision FP values of
12263 the source operand from those of the destination operand, and
12264 stores the result in the destination operation.
12267 \S{insSUBSD} \i\c{SUBSD}: Scalar Single-FP Subtract
12269 \c SUBSD xmm1,xmm2/m128 ; F2 0F 5C /r [WILLAMETTE,SSE2]
12271 \c{SUBSD} subtracts the low-order double-precision FP value of
12272 the source operand from that of the destination operand, and
12273 stores the result in the destination operation. The high
12274 quadword is unchanged.
12277 \S{insSUBSS} \i\c{SUBSS}: Scalar Single-FP Subtract
12279 \c SUBSS xmm1,xmm2/m128 ; F3 0F 5C /r [KATMAI,SSE]
12281 \c{SUBSS} subtracts the low-order single-precision FP value of
12282 the source operand from that of the destination operand, and
12283 stores the result in the destination operation. The three high
12284 doublewords are unchanged.
12287 \S{insSVDC} \i\c{SVDC}: Save Segment Register and Descriptor
12289 \c SVDC m80,segreg ; 0F 78 /r [486,CYRIX,SMM]
12291 \c{SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its
12292 descriptor to mem80.
12295 \S{insSVLDT} \i\c{SVLDT}: Save LDTR and Descriptor
12297 \c SVLDT m80 ; 0F 7A /0 [486,CYRIX,SMM]
12299 \c{SVLDT} saves the Local Descriptor Table (LDTR) to mem80.
12302 \S{insSVTS} \i\c{SVTS}: Save TSR and Descriptor
12304 \c SVTS m80 ; 0F 7C /0 [486,CYRIX,SMM]
12306 \c{SVTS} saves the Task State Register (TSR) to mem80.
12309 \S{insSYSCALL} \i\c{SYSCALL}: Call Operating System
12311 \c SYSCALL ; 0F 05 [P6,AMD]
12313 \c{SYSCALL} provides a fast method of transferring control to a fixed
12314 entry point in an operating system.
12316 \b The \c{EIP} register is copied into the \c{ECX} register.
12318 \b Bits [31-0] of the 64-bit SYSCALL/SYSRET Target Address Register
12319 (\c{STAR}) are copied into the \c{EIP} register.
12321 \b Bits [47-32] of the \c{STAR} register specify the selector that is
12322 copied into the \c{CS} register.
12324 \b Bits [47-32]+1000b of the \c{STAR} register specify the selector that
12325 is copied into the SS register.
12327 The \c{CS} and \c{SS} registers should not be modified by the operating
12328 system between the execution of the \c{SYSCALL} instruction and its
12329 corresponding \c{SYSRET} instruction.
12331 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12332 (AMD document number 21086.pdf).
12335 \S{insSYSENTER} \i\c{SYSENTER}: Fast System Call
12337 \c SYSENTER ; 0F 34 [P6]
12339 \c{SYSENTER} executes a fast call to a level 0 system procedure or
12340 routine. Before using this instruction, various MSRs need to be set
12343 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12344 privilege level 0 code segment. (This value is also used to compute
12345 the segment selector of the privilege level 0 stack segment.)
12347 \b \c{SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege
12348 level 0 code segment to the first instruction of the selected operating
12349 procedure or routine.
12351 \b \c{SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the
12352 privilege level 0 stack.
12354 \c{SYSENTER} performs the following sequence of operations:
12356 \b Loads the segment selector from the \c{SYSENTER_CS_MSR} into the
12359 \b Loads the instruction pointer from the \c{SYSENTER_EIP_MSR} into
12360 the \c{EIP} register.
12362 \b Adds 8 to the value in \c{SYSENTER_CS_MSR} and loads it into the
12365 \b Loads the stack pointer from the \c{SYSENTER_ESP_MSR} into the
12368 \b Switches to privilege level 0.
12370 \b Clears the \c{VM} flag in the \c{EFLAGS} register, if the flag
12373 \b Begins executing the selected system procedure.
12375 In particular, note that this instruction des not save the values of
12376 \c{CS} or \c{(E)IP}. If you need to return to the calling code, you
12377 need to write your code to cater for this.
12379 For more information, see the Intel Architecture Software Developer's
12383 \S{insSYSEXIT} \i\c{SYSEXIT}: Fast Return From System Call
12385 \c SYSEXIT ; 0F 35 [P6,PRIV]
12387 \c{SYSEXIT} executes a fast return to privilege level 3 user code.
12388 This instruction is a companion instruction to the \c{SYSENTER}
12389 instruction, and can only be executed by privilege level 0 code.
12390 Various registers need to be set up before calling this instruction:
12392 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12393 privilege level 0 code segment in which the processor is currently
12394 executing. (This value is used to compute the segment selectors for
12395 the privilege level 3 code and stack segments.)
12397 \b \c{EDX} contains the 32-bit offset into the privilege level 3 code
12398 segment to the first instruction to be executed in the user code.
12400 \b \c{ECX} contains the 32-bit stack pointer for the privilege level 3
12403 \c{SYSEXIT} performs the following sequence of operations:
12405 \b Adds 16 to the value in \c{SYSENTER_CS_MSR} and loads the sum into
12406 the \c{CS} selector register.
12408 \b Loads the instruction pointer from the \c{EDX} register into the
12411 \b Adds 24 to the value in \c{SYSENTER_CS_MSR} and loads the sum
12412 into the \c{SS} selector register.
12414 \b Loads the stack pointer from the \c{ECX} register into the \c{ESP}
12417 \b Switches to privilege level 3.
12419 \b Begins executing the user code at the \c{EIP} address.
12421 For more information on the use of the \c{SYSENTER} and \c{SYSEXIT}
12422 instructions, see the Intel Architecture Software Developer's
12426 \S{insSYSRET} \i\c{SYSRET}: Return From Operating System
12428 \c SYSRET ; 0F 07 [P6,AMD,PRIV]
12430 \c{SYSRET} is the return instruction used in conjunction with the
12431 \c{SYSCALL} instruction to provide fast entry/exit to an operating system.
12433 \b The \c{ECX} register, which points to the next sequential instruction
12434 after the corresponding \c{SYSCALL} instruction, is copied into the \c{EIP}
12437 \b Bits [63-48] of the \c{STAR} register specify the selector that is copied
12438 into the \c{CS} register.
12440 \b Bits [63-48]+1000b of the \c{STAR} register specify the selector that is
12441 copied into the \c{SS} register.
12443 \b Bits [1-0] of the \c{SS} register are set to 11b (RPL of 3) regardless of
12444 the value of bits [49-48] of the \c{STAR} register.
12446 The \c{CS} and \c{SS} registers should not be modified by the operating
12447 system between the execution of the \c{SYSCALL} instruction and its
12448 corresponding \c{SYSRET} instruction.
12450 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12451 (AMD document number 21086.pdf).
12454 \S{insTEST} \i\c{TEST}: Test Bits (notional bitwise AND)
12456 \c TEST r/m8,reg8 ; 84 /r [8086]
12457 \c TEST r/m16,reg16 ; o16 85 /r [8086]
12458 \c TEST r/m32,reg32 ; o32 85 /r [386]
12460 \c TEST r/m8,imm8 ; F6 /0 ib [8086]
12461 \c TEST r/m16,imm16 ; o16 F7 /0 iw [8086]
12462 \c TEST r/m32,imm32 ; o32 F7 /0 id [386]
12464 \c TEST AL,imm8 ; A8 ib [8086]
12465 \c TEST AX,imm16 ; o16 A9 iw [8086]
12466 \c TEST EAX,imm32 ; o32 A9 id [386]
12468 \c{TEST} performs a `mental' bitwise AND of its two operands, and
12469 affects the flags as if the operation had taken place, but does not
12470 store the result of the operation anywhere.
12473 \S{insUCOMISD} \i\c{UCOMISD}: Unordered Scalar Double-Precision FP
12474 compare and set EFLAGS
12476 \c UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2]
12478 \c{UCOMISD} compares the low-order double-precision FP numbers in the
12479 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12480 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12481 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12482 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12483 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12486 \S{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-Precision FP
12487 compare and set EFLAGS
12489 \c UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE]
12491 \c{UCOMISS} compares the low-order single-precision FP numbers in the
12492 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12493 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12494 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12495 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12496 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12499 \S{insUD2} \i\c{UD0}, \i\c{UD1}, \i\c{UD2}: Undefined Instruction
12501 \c UD0 ; 0F FF [186,UNDOC]
12502 \c UD1 ; 0F B9 [186,UNDOC]
12503 \c UD2 ; 0F 0B [186]
12505 \c{UDx} can be used to generate an invalid opcode exception, for testing
12508 \c{UD0} is specifically documented by AMD as being reserved for this
12511 \c{UD1} is specifically documented by Intel as being reserved for this
12514 \c{UD2} is mentioned by Intel as being available, but is not mentioned
12517 All these opcodes can be used to generate invalid opcode exceptions on
12518 all processors that are available at the current time.
12521 \S{insUMOV} \i\c{UMOV}: User Move Data
12523 \c UMOV r/m8,reg8 ; 0F 10 /r [386,UNDOC]
12524 \c UMOV r/m16,reg16 ; o16 0F 11 /r [386,UNDOC]
12525 \c UMOV r/m32,reg32 ; o32 0F 11 /r [386,UNDOC]
12527 \c UMOV reg8,r/m8 ; 0F 12 /r [386,UNDOC]
12528 \c UMOV reg16,r/m16 ; o16 0F 13 /r [386,UNDOC]
12529 \c UMOV reg32,r/m32 ; o32 0F 13 /r [386,UNDOC]
12531 This undocumented instruction is used by in-circuit emulators to
12532 access user memory (as opposed to host memory). It is used just like
12533 an ordinary memory/register or register/register \c{MOV}
12534 instruction, but accesses user space.
12536 This instruction is only available on some AMD and IBM 386 and 486
12540 \S{insUNPCKHPD} \i\c{UNPCKHPD}: Unpack and Interleave High Packed
12541 Double-Precision FP Values
12543 \c UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2]
12545 \c{UNPCKHPD} performs an interleaved unpack of the high-order data
12546 elements of the source and destination operands, saving the result
12547 in \c{xmm1}. It ignores the lower half of the sources.
12549 The operation of this instruction is:
12551 \c dst[63-0] := dst[127-64];
12552 \c dst[127-64] := src[127-64].
12555 \S{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack and Interleave High Packed
12556 Single-Precision FP Values
12558 \c UNPCKHPS xmm1,xmm2/m128 ; 0F 15 /r [KATMAI,SSE]
12560 \c{UNPCKHPS} performs an interleaved unpack of the high-order data
12561 elements of the source and destination operands, saving the result
12562 in \c{xmm1}. It ignores the lower half of the sources.
12564 The operation of this instruction is:
12566 \c dst[31-0] := dst[95-64];
12567 \c dst[63-32] := src[95-64];
12568 \c dst[95-64] := dst[127-96];
12569 \c dst[127-96] := src[127-96].
12572 \S{insUNPCKLPD} \i\c{UNPCKLPD}: Unpack and Interleave Low Packed
12573 Double-Precision FP Data
12575 \c UNPCKLPD xmm1,xmm2/m128 ; 66 0F 14 /r [WILLAMETTE,SSE2]
12577 \c{UNPCKLPD} performs an interleaved unpack of the low-order data
12578 elements of the source and destination operands, saving the result
12579 in \c{xmm1}. It ignores the lower half of the sources.
12581 The operation of this instruction is:
12583 \c dst[63-0] := dst[63-0];
12584 \c dst[127-64] := src[63-0].
12587 \S{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack and Interleave Low Packed
12588 Single-Precision FP Data
12590 \c UNPCKLPS xmm1,xmm2/m128 ; 0F 14 /r [KATMAI,SSE]
12592 \c{UNPCKLPS} performs an interleaved unpack of the low-order data
12593 elements of the source and destination operands, saving the result
12594 in \c{xmm1}. It ignores the lower half of the sources.
12596 The operation of this instruction is:
12598 \c dst[31-0] := dst[31-0];
12599 \c dst[63-32] := src[31-0];
12600 \c dst[95-64] := dst[63-32];
12601 \c dst[127-96] := src[63-32].
12604 \S{insVERR} \i\c{VERR}, \i\c{VERW}: Verify Segment Readability/Writability
12606 \c VERR r/m16 ; 0F 00 /4 [286,PRIV]
12608 \c VERW r/m16 ; 0F 00 /5 [286,PRIV]
12610 \b \c{VERR} sets the zero flag if the segment specified by the selector
12611 in its operand can be read from at the current privilege level.
12612 Otherwise it is cleared.
12614 \b \c{VERW} sets the zero flag if the segment can be written.
12617 \S{insWAIT} \i\c{WAIT}: Wait for Floating-Point Processor
12619 \c WAIT ; 9B [8086]
12620 \c FWAIT ; 9B [8086]
12622 \c{WAIT}, on 8086 systems with a separate 8087 FPU, waits for the
12623 FPU to have finished any operation it is engaged in before
12624 continuing main processor operations, so that (for example) an FPU
12625 store to main memory can be guaranteed to have completed before the
12626 CPU tries to read the result back out.
12628 On higher processors, \c{WAIT} is unnecessary for this purpose, and
12629 it has the alternative purpose of ensuring that any pending unmasked
12630 FPU exceptions have happened before execution continues.
12633 \S{insWBINVD} \i\c{WBINVD}: Write Back and Invalidate Cache
12635 \c WBINVD ; 0F 09 [486]
12637 \c{WBINVD} invalidates and empties the processor's internal caches,
12638 and causes the processor to instruct external caches to do the same.
12639 It writes the contents of the caches back to memory first, so no
12640 data is lost. To flush the caches quickly without bothering to write
12641 the data back first, use \c{INVD} (\k{insINVD}).
12644 \S{insWRMSR} \i\c{WRMSR}: Write Model-Specific Registers
12646 \c WRMSR ; 0F 30 [PENT]
12648 \c{WRMSR} writes the value in \c{EDX:EAX} to the processor
12649 Model-Specific Register (MSR) whose index is stored in \c{ECX}.
12650 See also \c{RDMSR} (\k{insRDMSR}).
12653 \S{insWRSHR} \i\c{WRSHR}: Write SMM Header Pointer Register
12655 \c WRSHR r/m32 ; 0F 37 /0 [386,CYRIX,SMM]
12657 \c{WRSHR} loads the contents of either a 32-bit memory location or a
12658 32-bit register into the SMM header pointer register.
12660 See also \c{RDSHR} (\k{insRDSHR}).
12663 \S{insXADD} \i\c{XADD}: Exchange and Add
12665 \c XADD r/m8,reg8 ; 0F C0 /r [486]
12666 \c XADD r/m16,reg16 ; o16 0F C1 /r [486]
12667 \c XADD r/m32,reg32 ; o32 0F C1 /r [486]
12669 \c{XADD} exchanges the values in its two operands, and then adds
12670 them together and writes the result into the destination (first)
12671 operand. This instruction can be used with a \c{LOCK} prefix for
12672 multi-processor synchronisation purposes.
12675 \S{insXBTS} \i\c{XBTS}: Extract Bit String
12677 \c XBTS reg16,r/m16 ; o16 0F A6 /r [386,UNDOC]
12678 \c XBTS reg32,r/m32 ; o32 0F A6 /r [386,UNDOC]
12680 The implied operation of this instruction is:
12682 \c XBTS r/m16,reg16,AX,CL
12683 \c XBTS r/m32,reg32,EAX,CL
12685 Writes a bit string from the source operand to the destination. \c{CL}
12686 indicates the number of bits to be copied, and \c{(E)AX} indicates the
12687 low order bit offset in the source. The bits are written to the low
12688 order bits of the destination register. For example, if \c{CL} is set
12689 to 4 and \c{AX} (for 16-bit code) is set to 5, bits 5-8 of \c{src} will
12690 be copied to bits 0-3 of \c{dst}. This instruction is very poorly
12691 documented, and I have been unable to find any official source of
12692 documentation on it.
12694 \c{XBTS} is supported only on the early Intel 386s, and conflicts with
12695 the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM supports it
12696 only for completeness. Its counterpart is \c{IBTS} (see \k{insIBTS}).
12699 \S{insXCHG} \i\c{XCHG}: Exchange
12701 \c XCHG reg8,r/m8 ; 86 /r [8086]
12702 \c XCHG reg16,r/m8 ; o16 87 /r [8086]
12703 \c XCHG reg32,r/m32 ; o32 87 /r [386]
12705 \c XCHG r/m8,reg8 ; 86 /r [8086]
12706 \c XCHG r/m16,reg16 ; o16 87 /r [8086]
12707 \c XCHG r/m32,reg32 ; o32 87 /r [386]
12709 \c XCHG AX,reg16 ; o16 90+r [8086]
12710 \c XCHG EAX,reg32 ; o32 90+r [386]
12711 \c XCHG reg16,AX ; o16 90+r [8086]
12712 \c XCHG reg32,EAX ; o32 90+r [386]
12714 \c{XCHG} exchanges the values in its two operands. It can be used
12715 with a \c{LOCK} prefix for purposes of multi-processor
12718 \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the \c{BITS}
12719 setting) generates the opcode \c{90h}, and so is a synonym for
12720 \c{NOP} (\k{insNOP}).
12723 \S{insXLATB} \i\c{XLATB}: Translate Byte in Lookup Table
12725 \c XLAT ; D7 [8086]
12726 \c XLATB ; D7 [8086]
12728 \c{XLATB} adds the value in \c{AL}, treated as an unsigned byte, to
12729 \c{BX} or \c{EBX}, and loads the byte from the resulting address (in
12730 the segment specified by \c{DS}) back into \c{AL}.
12732 The base register used is \c{BX} if the address size is 16 bits, and
12733 \c{EBX} if it is 32 bits. If you need to use an address size not
12734 equal to the current \c{BITS} setting, you can use an explicit
12735 \i\c{a16} or \i\c{a32} prefix.
12737 The segment register used to load from \c{[BX+AL]} or \c{[EBX+AL]}
12738 can be overridden by using a segment register name as a prefix (for
12739 example, \c{es xlatb}).
12742 \S{insXOR} \i\c{XOR}: Bitwise Exclusive OR
12744 \c XOR r/m8,reg8 ; 30 /r [8086]
12745 \c XOR r/m16,reg16 ; o16 31 /r [8086]
12746 \c XOR r/m32,reg32 ; o32 31 /r [386]
12748 \c XOR reg8,r/m8 ; 32 /r [8086]
12749 \c XOR reg16,r/m16 ; o16 33 /r [8086]
12750 \c XOR reg32,r/m32 ; o32 33 /r [386]
12752 \c XOR r/m8,imm8 ; 80 /6 ib [8086]
12753 \c XOR r/m16,imm16 ; o16 81 /6 iw [8086]
12754 \c XOR r/m32,imm32 ; o32 81 /6 id [386]
12756 \c XOR r/m16,imm8 ; o16 83 /6 ib [8086]
12757 \c XOR r/m32,imm8 ; o32 83 /6 ib [386]
12759 \c XOR AL,imm8 ; 34 ib [8086]
12760 \c XOR AX,imm16 ; o16 35 iw [8086]
12761 \c XOR EAX,imm32 ; o32 35 id [386]
12763 \c{XOR} performs a bitwise XOR operation between its two operands
12764 (i.e. each bit of the result is 1 if and only if exactly one of the
12765 corresponding bits of the two inputs was 1), and stores the result
12766 in the destination (first) operand.
12768 In the forms with an 8-bit immediate second operand and a longer
12769 first operand, the second operand is considered to be signed, and is
12770 sign-extended to the length of the first operand. In these cases,
12771 the \c{BYTE} qualifier is necessary to force NASM to generate this
12772 form of the instruction.
12774 The \c{MMX} instruction \c{PXOR} (see \k{insPXOR}) performs the same
12775 operation on the 64-bit \c{MMX} registers.
12778 \S{insXORPD} \i\c{XORPD}: Bitwise Logical XOR of Double-Precision FP Values
12780 \c XORPD xmm1,xmm2/m128 ; 66 0F 57 /r [WILLAMETTE,SSE2]
12782 \c{XORPD} returns a bit-wise logical XOR between the source and
12783 destination operands, storing the result in the destination operand.
12786 \S{insXORPS} \i\c{XORPS}: Bitwise Logical XOR of Single-Precision FP Values
12788 \c XORPS xmm1,xmm2/m128 ; 0F 57 /r [KATMAI,SSE]
12790 \c{XORPS} returns a bit-wise logical XOR between the source and
12791 destination operands, storing the result in the destination operand.