3 \# Source code to NASM documentation
5 \M{category}{Programming}
6 \M{title}{NASM - The Netwide Assembler}
8 \M{author}{The NASM Development Team}
9 \M{license}{All rights reserved. This document is redistributable under the licence given in the file "COPYING" distributed in the NASM archive.}
10 \M{summary}{This file documents NASM, the Netwide Assembler: an assembler targetting the Intel x86 series of processors, with portable source.}
13 \M{infotitle}{The Netwide Assembler for x86}
14 \M{epslogo}{nasmlogo.eps}
20 \IR{-On} \c{-On} option
36 \IR{!=} \c{!=} operator
37 \IR{$, here} \c{$}, Here token
38 \IR{$, prefix} \c{$}, prefix
41 \IR{%%} \c{%%} operator
42 \IR{%+1} \c{%+1} and \c{%-1} syntax
44 \IR{%0} \c{%0} parameter count
46 \IR{&&} \c{&&} operator
48 \IR{..@} \c{..@} symbol prefix
50 \IR{//} \c{//} operator
52 \IR{<<} \c{<<} operator
53 \IR{<=} \c{<=} operator
54 \IR{<>} \c{<>} operator
56 \IR{==} \c{==} operator
58 \IR{>=} \c{>=} operator
59 \IR{>>} \c{>>} operator
60 \IR{?} \c{?} MASM syntax
62 \IR{^^} \c{^^} operator
64 \IR{||} \c{||} operator
66 \IR{%$} \c{%$} and \c{%$$} prefixes
68 \IR{+ opaddition} \c{+} operator, binary
69 \IR{+ opunary} \c{+} operator, unary
70 \IR{+ modifier} \c{+} modifier
71 \IR{- opsubtraction} \c{-} operator, binary
72 \IR{- opunary} \c{-} operator, unary
73 \IR{alignment, in bin sections} alignment, in \c{bin} sections
74 \IR{alignment, in elf sections} alignment, in \c{elf} sections
75 \IR{alignment, in win32 sections} alignment, in \c{win32} sections
76 \IR{alignment, of elf common variables} alignment, of \c{elf} common
78 \IR{alignment, in obj sections} alignment, in \c{obj} sections
79 \IR{a.out, bsd version} \c{a.out}, BSD version
80 \IR{a.out, linux version} \c{a.out}, Linux version
81 \IR{autoconf} Autoconf
82 \IR{bitwise and} bitwise AND
83 \IR{bitwise or} bitwise OR
84 \IR{bitwise xor} bitwise XOR
85 \IR{block ifs} block IFs
86 \IR{borland pascal} Borland, Pascal
87 \IR{borland's win32 compilers} Borland, Win32 compilers
88 \IR{braces, after % sign} braces, after \c{%} sign
90 \IR{c calling convention} C calling convention
91 \IR{c symbol names} C symbol names
92 \IA{critical expressions}{critical expression}
93 \IA{command line}{command-line}
94 \IA{case sensitivity}{case sensitive}
95 \IA{case-sensitive}{case sensitive}
96 \IA{case-insensitive}{case sensitive}
97 \IA{character constants}{character constant}
98 \IR{common object file format} Common Object File Format
99 \IR{common variables, alignment in elf} common variables, alignment
101 \IR{common, elf extensions to} \c{COMMON}, \c{elf} extensions to
102 \IR{common, obj extensions to} \c{COMMON}, \c{obj} extensions to
103 \IR{declaring structure} declaring structures
104 \IR{default-wrt mechanism} default-\c{WRT} mechanism
107 \IR{dll symbols, exporting} DLL symbols, exporting
108 \IR{dll symbols, importing} DLL symbols, importing
110 \IR{dos archive} DOS archive
111 \IR{dos source archive} DOS source archive
112 \IA{effective address}{effective addresses}
113 \IA{effective-address}{effective addresses}
115 \IR{elf, 16-bit code and} ELF, 16-bit code and
116 \IR{elf shared libraries} ELF, shared libraries
117 \IR{executable and linkable format} Executable and Linkable Format
118 \IR{extern, obj extensions to} \c{EXTERN}, \c{obj} extensions to
120 \IR{freelink} FreeLink
121 \IR{functions, c calling convention} functions, C calling convention
122 \IR{functions, pascal calling convention} functions, Pascal calling
124 \IR{global, aoutb extensions to} \c{GLOBAL}, \c{aoutb} extensions to
125 \IR{global, elf extensions to} \c{GLOBAL}, \c{elf} extensions to
126 \IR{global, rdf extensions to} \c{GLOBAL}, \c{rdf} extensions to
128 \IR{got relocations} \c{GOT} relocations
129 \IR{gotoff relocation} \c{GOTOFF} relocations
130 \IR{gotpc relocation} \c{GOTPC} relocations
131 \IR{intel number formats} Intel number formats
132 \IR{linux, elf} Linux, ELF
133 \IR{linux, a.out} Linux, \c{a.out}
134 \IR{linux, as86} Linux, \c{as86}
135 \IR{logical and} logical AND
136 \IR{logical or} logical OR
137 \IR{logical xor} logical XOR
139 \IA{memory reference}{memory references}
141 \IA{misc directory}{misc subdirectory}
142 \IR{misc subdirectory} \c{misc} subdirectory
143 \IR{microsoft omf} Microsoft OMF
144 \IR{mmx registers} MMX registers
145 \IA{modr/m}{modr/m byte}
146 \IR{modr/m byte} ModR/M byte
148 \IR{ms-dos device drivers} MS-DOS device drivers
149 \IR{multipush} \c{multipush} macro
150 \IR{nasm version} NASM version
154 \IR{operating system} operating system
156 \IR{pascal calling convention}Pascal calling convention
157 \IR{passes} passes, assembly
162 \IR{plt} \c{PLT} relocations
163 \IA{pre-defining macros}{pre-define}
164 \IA{preprocessor expressions}{preprocessor, expressions}
165 \IA{preprocessor loops}{preprocessor, loops}
166 \IA{preprocessor variables}{preprocessor, variables}
167 \IA{rdoff subdirectory}{rdoff}
168 \IR{rdoff} \c{rdoff} subdirectory
169 \IR{relocatable dynamic object file format} Relocatable Dynamic
171 \IR{relocations, pic-specific} relocations, PIC-specific
172 \IA{repeating}{repeating code}
173 \IR{section alignment, in elf} section alignment, in \c{elf}
174 \IR{section alignment, in bin} section alignment, in \c{bin}
175 \IR{section alignment, in obj} section alignment, in \c{obj}
176 \IR{section alignment, in win32} section alignment, in \c{win32}
177 \IR{section, elf extensions to} \c{SECTION}, \c{elf} extensions to
178 \IR{section, win32 extensions to} \c{SECTION}, \c{win32} extensions to
179 \IR{segment alignment, in bin} segment alignment, in \c{bin}
180 \IR{segment alignment, in obj} segment alignment, in \c{obj}
181 \IR{segment, obj extensions to} \c{SEGMENT}, \c{elf} extensions to
182 \IR{segment names, borland pascal} segment names, Borland Pascal
183 \IR{shift command} \c{shift} command
185 \IR{sib byte} SIB byte
186 \IR{solaris x86} Solaris x86
187 \IA{standard section names}{standardised section names}
188 \IR{symbols, exporting from dlls} symbols, exporting from DLLs
189 \IR{symbols, importing from dlls} symbols, importing from DLLs
190 \IR{test subdirectory} \c{test} subdirectory
192 \IR{underscore, in c symbols} underscore, in C symbols
194 \IA{sco unix}{unix, sco}
195 \IR{unix, sco} Unix, SCO
196 \IA{unix source archive}{unix, source archive}
197 \IR{unix, source archive} Unix, source archive
198 \IA{unix system v}{unix, system v}
199 \IR{unix, system v} Unix, System V
200 \IR{unixware} UnixWare
202 \IR{version number of nasm} version number of NASM
203 \IR{visual c++} Visual C++
204 \IR{www page} WWW page
207 \IR{windows 95} Windows 95
208 \IR{windows nt} Windows NT
209 \# \IC{program entry point}{entry point, program}
210 \# \IC{program entry point}{start point, program}
211 \# \IC{MS-DOS device drivers}{device drivers, MS-DOS}
212 \# \IC{16-bit mode, versus 32-bit mode}{32-bit mode, versus 16-bit mode}
213 \# \IC{c symbol names}{symbol names, in C}
216 \C{intro} Introduction
218 \H{whatsnasm} What Is NASM?
220 The Netwide Assembler, NASM, is an 80x86 assembler designed for
221 portability and modularity. It supports a range of object file
222 formats, including Linux and \c{NetBSD/FreeBSD} \c{a.out}, \c{ELF},
223 \c{COFF}, Microsoft 16-bit \c{OBJ} and \c{Win32}. It will also output
224 plain binary files. Its syntax is designed to be simple and easy to
225 understand, similar to Intel's but less complex. It supports \c{Pentium},
226 \c{P6}, \c{MMX}, \c{3DNow!}, \c{SSE} and \c{SSE2} opcodes, and has
230 \S{yaasm} Why Yet Another Assembler?
232 The Netwide Assembler grew out of an idea on \i\c{comp.lang.asm.x86}
233 (or possibly \i\c{alt.lang.asm} - I forget which), which was
234 essentially that there didn't seem to be a good \e{free} x86-series
235 assembler around, and that maybe someone ought to write one.
237 \b \i\c{a86} is good, but not free, and in particular you don't get any
238 32-bit capability until you pay. It's DOS only, too.
240 \b \i\c{gas} is free, and ports over DOS and Unix, but it's not
241 very good, since it's designed to be a back end to \i\c{gcc}, which
242 always feeds it correct code. So its error checking is minimal. Also,
243 its syntax is horrible, from the point of view of anyone trying to
244 actually \e{write} anything in it. Plus you can't write 16-bit code in
247 \b \i\c{as86} is Minix- and Linux-specific, and (my version at least)
248 doesn't seem to have much (or any) documentation.
250 \b \i\c{MASM} isn't very good, and it's expensive, and it runs only under
253 \b \i\c{TASM} is better, but still strives for MASM compatibility,
254 which means millions of directives and tons of red tape. And its syntax
255 is essentially MASM's, with the contradictions and quirks that
256 entails (although it sorts out some of those by means of Ideal mode).
257 It's expensive too. And it's DOS-only.
259 So here, for your coding pleasure, is NASM. At present it's
260 still in prototype stage - we don't promise that it can outperform
261 any of these assemblers. But please, \e{please} send us bug reports,
262 fixes, helpful information, and anything else you can get your hands
263 on (and thanks to the many people who've done this already! You all
264 know who you are), and we'll improve it out of all recognition.
268 \S{legal} Licence Conditions
270 Please see the file \c{Licence}, supplied as part of any NASM
271 distribution archive, for the \i{licence} conditions under which you
275 \H{contact} Contact Information
277 The current version of NASM (since about 0.98.08) are maintained by a
278 team of developers, accessible through the \c{nasm-devel} mailing list
279 (see below for the link).
280 If you want to report a bug, please read \k{bugs} first.
282 NASM has a \i{WWW page} at
283 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm},
284 and another, with additional information, at
285 \W{http://nasm.2y.net/}\c{http://nasm.2y.net/}
287 The original authors are \i{e\-mail}able as
288 \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} and
289 \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}.
290 The latter is no longer involved in the development team.
292 \i{New releases} of NASM are uploaded to the official sites
293 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm}
295 \W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org}
297 \W{ftp://ibiblio.org/pub/Linux/devel/lang/assemblers/}\i\c{ibiblio.org}.
299 Announcements are posted to
300 \W{news:comp.lang.asm.x86}\i\c{comp.lang.asm.x86},
301 \W{news:alt.lang.asm}\i\c{alt.lang.asm} and
302 \W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce}
304 If you want information about NASM beta releases, and the current
305 development status, please subscribe to the \i\c{nasm-devel} email list
307 \W{http://groups.yahoo.com/group/nasm-devel}\c{http://groups.yahoo.com/group/nasm-devel},
308 \W{http://www.pairlist.net/mailman/listinfo/nasm-devel}\c{http://www.pairlist.net/mailman/listinfo/nasm-devel}
310 \W{http://sourceforge.net/projects/nasm}\c{http://sourceforge.net/projects/nasm}.
312 The preferred list is the list at Sourceforge, which is also the home to
313 the latest nasm source code and releases. The other lists are open, but
314 may not continue to be supported in the long term.
317 \H{install} Installation
319 \S{instdos} \i{Installing} NASM under MS-\i{DOS} or Windows
321 Once you've obtained the \i{DOS archive} for NASM, \i\c{nasmXXX.zip}
322 (where \c{XXX} denotes the version number of NASM contained in the
323 archive), unpack it into its own directory (for example \c{c:\\nasm}).
325 The archive will contain four executable files: the NASM executable
326 files \i\c{nasm.exe} and \i\c{nasmw.exe}, and the NDISASM executable
327 files \i\c{ndisasm.exe} and \i\c{ndisasmw.exe}. In each case, the
328 file whose name ends in \c{w} is a \I{Win32}\c{Win32} executable,
329 designed to run under \I{Windows 95}\c{Windows 95} or \I{Windows NT}
330 \c{Windows NT} Intel, and the other one is a 16-bit \I{DOS}\c{DOS}
333 The only file NASM needs to run is its own executable, so copy
334 (at least) one of \c{nasm.exe} and \c{nasmw.exe} to a directory on
335 your PATH, or alternatively edit \i\c{autoexec.bat} to add the
336 \c{nasm} directory to your \i\c{PATH}. (If you're only installing the
337 \c{Win32} version, you may wish to rename it to \c{nasm.exe}.)
339 That's it - NASM is installed. You don't need the nasm directory
340 to be present to run NASM (unless you've added it to your \c{PATH}),
341 so you can delete it if you need to save space; however, you may
342 want to keep the documentation or test programs.
344 If you've downloaded the \i{DOS source archive}, \i\c{nasmXXXs.zip},
345 the \c{nasm} directory will also contain the full NASM \i{source
346 code}, and a selection of \i{Makefiles} you can (hopefully) use to
347 rebuild your copy of NASM from scratch.
349 Note that the source files \c{insnsa.c}, \c{insnsd.c}, \c{insnsi.h}
350 and \c{insnsn.c} are automatically generated from the master
351 instruction table \c{insns.dat} by a Perl script; the file
352 \c{macros.c} is generated from \c{standard.mac} by another Perl
353 script. Although the NASM 0.98 distribution includes these generated
354 files, you will need to rebuild them (and hence, will need a Perl
355 interpreter) if you change insns.dat, standard.mac or the
356 documentation. It is possible future source distributions may not
357 include these files at all. Ports of \i{Perl} for a variety of
358 platforms, including DOS and Windows, are available from
359 \W{http://www.cpan.org/ports/}\i{www.cpan.org}.
362 \S{instdos} Installing NASM under \i{Unix}
364 Once you've obtained the \i{Unix source archive} for NASM,
365 \i\c{nasm-X.XX.tar.gz} (where \c{X.XX} denotes the version number of
366 NASM contained in the archive), unpack it into a directory such
367 as \c{/usr/local/src}. The archive, when unpacked, will create its
368 own subdirectory \c{nasm-X.XX}.
370 NASM is an \I{Autoconf}\I\c{configure}auto-configuring package: once
371 you've unpacked it, \c{cd} to the directory it's been unpacked into
372 and type \c{./configure}. This shell script will find the best C
373 compiler to use for building NASM and set up \i{Makefiles}
376 Once NASM has auto-configured, you can type \i\c{make} to build the
377 \c{nasm} and \c{ndisasm} binaries, and then \c{make install} to
378 install them in \c{/usr/local/bin} and install the \i{man pages}
379 \i\c{nasm.1} and \i\c{ndisasm.1} in \c{/usr/local/man/man1}.
380 Alternatively, you can give options such as \c{--prefix} to the
381 configure script (see the file \i\c{INSTALL} for more details), or
382 install the programs yourself.
384 NASM also comes with a set of utilities for handling the \c{RDOFF}
385 custom object-file format, which are in the \i\c{rdoff} subdirectory
386 of the NASM archive. You can build these with \c{make rdf} and
387 install them with \c{make rdf_install}, if you want them.
389 If NASM fails to auto-configure, you may still be able to make it
390 compile by using the fall-back Unix makefile \i\c{Makefile.unx}.
391 Copy or rename that file to \c{Makefile} and try typing \c{make}.
392 There is also a Makefile.unx file in the \c{rdoff} subdirectory.
395 \C{running} Running NASM
397 \H{syntax} NASM \i{Command-Line} Syntax
399 To assemble a file, you issue a command of the form
401 \c nasm -f <format> <filename> [-o <output>]
405 \c nasm -f elf myfile.asm
407 will assemble \c{myfile.asm} into an \c{ELF} object file \c{myfile.o}. And
409 \c nasm -f bin myfile.asm -o myfile.com
411 will assemble \c{myfile.asm} into a raw binary file \c{myfile.com}.
413 To produce a listing file, with the hex codes output from NASM
414 displayed on the left of the original sources, use the \c{-l} option
415 to give a listing file name, for example:
417 \c nasm -f coff myfile.asm -l myfile.lst
419 To get further usage instructions from NASM, try typing
423 This will also list the available output file formats, and what they
426 If you use Linux but aren't sure whether your system is \c{a.out}
431 (in the directory in which you put the NASM binary when you
432 installed it). If it says something like
434 \c nasm: ELF 32-bit LSB executable i386 (386 and up) Version 1
436 then your system is \c{ELF}, and you should use the option \c{-f elf}
437 when you want NASM to produce Linux object files. If it says
439 \c nasm: Linux/i386 demand-paged executable (QMAGIC)
441 or something similar, your system is \c{a.out}, and you should use
442 \c{-f aout} instead (Linux \c{a.out} systems have long been obsolete,
443 and are rare these days.)
445 Like Unix compilers and assemblers, NASM is silent unless it
446 goes wrong: you won't see any output at all, unless it gives error
450 \S{opt-o} The \i\c{-o} Option: Specifying the Output File Name
452 NASM will normally choose the name of your output file for you;
453 precisely how it does this is dependent on the object file format.
454 For Microsoft object file formats (\i\c{obj} and \i\c{win32}), it
455 will remove the \c{.asm} \i{extension} (or whatever extension you
456 like to use - NASM doesn't care) from your source file name and
457 substitute \c{.obj}. For Unix object file formats (\i\c{aout},
458 \i\c{coff}, \i\c{elf} and \i\c{as86}) it will substitute \c{.o}. For
459 \i\c{rdf}, it will use \c{.rdf}, and for the \i\c{bin} format it
460 will simply remove the extension, so that \c{myfile.asm} produces
461 the output file \c{myfile}.
463 If the output file already exists, NASM will overwrite it, unless it
464 has the same name as the input file, in which case it will give a
465 warning and use \i\c{nasm.out} as the output file name instead.
467 For situations in which this behaviour is unacceptable, NASM
468 provides the \c{-o} command-line option, which allows you to specify
469 your desired output file name. You invoke \c{-o} by following it
470 with the name you wish for the output file, either with or without
471 an intervening space. For example:
473 \c nasm -f bin program.asm -o program.com
474 \c nasm -f bin driver.asm -odriver.sys
476 Note that this is a small o, and is different from a capital O , which
477 is used to specify the number of optimisation passes required. See \k{opt-On}.
480 \S{opt-f} The \i\c{-f} Option: Specifying the \i{Output File Format}
482 If you do not supply the \c{-f} option to NASM, it will choose an
483 output file format for you itself. In the distribution versions of
484 NASM, the default is always \i\c{bin}; if you've compiled your own
485 copy of NASM, you can redefine \i\c{OF_DEFAULT} at compile time and
486 choose what you want the default to be.
488 Like \c{-o}, the intervening space between \c{-f} and the output
489 file format is optional; so \c{-f elf} and \c{-felf} are both valid.
491 A complete list of the available output file formats can be given by
492 issuing the command \i\c{nasm -hf}.
495 \S{opt-l} The \i\c{-l} Option: Generating a \i{Listing File}
497 If you supply the \c{-l} option to NASM, followed (with the usual
498 optional space) by a file name, NASM will generate a
499 \i{source-listing file} for you, in which addresses and generated
500 code are listed on the left, and the actual source code, with
501 expansions of multi-line macros (except those which specifically
502 request no expansion in source listings: see \k{nolist}) on the
505 \c nasm -f elf myfile.asm -l myfile.lst
508 \S{opt-M} The \i\c{-M} Option: Generate \i{Makefile Dependencies}.
510 This option can be used to generate makefile dependencies on stdout.
511 This can be redirected to a file for further processing. For example:
513 \c NASM -M myfile.asm > myfile.dep
516 \S{opt-F} The \i\c{-F} Option: Selecting a \i{Debugging Format}
518 This option can be used to select a debugging format for the output file.
519 The syntax is the same as for the -f option, except that it produces
520 output in a debugging format.
522 A complete list of the available debug file formats for an output format
523 can be seen by issuing the command \i\c{nasm -f <format> -y}.
525 This option is not built into NASM by default. For information on how
526 to enable it when building from the sources, see \k{dbgfmt}
529 \S{opt-g} The \i\c{-g} Option: Enabling \i{Debug Information}.
531 This option can be used to generate debugging information in the specified
534 See \k{opt-F} for more information.
537 \S{opt-E} The \i\c{-E} Option: Send Errors to a File
539 Under \I{DOS}\c{MS-DOS} it can be difficult (though there are ways) to
540 redirect the standard-error output of a program to a file. Since
541 NASM usually produces its warning and \i{error messages} on
542 \i\c{stderr}, this can make it hard to capture the errors if (for
543 example) you want to load them into an editor.
545 NASM therefore provides the \c{-E} option, taking a filename argument
546 which causes errors to be sent to the specified files rather than
547 standard error. Therefore you can \I{redirecting errors}redirect
548 the errors into a file by typing
550 \c nasm -E myfile.err -f obj myfile.asm
553 \S{opt-s} The \i\c{-s} Option: Send Errors to \i\c{stdout}
555 The \c{-s} option redirects \i{error messages} to \c{stdout} rather
556 than \c{stderr}, so it can be redirected under \I{DOS}\c{MS-DOS}. To
557 assemble the file \c{myfile.asm} and pipe its output to the \c{more}
558 program, you can type:
560 \c nasm -s -f obj myfile.asm | more
562 See also the \c{-E} option, \k{opt-E}.
565 \S{opt-i} The \i\c{-i}\I\c{-I} Option: Include File Search Directories
567 When NASM sees the \i\c{%include} directive in a source file (see
568 \k{include}), it will search for the given file not only in the
569 current directory, but also in any directories specified on the
570 command line by the use of the \c{-i} option. Therefore you can
571 include files from a \i{macro library}, for example, by typing
573 \c nasm -ic:\macrolib\ -f obj myfile.asm
575 (As usual, a space between \c{-i} and the path name is allowed, and
578 NASM, in the interests of complete source-code portability, does not
579 understand the file naming conventions of the OS it is running on;
580 the string you provide as an argument to the \c{-i} option will be
581 prepended exactly as written to the name of the include file.
582 Therefore the trailing backslash in the above example is necessary.
583 Under Unix, a trailing forward slash is similarly necessary.
585 (You can use this to your advantage, if you're really \i{perverse},
586 by noting that the option \c{-ifoo} will cause \c{%include "bar.i"}
587 to search for the file \c{foobar.i}...)
589 If you want to define a \e{standard} \i{include search path},
590 similar to \c{/usr/include} on Unix systems, you should place one or
591 more \c{-i} directives in the \c{NASMENV} environment variable (see
594 For Makefile compatibility with many C compilers, this option can also
595 be specified as \c{-I}.
598 \S{opt-p} The \i\c{-p}\I\c{-P} Option: \I{pre-including files}Pre-Include a File
600 \I\c{%include}NASM allows you to specify files to be
601 \e{pre-included} into your source file, by the use of the \c{-p}
604 \c nasm myfile.asm -p myinc.inc
606 is equivalent to running \c{nasm myfile.asm} and placing the
607 directive \c{%include "myinc.inc"} at the start of the file.
609 For consistency with the \c{-I}, \c{-D} and \c{-U} options, this
610 option can also be specified as \c{-P}.
613 \S{opt-d} The \i\c{-d}\I\c{-D} Option: \I{pre-defining macros}Pre-Define a Macro
615 \I\c{%define}Just as the \c{-p} option gives an alternative to placing
616 \c{%include} directives at the start of a source file, the \c{-d}
617 option gives an alternative to placing a \c{%define} directive. You
620 \c nasm myfile.asm -dFOO=100
622 as an alternative to placing the directive
626 at the start of the file. You can miss off the macro value, as well:
627 the option \c{-dFOO} is equivalent to coding \c{%define FOO}. This
628 form of the directive may be useful for selecting \i{assembly-time
629 options} which are then tested using \c{%ifdef}, for example
632 For Makefile compatibility with many C compilers, this option can also
633 be specified as \c{-D}.
636 \S{opt-u} The \i\c{-u}\I\c{-U} Option: \I{Undefining macros}Undefine a Macro
638 \I\c{%undef}The \c{-u} option undefines a macro that would otherwise
639 have been pre-defined, either automatically or by a \c{-p} or \c{-d}
640 option specified earlier on the command lines.
642 For example, the following command line:
644 \c nasm myfile.asm -dFOO=100 -uFOO
646 would result in \c{FOO} \e{not} being a predefined macro in the
647 program. This is useful to override options specified at a different
650 For Makefile compatibility with many C compilers, this option can also
651 be specified as \c{-U}.
654 \S{opt-e} The \i\c{-e} Option: Preprocess Only
656 NASM allows the \i{preprocessor} to be run on its own, up to a
657 point. Using the \c{-e} option (which requires no arguments) will
658 cause NASM to preprocess its input file, expand all the macro
659 references, remove all the comments and preprocessor directives, and
660 print the resulting file on standard output (or save it to a file,
661 if the \c{-o} option is also used).
663 This option cannot be applied to programs which require the
664 preprocessor to evaluate \I{preprocessor expressions}\i{expressions}
665 which depend on the values of symbols: so code such as
667 \c %assign tablesize ($-tablestart)
669 will cause an error in \i{preprocess-only mode}.
672 \S{opt-a} The \i\c{-a} Option: Don't Preprocess At All
674 If NASM is being used as the back end to a compiler, it might be
675 desirable to \I{suppressing preprocessing}suppress preprocessing
676 completely and assume the compiler has already done it, to save time
677 and increase compilation speeds. The \c{-a} option, requiring no
678 argument, instructs NASM to replace its powerful \i{preprocessor}
679 with a \i{stub preprocessor} which does nothing.
682 \S{opt-On} The \i\c{-On} Option: Specifying \i{Multipass Optimization}.
684 NASM defaults to being a two pass assembler. This means that if you
685 have a complex source file which needs more than 2 passes to assemble
686 correctly, you have to tell it.
688 Using the \c{-O} option, you can tell NASM to carry out multiple passes.
691 \b \c{-O0} strict two-pass assembly, JMP and Jcc are handled more
692 like v0.98, except that backward JMPs are short, if possible.
693 Immediate operands take their long forms if a short form is
696 \b \c{-O1} strict two-pass assembly, but forward branches are assembled
697 with code guaranteed to reach; may produce larger code than
698 -O0, but will produce successful assembly more often if
699 branch offset sizes are not specified.
700 Additionally, immediate operands which will fit in a signed byte
701 are optimised, unless the long form is specified.
703 \b \c{-On} multi-pass optimization, minimize branch offsets; also will
704 minimize signed immediate bytes, overriding size specification
705 when the \c{strict} keyword hasn't been used (see \k{strict}).
706 If 2 <= n <= 3, then there are 5 * n passes, otherwise there
710 Note that this is a capital O, and is different from a small o, which
711 is used to specify the output format. See \k{opt-o}.
714 \S{opt-t} The \i\c{-t} option: Enable TASM Compatibility Mode
716 NASM includes a limited form of compatibility with Borland's \i\c{TASM}.
717 When NASM's \c{-t} option is used, the following changes are made:
719 \b local labels may be prefixed with \c{@@} instead of \c{.}
721 \b TASM-style response files beginning with \c{@} may be specified on
722 the command line. This is different from the \c{-@resp} style that NASM
725 \b size override is supported within brackets. In TASM compatible mode,
726 a size override inside square brackets changes the size of the operand,
727 and not the address type of the operand as it does in NASM syntax. E.g.
728 \c{mov eax,[DWORD val]} is valid syntax in TASM compatibility mode.
729 Note that you lose the ability to override the default address type for
732 \b \c{%arg} preprocessor directive is supported which is similar to
733 TASM's \c{ARG} directive.
735 \b \c{%local} preprocessor directive
737 \b \c{%stacksize} preprocessor directive
739 \b unprefixed forms of some directives supported (\c{arg}, \c{elif},
740 \c{else}, \c{endif}, \c{if}, \c{ifdef}, \c{ifdifi}, \c{ifndef},
741 \c{include}, \c{local})
745 For more information on the directives, see the section on TASM
746 Compatiblity preprocessor directives in \k{tasmcompat}.
749 \S{opt-w} The \i\c{-w} Option: Enable or Disable Assembly \i{Warnings}
751 NASM can observe many conditions during the course of assembly which
752 are worth mentioning to the user, but not a sufficiently severe
753 error to justify NASM refusing to generate an output file. These
754 conditions are reported like errors, but come up with the word
755 `warning' before the message. Warnings do not prevent NASM from
756 generating an output file and returning a success status to the
759 Some conditions are even less severe than that: they are only
760 sometimes worth mentioning to the user. Therefore NASM supports the
761 \c{-w} command-line option, which enables or disables certain
762 classes of assembly warning. Such warning classes are described by a
763 name, for example \c{orphan-labels}; you can enable warnings of
764 this class by the command-line option \c{-w+orphan-labels} and
765 disable it by \c{-w-orphan-labels}.
767 The \i{suppressible warning} classes are:
769 \b \i\c{macro-params} covers warnings about \i{multi-line macros}
770 being invoked with the wrong number of parameters. This warning
771 class is enabled by default; see \k{mlmacover} for an example of why
772 you might want to disable it.
774 \b \i\c{orphan-labels} covers warnings about source lines which
775 contain no instruction but define a label without a trailing colon.
776 NASM does not warn about this somewhat obscure condition by default;
777 see \k{syntax} for an example of why you might want it to.
779 \b \i\c{number-overflow} covers warnings about numeric constants which
780 don't fit in 32 bits (for example, it's easy to type one too many Fs
781 and produce \c{0x7ffffffff} by mistake). This warning class is
785 \S{opt-v} The \i\c{-v} Option: Display \i{Version} Info
787 Typing \c{NASM -v} will display the version of NASM which you are using,
788 and the date on which it was compiled.
790 You will need the version number if you report a bug.
793 \S{nasmenv} The \c{NASMENV} \i{Environment} Variable
795 If you define an environment variable called \c{NASMENV}, the program
796 will interpret it as a list of extra command-line options, which are
797 processed before the real command line. You can use this to define
798 standard search directories for include files, by putting \c{-i}
799 options in the \c{NASMENV} variable.
801 The value of the variable is split up at white space, so that the
802 value \c{-s -ic:\\nasmlib} will be treated as two separate options.
803 However, that means that the value \c{-dNAME="my name"} won't do
804 what you might want, because it will be split at the space and the
805 NASM command-line processing will get confused by the two
806 nonsensical words \c{-dNAME="my} and \c{name"}.
808 To get round this, NASM provides a feature whereby, if you begin the
809 \c{NASMENV} environment variable with some character that isn't a minus
810 sign, then NASM will treat this character as the \i{separator
811 character} for options. So setting the \c{NASMENV} variable to the
812 value \c{!-s!-ic:\\nasmlib} is equivalent to setting it to \c{-s
813 -ic:\\nasmlib}, but \c{!-dNAME="my name"} will work.
815 This environment variable was previously called \c{NASM}. This was
816 changed with version 0.98.31.
819 \H{qstart} \i{Quick Start} for \i{MASM} Users
821 If you're used to writing programs with MASM, or with \i{TASM} in
822 MASM-compatible (non-Ideal) mode, or with \i\c{a86}, this section
823 attempts to outline the major differences between MASM's syntax and
824 NASM's. If you're not already used to MASM, it's probably worth
825 skipping this section.
828 \S{qscs} NASM Is \I{case sensitivity}Case-Sensitive
830 One simple difference is that NASM is case-sensitive. It makes a
831 difference whether you call your label \c{foo}, \c{Foo} or \c{FOO}.
832 If you're assembling to \c{DOS} or \c{OS/2} \c{.OBJ} files, you can
833 invoke the \i\c{UPPERCASE} directive (documented in \k{objfmt}) to
834 ensure that all symbols exported to other code modules are forced
835 to be upper case; but even then, \e{within} a single module, NASM
836 will distinguish between labels differing only in case.
839 \S{qsbrackets} NASM Requires \i{Square Brackets} For \i{Memory References}
841 NASM was designed with simplicity of syntax in mind. One of the
842 \i{design goals} of NASM is that it should be possible, as far as is
843 practical, for the user to look at a single line of NASM code
844 and tell what opcode is generated by it. You can't do this in MASM:
845 if you declare, for example,
850 then the two lines of code
855 generate completely different opcodes, despite having
856 identical-looking syntaxes.
858 NASM avoids this undesirable situation by having a much simpler
859 syntax for memory references. The rule is simply that any access to
860 the \e{contents} of a memory location requires square brackets
861 around the address, and any access to the \e{address} of a variable
862 doesn't. So an instruction of the form \c{mov ax,foo} will
863 \e{always} refer to a compile-time constant, whether it's an \c{EQU}
864 or the address of a variable; and to access the \e{contents} of the
865 variable \c{bar}, you must code \c{mov ax,[bar]}.
867 This also means that NASM has no need for MASM's \i\c{OFFSET}
868 keyword, since the MASM code \c{mov ax,offset bar} means exactly the
869 same thing as NASM's \c{mov ax,bar}. If you're trying to get
870 large amounts of MASM code to assemble sensibly under NASM, you
871 can always code \c{%idefine offset} to make the preprocessor treat
872 the \c{OFFSET} keyword as a no-op.
874 This issue is even more confusing in \i\c{a86}, where declaring a
875 label with a trailing colon defines it to be a `label' as opposed to
876 a `variable' and causes \c{a86} to adopt NASM-style semantics; so in
877 \c{a86}, \c{mov ax,var} has different behaviour depending on whether
878 \c{var} was declared as \c{var: dw 0} (a label) or \c{var dw 0} (a
879 word-size variable). NASM is very simple by comparison:
880 \e{everything} is a label.
882 NASM, in the interests of simplicity, also does not support the
883 \i{hybrid syntaxes} supported by MASM and its clones, such as
884 \c{mov ax,table[bx]}, where a memory reference is denoted by one
885 portion outside square brackets and another portion inside. The
886 correct syntax for the above is \c{mov ax,[table+bx]}. Likewise,
887 \c{mov ax,es:[di]} is wrong and \c{mov ax,[es:di]} is right.
890 \S{qstypes} NASM Doesn't Store \i{Variable Types}
892 NASM, by design, chooses not to remember the types of variables you
893 declare. Whereas MASM will remember, on seeing \c{var dw 0}, that
894 you declared \c{var} as a word-size variable, and will then be able
895 to fill in the \i{ambiguity} in the size of the instruction \c{mov
896 var,2}, NASM will deliberately remember nothing about the symbol
897 \c{var} except where it begins, and so you must explicitly code
898 \c{mov word [var],2}.
900 For this reason, NASM doesn't support the \c{LODS}, \c{MOVS},
901 \c{STOS}, \c{SCAS}, \c{CMPS}, \c{INS}, or \c{OUTS} instructions,
902 but only supports the forms such as \c{LODSB}, \c{MOVSW}, and
903 \c{SCASD}, which explicitly specify the size of the components of
904 the strings being manipulated.
907 \S{qsassume} NASM Doesn't \i\c{ASSUME}
909 As part of NASM's drive for simplicity, it also does not support the
910 \c{ASSUME} directive. NASM will not keep track of what values you
911 choose to put in your segment registers, and will never
912 \e{automatically} generate a \i{segment override} prefix.
915 \S{qsmodel} NASM Doesn't Support \i{Memory Models}
917 NASM also does not have any directives to support different 16-bit
918 memory models. The programmer has to keep track of which functions
919 are supposed to be called with a \i{far call} and which with a
920 \i{near call}, and is responsible for putting the correct form of
921 \c{RET} instruction (\c{RETN} or \c{RETF}; NASM accepts \c{RET}
922 itself as an alternate form for \c{RETN}); in addition, the
923 programmer is responsible for coding CALL FAR instructions where
924 necessary when calling \e{external} functions, and must also keep
925 track of which external variable definitions are far and which are
929 \S{qsfpu} \i{Floating-Point} Differences
931 NASM uses different names to refer to floating-point registers from
932 MASM: where MASM would call them \c{ST(0)}, \c{ST(1)} and so on, and
933 \i\c{a86} would call them simply \c{0}, \c{1} and so on, NASM
934 chooses to call them \c{st0}, \c{st1} etc.
936 As of version 0.96, NASM now treats the instructions with
937 \i{`nowait'} forms in the same way as MASM-compatible assemblers.
938 The idiosyncratic treatment employed by 0.95 and earlier was based
939 on a misunderstanding by the authors.
942 \S{qsother} Other Differences
944 For historical reasons, NASM uses the keyword \i\c{TWORD} where MASM
945 and compatible assemblers use \i\c{TBYTE}.
947 NASM does not declare \i{uninitialised storage} in the same way as
948 MASM: where a MASM programmer might use \c{stack db 64 dup (?)},
949 NASM requires \c{stack resb 64}, intended to be read as `reserve 64
950 bytes'. For a limited amount of compatibility, since NASM treats
951 \c{?} as a valid character in symbol names, you can code \c{? equ 0}
952 and then writing \c{dw ?} will at least do something vaguely useful.
953 \I\c{RESB}\i\c{DUP} is still not a supported syntax, however.
955 In addition to all of this, macros and directives work completely
956 differently to MASM. See \k{preproc} and \k{directive} for further
960 \C{lang} The NASM Language
962 \H{syntax} Layout of a NASM Source Line
964 Like most assemblers, each NASM source line contains (unless it
965 is a macro, a preprocessor directive or an assembler directive: see
966 \k{preproc} and \k{directive}) some combination of the four fields
968 \c label: instruction operands ; comment
970 As usual, most of these fields are optional; the presence or absence
971 of any combination of a label, an instruction and a comment is allowed.
972 Of course, the operand field is either required or forbidden by the
973 presence and nature of the instruction field.
975 NASM uses backslash (\\) as the line continuation character; if a line
976 ends with backslash, the next line is considered to be a part of the
977 backslash-ended line.
979 NASM places no restrictions on white space within a line: labels may
980 have white space before them, or instructions may have no space
981 before them, or anything. The \i{colon} after a label is also
982 optional. (Note that this means that if you intend to code \c{lodsb}
983 alone on a line, and type \c{lodab} by accident, then that's still a
984 valid source line which does nothing but define a label. Running
985 NASM with the command-line option
986 \I{orphan-labels}\c{-w+orphan-labels} will cause it to warn you if
987 you define a label alone on a line without a \i{trailing colon}.)
989 \i{Valid characters} in labels are letters, numbers, \c{_}, \c{$},
990 \c{#}, \c{@}, \c{~}, \c{.}, and \c{?}. The only characters which may
991 be used as the \e{first} character of an identifier are letters,
992 \c{.} (with special meaning: see \k{locallab}), \c{_} and \c{?}.
993 An identifier may also be prefixed with a \I{$, prefix}\c{$} to
994 indicate that it is intended to be read as an identifier and not a
995 reserved word; thus, if some other module you are linking with
996 defines a symbol called \c{eax}, you can refer to \c{$eax} in NASM
997 code to distinguish the symbol from the register.
999 The instruction field may contain any machine instruction: Pentium
1000 and P6 instructions, FPU instructions, MMX instructions and even
1001 undocumented instructions are all supported. The instruction may be
1002 prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or
1003 \c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size
1004 prefixes}address-size and \i{operand-size prefixes} \c{A16},
1005 \c{A32}, \c{O16} and \c{O32} are provided - one example of their use
1006 is given in \k{mixsize}. You can also use the name of a \I{segment
1007 override}segment register as an instruction prefix: coding
1008 \c{es mov [bx],ax} is equivalent to coding \c{mov [es:bx],ax}. We
1009 recommend the latter syntax, since it is consistent with other
1010 syntactic features of the language, but for instructions such as
1011 \c{LODSB}, which has no operands and yet can require a segment
1012 override, there is no clean syntactic way to proceed apart from
1015 An instruction is not required to use a prefix: prefixes such as
1016 \c{CS}, \c{A32}, \c{LOCK} or \c{REPE} can appear on a line by
1017 themselves, and NASM will just generate the prefix bytes.
1019 In addition to actual machine instructions, NASM also supports a
1020 number of pseudo-instructions, described in \k{pseudop}.
1022 Instruction \i{operands} may take a number of forms: they can be
1023 registers, described simply by the register name (e.g. \c{ax},
1024 \c{bp}, \c{ebx}, \c{cr0}: NASM does not use the \c{gas}-style
1025 syntax in which register names must be prefixed by a \c{%} sign), or
1026 they can be \i{effective addresses} (see \k{effaddr}), constants
1027 (\k{const}) or expressions (\k{expr}).
1029 For \i{floating-point} instructions, NASM accepts a wide range of
1030 syntaxes: you can use two-operand forms like MASM supports, or you
1031 can use NASM's native single-operand forms in most cases. Details of
1032 all forms of each supported instruction are given in
1033 \k{iref}. For example, you can code:
1035 \c fadd st1 ; this sets st0 := st0 + st1
1036 \c fadd st0,st1 ; so does this
1038 \c fadd st1,st0 ; this sets st1 := st1 + st0
1039 \c fadd to st1 ; so does this
1041 Almost any floating-point instruction that references memory must
1042 use one of the prefixes \i\c{DWORD}, \i\c{QWORD} or \i\c{TWORD} to
1043 indicate what size of \i{memory operand} it refers to.
1046 \H{pseudop} \i{Pseudo-Instructions}
1048 Pseudo-instructions are things which, though not real x86 machine
1049 instructions, are used in the instruction field anyway because
1050 that's the most convenient place to put them. The current
1051 pseudo-instructions are \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and
1052 \i\c{DT}, their \i{uninitialised} counterparts \i\c{RESB},
1053 \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST}, the \i\c{INCBIN}
1054 command, the \i\c{EQU} command, and the \i\c{TIMES} prefix.
1057 \S{db} \c{DB} and friends: Declaring Initialised Data
1059 \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and \i\c{DT} are used, much
1060 as in MASM, to declare initialised data in the output file. They can
1061 be invoked in a wide range of ways:
1062 \I{floating-point}\I{character constant}\I{string constant}
1064 \c db 0x55 ; just the byte 0x55
1065 \c db 0x55,0x56,0x57 ; three bytes in succession
1066 \c db 'a',0x55 ; character constants are OK
1067 \c db 'hello',13,10,'$' ; so are string constants
1068 \c dw 0x1234 ; 0x34 0x12
1069 \c dw 'a' ; 0x41 0x00 (it's just a number)
1070 \c dw 'ab' ; 0x41 0x42 (character constant)
1071 \c dw 'abc' ; 0x41 0x42 0x43 0x00 (string)
1072 \c dd 0x12345678 ; 0x78 0x56 0x34 0x12
1073 \c dd 1.234567e20 ; floating-point constant
1074 \c dq 1.234567e20 ; double-precision float
1075 \c dt 1.234567e20 ; extended-precision float
1077 \c{DQ} and \c{DT} do not accept \i{numeric constants} or string
1078 constants as operands.
1081 \S{resb} \c{RESB} and friends: Declaring \i{Uninitialised} Data
1083 \i\c{RESB}, \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST} are
1084 designed to be used in the BSS section of a module: they declare
1085 \e{uninitialised} storage space. Each takes a single operand, which
1086 is the number of bytes, words, doublewords or whatever to reserve.
1087 As stated in \k{qsother}, NASM does not support the MASM/TASM syntax
1088 of reserving uninitialised space by writing \I\c{?}\c{DW ?} or
1089 similar things: this is what it does instead. The operand to a
1090 \c{RESB}-type pseudo-instruction is a \i\e{critical expression}: see
1095 \c buffer: resb 64 ; reserve 64 bytes
1096 \c wordvar: resw 1 ; reserve a word
1097 \c realarray resq 10 ; array of ten reals
1100 \S{incbin} \i\c{INCBIN}: Including External \i{Binary Files}
1102 \c{INCBIN} is borrowed from the old Amiga assembler \i{DevPac}: it
1103 includes a binary file verbatim into the output file. This can be
1104 handy for (for example) including \i{graphics} and \i{sound} data
1105 directly into a game executable file. It can be called in one of
1108 \c incbin "file.dat" ; include the whole file
1109 \c incbin "file.dat",1024 ; skip the first 1024 bytes
1110 \c incbin "file.dat",1024,512 ; skip the first 1024, and
1111 \c ; actually include at most 512
1114 \S{equ} \i\c{EQU}: Defining Constants
1116 \c{EQU} defines a symbol to a given constant value: when \c{EQU} is
1117 used, the source line must contain a label. The action of \c{EQU} is
1118 to define the given label name to the value of its (only) operand.
1119 This definition is absolute, and cannot change later. So, for
1122 \c message db 'hello, world'
1123 \c msglen equ $-message
1125 defines \c{msglen} to be the constant 12. \c{msglen} may not then be
1126 redefined later. This is not a \i{preprocessor} definition either:
1127 the value of \c{msglen} is evaluated \e{once}, using the value of
1128 \c{$} (see \k{expr} for an explanation of \c{$}) at the point of
1129 definition, rather than being evaluated wherever it is referenced
1130 and using the value of \c{$} at the point of reference. Note that
1131 the operand to an \c{EQU} is also a \i{critical expression}
1135 \S{times} \i\c{TIMES}: \i{Repeating} Instructions or Data
1137 The \c{TIMES} prefix causes the instruction to be assembled multiple
1138 times. This is partly present as NASM's equivalent of the \i\c{DUP}
1139 syntax supported by \i{MASM}-compatible assemblers, in that you can
1142 \c zerobuf: times 64 db 0
1144 or similar things; but \c{TIMES} is more versatile than that. The
1145 argument to \c{TIMES} is not just a numeric constant, but a numeric
1146 \e{expression}, so you can do things like
1148 \c buffer: db 'hello, world'
1149 \c times 64-$+buffer db ' '
1151 which will store exactly enough spaces to make the total length of
1152 \c{buffer} up to 64. Finally, \c{TIMES} can be applied to ordinary
1153 instructions, so you can code trivial \i{unrolled loops} in it:
1157 Note that there is no effective difference between \c{times 100 resb
1158 1} and \c{resb 100}, except that the latter will be assembled about
1159 100 times faster due to the internal structure of the assembler.
1161 The operand to \c{TIMES}, like that of \c{EQU} and those of \c{RESB}
1162 and friends, is a critical expression (\k{crit}).
1164 Note also that \c{TIMES} can't be applied to \i{macros}: the reason
1165 for this is that \c{TIMES} is processed after the macro phase, which
1166 allows the argument to \c{TIMES} to contain expressions such as
1167 \c{64-$+buffer} as above. To repeat more than one line of code, or a
1168 complex macro, use the preprocessor \i\c{%rep} directive.
1171 \H{effaddr} Effective Addresses
1173 An \i{effective address} is any operand to an instruction which
1174 \I{memory reference}references memory. Effective addresses, in NASM,
1175 have a very simple syntax: they consist of an expression evaluating
1176 to the desired address, enclosed in \i{square brackets}. For
1181 \c mov ax,[wordvar+1]
1182 \c mov ax,[es:wordvar+bx]
1184 Anything not conforming to this simple system is not a valid memory
1185 reference in NASM, for example \c{es:wordvar[bx]}.
1187 More complicated effective addresses, such as those involving more
1188 than one register, work in exactly the same way:
1190 \c mov eax,[ebx*2+ecx+offset]
1193 NASM is capable of doing \i{algebra} on these effective addresses,
1194 so that things which don't necessarily \e{look} legal are perfectly
1197 \c mov eax,[ebx*5] ; assembles as [ebx*4+ebx]
1198 \c mov eax,[label1*2-label2] ; ie [label1+(label1-label2)]
1200 Some forms of effective address have more than one assembled form;
1201 in most such cases NASM will generate the smallest form it can. For
1202 example, there are distinct assembled forms for the 32-bit effective
1203 addresses \c{[eax*2+0]} and \c{[eax+eax]}, and NASM will generally
1204 generate the latter on the grounds that the former requires four
1205 bytes to store a zero offset.
1207 NASM has a hinting mechanism which will cause \c{[eax+ebx]} and
1208 \c{[ebx+eax]} to generate different opcodes; this is occasionally
1209 useful because \c{[esi+ebp]} and \c{[ebp+esi]} have different
1210 default segment registers.
1212 However, you can force NASM to generate an effective address in a
1213 particular form by the use of the keywords \c{BYTE}, \c{WORD},
1214 \c{DWORD} and \c{NOSPLIT}. If you need \c{[eax+3]} to be assembled
1215 using a double-word offset field instead of the one byte NASM will
1216 normally generate, you can code \c{[dword eax+3]}. Similarly, you
1217 can force NASM to use a byte offset for a small value which it
1218 hasn't seen on the first pass (see \k{crit} for an example of such a
1219 code fragment) by using \c{[byte eax+offset]}. As special cases,
1220 \c{[byte eax]} will code \c{[eax+0]} with a byte offset of zero, and
1221 \c{[dword eax]} will code it with a double-word offset of zero. The
1222 normal form, \c{[eax]}, will be coded with no offset field.
1224 The form described in the previous paragraph is also useful if you
1225 are trying to access data in a 32-bit segment from within 16 bit code.
1226 For more information on this see the section on mixed-size addressing
1227 (\k{mixaddr}). In particular, if you need to access data with a known
1228 offset that is larger than will fit in a 16-bit value, if you don't
1229 specify that it is a dword offset, nasm will cause the high word of
1230 the offset to be lost.
1232 Similarly, NASM will split \c{[eax*2]} into \c{[eax+eax]} because
1233 that allows the offset field to be absent and space to be saved; in
1234 fact, it will also split \c{[eax*2+offset]} into
1235 \c{[eax+eax+offset]}. You can combat this behaviour by the use of
1236 the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force
1237 \c{[eax*2+0]} to be generated literally.
1240 \H{const} \i{Constants}
1242 NASM understands four different types of constant: numeric,
1243 character, string and floating-point.
1246 \S{numconst} \i{Numeric Constants}
1248 A numeric constant is simply a number. NASM allows you to specify
1249 numbers in a variety of number bases, in a variety of ways: you can
1250 suffix \c{H}, \c{Q} and \c{B} for \i{hex}, \i{octal} and \i{binary},
1251 or you can prefix \c{0x} for hex in the style of C, or you can
1252 prefix \c{$} for hex in the style of Borland Pascal. Note, though,
1253 that the \I{$, prefix}\c{$} prefix does double duty as a prefix on
1254 identifiers (see \k{syntax}), so a hex number prefixed with a \c{$}
1255 sign must have a digit after the \c{$} rather than a letter.
1259 \c mov ax,100 ; decimal
1260 \c mov ax,0a2h ; hex
1261 \c mov ax,$0a2 ; hex again: the 0 is required
1262 \c mov ax,0xa2 ; hex yet again
1263 \c mov ax,777q ; octal
1264 \c mov ax,10010011b ; binary
1267 \S{chrconst} \i{Character Constants}
1269 A character constant consists of up to four characters enclosed in
1270 either single or double quotes. The type of quote makes no
1271 difference to NASM, except of course that surrounding the constant
1272 with single quotes allows double quotes to appear within it and vice
1275 A character constant with more than one character will be arranged
1276 with \i{little-endian} order in mind: if you code
1280 then the constant generated is not \c{0x61626364}, but
1281 \c{0x64636261}, so that if you were then to store the value into
1282 memory, it would read \c{abcd} rather than \c{dcba}. This is also
1283 the sense of character constants understood by the Pentium's
1284 \i\c{CPUID} instruction (see \k{insCPUID}).
1287 \S{strconst} String Constants
1289 String constants are only acceptable to some pseudo-instructions,
1290 namely the \I\c{DW}\I\c{DD}\I\c{DQ}\I\c{DT}\i\c{DB} family and
1293 A string constant looks like a character constant, only longer. It
1294 is treated as a concatenation of maximum-size character constants
1295 for the conditions. So the following are equivalent:
1297 \c db 'hello' ; string constant
1298 \c db 'h','e','l','l','o' ; equivalent character constants
1300 And the following are also equivalent:
1302 \c dd 'ninechars' ; doubleword string constant
1303 \c dd 'nine','char','s' ; becomes three doublewords
1304 \c db 'ninechars',0,0,0 ; and really looks like this
1306 Note that when used as an operand to \c{db}, a constant like
1307 \c{'ab'} is treated as a string constant despite being short enough
1308 to be a character constant, because otherwise \c{db 'ab'} would have
1309 the same effect as \c{db 'a'}, which would be silly. Similarly,
1310 three-character or four-character constants are treated as strings
1311 when they are operands to \c{dw}.
1314 \S{fltconst} \I{floating-point, constants}Floating-Point Constants
1316 \i{Floating-point} constants are acceptable only as arguments to
1317 \i\c{DD}, \i\c{DQ} and \i\c{DT}. They are expressed in the
1318 traditional form: digits, then a period, then optionally more
1319 digits, then optionally an \c{E} followed by an exponent. The period
1320 is mandatory, so that NASM can distinguish between \c{dd 1}, which
1321 declares an integer constant, and \c{dd 1.0} which declares a
1322 floating-point constant.
1326 \c dd 1.2 ; an easy one
1327 \c dq 1.e10 ; 10,000,000,000
1328 \c dq 1.e+10 ; synonymous with 1.e10
1329 \c dq 1.e-10 ; 0.000 000 000 1
1330 \c dt 3.141592653589793238462 ; pi
1332 NASM cannot do compile-time arithmetic on floating-point constants.
1333 This is because NASM is designed to be portable - although it always
1334 generates code to run on x86 processors, the assembler itself can
1335 run on any system with an ANSI C compiler. Therefore, the assembler
1336 cannot guarantee the presence of a floating-point unit capable of
1337 handling the \i{Intel number formats}, and so for NASM to be able to
1338 do floating arithmetic it would have to include its own complete set
1339 of floating-point routines, which would significantly increase the
1340 size of the assembler for very little benefit.
1343 \H{expr} \i{Expressions}
1345 Expressions in NASM are similar in syntax to those in C.
1347 NASM does not guarantee the size of the integers used to evaluate
1348 expressions at compile time: since NASM can compile and run on
1349 64-bit systems quite happily, don't assume that expressions are
1350 evaluated in 32-bit registers and so try to make deliberate use of
1351 \i{integer overflow}. It might not always work. The only thing NASM
1352 will guarantee is what's guaranteed by ANSI C: you always have \e{at
1353 least} 32 bits to work in.
1355 NASM supports two special tokens in expressions, allowing
1356 calculations to involve the current assembly position: the
1357 \I{$, here}\c{$} and \i\c{$$} tokens. \c{$} evaluates to the assembly
1358 position at the beginning of the line containing the expression; so
1359 you can code an \i{infinite loop} using \c{JMP $}. \c{$$} evaluates
1360 to the beginning of the current section; so you can tell how far
1361 into the section you are by using \c{($-$$)}.
1363 The arithmetic \i{operators} provided by NASM are listed here, in
1364 increasing order of \i{precedence}.
1367 \S{expor} \i\c{|}: \i{Bitwise OR} Operator
1369 The \c{|} operator gives a bitwise OR, exactly as performed by the
1370 \c{OR} machine instruction. Bitwise OR is the lowest-priority
1371 arithmetic operator supported by NASM.
1374 \S{expxor} \i\c{^}: \i{Bitwise XOR} Operator
1376 \c{^} provides the bitwise XOR operation.
1379 \S{expand} \i\c{&}: \i{Bitwise AND} Operator
1381 \c{&} provides the bitwise AND operation.
1384 \S{expshift} \i\c{<<} and \i\c{>>}: \i{Bit Shift} Operators
1386 \c{<<} gives a bit-shift to the left, just as it does in C. So \c{5<<3}
1387 evaluates to 5 times 8, or 40. \c{>>} gives a bit-shift to the
1388 right; in NASM, such a shift is \e{always} unsigned, so that
1389 the bits shifted in from the left-hand end are filled with zero
1390 rather than a sign-extension of the previous highest bit.
1393 \S{expplmi} \I{+ opaddition}\c{+} and \I{- opsubtraction}\c{-}:
1394 \i{Addition} and \i{Subtraction} Operators
1396 The \c{+} and \c{-} operators do perfectly ordinary addition and
1400 \S{expmul} \i\c{*}, \i\c{/}, \i\c{//}, \i\c{%} and \i\c{%%}:
1401 \i{Multiplication} and \i{Division}
1403 \c{*} is the multiplication operator. \c{/} and \c{//} are both
1404 division operators: \c{/} is \i{unsigned division} and \c{//} is
1405 \i{signed division}. Similarly, \c{%} and \c{%%} provide \I{unsigned
1406 modulo}\I{modulo operators}unsigned and
1407 \i{signed modulo} operators respectively.
1409 NASM, like ANSI C, provides no guarantees about the sensible
1410 operation of the signed modulo operator.
1412 Since the \c{%} character is used extensively by the macro
1413 \i{preprocessor}, you should ensure that both the signed and unsigned
1414 modulo operators are followed by white space wherever they appear.
1417 \S{expmul} \i{Unary Operators}: \I{+ opunary}\c{+}, \I{- opunary}\c{-},
1418 \i\c{~} and \i\c{SEG}
1420 The highest-priority operators in NASM's expression grammar are
1421 those which only apply to one argument. \c{-} negates its operand,
1422 \c{+} does nothing (it's provided for symmetry with \c{-}), \c{~}
1423 computes the \i{one's complement} of its operand, and \c{SEG}
1424 provides the \i{segment address} of its operand (explained in more
1425 detail in \k{segwrt}).
1428 \H{segwrt} \i\c{SEG} and \i\c{WRT}
1430 When writing large 16-bit programs, which must be split into
1431 multiple \i{segments}, it is often necessary to be able to refer to
1432 the \I{segment address}segment part of the address of a symbol. NASM
1433 supports the \c{SEG} operator to perform this function.
1435 The \c{SEG} operator returns the \i\e{preferred} segment base of a
1436 symbol, defined as the segment base relative to which the offset of
1437 the symbol makes sense. So the code
1439 \c mov ax,seg symbol
1443 will load \c{ES:BX} with a valid pointer to the symbol \c{symbol}.
1445 Things can be more complex than this: since 16-bit segments and
1446 \i{groups} may \I{overlapping segments}overlap, you might occasionally
1447 want to refer to some symbol using a different segment base from the
1448 preferred one. NASM lets you do this, by the use of the \c{WRT}
1449 (With Reference To) keyword. So you can do things like
1451 \c mov ax,weird_seg ; weird_seg is a segment base
1453 \c mov bx,symbol wrt weird_seg
1455 to load \c{ES:BX} with a different, but functionally equivalent,
1456 pointer to the symbol \c{symbol}.
1458 NASM supports far (inter-segment) calls and jumps by means of the
1459 syntax \c{call segment:offset}, where \c{segment} and \c{offset}
1460 both represent immediate values. So to call a far procedure, you
1461 could code either of
1463 \c call (seg procedure):procedure
1464 \c call weird_seg:(procedure wrt weird_seg)
1466 (The parentheses are included for clarity, to show the intended
1467 parsing of the above instructions. They are not necessary in
1470 NASM supports the syntax \I\c{CALL FAR}\c{call far procedure} as a
1471 synonym for the first of the above usages. \c{JMP} works identically
1472 to \c{CALL} in these examples.
1474 To declare a \i{far pointer} to a data item in a data segment, you
1477 \c dw symbol, seg symbol
1479 NASM supports no convenient synonym for this, though you can always
1480 invent one using the macro processor.
1483 \H{strict} \i\c{STRICT}: Inhibiting Optimization
1485 When assembling with the optimizer set to level 2 or higher (see
1486 \k{opt-On}), NASM will usee size specifiers (\c{BYTE}, \c{WORD},
1487 \c{DWORD}, \c{QWORD}, or \c{TWORD}), but will give them the smallest
1488 possible size. The keyword \c{STRICT} can be used to inhibit
1489 optimization and force a particular operand to be emitted in the
1490 specified size. For example, with the optimizer on, and in
1495 is encoded in three bytes \c{66 6A 21}, whereas
1497 \c push strict dword 33
1499 is encoded in six bytes, with a full dword immediate operand \c{66 68
1502 With the optimizer off, the same code (six bytes) is generated whether
1503 the \c{STRICT} keyword was used or not.
1506 \H{crit} \i{Critical Expressions}
1508 A limitation of NASM is that it is a \i{two-pass assembler}; unlike
1509 TASM and others, it will always do exactly two \I{passes}\i{assembly
1510 passes}. Therefore it is unable to cope with source files that are
1511 complex enough to require three or more passes.
1513 The first pass is used to determine the size of all the assembled
1514 code and data, so that the second pass, when generating all the
1515 code, knows all the symbol addresses the code refers to. So one
1516 thing NASM can't handle is code whose size depends on the value of a
1517 symbol declared after the code in question. For example,
1519 \c times (label-$) db 0
1520 \c label: db 'Where am I?'
1522 The argument to \i\c{TIMES} in this case could equally legally
1523 evaluate to anything at all; NASM will reject this example because
1524 it cannot tell the size of the \c{TIMES} line when it first sees it.
1525 It will just as firmly reject the slightly \I{paradox}paradoxical
1528 \c times (label-$+1) db 0
1529 \c label: db 'NOW where am I?'
1531 in which \e{any} value for the \c{TIMES} argument is by definition
1534 NASM rejects these examples by means of a concept called a
1535 \e{critical expression}, which is defined to be an expression whose
1536 value is required to be computable in the first pass, and which must
1537 therefore depend only on symbols defined before it. The argument to
1538 the \c{TIMES} prefix is a critical expression; for the same reason,
1539 the arguments to the \i\c{RESB} family of pseudo-instructions are
1540 also critical expressions.
1542 Critical expressions can crop up in other contexts as well: consider
1546 \c symbol1 equ symbol2
1549 On the first pass, NASM cannot determine the value of \c{symbol1},
1550 because \c{symbol1} is defined to be equal to \c{symbol2} which NASM
1551 hasn't seen yet. On the second pass, therefore, when it encounters
1552 the line \c{mov ax,symbol1}, it is unable to generate the code for
1553 it because it still doesn't know the value of \c{symbol1}. On the
1554 next line, it would see the \i\c{EQU} again and be able to determine
1555 the value of \c{symbol1}, but by then it would be too late.
1557 NASM avoids this problem by defining the right-hand side of an
1558 \c{EQU} statement to be a critical expression, so the definition of
1559 \c{symbol1} would be rejected in the first pass.
1561 There is a related issue involving \i{forward references}: consider
1564 \c mov eax,[ebx+offset]
1567 NASM, on pass one, must calculate the size of the instruction \c{mov
1568 eax,[ebx+offset]} without knowing the value of \c{offset}. It has no
1569 way of knowing that \c{offset} is small enough to fit into a
1570 one-byte offset field and that it could therefore get away with
1571 generating a shorter form of the \i{effective-address} encoding; for
1572 all it knows, in pass one, \c{offset} could be a symbol in the code
1573 segment, and it might need the full four-byte form. So it is forced
1574 to compute the size of the instruction to accommodate a four-byte
1575 address part. In pass two, having made this decision, it is now
1576 forced to honour it and keep the instruction large, so the code
1577 generated in this case is not as small as it could have been. This
1578 problem can be solved by defining \c{offset} before using it, or by
1579 forcing byte size in the effective address by coding \c{[byte
1583 \H{locallab} \i{Local Labels}
1585 NASM gives special treatment to symbols beginning with a \i{period}.
1586 A label beginning with a single period is treated as a \e{local}
1587 label, which means that it is associated with the previous non-local
1588 label. So, for example:
1590 \c label1 ; some code
1598 \c label2 ; some code
1606 In the above code fragment, each \c{JNE} instruction jumps to the
1607 line immediately before it, because the two definitions of \c{.loop}
1608 are kept separate by virtue of each being associated with the
1609 previous non-local label.
1611 This form of local label handling is borrowed from the old Amiga
1612 assembler \i{DevPac}; however, NASM goes one step further, in
1613 allowing access to local labels from other parts of the code. This
1614 is achieved by means of \e{defining} a local label in terms of the
1615 previous non-local label: the first definition of \c{.loop} above is
1616 really defining a symbol called \c{label1.loop}, and the second
1617 defines a symbol called \c{label2.loop}. So, if you really needed
1620 \c label3 ; some more code
1625 Sometimes it is useful - in a macro, for instance - to be able to
1626 define a label which can be referenced from anywhere but which
1627 doesn't interfere with the normal local-label mechanism. Such a
1628 label can't be non-local because it would interfere with subsequent
1629 definitions of, and references to, local labels; and it can't be
1630 local because the macro that defined it wouldn't know the label's
1631 full name. NASM therefore introduces a third type of label, which is
1632 probably only useful in macro definitions: if a label begins with
1633 the \I{label prefix}special prefix \i\c{..@}, then it does nothing
1634 to the local label mechanism. So you could code
1636 \c label1: ; a non-local label
1637 \c .local: ; this is really label1.local
1638 \c ..@foo: ; this is a special symbol
1639 \c label2: ; another non-local label
1640 \c .local: ; this is really label2.local
1642 \c jmp ..@foo ; this will jump three lines up
1644 NASM has the capacity to define other special symbols beginning with
1645 a double period: for example, \c{..start} is used to specify the
1646 entry point in the \c{obj} output format (see \k{dotdotstart}).
1649 \C{preproc} The NASM \i{Preprocessor}
1651 NASM contains a powerful \i{macro processor}, which supports
1652 conditional assembly, multi-level file inclusion, two forms of macro
1653 (single-line and multi-line), and a `context stack' mechanism for
1654 extra macro power. Preprocessor directives all begin with a \c{%}
1657 The preprocessor collapses all lines which end with a backslash (\\)
1658 character into a single line. Thus:
1660 \c %define THIS_VERY_LONG_MACRO_NAME_IS_DEFINED_TO \\
1663 will work like a single-line macro without the backslash-newline
1666 \H{slmacro} \i{Single-Line Macros}
1668 \S{define} The Normal Way: \I\c{%idefine}\i\c{%define}
1670 Single-line macros are defined using the \c{%define} preprocessor
1671 directive. The definitions work in a similar way to C; so you can do
1674 \c %define ctrl 0x1F &
1675 \c %define param(a,b) ((a)+(a)*(b))
1677 \c mov byte [param(2,ebx)], ctrl 'D'
1679 which will expand to
1681 \c mov byte [(2)+(2)*(ebx)], 0x1F & 'D'
1683 When the expansion of a single-line macro contains tokens which
1684 invoke another macro, the expansion is performed at invocation time,
1685 not at definition time. Thus the code
1687 \c %define a(x) 1+b(x)
1692 will evaluate in the expected way to \c{mov ax,1+2*8}, even though
1693 the macro \c{b} wasn't defined at the time of definition of \c{a}.
1695 Macros defined with \c{%define} are \i{case sensitive}: after
1696 \c{%define foo bar}, only \c{foo} will expand to \c{bar}: \c{Foo} or
1697 \c{FOO} will not. By using \c{%idefine} instead of \c{%define} (the
1698 `i' stands for `insensitive') you can define all the case variants
1699 of a macro at once, so that \c{%idefine foo bar} would cause
1700 \c{foo}, \c{Foo}, \c{FOO}, \c{fOO} and so on all to expand to
1703 There is a mechanism which detects when a macro call has occurred as
1704 a result of a previous expansion of the same macro, to guard against
1705 \i{circular references} and infinite loops. If this happens, the
1706 preprocessor will only expand the first occurrence of the macro.
1709 \c %define a(x) 1+a(x)
1713 the macro \c{a(3)} will expand once, becoming \c{1+a(3)}, and will
1714 then expand no further. This behaviour can be useful: see \k{32c}
1715 for an example of its use.
1717 You can \I{overloading, single-line macros}overload single-line
1718 macros: if you write
1720 \c %define foo(x) 1+x
1721 \c %define foo(x,y) 1+x*y
1723 the preprocessor will be able to handle both types of macro call,
1724 by counting the parameters you pass; so \c{foo(3)} will become
1725 \c{1+3} whereas \c{foo(ebx,2)} will become \c{1+ebx*2}. However, if
1730 then no other definition of \c{foo} will be accepted: a macro with
1731 no parameters prohibits the definition of the same name as a macro
1732 \e{with} parameters, and vice versa.
1734 This doesn't prevent single-line macros being \e{redefined}: you can
1735 perfectly well define a macro with
1739 and then re-define it later in the same source file with
1743 Then everywhere the macro \c{foo} is invoked, it will be expanded
1744 according to the most recent definition. This is particularly useful
1745 when defining single-line macros with \c{%assign} (see \k{assign}).
1747 You can \i{pre-define} single-line macros using the `-d' option on
1748 the NASM command line: see \k{opt-d}.
1751 \S{concat%+} Concatenating Single Line Macro Tokens: \i\c{%+}
1753 Individual tokens in single line macros can be concatenated, to produce
1754 longer tokens for later processing. This can be useful if there are
1755 several similar macros that perform similar functions.
1757 As an example, consider the following:
1759 \c %define BDASTART 400h ; Start of BIOS data area
1761 \c struc tBIOSDA ; its structure
1767 Now, if we need to access the elements of tBIOSDA in different places,
1770 \c mov ax,BDASTART + tBIOSDA.COM1addr
1771 \c mov bx,BDASTART + tBIOSDA.COM2addr
1773 This will become pretty ugly (and tedious) if used in many places, and
1774 can be reduced in size significantly by using the following macro:
1776 \c ; Macro to access BIOS variables by their names (from tBDA):
1778 \c %define BDA(x) BDASTART + tBIOSDA. %+ x
1780 Now the above code can be written as:
1782 \c mov ax,BDA(COM1addr)
1783 \c mov bx,BDA(COM2addr)
1785 Using this feature, we can simplify references to a lot of macros (and,
1786 in turn, reduce typing errors).
1789 \S{undef} Undefining macros: \i\c{%undef}
1791 Single-line macros can be removed with the \c{%undef} command. For
1792 example, the following sequence:
1799 will expand to the instruction \c{mov eax, foo}, since after
1800 \c{%undef} the macro \c{foo} is no longer defined.
1802 Macros that would otherwise be pre-defined can be undefined on the
1803 command-line using the `-u' option on the NASM command line: see
1807 \S{assign} \i{Preprocessor Variables}: \i\c{%assign}
1809 An alternative way to define single-line macros is by means of the
1810 \c{%assign} command (and its \i{case sensitive}case-insensitive
1811 counterpart \i\c{%iassign}, which differs from \c{%assign} in
1812 exactly the same way that \c{%idefine} differs from \c{%define}).
1814 \c{%assign} is used to define single-line macros which take no
1815 parameters and have a numeric value. This value can be specified in
1816 the form of an expression, and it will be evaluated once, when the
1817 \c{%assign} directive is processed.
1819 Like \c{%define}, macros defined using \c{%assign} can be re-defined
1820 later, so you can do things like
1824 to increment the numeric value of a macro.
1826 \c{%assign} is useful for controlling the termination of \c{%rep}
1827 preprocessor loops: see \k{rep} for an example of this. Another
1828 use for \c{%assign} is given in \k{16c} and \k{32c}.
1830 The expression passed to \c{%assign} is a \i{critical expression}
1831 (see \k{crit}), and must also evaluate to a pure number (rather than
1832 a relocatable reference such as a code or data address, or anything
1833 involving a register).
1836 \H{strlen} \i{String Handling in Macros}: \i\c{%strlen} and \i\c{%substr}
1838 It's often useful to be able to handle strings in macros. NASM
1839 supports two simple string handling macro operators from which
1840 more complex operations can be constructed.
1843 \S{strlen} \i{String Length}: \i\c{%strlen}
1845 The \c{%strlen} macro is like \c{%assign} macro in that it creates
1846 (or redefines) a numeric value to a macro. The difference is that
1847 with \c{%strlen}, the numeric value is the length of a string. An
1848 example of the use of this would be:
1850 \c %strlen charcnt 'my string'
1852 In this example, \c{charcnt} would receive the value 8, just as
1853 if an \c{%assign} had been used. In this example, \c{'my string'}
1854 was a literal string but it could also have been a single-line
1855 macro that expands to a string, as in the following example:
1857 \c %define sometext 'my string'
1858 \c %strlen charcnt sometext
1860 As in the first case, this would result in \c{charcnt} being
1861 assigned the value of 8.
1864 \S{substr} \i{Sub-strings}: \i\c{%substr}
1866 Individual letters in strings can be extracted using \c{%substr}.
1867 An example of its use is probably more useful than the description:
1869 \c %substr mychar 'xyz' 1 ; equivalent to %define mychar 'x'
1870 \c %substr mychar 'xyz' 2 ; equivalent to %define mychar 'y'
1871 \c %substr mychar 'xyz' 3 ; equivalent to %define mychar 'z'
1873 In this example, mychar gets the value of 'y'. As with \c{%strlen}
1874 (see \k{strlen}), the first parameter is the single-line macro to
1875 be created and the second is the string. The third parameter
1876 specifies which character is to be selected. Note that the first
1877 index is 1, not 0 and the last index is equal to the value that
1878 \c{%strlen} would assign given the same string. Index values out
1879 of range result in an empty string.
1882 \H{mlmacro} \i{Multi-Line Macros}: \I\c{%imacro}\i\c{%macro}
1884 Multi-line macros are much more like the type of macro seen in MASM
1885 and TASM: a multi-line macro definition in NASM looks something like
1888 \c %macro prologue 1
1896 This defines a C-like function prologue as a macro: so you would
1897 invoke the macro with a call such as
1899 \c myfunc: prologue 12
1901 which would expand to the three lines of code
1907 The number \c{1} after the macro name in the \c{%macro} line defines
1908 the number of parameters the macro \c{prologue} expects to receive.
1909 The use of \c{%1} inside the macro definition refers to the first
1910 parameter to the macro call. With a macro taking more than one
1911 parameter, subsequent parameters would be referred to as \c{%2},
1914 Multi-line macros, like single-line macros, are \i{case-sensitive},
1915 unless you define them using the alternative directive \c{%imacro}.
1917 If you need to pass a comma as \e{part} of a parameter to a
1918 multi-line macro, you can do that by enclosing the entire parameter
1919 in \I{braces, around macro parameters}braces. So you could code
1928 \c silly 'a', letter_a ; letter_a: db 'a'
1929 \c silly 'ab', string_ab ; string_ab: db 'ab'
1930 \c silly {13,10}, crlf ; crlf: db 13,10
1933 \S{mlmacover} Overloading Multi-Line Macros\I{overloading, multi-line macros}
1935 As with single-line macros, multi-line macros can be overloaded by
1936 defining the same macro name several times with different numbers of
1937 parameters. This time, no exception is made for macros with no
1938 parameters at all. So you could define
1940 \c %macro prologue 0
1947 to define an alternative form of the function prologue which
1948 allocates no local stack space.
1950 Sometimes, however, you might want to `overload' a machine
1951 instruction; for example, you might want to define
1960 so that you could code
1962 \c push ebx ; this line is not a macro call
1963 \c push eax,ecx ; but this one is
1965 Ordinarily, NASM will give a warning for the first of the above two
1966 lines, since \c{push} is now defined to be a macro, and is being
1967 invoked with a number of parameters for which no definition has been
1968 given. The correct code will still be generated, but the assembler
1969 will give a warning. This warning can be disabled by the use of the
1970 \c{-w-macro-params} command-line option (see \k{opt-w}).
1973 \S{maclocal} \i{Macro-Local Labels}
1975 NASM allows you to define labels within a multi-line macro
1976 definition in such a way as to make them local to the macro call: so
1977 calling the same macro multiple times will use a different label
1978 each time. You do this by prefixing \i\c{%%} to the label name. So
1979 you can invent an instruction which executes a \c{RET} if the \c{Z}
1980 flag is set by doing this:
1990 You can call this macro as many times as you want, and every time
1991 you call it NASM will make up a different `real' name to substitute
1992 for the label \c{%%skip}. The names NASM invents are of the form
1993 \c{..@2345.skip}, where the number 2345 changes with every macro
1994 call. The \i\c{..@} prefix prevents macro-local labels from
1995 interfering with the local label mechanism, as described in
1996 \k{locallab}. You should avoid defining your own labels in this form
1997 (the \c{..@} prefix, then a number, then another period) in case
1998 they interfere with macro-local labels.
2001 \S{mlmacgre} \i{Greedy Macro Parameters}
2003 Occasionally it is useful to define a macro which lumps its entire
2004 command line into one parameter definition, possibly after
2005 extracting one or two smaller parameters from the front. An example
2006 might be a macro to write a text string to a file in MS-DOS, where
2007 you might want to be able to write
2009 \c writefile [filehandle],"hello, world",13,10
2011 NASM allows you to define the last parameter of a macro to be
2012 \e{greedy}, meaning that if you invoke the macro with more
2013 parameters than it expects, all the spare parameters get lumped into
2014 the last defined one along with the separating commas. So if you
2017 \c %macro writefile 2+
2023 \c mov cx,%%endstr-%%str
2030 then the example call to \c{writefile} above will work as expected:
2031 the text before the first comma, \c{[filehandle]}, is used as the
2032 first macro parameter and expanded when \c{%1} is referred to, and
2033 all the subsequent text is lumped into \c{%2} and placed after the
2036 The greedy nature of the macro is indicated to NASM by the use of
2037 the \I{+ modifier}\c{+} sign after the parameter count on the
2040 If you define a greedy macro, you are effectively telling NASM how
2041 it should expand the macro given \e{any} number of parameters from
2042 the actual number specified up to infinity; in this case, for
2043 example, NASM now knows what to do when it sees a call to
2044 \c{writefile} with 2, 3, 4 or more parameters. NASM will take this
2045 into account when overloading macros, and will not allow you to
2046 define another form of \c{writefile} taking 4 parameters (for
2049 Of course, the above macro could have been implemented as a
2050 non-greedy macro, in which case the call to it would have had to
2053 \c writefile [filehandle], {"hello, world",13,10}
2055 NASM provides both mechanisms for putting \i{commas in macro
2056 parameters}, and you choose which one you prefer for each macro
2059 See \k{sectmac} for a better way to write the above macro.
2062 \S{mlmacdef} \i{Default Macro Parameters}
2064 NASM also allows you to define a multi-line macro with a \e{range}
2065 of allowable parameter counts. If you do this, you can specify
2066 defaults for \i{omitted parameters}. So, for example:
2068 \c %macro die 0-1 "Painful program death has occurred."
2076 This macro (which makes use of the \c{writefile} macro defined in
2077 \k{mlmacgre}) can be called with an explicit error message, which it
2078 will display on the error output stream before exiting, or it can be
2079 called with no parameters, in which case it will use the default
2080 error message supplied in the macro definition.
2082 In general, you supply a minimum and maximum number of parameters
2083 for a macro of this type; the minimum number of parameters are then
2084 required in the macro call, and then you provide defaults for the
2085 optional ones. So if a macro definition began with the line
2087 \c %macro foobar 1-3 eax,[ebx+2]
2089 then it could be called with between one and three parameters, and
2090 \c{%1} would always be taken from the macro call. \c{%2}, if not
2091 specified by the macro call, would default to \c{eax}, and \c{%3} if
2092 not specified would default to \c{[ebx+2]}.
2094 You may omit parameter defaults from the macro definition, in which
2095 case the parameter default is taken to be blank. This can be useful
2096 for macros which can take a variable number of parameters, since the
2097 \i\c{%0} token (see \k{percent0}) allows you to determine how many
2098 parameters were really passed to the macro call.
2100 This defaulting mechanism can be combined with the greedy-parameter
2101 mechanism; so the \c{die} macro above could be made more powerful,
2102 and more useful, by changing the first line of the definition to
2104 \c %macro die 0-1+ "Painful program death has occurred.",13,10
2106 The maximum parameter count can be infinite, denoted by \c{*}. In
2107 this case, of course, it is impossible to provide a \e{full} set of
2108 default parameters. Examples of this usage are shown in \k{rotate}.
2111 \S{percent0} \i\c{%0}: \I{counting macro parameters}Macro Parameter Counter
2113 For a macro which can take a variable number of parameters, the
2114 parameter reference \c{%0} will return a numeric constant giving the
2115 number of parameters passed to the macro. This can be used as an
2116 argument to \c{%rep} (see \k{rep}) in order to iterate through all
2117 the parameters of a macro. Examples are given in \k{rotate}.
2120 \S{rotate} \i\c{%rotate}: \i{Rotating Macro Parameters}
2122 Unix shell programmers will be familiar with the \I{shift
2123 command}\c{shift} shell command, which allows the arguments passed
2124 to a shell script (referenced as \c{$1}, \c{$2} and so on) to be
2125 moved left by one place, so that the argument previously referenced
2126 as \c{$2} becomes available as \c{$1}, and the argument previously
2127 referenced as \c{$1} is no longer available at all.
2129 NASM provides a similar mechanism, in the form of \c{%rotate}. As
2130 its name suggests, it differs from the Unix \c{shift} in that no
2131 parameters are lost: parameters rotated off the left end of the
2132 argument list reappear on the right, and vice versa.
2134 \c{%rotate} is invoked with a single numeric argument (which may be
2135 an expression). The macro parameters are rotated to the left by that
2136 many places. If the argument to \c{%rotate} is negative, the macro
2137 parameters are rotated to the right.
2139 \I{iterating over macro parameters}So a pair of macros to save and
2140 restore a set of registers might work as follows:
2142 \c %macro multipush 1-*
2151 This macro invokes the \c{PUSH} instruction on each of its arguments
2152 in turn, from left to right. It begins by pushing its first
2153 argument, \c{%1}, then invokes \c{%rotate} to move all the arguments
2154 one place to the left, so that the original second argument is now
2155 available as \c{%1}. Repeating this procedure as many times as there
2156 were arguments (achieved by supplying \c{%0} as the argument to
2157 \c{%rep}) causes each argument in turn to be pushed.
2159 Note also the use of \c{*} as the maximum parameter count,
2160 indicating that there is no upper limit on the number of parameters
2161 you may supply to the \i\c{multipush} macro.
2163 It would be convenient, when using this macro, to have a \c{POP}
2164 equivalent, which \e{didn't} require the arguments to be given in
2165 reverse order. Ideally, you would write the \c{multipush} macro
2166 call, then cut-and-paste the line to where the pop needed to be
2167 done, and change the name of the called macro to \c{multipop}, and
2168 the macro would take care of popping the registers in the opposite
2169 order from the one in which they were pushed.
2171 This can be done by the following definition:
2173 \c %macro multipop 1-*
2182 This macro begins by rotating its arguments one place to the
2183 \e{right}, so that the original \e{last} argument appears as \c{%1}.
2184 This is then popped, and the arguments are rotated right again, so
2185 the second-to-last argument becomes \c{%1}. Thus the arguments are
2186 iterated through in reverse order.
2189 \S{concat} \i{Concatenating Macro Parameters}
2191 NASM can concatenate macro parameters on to other text surrounding
2192 them. This allows you to declare a family of symbols, for example,
2193 in a macro definition. If, for example, you wanted to generate a
2194 table of key codes along with offsets into the table, you could code
2197 \c %macro keytab_entry 2
2199 \c keypos%1 equ $-keytab
2205 \c keytab_entry F1,128+1
2206 \c keytab_entry F2,128+2
2207 \c keytab_entry Return,13
2209 which would expand to
2212 \c keyposF1 equ $-keytab
2214 \c keyposF2 equ $-keytab
2216 \c keyposReturn equ $-keytab
2219 You can just as easily concatenate text on to the other end of a
2220 macro parameter, by writing \c{%1foo}.
2222 If you need to append a \e{digit} to a macro parameter, for example
2223 defining labels \c{foo1} and \c{foo2} when passed the parameter
2224 \c{foo}, you can't code \c{%11} because that would be taken as the
2225 eleventh macro parameter. Instead, you must code
2226 \I{braces, after % sign}\c{%\{1\}1}, which will separate the first
2227 \c{1} (giving the number of the macro parameter) from the second
2228 (literal text to be concatenated to the parameter).
2230 This concatenation can also be applied to other preprocessor in-line
2231 objects, such as macro-local labels (\k{maclocal}) and context-local
2232 labels (\k{ctxlocal}). In all cases, ambiguities in syntax can be
2233 resolved by enclosing everything after the \c{%} sign and before the
2234 literal text in braces: so \c{%\{%foo\}bar} concatenates the text
2235 \c{bar} to the end of the real name of the macro-local label
2236 \c{%%foo}. (This is unnecessary, since the form NASM uses for the
2237 real names of macro-local labels means that the two usages
2238 \c{%\{%foo\}bar} and \c{%%foobar} would both expand to the same
2239 thing anyway; nevertheless, the capability is there.)
2242 \S{mlmaccc} \i{Condition Codes as Macro Parameters}
2244 NASM can give special treatment to a macro parameter which contains
2245 a condition code. For a start, you can refer to the macro parameter
2246 \c{%1} by means of the alternative syntax \i\c{%+1}, which informs
2247 NASM that this macro parameter is supposed to contain a condition
2248 code, and will cause the preprocessor to report an error message if
2249 the macro is called with a parameter which is \e{not} a valid
2252 Far more usefully, though, you can refer to the macro parameter by
2253 means of \i\c{%-1}, which NASM will expand as the \e{inverse}
2254 condition code. So the \c{retz} macro defined in \k{maclocal} can be
2255 replaced by a general \i{conditional-return macro} like this:
2265 This macro can now be invoked using calls like \c{retc ne}, which
2266 will cause the conditional-jump instruction in the macro expansion
2267 to come out as \c{JE}, or \c{retc po} which will make the jump a
2270 The \c{%+1} macro-parameter reference is quite happy to interpret
2271 the arguments \c{CXZ} and \c{ECXZ} as valid condition codes;
2272 however, \c{%-1} will report an error if passed either of these,
2273 because no inverse condition code exists.
2276 \S{nolist} \i{Disabling Listing Expansion}\I\c{.nolist}
2278 When NASM is generating a listing file from your program, it will
2279 generally expand multi-line macros by means of writing the macro
2280 call and then listing each line of the expansion. This allows you to
2281 see which instructions in the macro expansion are generating what
2282 code; however, for some macros this clutters the listing up
2285 NASM therefore provides the \c{.nolist} qualifier, which you can
2286 include in a macro definition to inhibit the expansion of the macro
2287 in the listing file. The \c{.nolist} qualifier comes directly after
2288 the number of parameters, like this:
2290 \c %macro foo 1.nolist
2294 \c %macro bar 1-5+.nolist a,b,c,d,e,f,g,h
2296 \H{condasm} \i{Conditional Assembly}\I\c{%if}
2298 Similarly to the C preprocessor, NASM allows sections of a source
2299 file to be assembled only if certain conditions are met. The general
2300 syntax of this feature looks like this:
2303 \c ; some code which only appears if <condition> is met
2304 \c %elif<condition2>
2305 \c ; only appears if <condition> is not met but <condition2> is
2307 \c ; this appears if neither <condition> nor <condition2> was met
2310 The \i\c{%else} clause is optional, as is the \i\c{%elif} clause.
2311 You can have more than one \c{%elif} clause as well.
2314 \S{ifdef} \i\c{%ifdef}: Testing Single-Line Macro Existence\I{testing,
2315 single-line macro existence}
2317 Beginning a conditional-assembly block with the line \c{%ifdef
2318 MACRO} will assemble the subsequent code if, and only if, a
2319 single-line macro called \c{MACRO} is defined. If not, then the
2320 \c{%elif} and \c{%else} blocks (if any) will be processed instead.
2322 For example, when debugging a program, you might want to write code
2325 \c ; perform some function
2327 \c writefile 2,"Function performed successfully",13,10
2329 \c ; go and do something else
2331 Then you could use the command-line option \c{-dDEBUG} to create a
2332 version of the program which produced debugging messages, and remove
2333 the option to generate the final release version of the program.
2335 You can test for a macro \e{not} being defined by using
2336 \i\c{%ifndef} instead of \c{%ifdef}. You can also test for macro
2337 definitions in \c{%elif} blocks by using \i\c{%elifdef} and
2341 \S{ifmacro} \i\c{ifmacro}: Testing Multi-Line Macro
2342 Existence\I{testing, multi-line macro existence}
2344 The \c{%ifmacro} directive operates in the same way as the \c{%ifdef}
2345 directive, except that it checks for the existence of a multi-line macro.
2347 For example, you may be working with a large project and not have control
2348 over the macros in a library. You may want to create a macro with one
2349 name if it doesn't already exist, and another name if one with that name
2352 The \c{%ifmacro} is considered true if defining a macro with the given name
2353 and number of arguments would cause a definitions conflict. For example:
2355 \c %ifmacro MyMacro 1-3
2357 \c %error "MyMacro 1-3" causes a conflict with an existing macro.
2361 \c %macro MyMacro 1-3
2363 \c ; insert code to define the macro
2369 This will create the macro "MyMacro 1-3" if no macro already exists which
2370 would conflict with it, and emits a warning if there would be a definition
2373 You can test for the macro not existing by using the \i\c{%ifnmacro} instead
2374 of \c{%ifmacro}. Additional tests can be performed in \c{%elif} blocks by using
2375 \i\c{%elifmacro} and \i\c{%elifnmacro}.
2378 \S{ifctx} \i\c{%ifctx}: Testing the Context Stack\I{testing, context
2381 The conditional-assembly construct \c{%ifctx ctxname} will cause the
2382 subsequent code to be assembled if and only if the top context on
2383 the preprocessor's context stack has the name \c{ctxname}. As with
2384 \c{%ifdef}, the inverse and \c{%elif} forms \i\c{%ifnctx},
2385 \i\c{%elifctx} and \i\c{%elifnctx} are also supported.
2387 For more details of the context stack, see \k{ctxstack}. For a
2388 sample use of \c{%ifctx}, see \k{blockif}.
2391 \S{if} \i\c{%if}: Testing Arbitrary Numeric Expressions\I{testing,
2392 arbitrary numeric expressions}
2394 The conditional-assembly construct \c{%if expr} will cause the
2395 subsequent code to be assembled if and only if the value of the
2396 numeric expression \c{expr} is non-zero. An example of the use of
2397 this feature is in deciding when to break out of a \c{%rep}
2398 preprocessor loop: see \k{rep} for a detailed example.
2400 The expression given to \c{%if}, and its counterpart \i\c{%elif}, is
2401 a critical expression (see \k{crit}).
2403 \c{%if} extends the normal NASM expression syntax, by providing a
2404 set of \i{relational operators} which are not normally available in
2405 expressions. The operators \i\c{=}, \i\c{<}, \i\c{>}, \i\c{<=},
2406 \i\c{>=} and \i\c{<>} test equality, less-than, greater-than,
2407 less-or-equal, greater-or-equal and not-equal respectively. The
2408 C-like forms \i\c{==} and \i\c{!=} are supported as alternative
2409 forms of \c{=} and \c{<>}. In addition, low-priority logical
2410 operators \i\c{&&}, \i\c{^^} and \i\c{||} are provided, supplying
2411 \i{logical AND}, \i{logical XOR} and \i{logical OR}. These work like
2412 the C logical operators (although C has no logical XOR), in that
2413 they always return either 0 or 1, and treat any non-zero input as 1
2414 (so that \c{^^}, for example, returns 1 if exactly one of its inputs
2415 is zero, and 0 otherwise). The relational operators also return 1
2416 for true and 0 for false.
2419 \S{ifidn} \i\c{%ifidn} and \i\c{%ifidni}: Testing Exact Text
2420 Identity\I{testing, exact text identity}
2422 The construct \c{%ifidn text1,text2} will cause the subsequent code
2423 to be assembled if and only if \c{text1} and \c{text2}, after
2424 expanding single-line macros, are identical pieces of text.
2425 Differences in white space are not counted.
2427 \c{%ifidni} is similar to \c{%ifidn}, but is \i{case-insensitive}.
2429 For example, the following macro pushes a register or number on the
2430 stack, and allows you to treat \c{IP} as a real register:
2432 \c %macro pushparam 1
2443 Like most other \c{%if} constructs, \c{%ifidn} has a counterpart
2444 \i\c{%elifidn}, and negative forms \i\c{%ifnidn} and \i\c{%elifnidn}.
2445 Similarly, \c{%ifidni} has counterparts \i\c{%elifidni},
2446 \i\c{%ifnidni} and \i\c{%elifnidni}.
2449 \S{iftyp} \i\c{%ifid}, \i\c{%ifnum}, \i\c{%ifstr}: Testing Token
2450 Types\I{testing, token types}
2452 Some macros will want to perform different tasks depending on
2453 whether they are passed a number, a string, or an identifier. For
2454 example, a string output macro might want to be able to cope with
2455 being passed either a string constant or a pointer to an existing
2458 The conditional assembly construct \c{%ifid}, taking one parameter
2459 (which may be blank), assembles the subsequent code if and only if
2460 the first token in the parameter exists and is an identifier.
2461 \c{%ifnum} works similarly, but tests for the token being a numeric
2462 constant; \c{%ifstr} tests for it being a string.
2464 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
2465 extended to take advantage of \c{%ifstr} in the following fashion:
2467 \c %macro writefile 2-3+
2476 \c %%endstr: mov dx,%%str
2477 \c mov cx,%%endstr-%%str
2488 Then the \c{writefile} macro can cope with being called in either of
2489 the following two ways:
2491 \c writefile [file], strpointer, length
2492 \c writefile [file], "hello", 13, 10
2494 In the first, \c{strpointer} is used as the address of an
2495 already-declared string, and \c{length} is used as its length; in
2496 the second, a string is given to the macro, which therefore declares
2497 it itself and works out the address and length for itself.
2499 Note the use of \c{%if} inside the \c{%ifstr}: this is to detect
2500 whether the macro was passed two arguments (so the string would be a
2501 single string constant, and \c{db %2} would be adequate) or more (in
2502 which case, all but the first two would be lumped together into
2503 \c{%3}, and \c{db %2,%3} would be required).
2505 \I\c{%ifnid}\I\c{%elifid}\I\c{%elifnid}\I\c{%ifnnum}\I\c{%elifnum}
2506 \I\c{%elifnnum}\I\c{%ifnstr}\I\c{%elifstr}\I\c{%elifnstr}
2507 The usual \c{%elifXXX}, \c{%ifnXXX} and \c{%elifnXXX} versions exist
2508 for each of \c{%ifid}, \c{%ifnum} and \c{%ifstr}.
2511 \S{pperror} \i\c{%error}: Reporting \i{User-Defined Errors}
2513 The preprocessor directive \c{%error} will cause NASM to report an
2514 error if it occurs in assembled code. So if other users are going to
2515 try to assemble your source files, you can ensure that they define
2516 the right macros by means of code like this:
2518 \c %ifdef SOME_MACRO
2520 \c %elifdef SOME_OTHER_MACRO
2521 \c ; do some different setup
2523 \c %error Neither SOME_MACRO nor SOME_OTHER_MACRO was defined.
2526 Then any user who fails to understand the way your code is supposed
2527 to be assembled will be quickly warned of their mistake, rather than
2528 having to wait until the program crashes on being run and then not
2529 knowing what went wrong.
2532 \H{rep} \i{Preprocessor Loops}\I{repeating code}: \i\c{%rep}
2534 NASM's \c{TIMES} prefix, though useful, cannot be used to invoke a
2535 multi-line macro multiple times, because it is processed by NASM
2536 after macros have already been expanded. Therefore NASM provides
2537 another form of loop, this time at the preprocessor level: \c{%rep}.
2539 The directives \c{%rep} and \i\c{%endrep} (\c{%rep} takes a numeric
2540 argument, which can be an expression; \c{%endrep} takes no
2541 arguments) can be used to enclose a chunk of code, which is then
2542 replicated as many times as specified by the preprocessor:
2546 \c inc word [table+2*i]
2550 This will generate a sequence of 64 \c{INC} instructions,
2551 incrementing every word of memory from \c{[table]} to
2554 For more complex termination conditions, or to break out of a repeat
2555 loop part way along, you can use the \i\c{%exitrep} directive to
2556 terminate the loop, like this:
2571 \c fib_number equ ($-fibonacci)/2
2573 This produces a list of all the Fibonacci numbers that will fit in
2574 16 bits. Note that a maximum repeat count must still be given to
2575 \c{%rep}. This is to prevent the possibility of NASM getting into an
2576 infinite loop in the preprocessor, which (on multitasking or
2577 multi-user systems) would typically cause all the system memory to
2578 be gradually used up and other applications to start crashing.
2581 \H{include} \i{Including Other Files}
2583 Using, once again, a very similar syntax to the C preprocessor,
2584 NASM's preprocessor lets you include other source files into your
2585 code. This is done by the use of the \i\c{%include} directive:
2587 \c %include "macros.mac"
2589 will include the contents of the file \c{macros.mac} into the source
2590 file containing the \c{%include} directive.
2592 Include files are \I{searching for include files}searched for in the
2593 current directory (the directory you're in when you run NASM, as
2594 opposed to the location of the NASM executable or the location of
2595 the source file), plus any directories specified on the NASM command
2596 line using the \c{-i} option.
2598 The standard C idiom for preventing a file being included more than
2599 once is just as applicable in NASM: if the file \c{macros.mac} has
2602 \c %ifndef MACROS_MAC
2603 \c %define MACROS_MAC
2604 \c ; now define some macros
2607 then including the file more than once will not cause errors,
2608 because the second time the file is included nothing will happen
2609 because the macro \c{MACROS_MAC} will already be defined.
2611 You can force a file to be included even if there is no \c{%include}
2612 directive that explicitly includes it, by using the \i\c{-p} option
2613 on the NASM command line (see \k{opt-p}).
2616 \H{ctxstack} The \i{Context Stack}
2618 Having labels that are local to a macro definition is sometimes not
2619 quite powerful enough: sometimes you want to be able to share labels
2620 between several macro calls. An example might be a \c{REPEAT} ...
2621 \c{UNTIL} loop, in which the expansion of the \c{REPEAT} macro
2622 would need to be able to refer to a label which the \c{UNTIL} macro
2623 had defined. However, for such a macro you would also want to be
2624 able to nest these loops.
2626 NASM provides this level of power by means of a \e{context stack}.
2627 The preprocessor maintains a stack of \e{contexts}, each of which is
2628 characterised by a name. You add a new context to the stack using
2629 the \i\c{%push} directive, and remove one using \i\c{%pop}. You can
2630 define labels that are local to a particular context on the stack.
2633 \S{pushpop} \i\c{%push} and \i\c{%pop}: \I{creating
2634 contexts}\I{removing contexts}Creating and Removing Contexts
2636 The \c{%push} directive is used to create a new context and place it
2637 on the top of the context stack. \c{%push} requires one argument,
2638 which is the name of the context. For example:
2642 This pushes a new context called \c{foobar} on the stack. You can
2643 have several contexts on the stack with the same name: they can
2644 still be distinguished.
2646 The directive \c{%pop}, requiring no arguments, removes the top
2647 context from the context stack and destroys it, along with any
2648 labels associated with it.
2651 \S{ctxlocal} \i{Context-Local Labels}
2653 Just as the usage \c{%%foo} defines a label which is local to the
2654 particular macro call in which it is used, the usage \I{%$}\c{%$foo}
2655 is used to define a label which is local to the context on the top
2656 of the context stack. So the \c{REPEAT} and \c{UNTIL} example given
2657 above could be implemented by means of:
2673 and invoked by means of, for example,
2681 which would scan every fourth byte of a string in search of the byte
2684 If you need to define, or access, labels local to the context
2685 \e{below} the top one on the stack, you can use \I{%$$}\c{%$$foo}, or
2686 \c{%$$$foo} for the context below that, and so on.
2689 \S{ctxdefine} \i{Context-Local Single-Line Macros}
2691 NASM also allows you to define single-line macros which are local to
2692 a particular context, in just the same way:
2694 \c %define %$localmac 3
2696 will define the single-line macro \c{%$localmac} to be local to the
2697 top context on the stack. Of course, after a subsequent \c{%push},
2698 it can then still be accessed by the name \c{%$$localmac}.
2701 \S{ctxrepl} \i\c{%repl}: \I{renaming contexts}Renaming a Context
2703 If you need to change the name of the top context on the stack (in
2704 order, for example, to have it respond differently to \c{%ifctx}),
2705 you can execute a \c{%pop} followed by a \c{%push}; but this will
2706 have the side effect of destroying all context-local labels and
2707 macros associated with the context that was just popped.
2709 NASM provides the directive \c{%repl}, which \e{replaces} a context
2710 with a different name, without touching the associated macros and
2711 labels. So you could replace the destructive code
2716 with the non-destructive version \c{%repl newname}.
2719 \S{blockif} Example Use of the \i{Context Stack}: \i{Block IFs}
2721 This example makes use of almost all the context-stack features,
2722 including the conditional-assembly construct \i\c{%ifctx}, to
2723 implement a block IF statement as a set of macros.
2739 \c %error "expected `if' before `else'"
2753 \c %error "expected `if' or `else' before `endif'"
2758 This code is more robust than the \c{REPEAT} and \c{UNTIL} macros
2759 given in \k{ctxlocal}, because it uses conditional assembly to check
2760 that the macros are issued in the right order (for example, not
2761 calling \c{endif} before \c{if}) and issues a \c{%error} if they're
2764 In addition, the \c{endif} macro has to be able to cope with the two
2765 distinct cases of either directly following an \c{if}, or following
2766 an \c{else}. It achieves this, again, by using conditional assembly
2767 to do different things depending on whether the context on top of
2768 the stack is \c{if} or \c{else}.
2770 The \c{else} macro has to preserve the context on the stack, in
2771 order to have the \c{%$ifnot} referred to by the \c{if} macro be the
2772 same as the one defined by the \c{endif} macro, but has to change
2773 the context's name so that \c{endif} will know there was an
2774 intervening \c{else}. It does this by the use of \c{%repl}.
2776 A sample usage of these macros might look like:
2798 The block-\c{IF} macros handle nesting quite happily, by means of
2799 pushing another context, describing the inner \c{if}, on top of the
2800 one describing the outer \c{if}; thus \c{else} and \c{endif} always
2801 refer to the last unmatched \c{if} or \c{else}.
2804 \H{stdmac} \i{Standard Macros}
2806 NASM defines a set of standard macros, which are already defined
2807 when it starts to process any source file. If you really need a
2808 program to be assembled with no pre-defined macros, you can use the
2809 \i\c{%clear} directive to empty the preprocessor of everything.
2811 Most \i{user-level assembler directives} (see \k{directive}) are
2812 implemented as macros which invoke primitive directives; these are
2813 described in \k{directive}. The rest of the standard macro set is
2817 \S{stdmacver} \i\c{__NASM_MAJOR__}, \i\c{__NASM_MINOR__} and
2818 \i\c{__NASM_SUBMINOR__}: \i{NASM Version}
2820 The single-line macros \c{__NASM_MAJOR__}, \c{__NASM_MINOR__} and
2821 \c{__NASM_SUBMINOR__} expand to the major, minor and subminor parts of
2822 the \i{version number of NASM} being used. So, under NASM 0.98.31 for
2823 example, \c{__NASM_MAJOR__} would be defined to be 0, \c{__NASM_MINOR__}
2824 would be defined as 98 and \c{__NASM_SUBMINOR__} would be defined to 31.
2827 \S{stdmacverstr} \i\c{__NASM_VER__}: \i{NASM Version string}
2829 The single-line macro \c{__NASM_VER__} expands to a string which defines
2830 the version number of nasm being used. So, under NASM 0.98.31 for example,
2839 \S{fileline} \i\c{__FILE__} and \i\c{__LINE__}: File Name and Line Number
2841 Like the C preprocessor, NASM allows the user to find out the file
2842 name and line number containing the current instruction. The macro
2843 \c{__FILE__} expands to a string constant giving the name of the
2844 current input file (which may change through the course of assembly
2845 if \c{%include} directives are used), and \c{__LINE__} expands to a
2846 numeric constant giving the current line number in the input file.
2848 These macros could be used, for example, to communicate debugging
2849 information to a macro, since invoking \c{__LINE__} inside a macro
2850 definition (either single-line or multi-line) will return the line
2851 number of the macro \e{call}, rather than \e{definition}. So to
2852 determine where in a piece of code a crash is occurring, for
2853 example, one could write a routine \c{stillhere}, which is passed a
2854 line number in \c{EAX} and outputs something like `line 155: still
2855 here'. You could then write a macro
2857 \c %macro notdeadyet 0
2866 and then pepper your code with calls to \c{notdeadyet} until you
2867 find the crash point.
2870 \S{struc} \i\c{STRUC} and \i\c{ENDSTRUC}: \i{Declaring Structure} Data Types
2872 The core of NASM contains no intrinsic means of defining data
2873 structures; instead, the preprocessor is sufficiently powerful that
2874 data structures can be implemented as a set of macros. The macros
2875 \c{STRUC} and \c{ENDSTRUC} are used to define a structure data type.
2877 \c{STRUC} takes one parameter, which is the name of the data type.
2878 This name is defined as a symbol with the value zero, and also has
2879 the suffix \c{_size} appended to it and is then defined as an
2880 \c{EQU} giving the size of the structure. Once \c{STRUC} has been
2881 issued, you are defining the structure, and should define fields
2882 using the \c{RESB} family of pseudo-instructions, and then invoke
2883 \c{ENDSTRUC} to finish the definition.
2885 For example, to define a structure called \c{mytype} containing a
2886 longword, a word, a byte and a string of bytes, you might code
2897 The above code defines six symbols: \c{mt_long} as 0 (the offset
2898 from the beginning of a \c{mytype} structure to the longword field),
2899 \c{mt_word} as 4, \c{mt_byte} as 6, \c{mt_str} as 7, \c{mytype_size}
2900 as 39, and \c{mytype} itself as zero.
2902 The reason why the structure type name is defined at zero is a side
2903 effect of allowing structures to work with the local label
2904 mechanism: if your structure members tend to have the same names in
2905 more than one structure, you can define the above structure like this:
2916 This defines the offsets to the structure fields as \c{mytype.long},
2917 \c{mytype.word}, \c{mytype.byte} and \c{mytype.str}.
2919 NASM, since it has no \e{intrinsic} structure support, does not
2920 support any form of period notation to refer to the elements of a
2921 structure once you have one (except the above local-label notation),
2922 so code such as \c{mov ax,[mystruc.mt_word]} is not valid.
2923 \c{mt_word} is a constant just like any other constant, so the
2924 correct syntax is \c{mov ax,[mystruc+mt_word]} or \c{mov
2925 ax,[mystruc+mytype.word]}.
2928 \S{istruc} \i\c{ISTRUC}, \i\c{AT} and \i\c{IEND}: Declaring
2929 \i{Instances of Structures}
2931 Having defined a structure type, the next thing you typically want
2932 to do is to declare instances of that structure in your data
2933 segment. NASM provides an easy way to do this in the \c{ISTRUC}
2934 mechanism. To declare a structure of type \c{mytype} in a program,
2935 you code something like this:
2940 \c at mt_long, dd 123456
2941 \c at mt_word, dw 1024
2942 \c at mt_byte, db 'x'
2943 \c at mt_str, db 'hello, world', 13, 10, 0
2947 The function of the \c{AT} macro is to make use of the \c{TIMES}
2948 prefix to advance the assembly position to the correct point for the
2949 specified structure field, and then to declare the specified data.
2950 Therefore the structure fields must be declared in the same order as
2951 they were specified in the structure definition.
2953 If the data to go in a structure field requires more than one source
2954 line to specify, the remaining source lines can easily come after
2955 the \c{AT} line. For example:
2957 \c at mt_str, db 123,134,145,156,167,178,189
2960 Depending on personal taste, you can also omit the code part of the
2961 \c{AT} line completely, and start the structure field on the next
2965 \c db 'hello, world'
2969 \S{align} \i\c{ALIGN} and \i\c{ALIGNB}: Data Alignment
2971 The \c{ALIGN} and \c{ALIGNB} macros provides a convenient way to
2972 align code or data on a word, longword, paragraph or other boundary.
2973 (Some assemblers call this directive \i\c{EVEN}.) The syntax of the
2974 \c{ALIGN} and \c{ALIGNB} macros is
2976 \c align 4 ; align on 4-byte boundary
2977 \c align 16 ; align on 16-byte boundary
2978 \c align 8,db 0 ; pad with 0s rather than NOPs
2979 \c align 4,resb 1 ; align to 4 in the BSS
2980 \c alignb 4 ; equivalent to previous line
2982 Both macros require their first argument to be a power of two; they
2983 both compute the number of additional bytes required to bring the
2984 length of the current section up to a multiple of that power of two,
2985 and then apply the \c{TIMES} prefix to their second argument to
2986 perform the alignment.
2988 If the second argument is not specified, the default for \c{ALIGN}
2989 is \c{NOP}, and the default for \c{ALIGNB} is \c{RESB 1}. So if the
2990 second argument is specified, the two macros are equivalent.
2991 Normally, you can just use \c{ALIGN} in code and data sections and
2992 \c{ALIGNB} in BSS sections, and never need the second argument
2993 except for special purposes.
2995 \c{ALIGN} and \c{ALIGNB}, being simple macros, perform no error
2996 checking: they cannot warn you if their first argument fails to be a
2997 power of two, or if their second argument generates more than one
2998 byte of code. In each of these cases they will silently do the wrong
3001 \c{ALIGNB} (or \c{ALIGN} with a second argument of \c{RESB 1}) can
3002 be used within structure definitions:
3019 This will ensure that the structure members are sensibly aligned
3020 relative to the base of the structure.
3022 A final caveat: \c{ALIGN} and \c{ALIGNB} work relative to the
3023 beginning of the \e{section}, not the beginning of the address space
3024 in the final executable. Aligning to a 16-byte boundary when the
3025 section you're in is only guaranteed to be aligned to a 4-byte
3026 boundary, for example, is a waste of effort. Again, NASM does not
3027 check that the section's alignment characteristics are sensible for
3028 the use of \c{ALIGN} or \c{ALIGNB}.
3031 \H{tasmcompat} \i{TASM Compatible Preprocessor Directives}
3033 The following preprocessor directives may only be used when TASM
3034 compatibility is turned on using the \c{-t} command line switch
3035 (This switch is described in \k{opt-t}.)
3037 \b\c{%arg} (see \k{arg})
3039 \b\c{%stacksize} (see \k{stacksize})
3041 \b\c{%local} (see \k{local})
3044 \S{arg} \i\c{%arg} Directive
3046 The \c{%arg} directive is used to simplify the handling of
3047 parameters passed on the stack. Stack based parameter passing
3048 is used by many high level languages, including C, C++ and Pascal.
3050 While NASM comes with macros which attempt to duplicate this
3051 functionality (see \k{16cmacro}), the syntax is not particularly
3052 convenient to use and is not TASM compatible. Here is an example
3053 which shows the use of \c{%arg} without any external macros:
3057 \c %push mycontext ; save the current context
3058 \c %stacksize large ; tell NASM to use bp
3059 \c %arg i:word, j_ptr:word
3066 \c %pop ; restore original context
3068 This is similar to the procedure defined in \k{16cmacro} and adds
3069 the value in i to the value pointed to by j_ptr and returns the
3070 sum in the ax register. See \k{pushpop} for an explanation of
3071 \c{push} and \c{pop} and the use of context stacks.
3074 \S{stacksize} \i\c{%stacksize} Directive
3076 The \c{%stacksize} directive is used in conjunction with the
3077 \c{%arg} (see \k{arg}) and the \c{%local} (see \k{local}) directives.
3078 It tells NASM the default size to use for subsequent \c{%arg} and
3079 \c{%local} directives. The \c{%stacksize} directive takes one
3080 required argument which is one of \c{flat}, \c{large} or \c{small}.
3084 This form causes NASM to use stack-based parameter addressing
3085 relative to \c{ebp} and it assumes that a near form of call was used
3086 to get to this label (i.e. that \c{eip} is on the stack).
3090 This form uses \c{bp} to do stack-based parameter addressing and
3091 assumes that a far form of call was used to get to this address
3092 (i.e. that \c{ip} and \c{cs} are on the stack).
3096 This form also uses \c{bp} to address stack parameters, but it is
3097 different from \c{large} because it also assumes that the old value
3098 of bp is pushed onto the stack (i.e. it expects an \c{ENTER}
3099 instruction). In other words, it expects that \c{bp}, \c{ip} and
3100 \c{cs} are on the top of the stack, underneath any local space which
3101 may have been allocated by \c{ENTER}. This form is probably most
3102 useful when used in combination with the \c{%local} directive
3106 \S{local} \i\c{%local} Directive
3108 The \c{%local} directive is used to simplify the use of local
3109 temporary stack variables allocated in a stack frame. Automatic
3110 local variables in C are an example of this kind of variable. The
3111 \c{%local} directive is most useful when used with the \c{%stacksize}
3112 (see \k{stacksize} and is also compatible with the \c{%arg} directive
3113 (see \k{arg}). It allows simplified reference to variables on the
3114 stack which have been allocated typically by using the \c{ENTER}
3115 instruction (see \k{insENTER} for a description of that instruction).
3116 An example of its use is the following:
3120 \c %push mycontext ; save the current context
3121 \c %stacksize small ; tell NASM to use bp
3122 \c %assign %$localsize 0 ; see text for explanation
3123 \c %local old_ax:word, old_dx:word
3125 \c enter %$localsize,0 ; see text for explanation
3126 \c mov [old_ax],ax ; swap ax & bx
3127 \c mov [old_dx],dx ; and swap dx & cx
3132 \c leave ; restore old bp
3135 \c %pop ; restore original context
3137 The \c{%$localsize} variable is used internally by the
3138 \c{%local} directive and \e{must} be defined within the
3139 current context before the \c{%local} directive may be used.
3140 Failure to do so will result in one expression syntax error for
3141 each \c{%local} variable declared. It then may be used in
3142 the construction of an appropriately sized ENTER instruction
3143 as shown in the example.
3145 \H{otherpreproc} \i{Other Preprocessor Directives}
3147 The following preprocessor directive is supported to allow NASM to
3148 correctly handle output of the cpp C language preprocessor.
3150 \b\c{%line} (see \k{line})
3152 \S{line} \i\c{%line} Directive
3154 The \c{%line} directive is used to notify NASM that the input line
3155 corresponds to a specific line number in another file. Typically
3156 this other file would be an original source file, with the current
3157 NASM input being the output of a pre-processor. The \c{%line}
3158 directive allows NASM to output messages which indicate the line
3159 number of the original source file, instead of the file that is being
3162 This preprocessor directive is not generally of use to programmers,
3163 by may be of interest to preprocessor authors. The usage of the
3164 \c{%line} preprocessor directive is as follows:
3166 \c %line nnn[+mmm] [filename]
3168 In this directive, \c{nnn} indentifies the line of the original source
3169 file which this line corresponds to. \c{mmm} is an optional parameter
3170 which specifies a line increment value; each line of the input file
3171 read in is considered to correspond to \c{mmm} lines of the original
3172 source file. Finally, \c{filename} is an optional parameter which
3173 specifies the file name of the original source file.
3175 After reading a \c{%line} preprocessor directive, NASM will report
3176 all file name and line numbers relative to the values specified
3179 \C{directive} \i{Assembler Directives}
3181 NASM, though it attempts to avoid the bureaucracy of assemblers like
3182 MASM and TASM, is nevertheless forced to support a \e{few}
3183 directives. These are described in this chapter.
3185 NASM's directives come in two types: \I{user-level
3186 directives}\e{user-level} directives and \I{primitive
3187 directives}\e{primitive} directives. Typically, each directive has a
3188 user-level form and a primitive form. In almost all cases, we
3189 recommend that users use the user-level forms of the directives,
3190 which are implemented as macros which call the primitive forms.
3192 Primitive directives are enclosed in square brackets; user-level
3195 In addition to the universal directives described in this chapter,
3196 each object file format can optionally supply extra directives in
3197 order to control particular features of that file format. These
3198 \I{format-specific directives}\e{format-specific} directives are
3199 documented along with the formats that implement them, in \k{outfmt}.
3202 \H{bits} \i\c{BITS}: Specifying Target \i{Processor Mode}
3204 The \c{BITS} directive specifies whether NASM should generate code
3205 \I{16-bit mode, versus 32-bit mode}designed to run on a processor
3206 operating in 16-bit mode, or code designed to run on a processor
3207 operating in 32-bit mode. The syntax is \c{BITS 16} or \c{BITS 32}.
3209 In most cases, you should not need to use \c{BITS} explicitly. The
3210 \c{aout}, \c{coff}, \c{elf} and \c{win32} object formats, which are
3211 designed for use in 32-bit operating systems, all cause NASM to
3212 select 32-bit mode by default. The \c{obj} object format allows you
3213 to specify each segment you define as either \c{USE16} or \c{USE32},
3214 and NASM will set its operating mode accordingly, so the use of the
3215 \c{BITS} directive is once again unnecessary.
3217 The most likely reason for using the \c{BITS} directive is to write
3218 32-bit code in a flat binary file; this is because the \c{bin}
3219 output format defaults to 16-bit mode in anticipation of it being
3220 used most frequently to write DOS \c{.COM} programs, DOS \c{.SYS}
3221 device drivers and boot loader software.
3223 You do \e{not} need to specify \c{BITS 32} merely in order to use
3224 32-bit instructions in a 16-bit DOS program; if you do, the
3225 assembler will generate incorrect code because it will be writing
3226 code targeted at a 32-bit platform, to be run on a 16-bit one.
3228 When NASM is in \c{BITS 16} state, instructions which use 32-bit
3229 data are prefixed with an 0x66 byte, and those referring to 32-bit
3230 addresses have an 0x67 prefix. In \c{BITS 32} state, the reverse is
3231 true: 32-bit instructions require no prefixes, whereas instructions
3232 using 16-bit data need an 0x66 and those working on 16-bit addresses
3235 The \c{BITS} directive has an exactly equivalent primitive form,
3236 \c{[BITS 16]} and \c{[BITS 32]}. The user-level form is a macro
3237 which has no function other than to call the primitive form.
3240 \S{USE16 & USE32} \i\c{USE16} & \i\c{USE32}: Aliases for BITS
3242 The `\c{USE16}' and `\c{USE32}' directives can be used in place of
3243 `\c{BIT 16}' and `\c{BITS 32}', for compatibility with other assemblers.
3246 \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining
3249 \I{changing sections}\I{switching between sections}The \c{SECTION}
3250 directive (\c{SEGMENT} is an exactly equivalent synonym) changes
3251 which section of the output file the code you write will be
3252 assembled into. In some object file formats, the number and names of
3253 sections are fixed; in others, the user may make up as many as they
3254 wish. Hence \c{SECTION} may sometimes give an error message, or may
3255 define a new section, if you try to switch to a section that does
3258 The Unix object formats, and the \c{bin} object format, all support
3259 the \i{standardised section names} \c{.text}, \c{.data} and \c{.bss}
3260 for the code, data and uninitialised-data sections. The \c{obj}
3261 format, by contrast, does not recognise these section names as being
3262 special, and indeed will strip off the leading period of any section
3266 \S{sectmac} The \i\c{__SECT__} Macro
3268 The \c{SECTION} directive is unusual in that its user-level form
3269 functions differently from its primitive form. The primitive form,
3270 \c{[SECTION xyz]}, simply switches the current target section to the
3271 one given. The user-level form, \c{SECTION xyz}, however, first
3272 defines the single-line macro \c{__SECT__} to be the primitive
3273 \c{[SECTION]} directive which it is about to issue, and then issues
3274 it. So the user-level directive
3278 expands to the two lines
3280 \c %define __SECT__ [SECTION .text]
3283 Users may find it useful to make use of this in their own macros.
3284 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
3285 usefully rewritten in the following more sophisticated form:
3287 \c %macro writefile 2+
3297 \c mov cx,%%endstr-%%str
3304 This form of the macro, once passed a string to output, first
3305 switches temporarily to the data section of the file, using the
3306 primitive form of the \c{SECTION} directive so as not to modify
3307 \c{__SECT__}. It then declares its string in the data section, and
3308 then invokes \c{__SECT__} to switch back to \e{whichever} section
3309 the user was previously working in. It thus avoids the need, in the
3310 previous version of the macro, to include a \c{JMP} instruction to
3311 jump over the data, and also does not fail if, in a complicated
3312 \c{OBJ} format module, the user could potentially be assembling the
3313 code in any of several separate code sections.
3316 \H{absolute} \i\c{ABSOLUTE}: Defining Absolute Labels
3318 The \c{ABSOLUTE} directive can be thought of as an alternative form
3319 of \c{SECTION}: it causes the subsequent code to be directed at no
3320 physical section, but at the hypothetical section starting at the
3321 given absolute address. The only instructions you can use in this
3322 mode are the \c{RESB} family.
3324 \c{ABSOLUTE} is used as follows:
3332 This example describes a section of the PC BIOS data area, at
3333 segment address 0x40: the above code defines \c{kbuf_chr} to be
3334 0x1A, \c{kbuf_free} to be 0x1C, and \c{kbuf} to be 0x1E.
3336 The user-level form of \c{ABSOLUTE}, like that of \c{SECTION},
3337 redefines the \i\c{__SECT__} macro when it is invoked.
3339 \i\c{STRUC} and \i\c{ENDSTRUC} are defined as macros which use
3340 \c{ABSOLUTE} (and also \c{__SECT__}).
3342 \c{ABSOLUTE} doesn't have to take an absolute constant as an
3343 argument: it can take an expression (actually, a \i{critical
3344 expression}: see \k{crit}) and it can be a value in a segment. For
3345 example, a TSR can re-use its setup code as run-time BSS like this:
3347 \c org 100h ; it's a .COM program
3349 \c jmp setup ; setup code comes last
3351 \c ; the resident part of the TSR goes here
3353 \c ; now write the code that installs the TSR here
3357 \c runtimevar1 resw 1
3358 \c runtimevar2 resd 20
3362 This defines some variables `on top of' the setup code, so that
3363 after the setup has finished running, the space it took up can be
3364 re-used as data storage for the running TSR. The symbol `tsr_end'
3365 can be used to calculate the total size of the part of the TSR that
3366 needs to be made resident.
3369 \H{extern} \i\c{EXTERN}: \i{Importing Symbols} from Other Modules
3371 \c{EXTERN} is similar to the MASM directive \c{EXTRN} and the C
3372 keyword \c{extern}: it is used to declare a symbol which is not
3373 defined anywhere in the module being assembled, but is assumed to be
3374 defined in some other module and needs to be referred to by this
3375 one. Not every object-file format can support external variables:
3376 the \c{bin} format cannot.
3378 The \c{EXTERN} directive takes as many arguments as you like. Each
3379 argument is the name of a symbol:
3382 \c extern _sscanf,_fscanf
3384 Some object-file formats provide extra features to the \c{EXTERN}
3385 directive. In all cases, the extra features are used by suffixing a
3386 colon to the symbol name followed by object-format specific text.
3387 For example, the \c{obj} format allows you to declare that the
3388 default segment base of an external should be the group \c{dgroup}
3389 by means of the directive
3391 \c extern _variable:wrt dgroup
3393 The primitive form of \c{EXTERN} differs from the user-level form
3394 only in that it can take only one argument at a time: the support
3395 for multiple arguments is implemented at the preprocessor level.
3397 You can declare the same variable as \c{EXTERN} more than once: NASM
3398 will quietly ignore the second and later redeclarations. You can't
3399 declare a variable as \c{EXTERN} as well as something else, though.
3402 \H{global} \i\c{GLOBAL}: \i{Exporting Symbols} to Other Modules
3404 \c{GLOBAL} is the other end of \c{EXTERN}: if one module declares a
3405 symbol as \c{EXTERN} and refers to it, then in order to prevent
3406 linker errors, some other module must actually \e{define} the
3407 symbol and declare it as \c{GLOBAL}. Some assemblers use the name
3408 \i\c{PUBLIC} for this purpose.
3410 The \c{GLOBAL} directive applying to a symbol must appear \e{before}
3411 the definition of the symbol.
3413 \c{GLOBAL} uses the same syntax as \c{EXTERN}, except that it must
3414 refer to symbols which \e{are} defined in the same module as the
3415 \c{GLOBAL} directive. For example:
3421 \c{GLOBAL}, like \c{EXTERN}, allows object formats to define private
3422 extensions by means of a colon. The \c{elf} object format, for
3423 example, lets you specify whether global data items are functions or
3426 \c global hashlookup:function, hashtable:data
3428 Like \c{EXTERN}, the primitive form of \c{GLOBAL} differs from the
3429 user-level form only in that it can take only one argument at a
3433 \H{common} \i\c{COMMON}: Defining Common Data Areas
3435 The \c{COMMON} directive is used to declare \i\e{common variables}.
3436 A common variable is much like a global variable declared in the
3437 uninitialised data section, so that
3441 is similar in function to
3448 The difference is that if more than one module defines the same
3449 common variable, then at link time those variables will be
3450 \e{merged}, and references to \c{intvar} in all modules will point
3451 at the same piece of memory.
3453 Like \c{GLOBAL} and \c{EXTERN}, \c{COMMON} supports object-format
3454 specific extensions. For example, the \c{obj} format allows common
3455 variables to be NEAR or FAR, and the \c{elf} format allows you to
3456 specify the alignment requirements of a common variable:
3458 \c common commvar 4:near ; works in OBJ
3459 \c common intarray 100:4 ; works in ELF: 4 byte aligned
3461 Once again, like \c{EXTERN} and \c{GLOBAL}, the primitive form of
3462 \c{COMMON} differs from the user-level form only in that it can take
3463 only one argument at a time.
3466 \H{CPU} \i\c{CPU XXX}: Defining CPU Dependencies
3468 The \i\c{CPU} directive restricts assembly to those instructions which
3469 are available on the specified CPU.
3473 \b\c{CPU 8086} Assemble only 8086 instruction set
3475 \b\c{CPU 186} Assemble instructions up to the 80186 instruction set
3477 \b\c{CPU 286} Assemble instructions up to the 286 instruction set
3479 \b\c{CPU 386} Assemble instructions up to the 386 instruction set
3481 \b\c{CPU 486} 486 instruction set
3483 \b\c{CPU 586} Pentium instruction set
3485 \b\c{CPU PENTIUM} Same as 586
3487 \b\c{CPU 686} P6 instruction set
3489 \b\c{CPU PPRO} Same as 686
3491 \b\c{CPU P2} Same as 686
3493 \b\c{CPU P3} Pentium III and Katmai instruction sets
3495 \b\c{CPU KATMAI} Same as P3
3497 \b\c{CPU P4} Pentium 4 (Willamette) instruction set
3499 \b\c{CPU WILLAMETTE} Same as P4
3501 All options are case insensitive. All instructions will
3502 be selected only if they apply to the selected cpu or lower.
3505 \C{outfmt} \i{Output Formats}
3507 NASM is a portable assembler, designed to be able to compile on any
3508 ANSI C-supporting platform and produce output to run on a variety of
3509 Intel x86 operating systems. For this reason, it has a large number
3510 of available output formats, selected using the \i\c{-f} option on
3511 the NASM \i{command line}. Each of these formats, along with its
3512 extensions to the base NASM syntax, is detailed in this chapter.
3514 As stated in \k{opt-o}, NASM chooses a \i{default name} for your
3515 output file based on the input file name and the chosen output
3516 format. This will be generated by removing the \i{extension}
3517 (\c{.asm}, \c{.s}, or whatever you like to use) from the input file
3518 name, and substituting an extension defined by the output format.
3519 The extensions are given with each format below.
3522 \H{binfmt} \i\c{bin}: \i{Flat-Form Binary}\I{pure binary} Output
3524 The \c{bin} format does not produce object files: it generates
3525 nothing in the output file except the code you wrote. Such `pure
3526 binary' files are used by \i{MS-DOS}: \i\c{.COM} executables and
3527 \i\c{.SYS} device drivers are pure binary files. Pure binary output
3528 is also useful for \i{operating system} and \i{boot loader}
3531 \c{bin} supports the three \i{standardised section names} \i\c{.text},
3532 \i\c{.data} and \i\c{.bss} only. The file NASM outputs will contain the
3533 contents of the \c{.text} section first, followed by the contents of
3534 the \c{.data} section, aligned on a four-byte boundary. The \c{.bss}
3535 section is not stored in the output file at all, but is assumed to
3536 appear directly after the end of the \c{.data} section, again
3537 aligned on a four-byte boundary.
3539 If you specify no explicit \c{SECTION} directive, the code you write
3540 will be directed by default into the \c{.text} section.
3542 Using the \c{bin} format puts NASM by default into 16-bit mode (see
3543 \k{bits}). In order to use \c{bin} to write 32-bit code such as an
3544 OS kernel, you need to explicitly issue the \I\c{BITS}\c{BITS 32}
3547 \c{bin} has no default output file name extension: instead, it
3548 leaves your file name as it is once the original extension has been
3549 removed. Thus, the default is for NASM to assemble \c{binprog.asm}
3550 into a binary file called \c{binprog}.
3553 \S{org} \i\c{ORG}: Binary File \i{Program Origin}
3555 The \c{bin} format provides an additional directive to the list
3556 given in \k{directive}: \c{ORG}. The function of the \c{ORG}
3557 directive is to specify the origin address which NASM will assume
3558 the program begins at when it is loaded into memory.
3560 For example, the following code will generate the longword
3567 Unlike the \c{ORG} directive provided by MASM-compatible assemblers,
3568 which allows you to jump around in the object file and overwrite
3569 code you have already generated, NASM's \c{ORG} does exactly what
3570 the directive says: \e{origin}. Its sole function is to specify one
3571 offset which is added to all internal address references within the
3572 file; it does not permit any of the trickery that MASM's version
3573 does. See \k{proborg} for further comments.
3576 \S{binseg} \c{bin} Extensions to the \c{SECTION}
3577 Directive\I{SECTION, bin extensions to}
3579 The \c{bin} output format extends the \c{SECTION} (or \c{SEGMENT})
3580 directive to allow you to specify the alignment requirements of
3581 segments. This is done by appending the \i\c{ALIGN} qualifier to the
3582 end of the section-definition line. For example,
3584 \c section .data align=16
3586 switches to the section \c{.data} and also specifies that it must be
3587 aligned on a 16-byte boundary.
3589 The parameter to \c{ALIGN} specifies how many low bits of the
3590 section start address must be forced to zero. The alignment value
3591 given may be any power of two.\I{section alignment, in
3592 bin}\I{segment alignment, in bin}\I{alignment, in bin sections}
3595 \H{objfmt} \i\c{obj}: \i{Microsoft OMF}\I{OMF} Object Files
3597 The \c{obj} file format (NASM calls it \c{obj} rather than \c{omf}
3598 for historical reasons) is the one produced by \i{MASM} and
3599 \i{TASM}, which is typically fed to 16-bit DOS linkers to produce
3600 \i\c{.EXE} files. It is also the format used by \i{OS/2}.
3602 \c{obj} provides a default output file-name extension of \c{.obj}.
3604 \c{obj} is not exclusively a 16-bit format, though: NASM has full
3605 support for the 32-bit extensions to the format. In particular,
3606 32-bit \c{obj} format files are used by \i{Borland's Win32
3607 compilers}, instead of using Microsoft's newer \i\c{win32} object
3610 The \c{obj} format does not define any special segment names: you
3611 can call your segments anything you like. Typical names for segments
3612 in \c{obj} format files are \c{CODE}, \c{DATA} and \c{BSS}.
3614 If your source file contains code before specifying an explicit
3615 \c{SEGMENT} directive, then NASM will invent its own segment called
3616 \i\c{__NASMDEFSEG} for you.
3618 When you define a segment in an \c{obj} file, NASM defines the
3619 segment name as a symbol as well, so that you can access the segment
3620 address of the segment. So, for example:
3629 \c mov ax,data ; get segment address of data
3630 \c mov ds,ax ; and move it into DS
3631 \c inc word [dvar] ; now this reference will work
3634 The \c{obj} format also enables the use of the \i\c{SEG} and
3635 \i\c{WRT} operators, so that you can write code which does things
3640 \c mov ax,seg foo ; get preferred segment of foo
3642 \c mov ax,data ; a different segment
3644 \c mov ax,[ds:foo] ; this accesses `foo'
3645 \c mov [es:foo wrt data],bx ; so does this
3648 \S{objseg} \c{obj} Extensions to the \c{SEGMENT}
3649 Directive\I{SEGMENT, obj extensions to}
3651 The \c{obj} output format extends the \c{SEGMENT} (or \c{SECTION})
3652 directive to allow you to specify various properties of the segment
3653 you are defining. This is done by appending extra qualifiers to the
3654 end of the segment-definition line. For example,
3656 \c segment code private align=16
3658 defines the segment \c{code}, but also declares it to be a private
3659 segment, and requires that the portion of it described in this code
3660 module must be aligned on a 16-byte boundary.
3662 The available qualifiers are:
3664 \b \i\c{PRIVATE}, \i\c{PUBLIC}, \i\c{COMMON} and \i\c{STACK} specify
3665 the combination characteristics of the segment. \c{PRIVATE} segments
3666 do not get combined with any others by the linker; \c{PUBLIC} and
3667 \c{STACK} segments get concatenated together at link time; and
3668 \c{COMMON} segments all get overlaid on top of each other rather
3669 than stuck end-to-end.
3671 \b \i\c{ALIGN} is used, as shown above, to specify how many low bits
3672 of the segment start address must be forced to zero. The alignment
3673 value given may be any power of two from 1 to 4096; in reality, the
3674 only values supported are 1, 2, 4, 16, 256 and 4096, so if 8 is
3675 specified it will be rounded up to 16, and 32, 64 and 128 will all
3676 be rounded up to 256, and so on. Note that alignment to 4096-byte
3677 boundaries is a \i{PharLap} extension to the format and may not be
3678 supported by all linkers.\I{section alignment, in OBJ}\I{segment
3679 alignment, in OBJ}\I{alignment, in OBJ sections}
3681 \b \i\c{CLASS} can be used to specify the segment class; this feature
3682 indicates to the linker that segments of the same class should be
3683 placed near each other in the output file. The class name can be any
3684 word, e.g. \c{CLASS=CODE}.
3686 \b \i\c{OVERLAY}, like \c{CLASS}, is specified with an arbitrary word
3687 as an argument, and provides overlay information to an
3688 overlay-capable linker.
3690 \b Segments can be declared as \i\c{USE16} or \i\c{USE32}, which has
3691 the effect of recording the choice in the object file and also
3692 ensuring that NASM's default assembly mode when assembling in that
3693 segment is 16-bit or 32-bit respectively.
3695 \b When writing \i{OS/2} object files, you should declare 32-bit
3696 segments as \i\c{FLAT}, which causes the default segment base for
3697 anything in the segment to be the special group \c{FLAT}, and also
3698 defines the group if it is not already defined.
3700 \b The \c{obj} file format also allows segments to be declared as
3701 having a pre-defined absolute segment address, although no linkers
3702 are currently known to make sensible use of this feature;
3703 nevertheless, NASM allows you to declare a segment such as
3704 \c{SEGMENT SCREEN ABSOLUTE=0xB800} if you need to. The \i\c{ABSOLUTE}
3705 and \c{ALIGN} keywords are mutually exclusive.
3707 NASM's default segment attributes are \c{PUBLIC}, \c{ALIGN=1}, no
3708 class, no overlay, and \c{USE16}.
3711 \S{group} \i\c{GROUP}: Defining Groups of Segments\I{segments, groups of}
3713 The \c{obj} format also allows segments to be grouped, so that a
3714 single segment register can be used to refer to all the segments in
3715 a group. NASM therefore supplies the \c{GROUP} directive, whereby
3724 \c ; some uninitialised data
3726 \c group dgroup data bss
3728 which will define a group called \c{dgroup} to contain the segments
3729 \c{data} and \c{bss}. Like \c{SEGMENT}, \c{GROUP} causes the group
3730 name to be defined as a symbol, so that you can refer to a variable
3731 \c{var} in the \c{data} segment as \c{var wrt data} or as \c{var wrt
3732 dgroup}, depending on which segment value is currently in your
3735 If you just refer to \c{var}, however, and \c{var} is declared in a
3736 segment which is part of a group, then NASM will default to giving
3737 you the offset of \c{var} from the beginning of the \e{group}, not
3738 the \e{segment}. Therefore \c{SEG var}, also, will return the group
3739 base rather than the segment base.
3741 NASM will allow a segment to be part of more than one group, but
3742 will generate a warning if you do this. Variables declared in a
3743 segment which is part of more than one group will default to being
3744 relative to the first group that was defined to contain the segment.
3746 A group does not have to contain any segments; you can still make
3747 \c{WRT} references to a group which does not contain the variable
3748 you are referring to. OS/2, for example, defines the special group
3749 \c{FLAT} with no segments in it.
3752 \S{uppercase} \i\c{UPPERCASE}: Disabling Case Sensitivity in Output
3754 Although NASM itself is \i{case sensitive}, some OMF linkers are
3755 not; therefore it can be useful for NASM to output single-case
3756 object files. The \c{UPPERCASE} format-specific directive causes all
3757 segment, group and symbol names that are written to the object file
3758 to be forced to upper case just before being written. Within a
3759 source file, NASM is still case-sensitive; but the object file can
3760 be written entirely in upper case if desired.
3762 \c{UPPERCASE} is used alone on a line; it requires no parameters.
3765 \S{import} \i\c{IMPORT}: Importing DLL Symbols\I{DLL symbols,
3766 importing}\I{symbols, importing from DLLs}
3768 The \c{IMPORT} format-specific directive defines a symbol to be
3769 imported from a DLL, for use if you are writing a DLL's \i{import
3770 library} in NASM. You still need to declare the symbol as \c{EXTERN}
3771 as well as using the \c{IMPORT} directive.
3773 The \c{IMPORT} directive takes two required parameters, separated by
3774 white space, which are (respectively) the name of the symbol you
3775 wish to import and the name of the library you wish to import it
3778 \c import WSAStartup wsock32.dll
3780 A third optional parameter gives the name by which the symbol is
3781 known in the library you are importing it from, in case this is not
3782 the same as the name you wish the symbol to be known by to your code
3783 once you have imported it. For example:
3785 \c import asyncsel wsock32.dll WSAAsyncSelect
3788 \S{export} \i\c{EXPORT}: Exporting DLL Symbols\I{DLL symbols,
3789 exporting}\I{symbols, exporting from DLLs}
3791 The \c{EXPORT} format-specific directive defines a global symbol to
3792 be exported as a DLL symbol, for use if you are writing a DLL in
3793 NASM. You still need to declare the symbol as \c{GLOBAL} as well as
3794 using the \c{EXPORT} directive.
3796 \c{EXPORT} takes one required parameter, which is the name of the
3797 symbol you wish to export, as it was defined in your source file. An
3798 optional second parameter (separated by white space from the first)
3799 gives the \e{external} name of the symbol: the name by which you
3800 wish the symbol to be known to programs using the DLL. If this name
3801 is the same as the internal name, you may leave the second parameter
3804 Further parameters can be given to define attributes of the exported
3805 symbol. These parameters, like the second, are separated by white
3806 space. If further parameters are given, the external name must also
3807 be specified, even if it is the same as the internal name. The
3808 available attributes are:
3810 \b \c{resident} indicates that the exported name is to be kept
3811 resident by the system loader. This is an optimisation for
3812 frequently used symbols imported by name.
3814 \b \c{nodata} indicates that the exported symbol is a function which
3815 does not make use of any initialised data.
3817 \b \c{parm=NNN}, where \c{NNN} is an integer, sets the number of
3818 parameter words for the case in which the symbol is a call gate
3819 between 32-bit and 16-bit segments.
3821 \b An attribute which is just a number indicates that the symbol
3822 should be exported with an identifying number (ordinal), and gives
3828 \c export myfunc TheRealMoreFormalLookingFunctionName
3829 \c export myfunc myfunc 1234 ; export by ordinal
3830 \c export myfunc myfunc resident parm=23 nodata
3833 \S{dotdotstart} \i\c{..start}: Defining the \i{Program Entry
3836 \c{OMF} linkers require exactly one of the object files being linked to
3837 define the program entry point, where execution will begin when the
3838 program is run. If the object file that defines the entry point is
3839 assembled using NASM, you specify the entry point by declaring the
3840 special symbol \c{..start} at the point where you wish execution to
3844 \S{objextern} \c{obj} Extensions to the \c{EXTERN}
3845 Directive\I{EXTERN, obj extensions to}
3847 If you declare an external symbol with the directive
3851 then references such as \c{mov ax,foo} will give you the offset of
3852 \c{foo} from its preferred segment base (as specified in whichever
3853 module \c{foo} is actually defined in). So to access the contents of
3854 \c{foo} you will usually need to do something like
3856 \c mov ax,seg foo ; get preferred segment base
3857 \c mov es,ax ; move it into ES
3858 \c mov ax,[es:foo] ; and use offset `foo' from it
3860 This is a little unwieldy, particularly if you know that an external
3861 is going to be accessible from a given segment or group, say
3862 \c{dgroup}. So if \c{DS} already contained \c{dgroup}, you could
3865 \c mov ax,[foo wrt dgroup]
3867 However, having to type this every time you want to access \c{foo}
3868 can be a pain; so NASM allows you to declare \c{foo} in the
3871 \c extern foo:wrt dgroup
3873 This form causes NASM to pretend that the preferred segment base of
3874 \c{foo} is in fact \c{dgroup}; so the expression \c{seg foo} will
3875 now return \c{dgroup}, and the expression \c{foo} is equivalent to
3878 This \I{default-WRT mechanism}default-\c{WRT} mechanism can be used
3879 to make externals appear to be relative to any group or segment in
3880 your program. It can also be applied to common variables: see
3884 \S{objcommon} \c{obj} Extensions to the \c{COMMON}
3885 Directive\I{COMMON, obj extensions to}
3887 The \c{obj} format allows common variables to be either near\I{near
3888 common variables} or far\I{far common variables}; NASM allows you to
3889 specify which your variables should be by the use of the syntax
3891 \c common nearvar 2:near ; `nearvar' is a near common
3892 \c common farvar 10:far ; and `farvar' is far
3894 Far common variables may be greater in size than 64Kb, and so the
3895 OMF specification says that they are declared as a number of
3896 \e{elements} of a given size. So a 10-byte far common variable could
3897 be declared as ten one-byte elements, five two-byte elements, two
3898 five-byte elements or one ten-byte element.
3900 Some \c{OMF} linkers require the \I{element size, in common
3901 variables}\I{common variables, element size}element size, as well as
3902 the variable size, to match when resolving common variables declared
3903 in more than one module. Therefore NASM must allow you to specify
3904 the element size on your far common variables. This is done by the
3907 \c common c_5by2 10:far 5 ; two five-byte elements
3908 \c common c_2by5 10:far 2 ; five two-byte elements
3910 If no element size is specified, the default is 1. Also, the \c{FAR}
3911 keyword is not required when an element size is specified, since
3912 only far commons may have element sizes at all. So the above
3913 declarations could equivalently be
3915 \c common c_5by2 10:5 ; two five-byte elements
3916 \c common c_2by5 10:2 ; five two-byte elements
3918 In addition to these extensions, the \c{COMMON} directive in \c{obj}
3919 also supports default-\c{WRT} specification like \c{EXTERN} does
3920 (explained in \k{objextern}). So you can also declare things like
3922 \c common foo 10:wrt dgroup
3923 \c common bar 16:far 2:wrt data
3924 \c common baz 24:wrt data:6
3927 \H{win32fmt} \i\c{win32}: Microsoft Win32 Object Files
3929 The \c{win32} output format generates Microsoft Win32 object files,
3930 suitable for passing to Microsoft linkers such as \i{Visual C++}.
3931 Note that Borland Win32 compilers do not use this format, but use
3932 \c{obj} instead (see \k{objfmt}).
3934 \c{win32} provides a default output file-name extension of \c{.obj}.
3936 Note that although Microsoft say that Win32 object files follow the
3937 \c{COFF} (Common Object File Format) standard, the object files produced
3938 by Microsoft Win32 compilers are not compatible with COFF linkers
3939 such as DJGPP's, and vice versa. This is due to a difference of
3940 opinion over the precise semantics of PC-relative relocations. To
3941 produce COFF files suitable for DJGPP, use NASM's \c{coff} output
3942 format; conversely, the \c{coff} format does not produce object
3943 files that Win32 linkers can generate correct output from.
3946 \S{win32sect} \c{win32} Extensions to the \c{SECTION}
3947 Directive\I{SECTION, win32 extensions to}
3949 Like the \c{obj} format, \c{win32} allows you to specify additional
3950 information on the \c{SECTION} directive line, to control the type
3951 and properties of sections you declare. Section types and properties
3952 are generated automatically by NASM for the \i{standard section names}
3953 \c{.text}, \c{.data} and \c{.bss}, but may still be overridden by
3956 The available qualifiers are:
3958 \b \c{code}, or equivalently \c{text}, defines the section to be a
3959 code section. This marks the section as readable and executable, but
3960 not writable, and also indicates to the linker that the type of the
3963 \b \c{data} and \c{bss} define the section to be a data section,
3964 analogously to \c{code}. Data sections are marked as readable and
3965 writable, but not executable. \c{data} declares an initialised data
3966 section, whereas \c{bss} declares an uninitialised data section.
3968 \b \c{rdata} declares an initialised data section that is readable
3969 but not writable. Microsoft compilers use this section to place
3972 \b \c{info} defines the section to be an \i{informational section},
3973 which is not included in the executable file by the linker, but may
3974 (for example) pass information \e{to} the linker. For example,
3975 declaring an \c{info}-type section called \i\c{.drectve} causes the
3976 linker to interpret the contents of the section as command-line
3979 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
3980 \I{section alignment, in win32}\I{alignment, in win32
3981 sections}alignment requirements of the section. The maximum you may
3982 specify is 64: the Win32 object file format contains no means to
3983 request a greater section alignment than this. If alignment is not
3984 explicitly specified, the defaults are 16-byte alignment for code
3985 sections, 8-byte alignment for rdata sections and 4-byte alignment
3986 for data (and BSS) sections.
3987 Informational sections get a default alignment of 1 byte (no
3988 alignment), though the value does not matter.
3990 The defaults assumed by NASM if you do not specify the above
3993 \c section .text code align=16
3994 \c section .data data align=4
3995 \c section .rdata rdata align=8
3996 \c section .bss bss align=4
3998 Any other section name is treated by default like \c{.text}.
4001 \H{cofffmt} \i\c{coff}: \i{Common Object File Format}
4003 The \c{coff} output type produces \c{COFF} object files suitable for
4004 linking with the \i{DJGPP} linker.
4006 \c{coff} provides a default output file-name extension of \c{.o}.
4008 The \c{coff} format supports the same extensions to the \c{SECTION}
4009 directive as \c{win32} does, except that the \c{align} qualifier and
4010 the \c{info} section type are not supported.
4013 \H{elffmt} \i\c{elf}: \I{ELF}\I{linux, elf}\i{Executable and Linkable
4014 Format} Object Files
4016 The \c{elf} output format generates \c{ELF32} (Executable and Linkable
4017 Format) object files, as used by Linux as well as \i{Unix System V},
4018 including \i{Solaris x86}, \i{UnixWare} and \i{SCO Unix}. \c{elf}
4019 provides a default output file-name extension of \c{.o}.
4022 \S{elfsect} \c{elf} Extensions to the \c{SECTION}
4023 Directive\I{SECTION, elf extensions to}
4025 Like the \c{obj} format, \c{elf} allows you to specify additional
4026 information on the \c{SECTION} directive line, to control the type
4027 and properties of sections you declare. Section types and properties
4028 are generated automatically by NASM for the \i{standard section
4029 names} \i\c{.text}, \i\c{.data} and \i\c{.bss}, but may still be
4030 overridden by these qualifiers.
4032 The available qualifiers are:
4034 \b \i\c{alloc} defines the section to be one which is loaded into
4035 memory when the program is run. \i\c{noalloc} defines it to be one
4036 which is not, such as an informational or comment section.
4038 \b \i\c{exec} defines the section to be one which should have execute
4039 permission when the program is run. \i\c{noexec} defines it as one
4042 \b \i\c{write} defines the section to be one which should be writable
4043 when the program is run. \i\c{nowrite} defines it as one which should
4046 \b \i\c{progbits} defines the section to be one with explicit contents
4047 stored in the object file: an ordinary code or data section, for
4048 example, \i\c{nobits} defines the section to be one with no explicit
4049 contents given, such as a BSS section.
4051 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
4052 \I{section alignment, in elf}\I{alignment, in elf sections}alignment
4053 requirements of the section.
4055 The defaults assumed by NASM if you do not specify the above
4058 \c section .text progbits alloc exec nowrite align=16
4059 \c section .rodata progbits alloc noexec nowrite align=4
4060 \c section .data progbits alloc noexec write align=4
4061 \c section .bss nobits alloc noexec write align=4
4062 \c section other progbits alloc noexec nowrite align=1
4064 (Any section name other than \c{.text}, \c{.rodata}, \c{.data} and
4065 \c{.bss} is treated by default like \c{other} in the above code.)
4068 \S{elfwrt} \i{Position-Independent Code}\I{PIC}: \c{elf} Special
4069 Symbols and \i\c{WRT}
4071 The \c{ELF} specification contains enough features to allow
4072 position-independent code (PIC) to be written, which makes \i{ELF
4073 shared libraries} very flexible. However, it also means NASM has to
4074 be able to generate a variety of strange relocation types in ELF
4075 object files, if it is to be an assembler which can write PIC.
4077 Since \c{ELF} does not support segment-base references, the \c{WRT}
4078 operator is not used for its normal purpose; therefore NASM's
4079 \c{elf} output format makes use of \c{WRT} for a different purpose,
4080 namely the PIC-specific \I{relocations, PIC-specific}relocation
4083 \c{elf} defines five special symbols which you can use as the
4084 right-hand side of the \c{WRT} operator to obtain PIC relocation
4085 types. They are \i\c{..gotpc}, \i\c{..gotoff}, \i\c{..got},
4086 \i\c{..plt} and \i\c{..sym}. Their functions are summarised here:
4088 \b Referring to the symbol marking the global offset table base
4089 using \c{wrt ..gotpc} will end up giving the distance from the
4090 beginning of the current section to the global offset table.
4091 (\i\c{_GLOBAL_OFFSET_TABLE_} is the standard symbol name used to
4092 refer to the \i{GOT}.) So you would then need to add \i\c{$$} to the
4093 result to get the real address of the GOT.
4095 \b Referring to a location in one of your own sections using \c{wrt
4096 ..gotoff} will give the distance from the beginning of the GOT to
4097 the specified location, so that adding on the address of the GOT
4098 would give the real address of the location you wanted.
4100 \b Referring to an external or global symbol using \c{wrt ..got}
4101 causes the linker to build an entry \e{in} the GOT containing the
4102 address of the symbol, and the reference gives the distance from the
4103 beginning of the GOT to the entry; so you can add on the address of
4104 the GOT, load from the resulting address, and end up with the
4105 address of the symbol.
4107 \b Referring to a procedure name using \c{wrt ..plt} causes the
4108 linker to build a \i{procedure linkage table} entry for the symbol,
4109 and the reference gives the address of the \i{PLT} entry. You can
4110 only use this in contexts which would generate a PC-relative
4111 relocation normally (i.e. as the destination for \c{CALL} or
4112 \c{JMP}), since ELF contains no relocation type to refer to PLT
4115 \b Referring to a symbol name using \c{wrt ..sym} causes NASM to
4116 write an ordinary relocation, but instead of making the relocation
4117 relative to the start of the section and then adding on the offset
4118 to the symbol, it will write a relocation record aimed directly at
4119 the symbol in question. The distinction is a necessary one due to a
4120 peculiarity of the dynamic linker.
4122 A fuller explanation of how to use these relocation types to write
4123 shared libraries entirely in NASM is given in \k{picdll}.
4126 \S{elfglob} \c{elf} Extensions to the \c{GLOBAL} Directive\I{GLOBAL,
4127 elf extensions to}\I{GLOBAL, aoutb extensions to}
4129 \c{ELF} object files can contain more information about a global symbol
4130 than just its address: they can contain the \I{symbol sizes,
4131 specifying}\I{size, of symbols}size of the symbol and its \I{symbol
4132 types, specifying}\I{type, of symbols}type as well. These are not
4133 merely debugger conveniences, but are actually necessary when the
4134 program being written is a \i{shared library}. NASM therefore
4135 supports some extensions to the \c{GLOBAL} directive, allowing you
4136 to specify these features.
4138 You can specify whether a global variable is a function or a data
4139 object by suffixing the name with a colon and the word
4140 \i\c{function} or \i\c{data}. (\i\c{object} is a synonym for
4141 \c{data}.) For example:
4143 \c global hashlookup:function, hashtable:data
4145 exports the global symbol \c{hashlookup} as a function and
4146 \c{hashtable} as a data object.
4148 You can also specify the size of the data associated with the
4149 symbol, as a numeric expression (which may involve labels, and even
4150 forward references) after the type specifier. Like this:
4152 \c global hashtable:data (hashtable.end - hashtable)
4155 \c db this,that,theother ; some data here
4158 This makes NASM automatically calculate the length of the table and
4159 place that information into the \c{ELF} symbol table.
4161 Declaring the type and size of global symbols is necessary when
4162 writing shared library code. For more information, see
4166 \S{elfcomm} \c{elf} Extensions to the \c{COMMON} Directive
4167 \I{COMMON, elf extensions to}
4169 \c{ELF} also allows you to specify alignment requirements \I{common
4170 variables, alignment in elf}\I{alignment, of elf common variables}on
4171 common variables. This is done by putting a number (which must be a
4172 power of two) after the name and size of the common variable,
4173 separated (as usual) by a colon. For example, an array of
4174 doublewords would benefit from 4-byte alignment:
4176 \c common dwordarray 128:4
4178 This declares the total size of the array to be 128 bytes, and
4179 requires that it be aligned on a 4-byte boundary.
4182 \S{elf16} 16-bit code and ELF
4183 \I{ELF, 16-bit code and}
4185 The \c{ELF32} specification doesn't provide relocations for 8- and
4186 16-bit values, but the GNU \c{ld} linker adds these as an extension.
4187 NASM can generate GNU-compatible relocations, to allow 16-bit code to
4188 be linked as ELF using GNU \c{ld}. If NASM is used with the
4189 \c{-w+gnu-elf-extensions} option, a warning is issued when one of
4190 these relocations is generated.
4192 \H{aoutfmt} \i\c{aout}: Linux \I{a.out, Linux version}\I{linux, a.out}\c{a.out} Object Files
4194 The \c{aout} format generates \c{a.out} object files, in the form used
4195 by early Linux systems (current Linux systems use ELF, see
4196 \k{elffmt}.) These differ from other \c{a.out} object files in that
4197 the magic number in the first four bytes of the file is
4198 different; also, some implementations of \c{a.out}, for example
4199 NetBSD's, support position-independent code, which Linux's
4200 implementation does not.
4202 \c{a.out} provides a default output file-name extension of \c{.o}.
4204 \c{a.out} is a very simple object format. It supports no special
4205 directives, no special symbols, no use of \c{SEG} or \c{WRT}, and no
4206 extensions to any standard directives. It supports only the three
4207 \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4210 \H{aoutfmt} \i\c{aoutb}: \i{NetBSD}/\i{FreeBSD}/\i{OpenBSD}
4211 \I{a.out, BSD version}\c{a.out} Object Files
4213 The \c{aoutb} format generates \c{a.out} object files, in the form
4214 used by the various free \c{BSD Unix} clones, \c{NetBSD}, \c{FreeBSD}
4215 and \c{OpenBSD}. For simple object files, this object format is exactly
4216 the same as \c{aout} except for the magic number in the first four bytes
4217 of the file. However, the \c{aoutb} format supports
4218 \I{PIC}\i{position-independent code} in the same way as the \c{elf}
4219 format, so you can use it to write \c{BSD} \i{shared libraries}.
4221 \c{aoutb} provides a default output file-name extension of \c{.o}.
4223 \c{aoutb} supports no special directives, no special symbols, and
4224 only the three \i{standard section names} \i\c{.text}, \i\c{.data}
4225 and \i\c{.bss}. However, it also supports the same use of \i\c{WRT} as
4226 \c{elf} does, to provide position-independent code relocation types.
4227 See \k{elfwrt} for full documentation of this feature.
4229 \c{aoutb} also supports the same extensions to the \c{GLOBAL}
4230 directive as \c{elf} does: see \k{elfglob} for documentation of
4234 \H{as86fmt} \c{as86}: \i{Minix}/Linux\I{linux, as86} \i\c{as86} Object Files
4236 The Minix/Linux 16-bit assembler \c{as86} has its own non-standard
4237 object file format. Although its companion linker \i\c{ld86} produces
4238 something close to ordinary \c{a.out} binaries as output, the object
4239 file format used to communicate between \c{as86} and \c{ld86} is not
4242 NASM supports this format, just in case it is useful, as \c{as86}.
4243 \c{as86} provides a default output file-name extension of \c{.o}.
4245 \c{as86} is a very simple object format (from the NASM user's point
4246 of view). It supports no special directives, no special symbols, no
4247 use of \c{SEG} or \c{WRT}, and no extensions to any standard
4248 directives. It supports only the three \i{standard section names}
4249 \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4252 \H{rdffmt} \I{RDOFF}\i\c{rdf}: \i{Relocatable Dynamic Object File
4255 The \c{rdf} output format produces \c{RDOFF} object files. \c{RDOFF}
4256 (Relocatable Dynamic Object File Format) is a home-grown object-file
4257 format, designed alongside NASM itself and reflecting in its file
4258 format the internal structure of the assembler.
4260 \c{RDOFF} is not used by any well-known operating systems. Those
4261 writing their own systems, however, may well wish to use \c{RDOFF}
4262 as their object format, on the grounds that it is designed primarily
4263 for simplicity and contains very little file-header bureaucracy.
4265 The Unix NASM archive, and the DOS archive which includes sources,
4266 both contain an \I{rdoff subdirectory}\c{rdoff} subdirectory holding
4267 a set of RDOFF utilities: an RDF linker, an \c{RDF} static-library
4268 manager, an RDF file dump utility, and a program which will load and
4269 execute an RDF executable under Linux.
4271 \c{rdf} supports only the \i{standard section names} \i\c{.text},
4272 \i\c{.data} and \i\c{.bss}.
4275 \S{rdflib} Requiring a Library: The \i\c{LIBRARY} Directive
4277 \c{RDOFF} contains a mechanism for an object file to demand a given
4278 library to be linked to the module, either at load time or run time.
4279 This is done by the \c{LIBRARY} directive, which takes one argument
4280 which is the name of the module:
4282 \c library mylib.rdl
4285 \S{rdfmod} Specifying a Module Name: The \i\c{MODULE} Directive
4287 Special \c{RDOFF} header record is used to store the name of the module.
4288 It can be used, for example, by run-time loader to perform dynamic
4289 linking. \c{MODULE} directive takes one argument which is the name
4294 Note that when you statically link modules and tell linker to strip
4295 the symbols from output file, all module names will be stripped too.
4296 To avoid it, you should start module names with \I{$, prefix}\c{$}, like:
4298 \c module $kernel.core
4301 \S{rdfglob} \c{rdf} Extensions to the \c{GLOBAL} directive\I{GLOBAL,
4304 \c{RDOFF} global symbols can contain additional information needed by
4305 the static linker. You can mark a global symbol as exported, thus
4306 telling the linker do not strip it from target executable or library
4307 file. Like in \c{ELF}, you can also specify whether an exported symbol
4308 is a procedure (function) or data object.
4310 Suffixing the name with a colon and the word \i\c{export} you make the
4313 \c global sys_open:export
4315 To specify that exported symbol is a procedure (function), you add the
4316 word \i\c{proc} or \i\c{function} after declaration:
4318 \c global sys_open:export proc
4320 Similarly, to specify exported data object, add the word \i\c{data}
4321 or \i\c{object} to the directive:
4323 \c global kernel_ticks:export data
4326 \H{dbgfmt} \i\c{dbg}: Debugging Format
4328 The \c{dbg} output format is not built into NASM in the default
4329 configuration. If you are building your own NASM executable from the
4330 sources, you can define \i\c{OF_DBG} in \c{outform.h} or on the
4331 compiler command line, and obtain the \c{dbg} output format.
4333 The \c{dbg} format does not output an object file as such; instead,
4334 it outputs a text file which contains a complete list of all the
4335 transactions between the main body of NASM and the output-format
4336 back end module. It is primarily intended to aid people who want to
4337 write their own output drivers, so that they can get a clearer idea
4338 of the various requests the main program makes of the output driver,
4339 and in what order they happen.
4341 For simple files, one can easily use the \c{dbg} format like this:
4343 \c nasm -f dbg filename.asm
4345 which will generate a diagnostic file called \c{filename.dbg}.
4346 However, this will not work well on files which were designed for a
4347 different object format, because each object format defines its own
4348 macros (usually user-level forms of directives), and those macros
4349 will not be defined in the \c{dbg} format. Therefore it can be
4350 useful to run NASM twice, in order to do the preprocessing with the
4351 native object format selected:
4353 \c nasm -e -f rdf -o rdfprog.i rdfprog.asm
4354 \c nasm -a -f dbg rdfprog.i
4356 This preprocesses \c{rdfprog.asm} into \c{rdfprog.i}, keeping the
4357 \c{rdf} object format selected in order to make sure RDF special
4358 directives are converted into primitive form correctly. Then the
4359 preprocessed source is fed through the \c{dbg} format to generate
4360 the final diagnostic output.
4362 This workaround will still typically not work for programs intended
4363 for \c{obj} format, because the \c{obj} \c{SEGMENT} and \c{GROUP}
4364 directives have side effects of defining the segment and group names
4365 as symbols; \c{dbg} will not do this, so the program will not
4366 assemble. You will have to work around that by defining the symbols
4367 yourself (using \c{EXTERN}, for example) if you really need to get a
4368 \c{dbg} trace of an \c{obj}-specific source file.
4370 \c{dbg} accepts any section name and any directives at all, and logs
4371 them all to its output file.
4374 \C{16bit} Writing 16-bit Code (DOS, Windows 3/3.1)
4376 This chapter attempts to cover some of the common issues encountered
4377 when writing 16-bit code to run under \c{MS-DOS} or \c{Windows 3.x}. It
4378 covers how to link programs to produce \c{.EXE} or \c{.COM} files,
4379 how to write \c{.SYS} device drivers, and how to interface assembly
4380 language code with 16-bit C compilers and with Borland Pascal.
4383 \H{exefiles} Producing \i\c{.EXE} Files
4385 Any large program written under DOS needs to be built as a \c{.EXE}
4386 file: only \c{.EXE} files have the necessary internal structure
4387 required to span more than one 64K segment. \i{Windows} programs,
4388 also, have to be built as \c{.EXE} files, since Windows does not
4389 support the \c{.COM} format.
4391 In general, you generate \c{.EXE} files by using the \c{obj} output
4392 format to produce one or more \i\c{.OBJ} files, and then linking
4393 them together using a linker. However, NASM also supports the direct
4394 generation of simple DOS \c{.EXE} files using the \c{bin} output
4395 format (by using \c{DB} and \c{DW} to construct the \c{.EXE} file
4396 header), and a macro package is supplied to do this. Thanks to
4397 Yann Guidon for contributing the code for this.
4399 NASM may also support \c{.EXE} natively as another output format in
4403 \S{objexe} Using the \c{obj} Format To Generate \c{.EXE} Files
4405 This section describes the usual method of generating \c{.EXE} files
4406 by linking \c{.OBJ} files together.
4408 Most 16-bit programming language packages come with a suitable
4409 linker; if you have none of these, there is a free linker called
4410 \i{VAL}\I{linker, free}, available in \c{LZH} archive format from
4411 \W{ftp://x2ftp.oulu.fi/pub/msdos/programming/lang/}\i\c{x2ftp.oulu.fi}.
4412 An LZH archiver can be found at
4413 \W{ftp://ftp.simtel.net/pub/simtelnet/msdos/arcers}\i\c{ftp.simtel.net}.
4414 There is another `free' linker (though this one doesn't come with
4415 sources) called \i{FREELINK}, available from
4416 \W{http://www.pcorner.com/tpc/old/3-101.html}\i\c{www.pcorner.com}.
4417 A third, \i\c{djlink}, written by DJ Delorie, is available at
4418 \W{http://www.delorie.com/djgpp/16bit/djlink/}\i\c{www.delorie.com}.
4419 A fourth linker, \i\c{ALINK}, written by Anthony A.J. Williams, is
4420 available at \W{http://alink.sourceforge.net}\i\c{alink.sourceforge.net}.
4422 When linking several \c{.OBJ} files into a \c{.EXE} file, you should
4423 ensure that exactly one of them has a start point defined (using the
4424 \I{program entry point}\i\c{..start} special symbol defined by the
4425 \c{obj} format: see \k{dotdotstart}). If no module defines a start
4426 point, the linker will not know what value to give the entry-point
4427 field in the output file header; if more than one defines a start
4428 point, the linker will not know \e{which} value to use.
4430 An example of a NASM source file which can be assembled to a
4431 \c{.OBJ} file and linked on its own to a \c{.EXE} is given here. It
4432 demonstrates the basic principles of defining a stack, initialising
4433 the segment registers, and declaring a start point. This file is
4434 also provided in the \I{test subdirectory}\c{test} subdirectory of
4435 the NASM archives, under the name \c{objexe.asm}.
4446 This initial piece of code sets up \c{DS} to point to the data
4447 segment, and initialises \c{SS} and \c{SP} to point to the top of
4448 the provided stack. Notice that interrupts are implicitly disabled
4449 for one instruction after a move into \c{SS}, precisely for this
4450 situation, so that there's no chance of an interrupt occurring
4451 between the loads of \c{SS} and \c{SP} and not having a stack to
4454 Note also that the special symbol \c{..start} is defined at the
4455 beginning of this code, which means that will be the entry point
4456 into the resulting executable file.
4462 The above is the main program: load \c{DS:DX} with a pointer to the
4463 greeting message (\c{hello} is implicitly relative to the segment
4464 \c{data}, which was loaded into \c{DS} in the setup code, so the
4465 full pointer is valid), and call the DOS print-string function.
4470 This terminates the program using another DOS system call.
4474 \c hello: db 'hello, world', 13, 10, '$'
4476 The data segment contains the string we want to display.
4478 \c segment stack stack
4482 The above code declares a stack segment containing 64 bytes of
4483 uninitialised stack space, and points \c{stacktop} at the top of it.
4484 The directive \c{segment stack stack} defines a segment \e{called}
4485 \c{stack}, and also of \e{type} \c{STACK}. The latter is not
4486 necessary to the correct running of the program, but linkers are
4487 likely to issue warnings or errors if your program has no segment of
4490 The above file, when assembled into a \c{.OBJ} file, will link on
4491 its own to a valid \c{.EXE} file, which when run will print `hello,
4492 world' and then exit.
4495 \S{binexe} Using the \c{bin} Format To Generate \c{.EXE} Files
4497 The \c{.EXE} file format is simple enough that it's possible to
4498 build a \c{.EXE} file by writing a pure-binary program and sticking
4499 a 32-byte header on the front. This header is simple enough that it
4500 can be generated using \c{DB} and \c{DW} commands by NASM itself, so
4501 that you can use the \c{bin} output format to directly generate
4504 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4505 subdirectory, is a file \i\c{exebin.mac} of macros. It defines three
4506 macros: \i\c{EXE_begin}, \i\c{EXE_stack} and \i\c{EXE_end}.
4508 To produce a \c{.EXE} file using this method, you should start by
4509 using \c{%include} to load the \c{exebin.mac} macro package into
4510 your source file. You should then issue the \c{EXE_begin} macro call
4511 (which takes no arguments) to generate the file header data. Then
4512 write code as normal for the \c{bin} format - you can use all three
4513 standard sections \c{.text}, \c{.data} and \c{.bss}. At the end of
4514 the file you should call the \c{EXE_end} macro (again, no arguments),
4515 which defines some symbols to mark section sizes, and these symbols
4516 are referred to in the header code generated by \c{EXE_begin}.
4518 In this model, the code you end up writing starts at \c{0x100}, just
4519 like a \c{.COM} file - in fact, if you strip off the 32-byte header
4520 from the resulting \c{.EXE} file, you will have a valid \c{.COM}
4521 program. All the segment bases are the same, so you are limited to a
4522 64K program, again just like a \c{.COM} file. Note that an \c{ORG}
4523 directive is issued by the \c{EXE_begin} macro, so you should not
4524 explicitly issue one of your own.
4526 You can't directly refer to your segment base value, unfortunately,
4527 since this would require a relocation in the header, and things
4528 would get a lot more complicated. So you should get your segment
4529 base by copying it out of \c{CS} instead.
4531 On entry to your \c{.EXE} file, \c{SS:SP} are already set up to
4532 point to the top of a 2Kb stack. You can adjust the default stack
4533 size of 2Kb by calling the \c{EXE_stack} macro. For example, to
4534 change the stack size of your program to 64 bytes, you would call
4537 A sample program which generates a \c{.EXE} file in this way is
4538 given in the \c{test} subdirectory of the NASM archive, as
4542 \H{comfiles} Producing \i\c{.COM} Files
4544 While large DOS programs must be written as \c{.EXE} files, small
4545 ones are often better written as \c{.COM} files. \c{.COM} files are
4546 pure binary, and therefore most easily produced using the \c{bin}
4550 \S{combinfmt} Using the \c{bin} Format To Generate \c{.COM} Files
4552 \c{.COM} files expect to be loaded at offset \c{100h} into their
4553 segment (though the segment may change). Execution then begins at
4554 \I\c{ORG}\c{100h}, i.e. right at the start of the program. So to
4555 write a \c{.COM} program, you would create a source file looking
4563 \c ; put your code here
4567 \c ; put data items here
4571 \c ; put uninitialised data here
4573 The \c{bin} format puts the \c{.text} section first in the file, so
4574 you can declare data or BSS items before beginning to write code if
4575 you want to and the code will still end up at the front of the file
4578 The BSS (uninitialised data) section does not take up space in the
4579 \c{.COM} file itself: instead, addresses of BSS items are resolved
4580 to point at space beyond the end of the file, on the grounds that
4581 this will be free memory when the program is run. Therefore you
4582 should not rely on your BSS being initialised to all zeros when you
4585 To assemble the above program, you should use a command line like
4587 \c nasm myprog.asm -fbin -o myprog.com
4589 The \c{bin} format would produce a file called \c{myprog} if no
4590 explicit output file name were specified, so you have to override it
4591 and give the desired file name.
4594 \S{comobjfmt} Using the \c{obj} Format To Generate \c{.COM} Files
4596 If you are writing a \c{.COM} program as more than one module, you
4597 may wish to assemble several \c{.OBJ} files and link them together
4598 into a \c{.COM} program. You can do this, provided you have a linker
4599 capable of outputting \c{.COM} files directly (\i{TLINK} does this),
4600 or alternatively a converter program such as \i\c{EXE2BIN} to
4601 transform the \c{.EXE} file output from the linker into a \c{.COM}
4604 If you do this, you need to take care of several things:
4606 \b The first object file containing code should start its code
4607 segment with a line like \c{RESB 100h}. This is to ensure that the
4608 code begins at offset \c{100h} relative to the beginning of the code
4609 segment, so that the linker or converter program does not have to
4610 adjust address references within the file when generating the
4611 \c{.COM} file. Other assemblers use an \i\c{ORG} directive for this
4612 purpose, but \c{ORG} in NASM is a format-specific directive to the
4613 \c{bin} output format, and does not mean the same thing as it does
4614 in MASM-compatible assemblers.
4616 \b You don't need to define a stack segment.
4618 \b All your segments should be in the same group, so that every time
4619 your code or data references a symbol offset, all offsets are
4620 relative to the same segment base. This is because, when a \c{.COM}
4621 file is loaded, all the segment registers contain the same value.
4624 \H{sysfiles} Producing \i\c{.SYS} Files
4626 \i{MS-DOS device drivers} - \c{.SYS} files - are pure binary files,
4627 similar to \c{.COM} files, except that they start at origin zero
4628 rather than \c{100h}. Therefore, if you are writing a device driver
4629 using the \c{bin} format, you do not need the \c{ORG} directive,
4630 since the default origin for \c{bin} is zero. Similarly, if you are
4631 using \c{obj}, you do not need the \c{RESB 100h} at the start of
4634 \c{.SYS} files start with a header structure, containing pointers to
4635 the various routines inside the driver which do the work. This
4636 structure should be defined at the start of the code segment, even
4637 though it is not actually code.
4639 For more information on the format of \c{.SYS} files, and the data
4640 which has to go in the header structure, a list of books is given in
4641 the Frequently Asked Questions list for the newsgroup
4642 \W{news:comp.os.msdos.programmer}\i\c{comp.os.msdos.programmer}.
4645 \H{16c} Interfacing to 16-bit C Programs
4647 This section covers the basics of writing assembly routines that
4648 call, or are called from, C programs. To do this, you would
4649 typically write an assembly module as a \c{.OBJ} file, and link it
4650 with your C modules to produce a \i{mixed-language program}.
4653 \S{16cunder} External Symbol Names
4655 \I{C symbol names}\I{underscore, in C symbols}C compilers have the
4656 convention that the names of all global symbols (functions or data)
4657 they define are formed by prefixing an underscore to the name as it
4658 appears in the C program. So, for example, the function a C
4659 programmer thinks of as \c{printf} appears to an assembly language
4660 programmer as \c{_printf}. This means that in your assembly
4661 programs, you can define symbols without a leading underscore, and
4662 not have to worry about name clashes with C symbols.
4664 If you find the underscores inconvenient, you can define macros to
4665 replace the \c{GLOBAL} and \c{EXTERN} directives as follows:
4681 (These forms of the macros only take one argument at a time; a
4682 \c{%rep} construct could solve this.)
4684 If you then declare an external like this:
4688 then the macro will expand it as
4691 \c %define printf _printf
4693 Thereafter, you can reference \c{printf} as if it was a symbol, and
4694 the preprocessor will put the leading underscore on where necessary.
4696 The \c{cglobal} macro works similarly. You must use \c{cglobal}
4697 before defining the symbol in question, but you would have had to do
4698 that anyway if you used \c{GLOBAL}.
4701 \S{16cmodels} \i{Memory Models}
4703 NASM contains no mechanism to support the various C memory models
4704 directly; you have to keep track yourself of which one you are
4705 writing for. This means you have to keep track of the following
4708 \b In models using a single code segment (tiny, small and compact),
4709 functions are near. This means that function pointers, when stored
4710 in data segments or pushed on the stack as function arguments, are
4711 16 bits long and contain only an offset field (the \c{CS} register
4712 never changes its value, and always gives the segment part of the
4713 full function address), and that functions are called using ordinary
4714 near \c{CALL} instructions and return using \c{RETN} (which, in
4715 NASM, is synonymous with \c{RET} anyway). This means both that you
4716 should write your own routines to return with \c{RETN}, and that you
4717 should call external C routines with near \c{CALL} instructions.
4719 \b In models using more than one code segment (medium, large and
4720 huge), functions are far. This means that function pointers are 32
4721 bits long (consisting of a 16-bit offset followed by a 16-bit
4722 segment), and that functions are called using \c{CALL FAR} (or
4723 \c{CALL seg:offset}) and return using \c{RETF}. Again, you should
4724 therefore write your own routines to return with \c{RETF} and use
4725 \c{CALL FAR} to call external routines.
4727 \b In models using a single data segment (tiny, small and medium),
4728 data pointers are 16 bits long, containing only an offset field (the
4729 \c{DS} register doesn't change its value, and always gives the
4730 segment part of the full data item address).
4732 \b In models using more than one data segment (compact, large and
4733 huge), data pointers are 32 bits long, consisting of a 16-bit offset
4734 followed by a 16-bit segment. You should still be careful not to
4735 modify \c{DS} in your routines without restoring it afterwards, but
4736 \c{ES} is free for you to use to access the contents of 32-bit data
4737 pointers you are passed.
4739 \b The huge memory model allows single data items to exceed 64K in
4740 size. In all other memory models, you can access the whole of a data
4741 item just by doing arithmetic on the offset field of the pointer you
4742 are given, whether a segment field is present or not; in huge model,
4743 you have to be more careful of your pointer arithmetic.
4745 \b In most memory models, there is a \e{default} data segment, whose
4746 segment address is kept in \c{DS} throughout the program. This data
4747 segment is typically the same segment as the stack, kept in \c{SS},
4748 so that functions' local variables (which are stored on the stack)
4749 and global data items can both be accessed easily without changing
4750 \c{DS}. Particularly large data items are typically stored in other
4751 segments. However, some memory models (though not the standard
4752 ones, usually) allow the assumption that \c{SS} and \c{DS} hold the
4753 same value to be removed. Be careful about functions' local
4754 variables in this latter case.
4756 In models with a single code segment, the segment is called
4757 \i\c{_TEXT}, so your code segment must also go by this name in order
4758 to be linked into the same place as the main code segment. In models
4759 with a single data segment, or with a default data segment, it is
4763 \S{16cfunc} Function Definitions and Function Calls
4765 \I{functions, C calling convention}The \i{C calling convention} in
4766 16-bit programs is as follows. In the following description, the
4767 words \e{caller} and \e{callee} are used to denote the function
4768 doing the calling and the function which gets called.
4770 \b The caller pushes the function's parameters on the stack, one
4771 after another, in reverse order (right to left, so that the first
4772 argument specified to the function is pushed last).
4774 \b The caller then executes a \c{CALL} instruction to pass control
4775 to the callee. This \c{CALL} is either near or far depending on the
4778 \b The callee receives control, and typically (although this is not
4779 actually necessary, in functions which do not need to access their
4780 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
4781 be able to use \c{BP} as a base pointer to find its parameters on
4782 the stack. However, the caller was probably doing this too, so part
4783 of the calling convention states that \c{BP} must be preserved by
4784 any C function. Hence the callee, if it is going to set up \c{BP} as
4785 a \i\e{frame pointer}, must push the previous value first.
4787 \b The callee may then access its parameters relative to \c{BP}.
4788 The word at \c{[BP]} holds the previous value of \c{BP} as it was
4789 pushed; the next word, at \c{[BP+2]}, holds the offset part of the
4790 return address, pushed implicitly by \c{CALL}. In a small-model
4791 (near) function, the parameters start after that, at \c{[BP+4]}; in
4792 a large-model (far) function, the segment part of the return address
4793 lives at \c{[BP+4]}, and the parameters begin at \c{[BP+6]}. The
4794 leftmost parameter of the function, since it was pushed last, is
4795 accessible at this offset from \c{BP}; the others follow, at
4796 successively greater offsets. Thus, in a function such as \c{printf}
4797 which takes a variable number of parameters, the pushing of the
4798 parameters in reverse order means that the function knows where to
4799 find its first parameter, which tells it the number and type of the
4802 \b The callee may also wish to decrease \c{SP} further, so as to
4803 allocate space on the stack for local variables, which will then be
4804 accessible at negative offsets from \c{BP}.
4806 \b The callee, if it wishes to return a value to the caller, should
4807 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
4808 of the value. Floating-point results are sometimes (depending on the
4809 compiler) returned in \c{ST0}.
4811 \b Once the callee has finished processing, it restores \c{SP} from
4812 \c{BP} if it had allocated local stack space, then pops the previous
4813 value of \c{BP}, and returns via \c{RETN} or \c{RETF} depending on
4816 \b When the caller regains control from the callee, the function
4817 parameters are still on the stack, so it typically adds an immediate
4818 constant to \c{SP} to remove them (instead of executing a number of
4819 slow \c{POP} instructions). Thus, if a function is accidentally
4820 called with the wrong number of parameters due to a prototype
4821 mismatch, the stack will still be returned to a sensible state since
4822 the caller, which \e{knows} how many parameters it pushed, does the
4825 It is instructive to compare this calling convention with that for
4826 Pascal programs (described in \k{16bpfunc}). Pascal has a simpler
4827 convention, since no functions have variable numbers of parameters.
4828 Therefore the callee knows how many parameters it should have been
4829 passed, and is able to deallocate them from the stack itself by
4830 passing an immediate argument to the \c{RET} or \c{RETF}
4831 instruction, so the caller does not have to do it. Also, the
4832 parameters are pushed in left-to-right order, not right-to-left,
4833 which means that a compiler can give better guarantees about
4834 sequence points without performance suffering.
4836 Thus, you would define a function in C style in the following way.
4837 The following example is for small model:
4844 \c sub sp,0x40 ; 64 bytes of local stack space
4845 \c mov bx,[bp+4] ; first parameter to function
4849 \c mov sp,bp ; undo "sub sp,0x40" above
4853 For a large-model function, you would replace \c{RET} by \c{RETF},
4854 and look for the first parameter at \c{[BP+6]} instead of
4855 \c{[BP+4]}. Of course, if one of the parameters is a pointer, then
4856 the offsets of \e{subsequent} parameters will change depending on
4857 the memory model as well: far pointers take up four bytes on the
4858 stack when passed as a parameter, whereas near pointers take up two.
4860 At the other end of the process, to call a C function from your
4861 assembly code, you would do something like this:
4865 \c ; and then, further down...
4867 \c push word [myint] ; one of my integer variables
4868 \c push word mystring ; pointer into my data segment
4870 \c add sp,byte 4 ; `byte' saves space
4872 \c ; then those data items...
4877 \c mystring db 'This number -> %d <- should be 1234',10,0
4879 This piece of code is the small-model assembly equivalent of the C
4882 \c int myint = 1234;
4883 \c printf("This number -> %d <- should be 1234\n", myint);
4885 In large model, the function-call code might look more like this. In
4886 this example, it is assumed that \c{DS} already holds the segment
4887 base of the segment \c{_DATA}. If not, you would have to initialise
4890 \c push word [myint]
4891 \c push word seg mystring ; Now push the segment, and...
4892 \c push word mystring ; ... offset of "mystring"
4896 The integer value still takes up one word on the stack, since large
4897 model does not affect the size of the \c{int} data type. The first
4898 argument (pushed last) to \c{printf}, however, is a data pointer,
4899 and therefore has to contain a segment and offset part. The segment
4900 should be stored second in memory, and therefore must be pushed
4901 first. (Of course, \c{PUSH DS} would have been a shorter instruction
4902 than \c{PUSH WORD SEG mystring}, if \c{DS} was set up as the above
4903 example assumed.) Then the actual call becomes a far call, since
4904 functions expect far calls in large model; and \c{SP} has to be
4905 increased by 6 rather than 4 afterwards to make up for the extra
4909 \S{16cdata} Accessing Data Items
4911 To get at the contents of C variables, or to declare variables which
4912 C can access, you need only declare the names as \c{GLOBAL} or
4913 \c{EXTERN}. (Again, the names require leading underscores, as stated
4914 in \k{16cunder}.) Thus, a C variable declared as \c{int i} can be
4915 accessed from assembler as
4921 And to declare your own integer variable which C programs can access
4922 as \c{extern int j}, you do this (making sure you are assembling in
4923 the \c{_DATA} segment, if necessary):
4929 To access a C array, you need to know the size of the components of
4930 the array. For example, \c{int} variables are two bytes long, so if
4931 a C program declares an array as \c{int a[10]}, you can access
4932 \c{a[3]} by coding \c{mov ax,[_a+6]}. (The byte offset 6 is obtained
4933 by multiplying the desired array index, 3, by the size of the array
4934 element, 2.) The sizes of the C base types in 16-bit compilers are:
4935 1 for \c{char}, 2 for \c{short} and \c{int}, 4 for \c{long} and
4936 \c{float}, and 8 for \c{double}.
4938 To access a C \i{data structure}, you need to know the offset from
4939 the base of the structure to the field you are interested in. You
4940 can either do this by converting the C structure definition into a
4941 NASM structure definition (using \i\c{STRUC}), or by calculating the
4942 one offset and using just that.
4944 To do either of these, you should read your C compiler's manual to
4945 find out how it organises data structures. NASM gives no special
4946 alignment to structure members in its own \c{STRUC} macro, so you
4947 have to specify alignment yourself if the C compiler generates it.
4948 Typically, you might find that a structure like
4955 might be four bytes long rather than three, since the \c{int} field
4956 would be aligned to a two-byte boundary. However, this sort of
4957 feature tends to be a configurable option in the C compiler, either
4958 using command-line options or \c{#pragma} lines, so you have to find
4959 out how your own compiler does it.
4962 \S{16cmacro} \i\c{c16.mac}: Helper Macros for the 16-bit C Interface
4964 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4965 directory, is a file \c{c16.mac} of macros. It defines three macros:
4966 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
4967 used for C-style procedure definitions, and they automate a lot of
4968 the work involved in keeping track of the calling convention.
4970 (An alternative, TASM compatible form of \c{arg} is also now built
4971 into NASM's preprocessor. See \k{tasmcompat} for details.)
4973 An example of an assembly function using the macro set is given
4980 \c mov ax,[bp + %$i]
4981 \c mov bx,[bp + %$j]
4986 This defines \c{_nearproc} to be a procedure taking two arguments,
4987 the first (\c{i}) an integer and the second (\c{j}) a pointer to an
4988 integer. It returns \c{i + *j}.
4990 Note that the \c{arg} macro has an \c{EQU} as the first line of its
4991 expansion, and since the label before the macro call gets prepended
4992 to the first line of the expanded macro, the \c{EQU} works, defining
4993 \c{%$i} to be an offset from \c{BP}. A context-local variable is
4994 used, local to the context pushed by the \c{proc} macro and popped
4995 by the \c{endproc} macro, so that the same argument name can be used
4996 in later procedures. Of course, you don't \e{have} to do that.
4998 The macro set produces code for near functions (tiny, small and
4999 compact-model code) by default. You can have it generate far
5000 functions (medium, large and huge-model code) by means of coding
5001 \I\c{FARCODE}\c{%define FARCODE}. This changes the kind of return
5002 instruction generated by \c{endproc}, and also changes the starting
5003 point for the argument offsets. The macro set contains no intrinsic
5004 dependency on whether data pointers are far or not.
5006 \c{arg} can take an optional parameter, giving the size of the
5007 argument. If no size is given, 2 is assumed, since it is likely that
5008 many function parameters will be of type \c{int}.
5010 The large-model equivalent of the above function would look like this:
5018 \c mov ax,[bp + %$i]
5019 \c mov bx,[bp + %$j]
5020 \c mov es,[bp + %$j + 2]
5025 This makes use of the argument to the \c{arg} macro to define a
5026 parameter of size 4, because \c{j} is now a far pointer. When we
5027 load from \c{j}, we must load a segment and an offset.
5030 \H{16bp} Interfacing to \i{Borland Pascal} Programs
5032 Interfacing to Borland Pascal programs is similar in concept to
5033 interfacing to 16-bit C programs. The differences are:
5035 \b The leading underscore required for interfacing to C programs is
5036 not required for Pascal.
5038 \b The memory model is always large: functions are far, data
5039 pointers are far, and no data item can be more than 64K long.
5040 (Actually, some functions are near, but only those functions that
5041 are local to a Pascal unit and never called from outside it. All
5042 assembly functions that Pascal calls, and all Pascal functions that
5043 assembly routines are able to call, are far.) However, all static
5044 data declared in a Pascal program goes into the default data
5045 segment, which is the one whose segment address will be in \c{DS}
5046 when control is passed to your assembly code. The only things that
5047 do not live in the default data segment are local variables (they
5048 live in the stack segment) and dynamically allocated variables. All
5049 data \e{pointers}, however, are far.
5051 \b The function calling convention is different - described below.
5053 \b Some data types, such as strings, are stored differently.
5055 \b There are restrictions on the segment names you are allowed to
5056 use - Borland Pascal will ignore code or data declared in a segment
5057 it doesn't like the name of. The restrictions are described below.
5060 \S{16bpfunc} The Pascal Calling Convention
5062 \I{functions, Pascal calling convention}\I{Pascal calling
5063 convention}The 16-bit Pascal calling convention is as follows. In
5064 the following description, the words \e{caller} and \e{callee} are
5065 used to denote the function doing the calling and the function which
5068 \b The caller pushes the function's parameters on the stack, one
5069 after another, in normal order (left to right, so that the first
5070 argument specified to the function is pushed first).
5072 \b The caller then executes a far \c{CALL} instruction to pass
5073 control to the callee.
5075 \b The callee receives control, and typically (although this is not
5076 actually necessary, in functions which do not need to access their
5077 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
5078 be able to use \c{BP} as a base pointer to find its parameters on
5079 the stack. However, the caller was probably doing this too, so part
5080 of the calling convention states that \c{BP} must be preserved by
5081 any function. Hence the callee, if it is going to set up \c{BP} as a
5082 \i{frame pointer}, must push the previous value first.
5084 \b The callee may then access its parameters relative to \c{BP}.
5085 The word at \c{[BP]} holds the previous value of \c{BP} as it was
5086 pushed. The next word, at \c{[BP+2]}, holds the offset part of the
5087 return address, and the next one at \c{[BP+4]} the segment part. The
5088 parameters begin at \c{[BP+6]}. The rightmost parameter of the
5089 function, since it was pushed last, is accessible at this offset
5090 from \c{BP}; the others follow, at successively greater offsets.
5092 \b The callee may also wish to decrease \c{SP} further, so as to
5093 allocate space on the stack for local variables, which will then be
5094 accessible at negative offsets from \c{BP}.
5096 \b The callee, if it wishes to return a value to the caller, should
5097 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
5098 of the value. Floating-point results are returned in \c{ST0}.
5099 Results of type \c{Real} (Borland's own custom floating-point data
5100 type, not handled directly by the FPU) are returned in \c{DX:BX:AX}.
5101 To return a result of type \c{String}, the caller pushes a pointer
5102 to a temporary string before pushing the parameters, and the callee
5103 places the returned string value at that location. The pointer is
5104 not a parameter, and should not be removed from the stack by the
5105 \c{RETF} instruction.
5107 \b Once the callee has finished processing, it restores \c{SP} from
5108 \c{BP} if it had allocated local stack space, then pops the previous
5109 value of \c{BP}, and returns via \c{RETF}. It uses the form of
5110 \c{RETF} with an immediate parameter, giving the number of bytes
5111 taken up by the parameters on the stack. This causes the parameters
5112 to be removed from the stack as a side effect of the return
5115 \b When the caller regains control from the callee, the function
5116 parameters have already been removed from the stack, so it needs to
5119 Thus, you would define a function in Pascal style, taking two
5120 \c{Integer}-type parameters, in the following way:
5126 \c sub sp,0x40 ; 64 bytes of local stack space
5127 \c mov bx,[bp+8] ; first parameter to function
5128 \c mov bx,[bp+6] ; second parameter to function
5132 \c mov sp,bp ; undo "sub sp,0x40" above
5134 \c retf 4 ; total size of params is 4
5136 At the other end of the process, to call a Pascal function from your
5137 assembly code, you would do something like this:
5141 \c ; and then, further down...
5143 \c push word seg mystring ; Now push the segment, and...
5144 \c push word mystring ; ... offset of "mystring"
5145 \c push word [myint] ; one of my variables
5146 \c call far SomeFunc
5148 This is equivalent to the Pascal code
5150 \c procedure SomeFunc(String: PChar; Int: Integer);
5151 \c SomeFunc(@mystring, myint);
5154 \S{16bpseg} Borland Pascal \I{segment names, Borland Pascal}Segment
5157 Since Borland Pascal's internal unit file format is completely
5158 different from \c{OBJ}, it only makes a very sketchy job of actually
5159 reading and understanding the various information contained in a
5160 real \c{OBJ} file when it links that in. Therefore an object file
5161 intended to be linked to a Pascal program must obey a number of
5164 \b Procedures and functions must be in a segment whose name is
5165 either \c{CODE}, \c{CSEG}, or something ending in \c{_TEXT}.
5167 \b Initialised data must be in a segment whose name is either
5168 \c{CONST} or something ending in \c{_DATA}.
5170 \b Uninitialised data must be in a segment whose name is either
5171 \c{DATA}, \c{DSEG}, or something ending in \c{_BSS}.
5173 \b Any other segments in the object file are completely ignored.
5174 \c{GROUP} directives and segment attributes are also ignored.
5177 \S{16bpmacro} Using \i\c{c16.mac} With Pascal Programs
5179 The \c{c16.mac} macro package, described in \k{16cmacro}, can also
5180 be used to simplify writing functions to be called from Pascal
5181 programs, if you code \I\c{PASCAL}\c{%define PASCAL}. This
5182 definition ensures that functions are far (it implies
5183 \i\c{FARCODE}), and also causes procedure return instructions to be
5184 generated with an operand.
5186 Defining \c{PASCAL} does not change the code which calculates the
5187 argument offsets; you must declare your function's arguments in
5188 reverse order. For example:
5196 \c mov ax,[bp + %$i]
5197 \c mov bx,[bp + %$j]
5198 \c mov es,[bp + %$j + 2]
5203 This defines the same routine, conceptually, as the example in
5204 \k{16cmacro}: it defines a function taking two arguments, an integer
5205 and a pointer to an integer, which returns the sum of the integer
5206 and the contents of the pointer. The only difference between this
5207 code and the large-model C version is that \c{PASCAL} is defined
5208 instead of \c{FARCODE}, and that the arguments are declared in
5212 \C{32bit} Writing 32-bit Code (Unix, Win32, DJGPP)
5214 This chapter attempts to cover some of the common issues involved
5215 when writing 32-bit code, to run under \i{Win32} or Unix, or to be
5216 linked with C code generated by a Unix-style C compiler such as
5217 \i{DJGPP}. It covers how to write assembly code to interface with
5218 32-bit C routines, and how to write position-independent code for
5221 Almost all 32-bit code, and in particular all code running under
5222 \c{Win32}, \c{DJGPP} or any of the PC Unix variants, runs in \I{flat
5223 memory model}\e{flat} memory model. This means that the segment registers
5224 and paging have already been set up to give you the same 32-bit 4Gb
5225 address space no matter what segment you work relative to, and that
5226 you should ignore all segment registers completely. When writing
5227 flat-model application code, you never need to use a segment
5228 override or modify any segment register, and the code-section
5229 addresses you pass to \c{CALL} and \c{JMP} live in the same address
5230 space as the data-section addresses you access your variables by and
5231 the stack-section addresses you access local variables and procedure
5232 parameters by. Every address is 32 bits long and contains only an
5236 \H{32c} Interfacing to 32-bit C Programs
5238 A lot of the discussion in \k{16c}, about interfacing to 16-bit C
5239 programs, still applies when working in 32 bits. The absence of
5240 memory models or segmentation worries simplifies things a lot.
5243 \S{32cunder} External Symbol Names
5245 Most 32-bit C compilers share the convention used by 16-bit
5246 compilers, that the names of all global symbols (functions or data)
5247 they define are formed by prefixing an underscore to the name as it
5248 appears in the C program. However, not all of them do: the \c{ELF}
5249 specification states that C symbols do \e{not} have a leading
5250 underscore on their assembly-language names.
5252 The older Linux \c{a.out} C compiler, all \c{Win32} compilers,
5253 \c{DJGPP}, and \c{NetBSD} and \c{FreeBSD}, all use the leading
5254 underscore; for these compilers, the macros \c{cextern} and
5255 \c{cglobal}, as given in \k{16cunder}, will still work. For \c{ELF},
5256 though, the leading underscore should not be used.
5259 \S{32cfunc} Function Definitions and Function Calls
5261 \I{functions, C calling convention}The \i{C calling convention}The C
5262 calling convention in 32-bit programs is as follows. In the
5263 following description, the words \e{caller} and \e{callee} are used
5264 to denote the function doing the calling and the function which gets
5267 \b The caller pushes the function's parameters on the stack, one
5268 after another, in reverse order (right to left, so that the first
5269 argument specified to the function is pushed last).
5271 \b The caller then executes a near \c{CALL} instruction to pass
5272 control to the callee.
5274 \b The callee receives control, and typically (although this is not
5275 actually necessary, in functions which do not need to access their
5276 parameters) starts by saving the value of \c{ESP} in \c{EBP} so as
5277 to be able to use \c{EBP} as a base pointer to find its parameters
5278 on the stack. However, the caller was probably doing this too, so
5279 part of the calling convention states that \c{EBP} must be preserved
5280 by any C function. Hence the callee, if it is going to set up
5281 \c{EBP} as a \i{frame pointer}, must push the previous value first.
5283 \b The callee may then access its parameters relative to \c{EBP}.
5284 The doubleword at \c{[EBP]} holds the previous value of \c{EBP} as
5285 it was pushed; the next doubleword, at \c{[EBP+4]}, holds the return
5286 address, pushed implicitly by \c{CALL}. The parameters start after
5287 that, at \c{[EBP+8]}. The leftmost parameter of the function, since
5288 it was pushed last, is accessible at this offset from \c{EBP}; the
5289 others follow, at successively greater offsets. Thus, in a function
5290 such as \c{printf} which takes a variable number of parameters, the
5291 pushing of the parameters in reverse order means that the function
5292 knows where to find its first parameter, which tells it the number
5293 and type of the remaining ones.
5295 \b The callee may also wish to decrease \c{ESP} further, so as to
5296 allocate space on the stack for local variables, which will then be
5297 accessible at negative offsets from \c{EBP}.
5299 \b The callee, if it wishes to return a value to the caller, should
5300 leave the value in \c{AL}, \c{AX} or \c{EAX} depending on the size
5301 of the value. Floating-point results are typically returned in
5304 \b Once the callee has finished processing, it restores \c{ESP} from
5305 \c{EBP} if it had allocated local stack space, then pops the previous
5306 value of \c{EBP}, and returns via \c{RET} (equivalently, \c{RETN}).
5308 \b When the caller regains control from the callee, the function
5309 parameters are still on the stack, so it typically adds an immediate
5310 constant to \c{ESP} to remove them (instead of executing a number of
5311 slow \c{POP} instructions). Thus, if a function is accidentally
5312 called with the wrong number of parameters due to a prototype
5313 mismatch, the stack will still be returned to a sensible state since
5314 the caller, which \e{knows} how many parameters it pushed, does the
5317 There is an alternative calling convention used by Win32 programs
5318 for Windows API calls, and also for functions called \e{by} the
5319 Windows API such as window procedures: they follow what Microsoft
5320 calls the \c{__stdcall} convention. This is slightly closer to the
5321 Pascal convention, in that the callee clears the stack by passing a
5322 parameter to the \c{RET} instruction. However, the parameters are
5323 still pushed in right-to-left order.
5325 Thus, you would define a function in C style in the following way:
5332 \c sub esp,0x40 ; 64 bytes of local stack space
5333 \c mov ebx,[ebp+8] ; first parameter to function
5337 \c leave ; mov esp,ebp / pop ebp
5340 At the other end of the process, to call a C function from your
5341 assembly code, you would do something like this:
5345 \c ; and then, further down...
5347 \c push dword [myint] ; one of my integer variables
5348 \c push dword mystring ; pointer into my data segment
5350 \c add esp,byte 8 ; `byte' saves space
5352 \c ; then those data items...
5357 \c mystring db 'This number -> %d <- should be 1234',10,0
5359 This piece of code is the assembly equivalent of the C code
5361 \c int myint = 1234;
5362 \c printf("This number -> %d <- should be 1234\n", myint);
5365 \S{32cdata} Accessing Data Items
5367 To get at the contents of C variables, or to declare variables which
5368 C can access, you need only declare the names as \c{GLOBAL} or
5369 \c{EXTERN}. (Again, the names require leading underscores, as stated
5370 in \k{32cunder}.) Thus, a C variable declared as \c{int i} can be
5371 accessed from assembler as
5376 And to declare your own integer variable which C programs can access
5377 as \c{extern int j}, you do this (making sure you are assembling in
5378 the \c{_DATA} segment, if necessary):
5383 To access a C array, you need to know the size of the components of
5384 the array. For example, \c{int} variables are four bytes long, so if
5385 a C program declares an array as \c{int a[10]}, you can access
5386 \c{a[3]} by coding \c{mov ax,[_a+12]}. (The byte offset 12 is obtained
5387 by multiplying the desired array index, 3, by the size of the array
5388 element, 4.) The sizes of the C base types in 32-bit compilers are:
5389 1 for \c{char}, 2 for \c{short}, 4 for \c{int}, \c{long} and
5390 \c{float}, and 8 for \c{double}. Pointers, being 32-bit addresses,
5391 are also 4 bytes long.
5393 To access a C \i{data structure}, you need to know the offset from
5394 the base of the structure to the field you are interested in. You
5395 can either do this by converting the C structure definition into a
5396 NASM structure definition (using \c{STRUC}), or by calculating the
5397 one offset and using just that.
5399 To do either of these, you should read your C compiler's manual to
5400 find out how it organises data structures. NASM gives no special
5401 alignment to structure members in its own \i\c{STRUC} macro, so you
5402 have to specify alignment yourself if the C compiler generates it.
5403 Typically, you might find that a structure like
5410 might be eight bytes long rather than five, since the \c{int} field
5411 would be aligned to a four-byte boundary. However, this sort of
5412 feature is sometimes a configurable option in the C compiler, either
5413 using command-line options or \c{#pragma} lines, so you have to find
5414 out how your own compiler does it.
5417 \S{32cmacro} \i\c{c32.mac}: Helper Macros for the 32-bit C Interface
5419 Included in the NASM archives, in the \I{misc directory}\c{misc}
5420 directory, is a file \c{c32.mac} of macros. It defines three macros:
5421 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
5422 used for C-style procedure definitions, and they automate a lot of
5423 the work involved in keeping track of the calling convention.
5425 An example of an assembly function using the macro set is given
5432 \c mov eax,[ebp + %$i]
5433 \c mov ebx,[ebp + %$j]
5438 This defines \c{_proc32} to be a procedure taking two arguments, the
5439 first (\c{i}) an integer and the second (\c{j}) a pointer to an
5440 integer. It returns \c{i + *j}.
5442 Note that the \c{arg} macro has an \c{EQU} as the first line of its
5443 expansion, and since the label before the macro call gets prepended
5444 to the first line of the expanded macro, the \c{EQU} works, defining
5445 \c{%$i} to be an offset from \c{BP}. A context-local variable is
5446 used, local to the context pushed by the \c{proc} macro and popped
5447 by the \c{endproc} macro, so that the same argument name can be used
5448 in later procedures. Of course, you don't \e{have} to do that.
5450 \c{arg} can take an optional parameter, giving the size of the
5451 argument. If no size is given, 4 is assumed, since it is likely that
5452 many function parameters will be of type \c{int} or pointers.
5455 \H{picdll} Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF \i{Shared
5458 \c{ELF} replaced the older \c{a.out} object file format under Linux
5459 because it contains support for \i{position-independent code}
5460 (\i{PIC}), which makes writing shared libraries much easier. NASM
5461 supports the \c{ELF} position-independent code features, so you can
5462 write Linux \c{ELF} shared libraries in NASM.
5464 \i{NetBSD}, and its close cousins \i{FreeBSD} and \i{OpenBSD}, take
5465 a different approach by hacking PIC support into the \c{a.out}
5466 format. NASM supports this as the \i\c{aoutb} output format, so you
5467 can write \i{BSD} shared libraries in NASM too.
5469 The operating system loads a PIC shared library by memory-mapping
5470 the library file at an arbitrarily chosen point in the address space
5471 of the running process. The contents of the library's code section
5472 must therefore not depend on where it is loaded in memory.
5474 Therefore, you cannot get at your variables by writing code like
5477 \c mov eax,[myvar] ; WRONG
5479 Instead, the linker provides an area of memory called the
5480 \i\e{global offset table}, or \i{GOT}; the GOT is situated at a
5481 constant distance from your library's code, so if you can find out
5482 where your library is loaded (which is typically done using a
5483 \c{CALL} and \c{POP} combination), you can obtain the address of the
5484 GOT, and you can then load the addresses of your variables out of
5485 linker-generated entries in the GOT.
5487 The \e{data} section of a PIC shared library does not have these
5488 restrictions: since the data section is writable, it has to be
5489 copied into memory anyway rather than just paged in from the library
5490 file, so as long as it's being copied it can be relocated too. So
5491 you can put ordinary types of relocation in the data section without
5492 too much worry (but see \k{picglobal} for a caveat).
5495 \S{picgot} Obtaining the Address of the GOT
5497 Each code module in your shared library should define the GOT as an
5500 \c extern _GLOBAL_OFFSET_TABLE_ ; in ELF
5501 \c extern __GLOBAL_OFFSET_TABLE_ ; in BSD a.out
5503 At the beginning of any function in your shared library which plans
5504 to access your data or BSS sections, you must first calculate the
5505 address of the GOT. This is typically done by writing the function
5514 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-.get_GOT wrt ..gotpc
5516 \c ; the function body comes here
5523 (For BSD, again, the symbol \c{_GLOBAL_OFFSET_TABLE} requires a
5524 second leading underscore.)
5526 The first two lines of this function are simply the standard C
5527 prologue to set up a stack frame, and the last three lines are
5528 standard C function epilogue. The third line, and the fourth to last
5529 line, save and restore the \c{EBX} register, because PIC shared
5530 libraries use this register to store the address of the GOT.
5532 The interesting bit is the \c{CALL} instruction and the following
5533 two lines. The \c{CALL} and \c{POP} combination obtains the address
5534 of the label \c{.get_GOT}, without having to know in advance where
5535 the program was loaded (since the \c{CALL} instruction is encoded
5536 relative to the current position). The \c{ADD} instruction makes use
5537 of one of the special PIC relocation types: \i{GOTPC relocation}.
5538 With the \i\c{WRT ..gotpc} qualifier specified, the symbol
5539 referenced (here \c{_GLOBAL_OFFSET_TABLE_}, the special symbol
5540 assigned to the GOT) is given as an offset from the beginning of the
5541 section. (Actually, \c{ELF} encodes it as the offset from the operand
5542 field of the \c{ADD} instruction, but NASM simplifies this
5543 deliberately, so you do things the same way for both \c{ELF} and
5544 \c{BSD}.) So the instruction then \e{adds} the beginning of the section,
5545 to get the real address of the GOT, and subtracts the value of
5546 \c{.get_GOT} which it knows is in \c{EBX}. Therefore, by the time
5547 that instruction has finished, \c{EBX} contains the address of the GOT.
5549 If you didn't follow that, don't worry: it's never necessary to
5550 obtain the address of the GOT by any other means, so you can put
5551 those three instructions into a macro and safely ignore them:
5558 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc
5562 \S{piclocal} Finding Your Local Data Items
5564 Having got the GOT, you can then use it to obtain the addresses of
5565 your data items. Most variables will reside in the sections you have
5566 declared; they can be accessed using the \I{GOTOFF
5567 relocation}\c{..gotoff} special \I\c{WRT ..gotoff}\c{WRT} type. The
5568 way this works is like this:
5570 \c lea eax,[ebx+myvar wrt ..gotoff]
5572 The expression \c{myvar wrt ..gotoff} is calculated, when the shared
5573 library is linked, to be the offset to the local variable \c{myvar}
5574 from the beginning of the GOT. Therefore, adding it to \c{EBX} as
5575 above will place the real address of \c{myvar} in \c{EAX}.
5577 If you declare variables as \c{GLOBAL} without specifying a size for
5578 them, they are shared between code modules in the library, but do
5579 not get exported from the library to the program that loaded it.
5580 They will still be in your ordinary data and BSS sections, so you
5581 can access them in the same way as local variables, using the above
5582 \c{..gotoff} mechanism.
5584 Note that due to a peculiarity of the way BSD \c{a.out} format
5585 handles this relocation type, there must be at least one non-local
5586 symbol in the same section as the address you're trying to access.
5589 \S{picextern} Finding External and Common Data Items
5591 If your library needs to get at an external variable (external to
5592 the \e{library}, not just to one of the modules within it), you must
5593 use the \I{GOT relocations}\I\c{WRT ..got}\c{..got} type to get at
5594 it. The \c{..got} type, instead of giving you the offset from the
5595 GOT base to the variable, gives you the offset from the GOT base to
5596 a GOT \e{entry} containing the address of the variable. The linker
5597 will set up this GOT entry when it builds the library, and the
5598 dynamic linker will place the correct address in it at load time. So
5599 to obtain the address of an external variable \c{extvar} in \c{EAX},
5602 \c mov eax,[ebx+extvar wrt ..got]
5604 This loads the address of \c{extvar} out of an entry in the GOT. The
5605 linker, when it builds the shared library, collects together every
5606 relocation of type \c{..got}, and builds the GOT so as to ensure it
5607 has every necessary entry present.
5609 Common variables must also be accessed in this way.
5612 \S{picglobal} Exporting Symbols to the Library User
5614 If you want to export symbols to the user of the library, you have
5615 to declare whether they are functions or data, and if they are data,
5616 you have to give the size of the data item. This is because the
5617 dynamic linker has to build \I{PLT}\i{procedure linkage table}
5618 entries for any exported functions, and also moves exported data
5619 items away from the library's data section in which they were
5622 So to export a function to users of the library, you must use
5624 \c global func:function ; declare it as a function
5630 And to export a data item such as an array, you would have to code
5632 \c global array:data array.end-array ; give the size too
5637 Be careful: If you export a variable to the library user, by
5638 declaring it as \c{GLOBAL} and supplying a size, the variable will
5639 end up living in the data section of the main program, rather than
5640 in your library's data section, where you declared it. So you will
5641 have to access your own global variable with the \c{..got} mechanism
5642 rather than \c{..gotoff}, as if it were external (which,
5643 effectively, it has become).
5645 Equally, if you need to store the address of an exported global in
5646 one of your data sections, you can't do it by means of the standard
5649 \c dataptr: dd global_data_item ; WRONG
5651 NASM will interpret this code as an ordinary relocation, in which
5652 \c{global_data_item} is merely an offset from the beginning of the
5653 \c{.data} section (or whatever); so this reference will end up
5654 pointing at your data section instead of at the exported global
5655 which resides elsewhere.
5657 Instead of the above code, then, you must write
5659 \c dataptr: dd global_data_item wrt ..sym
5661 which makes use of the special \c{WRT} type \I\c{WRT ..sym}\c{..sym}
5662 to instruct NASM to search the symbol table for a particular symbol
5663 at that address, rather than just relocating by section base.
5665 Either method will work for functions: referring to one of your
5666 functions by means of
5668 \c funcptr: dd my_function
5670 will give the user the address of the code you wrote, whereas
5672 \c funcptr: dd my_function wrt .sym
5674 will give the address of the procedure linkage table for the
5675 function, which is where the calling program will \e{believe} the
5676 function lives. Either address is a valid way to call the function.
5679 \S{picproc} Calling Procedures Outside the Library
5681 Calling procedures outside your shared library has to be done by
5682 means of a \i\e{procedure linkage table}, or \i{PLT}. The PLT is
5683 placed at a known offset from where the library is loaded, so the
5684 library code can make calls to the PLT in a position-independent
5685 way. Within the PLT there is code to jump to offsets contained in
5686 the GOT, so function calls to other shared libraries or to routines
5687 in the main program can be transparently passed off to their real
5690 To call an external routine, you must use another special PIC
5691 relocation type, \I{PLT relocations}\i\c{WRT ..plt}. This is much
5692 easier than the GOT-based ones: you simply replace calls such as
5693 \c{CALL printf} with the PLT-relative version \c{CALL printf WRT
5697 \S{link} Generating the Library File
5699 Having written some code modules and assembled them to \c{.o} files,
5700 you then generate your shared library with a command such as
5702 \c ld -shared -o library.so module1.o module2.o # for ELF
5703 \c ld -Bshareable -o library.so module1.o module2.o # for BSD
5705 For ELF, if your shared library is going to reside in system
5706 directories such as \c{/usr/lib} or \c{/lib}, it is usually worth
5707 using the \i\c{-soname} flag to the linker, to store the final
5708 library file name, with a version number, into the library:
5710 \c ld -shared -soname library.so.1 -o library.so.1.2 *.o
5712 You would then copy \c{library.so.1.2} into the library directory,
5713 and create \c{library.so.1} as a symbolic link to it.
5716 \C{mixsize} Mixing 16 and 32 Bit Code
5718 This chapter tries to cover some of the issues, largely related to
5719 unusual forms of addressing and jump instructions, encountered when
5720 writing operating system code such as protected-mode initialisation
5721 routines, which require code that operates in mixed segment sizes,
5722 such as code in a 16-bit segment trying to modify data in a 32-bit
5723 one, or jumps between different-size segments.
5726 \H{mixjump} Mixed-Size Jumps\I{jumps, mixed-size}
5728 \I{operating system, writing}\I{writing operating systems}The most
5729 common form of \i{mixed-size instruction} is the one used when
5730 writing a 32-bit OS: having done your setup in 16-bit mode, such as
5731 loading the kernel, you then have to boot it by switching into
5732 protected mode and jumping to the 32-bit kernel start address. In a
5733 fully 32-bit OS, this tends to be the \e{only} mixed-size
5734 instruction you need, since everything before it can be done in pure
5735 16-bit code, and everything after it can be pure 32-bit.
5737 This jump must specify a 48-bit far address, since the target
5738 segment is a 32-bit one. However, it must be assembled in a 16-bit
5739 segment, so just coding, for example,
5741 \c jmp 0x1234:0x56789ABC ; wrong!
5743 will not work, since the offset part of the address will be
5744 truncated to \c{0x9ABC} and the jump will be an ordinary 16-bit far
5747 The Linux kernel setup code gets round the inability of \c{as86} to
5748 generate the required instruction by coding it manually, using
5749 \c{DB} instructions. NASM can go one better than that, by actually
5750 generating the right instruction itself. Here's how to do it right:
5752 \c jmp dword 0x1234:0x56789ABC ; right
5754 \I\c{JMP DWORD}The \c{DWORD} prefix (strictly speaking, it should
5755 come \e{after} the colon, since it is declaring the \e{offset} field
5756 to be a doubleword; but NASM will accept either form, since both are
5757 unambiguous) forces the offset part to be treated as far, in the
5758 assumption that you are deliberately writing a jump from a 16-bit
5759 segment to a 32-bit one.
5761 You can do the reverse operation, jumping from a 32-bit segment to a
5762 16-bit one, by means of the \c{WORD} prefix:
5764 \c jmp word 0x8765:0x4321 ; 32 to 16 bit
5766 If the \c{WORD} prefix is specified in 16-bit mode, or the \c{DWORD}
5767 prefix in 32-bit mode, they will be ignored, since each is
5768 explicitly forcing NASM into a mode it was in anyway.
5771 \H{mixaddr} Addressing Between Different-Size Segments\I{addressing,
5772 mixed-size}\I{mixed-size addressing}
5774 If your OS is mixed 16 and 32-bit, or if you are writing a DOS
5775 extender, you are likely to have to deal with some 16-bit segments
5776 and some 32-bit ones. At some point, you will probably end up
5777 writing code in a 16-bit segment which has to access data in a
5778 32-bit segment, or vice versa.
5780 If the data you are trying to access in a 32-bit segment lies within
5781 the first 64K of the segment, you may be able to get away with using
5782 an ordinary 16-bit addressing operation for the purpose; but sooner
5783 or later, you will want to do 32-bit addressing from 16-bit mode.
5785 The easiest way to do this is to make sure you use a register for
5786 the address, since any effective address containing a 32-bit
5787 register is forced to be a 32-bit address. So you can do
5789 \c mov eax,offset_into_32_bit_segment_specified_by_fs
5790 \c mov dword [fs:eax],0x11223344
5792 This is fine, but slightly cumbersome (since it wastes an
5793 instruction and a register) if you already know the precise offset
5794 you are aiming at. The x86 architecture does allow 32-bit effective
5795 addresses to specify nothing but a 4-byte offset, so why shouldn't
5796 NASM be able to generate the best instruction for the purpose?
5798 It can. As in \k{mixjump}, you need only prefix the address with the
5799 \c{DWORD} keyword, and it will be forced to be a 32-bit address:
5801 \c mov dword [fs:dword my_offset],0x11223344
5803 Also as in \k{mixjump}, NASM is not fussy about whether the
5804 \c{DWORD} prefix comes before or after the segment override, so
5805 arguably a nicer-looking way to code the above instruction is
5807 \c mov dword [dword fs:my_offset],0x11223344
5809 Don't confuse the \c{DWORD} prefix \e{outside} the square brackets,
5810 which controls the size of the data stored at the address, with the
5811 one \c{inside} the square brackets which controls the length of the
5812 address itself. The two can quite easily be different:
5814 \c mov word [dword 0x12345678],0x9ABC
5816 This moves 16 bits of data to an address specified by a 32-bit
5819 You can also specify \c{WORD} or \c{DWORD} prefixes along with the
5820 \c{FAR} prefix to indirect far jumps or calls. For example:
5822 \c call dword far [fs:word 0x4321]
5824 This instruction contains an address specified by a 16-bit offset;
5825 it loads a 48-bit far pointer from that (16-bit segment and 32-bit
5826 offset), and calls that address.
5829 \H{mixother} Other Mixed-Size Instructions
5831 The other way you might want to access data might be using the
5832 string instructions (\c{LODSx}, \c{STOSx} and so on) or the
5833 \c{XLATB} instruction. These instructions, since they take no
5834 parameters, might seem to have no easy way to make them perform
5835 32-bit addressing when assembled in a 16-bit segment.
5837 This is the purpose of NASM's \i\c{a16} and \i\c{a32} prefixes. If
5838 you are coding \c{LODSB} in a 16-bit segment but it is supposed to
5839 be accessing a string in a 32-bit segment, you should load the
5840 desired address into \c{ESI} and then code
5844 The prefix forces the addressing size to 32 bits, meaning that
5845 \c{LODSB} loads from \c{[DS:ESI]} instead of \c{[DS:SI]}. To access
5846 a string in a 16-bit segment when coding in a 32-bit one, the
5847 corresponding \c{a16} prefix can be used.
5849 The \c{a16} and \c{a32} prefixes can be applied to any instruction
5850 in NASM's instruction table, but most of them can generate all the
5851 useful forms without them. The prefixes are necessary only for
5852 instructions with implicit addressing: \c{CMPSx} (\k{insCMPSB}),
5853 \c{SCASx} (\k{insSCASB}), \c{LODSx} (\k{insLODSB}), \c{STOSx}
5854 (\k{insSTOSB}), \c{MOVSx} (\k{insMOVSB}), \c{INSx} (\k{insINSB}),
5855 \c{OUTSx} (\k{insOUTSB}), and \c{XLATB} (\k{insXLATB}). Also, the
5856 various push and pop instructions (\c{PUSHA} and \c{POPF} as well as
5857 the more usual \c{PUSH} and \c{POP}) can accept \c{a16} or \c{a32}
5858 prefixes to force a particular one of \c{SP} or \c{ESP} to be used
5859 as a stack pointer, in case the stack segment in use is a different
5860 size from the code segment.
5862 \c{PUSH} and \c{POP}, when applied to segment registers in 32-bit
5863 mode, also have the slightly odd behaviour that they push and pop 4
5864 bytes at a time, of which the top two are ignored and the bottom two
5865 give the value of the segment register being manipulated. To force
5866 the 16-bit behaviour of segment-register push and pop instructions,
5867 you can use the operand-size prefix \i\c{o16}:
5872 This code saves a doubleword of stack space by fitting two segment
5873 registers into the space which would normally be consumed by pushing
5876 (You can also use the \i\c{o32} prefix to force the 32-bit behaviour
5877 when in 16-bit mode, but this seems less useful.)
5880 \C{trouble} Troubleshooting
5882 This chapter describes some of the common problems that users have
5883 been known to encounter with NASM, and answers them. It also gives
5884 instructions for reporting bugs in NASM if you find a difficulty
5885 that isn't listed here.
5888 \H{problems} Common Problems
5890 \S{inefficient} NASM Generates \i{Inefficient Code}
5892 I get a lot of `bug' reports about NASM generating inefficient, or
5893 even `wrong', code on instructions such as \c{ADD ESP,8}. This is a
5894 deliberate design feature, connected to predictability of output:
5895 NASM, on seeing \c{ADD ESP,8}, will generate the form of the
5896 instruction which leaves room for a 32-bit offset. You need to code
5897 \I\c{BYTE}\c{ADD ESP,BYTE 8} if you want the space-efficient
5898 form of the instruction. This isn't a bug: at worst it's a
5899 misfeature, and that's a matter of opinion only.
5902 \S{jmprange} My Jumps are Out of Range\I{out of range, jumps}
5904 Similarly, people complain that when they issue \i{conditional
5905 jumps} (which are \c{SHORT} by default) that try to jump too far,
5906 NASM reports `short jump out of range' instead of making the jumps
5909 This, again, is partly a predictability issue, but in fact has a
5910 more practical reason as well. NASM has no means of being told what
5911 type of processor the code it is generating will be run on; so it
5912 cannot decide for itself that it should generate \i\c{Jcc NEAR} type
5913 instructions, because it doesn't know that it's working for a 386 or
5914 above. Alternatively, it could replace the out-of-range short
5915 \c{JNE} instruction with a very short \c{JE} instruction that jumps
5916 over a \c{JMP NEAR}; this is a sensible solution for processors
5917 below a 386, but hardly efficient on processors which have good
5918 branch prediction \e{and} could have used \c{JNE NEAR} instead. So,
5919 once again, it's up to the user, not the assembler, to decide what
5920 instructions should be generated.
5923 \S{proborg} \i\c{ORG} Doesn't Work
5925 People writing \i{boot sector} programs in the \c{bin} format often
5926 complain that \c{ORG} doesn't work the way they'd like: in order to
5927 place the \c{0xAA55} signature word at the end of a 512-byte boot
5928 sector, people who are used to MASM tend to code
5932 \c ; some boot sector code
5937 This is not the intended use of the \c{ORG} directive in NASM, and
5938 will not work. The correct way to solve this problem in NASM is to
5939 use the \i\c{TIMES} directive, like this:
5943 \c ; some boot sector code
5945 \c TIMES 510-($-$$) DB 0
5948 The \c{TIMES} directive will insert exactly enough zero bytes into
5949 the output to move the assembly point up to 510. This method also
5950 has the advantage that if you accidentally fill your boot sector too
5951 full, NASM will catch the problem at assembly time and report it, so
5952 you won't end up with a boot sector that you have to disassemble to
5953 find out what's wrong with it.
5956 \S{probtimes} \i\c{TIMES} Doesn't Work
5958 The other common problem with the above code is people who write the
5963 by reasoning that \c{$} should be a pure number, just like 510, so
5964 the difference between them is also a pure number and can happily be
5967 NASM is a \e{modular} assembler: the various component parts are
5968 designed to be easily separable for re-use, so they don't exchange
5969 information unnecessarily. In consequence, the \c{bin} output
5970 format, even though it has been told by the \c{ORG} directive that
5971 the \c{.text} section should start at 0, does not pass that
5972 information back to the expression evaluator. So from the
5973 evaluator's point of view, \c{$} isn't a pure number: it's an offset
5974 from a section base. Therefore the difference between \c{$} and 510
5975 is also not a pure number, but involves a section base. Values
5976 involving section bases cannot be passed as arguments to \c{TIMES}.
5978 The solution, as in the previous section, is to code the \c{TIMES}
5981 \c TIMES 510-($-$$) DB 0
5983 in which \c{$} and \c{$$} are offsets from the same section base,
5984 and so their difference is a pure number. This will solve the
5985 problem and generate sensible code.
5988 \H{bugs} \i{Bugs}\I{reporting bugs}
5990 We have never yet released a version of NASM with any \e{known}
5991 bugs. That doesn't usually stop there being plenty we didn't know
5992 about, though. Any that you find should be reported firstly via the
5994 \W{https://sourceforge.net/projects/nasm/}\c{https://sourceforge.net/projects/nasm/}
5995 (click on "Bugs"), or if that fails then through one of the
5996 contacts in \k{contact}.
5998 Please read \k{qstart} first, and don't report the bug if it's
5999 listed in there as a deliberate feature. (If you think the feature
6000 is badly thought out, feel free to send us reasons why you think it
6001 should be changed, but don't just send us mail saying `This is a
6002 bug' if the documentation says we did it on purpose.) Then read
6003 \k{problems}, and don't bother reporting the bug if it's listed
6006 If you do report a bug, \e{please} give us all of the following
6009 \b What operating system you're running NASM under. DOS, Linux,
6010 NetBSD, Win16, Win32, VMS (I'd be impressed), whatever.
6012 \b If you're running NASM under DOS or Win32, tell us whether you've
6013 compiled your own executable from the DOS source archive, or whether
6014 you were using the standard distribution binaries out of the
6015 archive. If you were using a locally built executable, try to
6016 reproduce the problem using one of the standard binaries, as this
6017 will make it easier for us to reproduce your problem prior to fixing
6020 \b Which version of NASM you're using, and exactly how you invoked
6021 it. Give us the precise command line, and the contents of the
6022 \c{NASMENV} environment variable if any.
6024 \b Which versions of any supplementary programs you're using, and
6025 how you invoked them. If the problem only becomes visible at link
6026 time, tell us what linker you're using, what version of it you've
6027 got, and the exact linker command line. If the problem involves
6028 linking against object files generated by a compiler, tell us what
6029 compiler, what version, and what command line or options you used.
6030 (If you're compiling in an IDE, please try to reproduce the problem
6031 with the command-line version of the compiler.)
6033 \b If at all possible, send us a NASM source file which exhibits the
6034 problem. If this causes copyright problems (e.g. you can only
6035 reproduce the bug in restricted-distribution code) then bear in mind
6036 the following two points: firstly, we guarantee that any source code
6037 sent to us for the purposes of debugging NASM will be used \e{only}
6038 for the purposes of debugging NASM, and that we will delete all our
6039 copies of it as soon as we have found and fixed the bug or bugs in
6040 question; and secondly, we would prefer \e{not} to be mailed large
6041 chunks of code anyway. The smaller the file, the better. A
6042 three-line sample file that does nothing useful \e{except}
6043 demonstrate the problem is much easier to work with than a
6044 fully fledged ten-thousand-line program. (Of course, some errors
6045 \e{do} only crop up in large files, so this may not be possible.)
6047 \b A description of what the problem actually \e{is}. `It doesn't
6048 work' is \e{not} a helpful description! Please describe exactly what
6049 is happening that shouldn't be, or what isn't happening that should.
6050 Examples might be: `NASM generates an error message saying Line 3
6051 for an error that's actually on Line 5'; `NASM generates an error
6052 message that I believe it shouldn't be generating at all'; `NASM
6053 fails to generate an error message that I believe it \e{should} be
6054 generating'; `the object file produced from this source code crashes
6055 my linker'; `the ninth byte of the output file is 66 and I think it
6056 should be 77 instead'.
6058 \b If you believe the output file from NASM to be faulty, send it to
6059 us. That allows us to determine whether our own copy of NASM
6060 generates the same file, or whether the problem is related to
6061 portability issues between our development platforms and yours. We
6062 can handle binary files mailed to us as MIME attachments, uuencoded,
6063 and even BinHex. Alternatively, we may be able to provide an FTP
6064 site you can upload the suspect files to; but mailing them is easier
6067 \b Any other information or data files that might be helpful. If,
6068 for example, the problem involves NASM failing to generate an object
6069 file while TASM can generate an equivalent file without trouble,
6070 then send us \e{both} object files, so we can see what TASM is doing
6071 differently from us.
6074 \A{ndisasm} \i{Ndisasm}
6076 The Netwide Disassembler, NDISASM
6078 \H{ndisintro} Introduction
6081 The Netwide Disassembler is a small companion program to the Netwide
6082 Assembler, NASM. It seemed a shame to have an x86 assembler,
6083 complete with a full instruction table, and not make as much use of
6084 it as possible, so here's a disassembler which shares the
6085 instruction table (and some other bits of code) with NASM.
6087 The Netwide Disassembler does nothing except to produce
6088 disassemblies of \e{binary} source files. NDISASM does not have any
6089 understanding of object file formats, like \c{objdump}, and it will
6090 not understand \c{DOS .EXE} files like \c{debug} will. It just
6094 \H{ndisstart} Getting Started: Installation
6096 See \k{install} for installation instructions. NDISASM, like NASM,
6097 has a \c{man page} which you may want to put somewhere useful, if you
6098 are on a Unix system.
6101 \H{ndisrun} Running NDISASM
6103 To disassemble a file, you will typically use a command of the form
6105 \c ndisasm [-b16 | -b32] filename
6107 NDISASM can disassemble 16-bit code or 32-bit code equally easily,
6108 provided of course that you remember to specify which it is to work
6109 with. If no \i\c{-b} switch is present, NDISASM works in 16-bit mode by
6110 default. The \i\c{-u} switch (for USE32) also invokes 32-bit mode.
6112 Two more command line options are \i\c{-r} which reports the version
6113 number of NDISASM you are running, and \i\c{-h} which gives a short
6114 summary of command line options.
6117 \S{ndiscom} COM Files: Specifying an Origin
6119 To disassemble a \c{DOS .COM} file correctly, a disassembler must assume
6120 that the first instruction in the file is loaded at address \c{0x100},
6121 rather than at zero. NDISASM, which assumes by default that any file
6122 you give it is loaded at zero, will therefore need to be informed of
6125 The \i\c{-o} option allows you to declare a different origin for the
6126 file you are disassembling. Its argument may be expressed in any of
6127 the NASM numeric formats: decimal by default, if it begins with `\c{$}'
6128 or `\c{0x}' or ends in `\c{H}' it's \c{hex}, if it ends in `\c{Q}' it's
6129 \c{octal}, and if it ends in `\c{B}' it's \c{binary}.
6131 Hence, to disassemble a \c{.COM} file:
6133 \c ndisasm -o100h filename.com
6138 \S{ndissync} Code Following Data: Synchronisation
6140 Suppose you are disassembling a file which contains some data which
6141 isn't machine code, and \e{then} contains some machine code. NDISASM
6142 will faithfully plough through the data section, producing machine
6143 instructions wherever it can (although most of them will look
6144 bizarre, and some may have unusual prefixes, e.g. `\c{FS OR AX,0x240A}'),
6145 and generating `DB' instructions ever so often if it's totally stumped.
6146 Then it will reach the code section.
6148 Supposing NDISASM has just finished generating a strange machine
6149 instruction from part of the data section, and its file position is
6150 now one byte \e{before} the beginning of the code section. It's
6151 entirely possible that another spurious instruction will get
6152 generated, starting with the final byte of the data section, and
6153 then the correct first instruction in the code section will not be
6154 seen because the starting point skipped over it. This isn't really
6157 To avoid this, you can specify a `\i\c{synchronisation}' point, or indeed
6158 as many synchronisation points as you like (although NDISASM can
6159 only handle 8192 sync points internally). The definition of a sync
6160 point is this: NDISASM guarantees to hit sync points exactly during
6161 disassembly. If it is thinking about generating an instruction which
6162 would cause it to jump over a sync point, it will discard that
6163 instruction and output a `\c{db}' instead. So it \e{will} start
6164 disassembly exactly from the sync point, and so you \e{will} see all
6165 the instructions in your code section.
6167 Sync points are specified using the \i\c{-s} option: they are measured
6168 in terms of the program origin, not the file position. So if you
6169 want to synchronise after 32 bytes of a \c{.COM} file, you would have to
6172 \c ndisasm -o100h -s120h file.com
6176 \c ndisasm -o100h -s20h file.com
6178 As stated above, you can specify multiple sync markers if you need
6179 to, just by repeating the \c{-s} option.
6182 \S{ndisisync} Mixed Code and Data: Automatic (Intelligent) Synchronisation
6185 Suppose you are disassembling the boot sector of a \c{DOS} floppy (maybe
6186 it has a virus, and you need to understand the virus so that you
6187 know what kinds of damage it might have done you). Typically, this
6188 will contain a \c{JMP} instruction, then some data, then the rest of the
6189 code. So there is a very good chance of NDISASM being \e{misaligned}
6190 when the data ends and the code begins. Hence a sync point is
6193 On the other hand, why should you have to specify the sync point
6194 manually? What you'd do in order to find where the sync point would
6195 be, surely, would be to read the \c{JMP} instruction, and then to use
6196 its target address as a sync point. So can NDISASM do that for you?
6198 The answer, of course, is yes: using either of the synonymous
6199 switches \i\c{-a} (for automatic sync) or \i\c{-i} (for intelligent
6200 sync) will enable \c{auto-sync} mode. Auto-sync mode automatically
6201 generates a sync point for any forward-referring PC-relative jump or
6202 call instruction that NDISASM encounters. (Since NDISASM is one-pass,
6203 if it encounters a PC-relative jump whose target has already been
6204 processed, there isn't much it can do about it...)
6206 Only PC-relative jumps are processed, since an absolute jump is
6207 either through a register (in which case NDISASM doesn't know what
6208 the register contains) or involves a segment address (in which case
6209 the target code isn't in the same segment that NDISASM is working
6210 in, and so the sync point can't be placed anywhere useful).
6212 For some kinds of file, this mechanism will automatically put sync
6213 points in all the right places, and save you from having to place
6214 any sync points manually. However, it should be stressed that
6215 auto-sync mode is \e{not} guaranteed to catch all the sync points, and
6216 you may still have to place some manually.
6218 Auto-sync mode doesn't prevent you from declaring manual sync
6219 points: it just adds automatically generated ones to the ones you
6220 provide. It's perfectly feasible to specify \c{-i} \e{and} some \c{-s}
6223 Another caveat with auto-sync mode is that if, by some unpleasant
6224 fluke, something in your data section should disassemble to a
6225 PC-relative call or jump instruction, NDISASM may obediently place a
6226 sync point in a totally random place, for example in the middle of
6227 one of the instructions in your code section. So you may end up with
6228 a wrong disassembly even if you use auto-sync. Again, there isn't
6229 much I can do about this. If you have problems, you'll have to use
6230 manual sync points, or use the \c{-k} option (documented below) to
6231 suppress disassembly of the data area.
6234 \S{ndisother} Other Options
6236 The \i\c{-e} option skips a header on the file, by ignoring the first N
6237 bytes. This means that the header is \e{not} counted towards the
6238 disassembly offset: if you give \c{-e10 -o10}, disassembly will start
6239 at byte 10 in the file, and this will be given offset 10, not 20.
6241 The \i\c{-k} option is provided with two comma-separated numeric
6242 arguments, the first of which is an assembly offset and the second
6243 is a number of bytes to skip. This \e{will} count the skipped bytes
6244 towards the assembly offset: its use is to suppress disassembly of a
6245 data section which wouldn't contain anything you wanted to see
6249 \H{ndisbugs} Bugs and Improvements
6251 There are no known bugs. However, any you find, with patches if
6252 possible, should be sent to \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk}
6253 or \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}, or to the
6255 \W{https://sourceforge.net/projects/nasm/}\c{https://sourceforge.net/projects/nasm/}
6256 and we'll try to fix them. Feel free to send contributions and
6257 new features as well.
6259 Future plans include awareness of which processors certain
6260 instructions will run on, and marking of instructions that are too
6261 advanced for some processor (or are \c{FPU} instructions, or are
6262 undocumented opcodes, or are privileged protected-mode instructions,
6267 I hope NDISASM is of some use to somebody. Including me. :-)
6269 I don't recommend taking NDISASM apart to see how an efficient
6270 disassembler works, because as far as I know, it isn't an efficient
6271 one anyway. You have been warned.
6274 \A{iref} x86 Instruction Reference
6276 This appendix provides a complete list of the machine instructions
6277 which NASM will assemble, and a short description of the function of
6280 It is not intended to be exhaustive documentation on the fine
6281 details of the instructions' function, such as which exceptions they
6282 can trigger: for such documentation, you should go to Intel's Web
6283 site, \W{http://developer.intel.com/design/Pentium4/manuals/}\c{http://developer.intel.com/design/Pentium4/manuals/}.
6285 Instead, this appendix is intended primarily to provide
6286 documentation on the way the instructions may be used within NASM.
6287 For example, looking up \c{LOOP} will tell you that NASM allows
6288 \c{CX} or \c{ECX} to be specified as an optional second argument to
6289 the \c{LOOP} instruction, to enforce which of the two possible
6290 counter registers should be used if the default is not the one
6293 The instructions are not quite listed in alphabetical order, since
6294 groups of instructions with similar functions are lumped together in
6295 the same entry. Most of them don't move very far from their
6296 alphabetic position because of this.
6299 \H{iref-opr} Key to Operand Specifications
6301 The instruction descriptions in this appendix specify their operands
6302 using the following notation:
6304 \b Registers: \c{reg8} denotes an 8-bit \i{general purpose
6305 register}, \c{reg16} denotes a 16-bit general purpose register, and
6306 \c{reg32} a 32-bit one. \c{fpureg} denotes one of the eight FPU
6307 stack registers, \c{mmxreg} denotes one of the eight 64-bit MMX
6308 registers, and \c{segreg} denotes a segment register. In addition,
6309 some registers (such as \c{AL}, \c{DX} or
6310 \c{ECX}) may be specified explicitly.
6312 \b Immediate operands: \c{imm} denotes a generic \i{immediate operand}.
6313 \c{imm8}, \c{imm16} and \c{imm32} are used when the operand is
6314 intended to be a specific size. For some of these instructions, NASM
6315 needs an explicit specifier: for example, \c{ADD ESP,16} could be
6316 interpreted as either \c{ADD r/m32,imm32} or \c{ADD r/m32,imm8}.
6317 NASM chooses the former by default, and so you must specify \c{ADD
6318 ESP,BYTE 16} for the latter.
6320 \b Memory references: \c{mem} denotes a generic \i{memory reference};
6321 \c{mem8}, \c{mem16}, \c{mem32}, \c{mem64} and \c{mem80} are used
6322 when the operand needs to be a specific size. Again, a specifier is
6323 needed in some cases: \c{DEC [address]} is ambiguous and will be
6324 rejected by NASM. You must specify \c{DEC BYTE [address]}, \c{DEC
6325 WORD [address]} or \c{DEC DWORD [address]} instead.
6327 \b \i{Restricted memory references}: one form of the \c{MOV}
6328 instruction allows a memory address to be specified \e{without}
6329 allowing the normal range of register combinations and effective
6330 address processing. This is denoted by \c{memoffs8}, \c{memoffs16}
6333 \b Register or memory choices: many instructions can accept either a
6334 register \e{or} a memory reference as an operand. \c{r/m8} is a
6335 shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}.
6336 \c{r/m64} is MMX-related, and is a shorthand for \c{mmxreg/mem64}.
6339 \H{iref-opc} Key to Opcode Descriptions
6341 This appendix also provides the opcodes which NASM will generate for
6342 each form of each instruction. The opcodes are listed in the
6345 \b A hex number, such as \c{3F}, indicates a fixed byte containing
6348 \b A hex number followed by \c{+r}, such as \c{C8+r}, indicates that
6349 one of the operands to the instruction is a register, and the
6350 `register value' of that register should be added to the hex number
6351 to produce the generated byte. For example, EDX has register value
6352 2, so the code \c{C8+r}, when the register operand is EDX, generates
6353 the hex byte \c{CA}. Register values for specific registers are
6354 given in \k{iref-rv}.
6356 \b A hex number followed by \c{+cc}, such as \c{40+cc}, indicates
6357 that the instruction name has a condition code suffix, and the
6358 numeric representation of the condition code should be added to the
6359 hex number to produce the generated byte. For example, the code
6360 \c{40+cc}, when the instruction contains the \c{NE} condition,
6361 generates the hex byte \c{45}. Condition codes and their numeric
6362 representations are given in \k{iref-cc}.
6364 \b A slash followed by a digit, such as \c{/2}, indicates that one
6365 of the operands to the instruction is a memory address or register
6366 (denoted \c{mem} or \c{r/m}, with an optional size). This is to be
6367 encoded as an effective address, with a \i{ModR/M byte}, an optional
6368 \i{SIB byte}, and an optional displacement, and the spare (register)
6369 field of the ModR/M byte should be the digit given (which will be
6370 from 0 to 7, so it fits in three bits). The encoding of effective
6371 addresses is given in \k{iref-ea}.
6373 \b The code \c{/r} combines the above two: it indicates that one of
6374 the operands is a memory address or \c{r/m}, and another is a
6375 register, and that an effective address should be generated with the
6376 spare (register) field in the ModR/M byte being equal to the
6377 `register value' of the register operand. The encoding of effective
6378 addresses is given in \k{iref-ea}; register values are given in
6381 \b The codes \c{ib}, \c{iw} and \c{id} indicate that one of the
6382 operands to the instruction is an immediate value, and that this is
6383 to be encoded as a byte, little-endian word or little-endian
6384 doubleword respectively.
6386 \b The codes \c{rb}, \c{rw} and \c{rd} indicate that one of the
6387 operands to the instruction is an immediate value, and that the
6388 \e{difference} between this value and the address of the end of the
6389 instruction is to be encoded as a byte, word or doubleword
6390 respectively. Where the form \c{rw/rd} appears, it indicates that
6391 either \c{rw} or \c{rd} should be used according to whether assembly
6392 is being performed in \c{BITS 16} or \c{BITS 32} state respectively.
6394 \b The codes \c{ow} and \c{od} indicate that one of the operands to
6395 the instruction is a reference to the contents of a memory address
6396 specified as an immediate value: this encoding is used in some forms
6397 of the \c{MOV} instruction in place of the standard
6398 effective-address mechanism. The displacement is encoded as a word
6399 or doubleword. Again, \c{ow/od} denotes that \c{ow} or \c{od} should
6400 be chosen according to the \c{BITS} setting.
6402 \b The codes \c{o16} and \c{o32} indicate that the given form of the
6403 instruction should be assembled with operand size 16 or 32 bits. In
6404 other words, \c{o16} indicates a \c{66} prefix in \c{BITS 32} state,
6405 but generates no code in \c{BITS 16} state; and \c{o32} indicates a
6406 \c{66} prefix in \c{BITS 16} state but generates nothing in \c{BITS
6409 \b The codes \c{a16} and \c{a32}, similarly to \c{o16} and \c{o32},
6410 indicate the address size of the given form of the instruction.
6411 Where this does not match the \c{BITS} setting, a \c{67} prefix is
6415 \S{iref-rv} Register Values
6417 Where an instruction requires a register value, it is already
6418 implicit in the encoding of the rest of the instruction what type of
6419 register is intended: an 8-bit general-purpose register, a segment
6420 register, a debug register, an MMX register, or whatever. Therefore
6421 there is no problem with registers of different types sharing an
6424 The encodings for the various classes of register are:
6426 \b 8-bit general registers: \c{AL} is 0, \c{CL} is 1, \c{DL} is 2,
6427 \c{BL} is 3, \c{AH} is 4, \c{CH} is 5, \c{DH} is 6, and \c{BH} is
6430 \b 16-bit general registers: \c{AX} is 0, \c{CX} is 1, \c{DX} is 2,
6431 \c{BX} is 3, \c{SP} is 4, \c{BP} is 5, \c{SI} is 6, and \c{DI} is 7.
6433 \b 32-bit general registers: \c{EAX} is 0, \c{ECX} is 1, \c{EDX} is
6434 2, \c{EBX} is 3, \c{ESP} is 4, \c{EBP} is 5, \c{ESI} is 6, and
6437 \b \i{Segment registers}: \c{ES} is 0, \c{CS} is 1, \c{SS} is 2, \c{DS}
6438 is 3, \c{FS} is 4, and \c{GS} is 5.
6440 \b \I{floating-point, registers}Floating-point registers: \c{ST0}
6441 is 0, \c{ST1} is 1, \c{ST2} is 2, \c{ST3} is 3, \c{ST4} is 4,
6442 \c{ST5} is 5, \c{ST6} is 6, and \c{ST7} is 7.
6444 \b 64-bit \i{MMX registers}: \c{MM0} is 0, \c{MM1} is 1, \c{MM2} is 2,
6445 \c{MM3} is 3, \c{MM4} is 4, \c{MM5} is 5, \c{MM6} is 6, and \c{MM7}
6448 \b \i{Control registers}: \c{CR0} is 0, \c{CR2} is 2, \c{CR3} is 3,
6451 \b \i{Debug registers}: \c{DR0} is 0, \c{DR1} is 1, \c{DR2} is 2,
6452 \c{DR3} is 3, \c{DR6} is 6, and \c{DR7} is 7.
6454 \b \i{Test registers}: \c{TR3} is 3, \c{TR4} is 4, \c{TR5} is 5,
6455 \c{TR6} is 6, and \c{TR7} is 7.
6457 (Note that wherever a register name contains a number, that number
6458 is also the register value for that register.)
6461 \S{iref-cc} \i{Condition Codes}
6463 The available condition codes are given here, along with their
6464 numeric representations as part of opcodes. Many of these condition
6465 codes have synonyms, so several will be listed at a time.
6467 In the following descriptions, the word `either', when applied to two
6468 possible trigger conditions, is used to mean `either or both'. If
6469 `either but not both' is meant, the phrase `exactly one of' is used.
6471 \b \c{O} is 0 (trigger if the overflow flag is set); \c{NO} is 1.
6473 \b \c{B}, \c{C} and \c{NAE} are 2 (trigger if the carry flag is
6474 set); \c{AE}, \c{NB} and \c{NC} are 3.
6476 \b \c{E} and \c{Z} are 4 (trigger if the zero flag is set); \c{NE}
6479 \b \c{BE} and \c{NA} are 6 (trigger if either of the carry or zero
6480 flags is set); \c{A} and \c{NBE} are 7.
6482 \b \c{S} is 8 (trigger if the sign flag is set); \c{NS} is 9.
6484 \b \c{P} and \c{PE} are 10 (trigger if the parity flag is set);
6485 \c{NP} and \c{PO} are 11.
6487 \b \c{L} and \c{NGE} are 12 (trigger if exactly one of the sign and
6488 overflow flags is set); \c{GE} and \c{NL} are 13.
6490 \b \c{LE} and \c{NG} are 14 (trigger if either the zero flag is set,
6491 or exactly one of the sign and overflow flags is set); \c{G} and
6494 Note that in all cases, the sense of a condition code may be
6495 reversed by changing the low bit of the numeric representation.
6497 For details of when an instruction sets each of the status flags,
6498 see the individual instruction, plus the Status Flags reference
6502 \S{iref-SSE-cc} \i{SSE Condition Predicates}
6504 The condition predicates for SSE comparison instructions are the
6505 codes used as part of the opcode, to determine what form of
6506 comparison is being carried out. In each case, the imm8 value is
6507 the final byte of the opcode encoding, and the predicate is the
6508 code used as part of the mnemonic for the instruction (equivalent
6509 to the "cc" in an integer instruction that used a condition code).
6510 The instructions that use this will give details of what the various
6511 mnemonics are, this table is used to help you work out details of what
6514 \c Predi- imm8 Description Relation where: Emula- Result QNaN
6515 \c cate Encod- A Is 1st Operand tion if NaN Signal
6516 \c ing B Is 2nd Operand Operand Invalid
6518 \c EQ 000B equal A = B False No
6520 \c LT 001B less-than A < B False Yes
6522 \c LE 010B less-than- A <= B False Yes
6525 \c --- ---- greater A > B Swap False Yes
6529 \c --- ---- greater- A >= B Swap False Yes
6530 \c than-or-equal Operands,
6533 \c UNORD 011B unordered A, B = Unordered True No
6535 \c NEQ 100B not-equal A != B True No
6537 \c NLT 101B not-less- NOT(A < B) True Yes
6540 \c NLE 110B not-less- NOT(A <= B) True Yes
6544 \c --- ---- not-greater NOT(A > B) Swap True Yes
6548 \c --- ---- not-greater NOT(A >= B) Swap True Yes
6552 \c ORD 111B ordered A , B = Ordered False No
6554 The unordered relationship is true when at least one of the two
6555 values being compared is a NaN or in an unsupported format.
6557 Note that the comparisons which are listed as not having a predicate
6558 or encoding can only be achieved through software emulation, as
6559 described in the "emulation" column. Note in particular that an
6560 instruction such as \c{greater-than} is not the same as \c{NLE}, as,
6561 unlike with the \c{CMP} instruction, it has to take into account the
6562 possibility of one operand containing a NaN or an unsupported numeric
6566 \S{iref-Flags} \i{Status Flags}
6568 The status flags provide some information about the result of the
6569 arithmetic instructions. This information can be used by conditional
6570 instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of
6571 the other instructions (such as \c{ADC} and \c{INTO}).
6573 There are 6 status flags:
6577 Set if an arithmetic operation generates a
6578 carry or a borrow out of the most-significant bit of the result;
6579 cleared otherwise. This flag indicates an overflow condition for
6580 unsigned-integer arithmetic. It is also used in multiple-precision
6583 \c PF - Parity flag.
6585 Set if the least-significant byte of the result contains an even
6586 number of 1 bits; cleared otherwise.
6588 \c AF - Adjust flag.
6590 Set if an arithmetic operation generates a carry or a borrow
6591 out of bit 3 of the result; cleared otherwise. This flag is used
6592 in binary-coded decimal (BCD) arithmetic.
6596 Set if the result is zero; cleared otherwise.
6600 Set equal to the most-significant bit of the result, which is the
6601 sign bit of a signed integer. (0 indicates a positive value and 1
6602 indicates a negative value.)
6604 \c OF - Overflow flag.
6606 Set if the integer result is too large a positive number or too
6607 small a negative number (excluding the sign-bit) to fit in the
6608 destination operand; cleared otherwise. This flag indicates an
6609 overflow condition for signed-integer (two's complement) arithmetic.
6612 \S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB}
6614 An \i{effective address} is encoded in up to three parts: a ModR/M
6615 byte, an optional SIB byte, and an optional byte, word or doubleword
6618 The ModR/M byte consists of three fields: the \c{mod} field, ranging
6619 from 0 to 3, in the upper two bits of the byte, the \c{r/m} field,
6620 ranging from 0 to 7, in the lower three bits, and the spare
6621 (register) field in the middle (bit 3 to bit 5). The spare field is
6622 not relevant to the effective address being encoded, and either
6623 contains an extension to the instruction opcode or the register
6624 value of another operand.
6626 The ModR/M system can be used to encode a direct register reference
6627 rather than a memory access. This is always done by setting the
6628 \c{mod} field to 3 and the \c{r/m} field to the register value of
6629 the register in question (it must be a general-purpose register, and
6630 the size of the register must already be implicit in the encoding of
6631 the rest of the instruction). In this case, the SIB byte and
6632 displacement field are both absent.
6634 In 16-bit addressing mode (either \c{BITS 16} with no \c{67} prefix,
6635 or \c{BITS 32} with a \c{67} prefix), the SIB byte is never used.
6636 The general rules for \c{mod} and \c{r/m} (there is an exception,
6639 \b The \c{mod} field gives the length of the displacement field: 0
6640 means no displacement, 1 means one byte, and 2 means two bytes.
6642 \b The \c{r/m} field encodes the combination of registers to be
6643 added to the displacement to give the accessed address: 0 means
6644 \c{BX+SI}, 1 means \c{BX+DI}, 2 means \c{BP+SI}, 3 means \c{BP+DI},
6645 4 means \c{SI} only, 5 means \c{DI} only, 6 means \c{BP} only, and 7
6648 However, there is a special case:
6650 \b If \c{mod} is 0 and \c{r/m} is 6, the effective address encoded
6651 is not \c{[BP]} as the above rules would suggest, but instead
6652 \c{[disp16]}: the displacement field is present and is two bytes
6653 long, and no registers are added to the displacement.
6655 Therefore the effective address \c{[BP]} cannot be encoded as
6656 efficiently as \c{[BX]}; so if you code \c{[BP]} in a program, NASM
6657 adds a notional 8-bit zero displacement, and sets \c{mod} to 1,
6658 \c{r/m} to 6, and the one-byte displacement field to 0.
6660 In 32-bit addressing mode (either \c{BITS 16} with a \c{67} prefix,
6661 or \c{BITS 32} with no \c{67} prefix) the general rules (again,
6662 there are exceptions) for \c{mod} and \c{r/m} are:
6664 \b The \c{mod} field gives the length of the displacement field: 0
6665 means no displacement, 1 means one byte, and 2 means four bytes.
6667 \b If only one register is to be added to the displacement, and it
6668 is not \c{ESP}, the \c{r/m} field gives its register value, and the
6669 SIB byte is absent. If the \c{r/m} field is 4 (which would encode
6670 \c{ESP}), the SIB byte is present and gives the combination and
6671 scaling of registers to be added to the displacement.
6673 If the SIB byte is present, it describes the combination of
6674 registers (an optional base register, and an optional index register
6675 scaled by multiplication by 1, 2, 4 or 8) to be added to the
6676 displacement. The SIB byte is divided into the \c{scale} field, in
6677 the top two bits, the \c{index} field in the next three, and the
6678 \c{base} field in the bottom three. The general rules are:
6680 \b The \c{base} field encodes the register value of the base
6683 \b The \c{index} field encodes the register value of the index
6684 register, unless it is 4, in which case no index register is used
6685 (so \c{ESP} cannot be used as an index register).
6687 \b The \c{scale} field encodes the multiplier by which the index
6688 register is scaled before adding it to the base and displacement: 0
6689 encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.
6691 The exceptions to the 32-bit encoding rules are:
6693 \b If \c{mod} is 0 and \c{r/m} is 5, the effective address encoded
6694 is not \c{[EBP]} as the above rules would suggest, but instead
6695 \c{[disp32]}: the displacement field is present and is four bytes
6696 long, and no registers are added to the displacement.
6698 \b If \c{mod} is 0, \c{r/m} is 4 (meaning the SIB byte is present)
6699 and \c{base} is 4, the effective address encoded is not
6700 \c{[EBP+index]} as the above rules would suggest, but instead
6701 \c{[disp32+index]}: the displacement field is present and is four
6702 bytes long, and there is no base register (but the index register is
6703 still processed in the normal way).
6706 \H{iref-flg} Key to Instruction Flags
6708 Given along with each instruction in this appendix is a set of
6709 flags, denoting the type of the instruction. The types are as follows:
6711 \b \c{8086}, \c{186}, \c{286}, \c{386}, \c{486}, \c{PENT} and \c{P6}
6712 denote the lowest processor type that supports the instruction. Most
6713 instructions run on all processors above the given type; those that
6714 do not are documented. The Pentium II contains no additional
6715 instructions beyond the P6 (Pentium Pro); from the point of view of
6716 its instruction set, it can be thought of as a P6 with MMX
6719 \b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will
6720 run on the AMD K6-2 and later processors. ATHLON extensions to the
6721 3DNow! instruction set are documented as such.
6723 \b \c{CYRIX} indicates that the instruction is specific to Cyrix
6724 processors, for example the extra MMX instructions in the Cyrix
6725 extended MMX instruction set.
6727 \b \c{FPU} indicates that the instruction is a floating-point one,
6728 and will only run on machines with a coprocessor (automatically
6729 including 486DX, Pentium and above).
6731 \b \c{KATMAI} indicates that the instruction was introduced as part
6732 of the Katmai New Instruction set. These instructions are available
6733 on the Pentium III and later processors. Those which are not
6734 specifically SSE instructions are also available on the AMD Athlon.
6736 \b \c{MMX} indicates that the instruction is an MMX one, and will
6737 run on MMX-capable Pentium processors and the Pentium II.
6739 \b \c{PRIV} indicates that the instruction is a protected-mode
6740 management instruction. Many of these may only be used in protected
6741 mode, or only at privilege level zero.
6743 \b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming
6744 SIMD Extension instruction. These instructions operate on multiple
6745 values in a single operation. SSE was introduced with the Pentium III
6746 and SSE2 was introduced with the Pentium 4.
6748 \b \c{UNDOC} indicates that the instruction is an undocumented one,
6749 and not part of the official Intel Architecture; it may or may not
6750 be supported on any given machine.
6752 \b \c{WILLAMETTE} indicates that the instruction was introduced as
6753 part of the new instruction set in the Pentium 4 and Intel Xeon
6754 processors. These instructions are also known as SSE2 instructions.
6757 \H{iref-inst} x86 Instruction Set
6760 \S{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII
6767 \c AAD ; D5 0A [8086]
6768 \c AAD imm ; D5 ib [8086]
6770 \c AAM ; D4 0A [8086]
6771 \c AAM imm ; D4 ib [8086]
6773 These instructions are used in conjunction with the add, subtract,
6774 multiply and divide instructions to perform binary-coded decimal
6775 arithmetic in \e{unpacked} (one BCD digit per byte - easy to
6776 translate to and from \c{ASCII}, hence the instruction names) form.
6777 There are also packed BCD instructions \c{DAA} and \c{DAS}: see
6780 \b \c{AAA} (ASCII Adjust After Addition) should be used after a
6781 one-byte \c{ADD} instruction whose destination was the \c{AL}
6782 register: by means of examining the value in the low nibble of
6783 \c{AL} and also the auxiliary carry flag \c{AF}, it determines
6784 whether the addition has overflowed, and adjusts it (and sets
6785 the carry flag) if so. You can add long BCD strings together
6786 by doing \c{ADD}/\c{AAA} on the low digits, then doing
6787 \c{ADC}/\c{AAA} on each subsequent digit.
6789 \b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to
6790 \c{AAA}, but is for use after \c{SUB} instructions rather than
6793 \b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you
6794 have multiplied two decimal digits together and left the result
6795 in \c{AL}: it divides \c{AL} by ten and stores the quotient in
6796 \c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be
6797 changed by specifying an operand to the instruction: a particularly
6798 handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL}
6799 to be separated into \c{AH} and \c{AL}.
6801 \b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse
6802 operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to
6803 \c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can
6807 \S{insADC} \i\c{ADC}: Add with Carry
6809 \c ADC r/m8,reg8 ; 10 /r [8086]
6810 \c ADC r/m16,reg16 ; o16 11 /r [8086]
6811 \c ADC r/m32,reg32 ; o32 11 /r [386]
6813 \c ADC reg8,r/m8 ; 12 /r [8086]
6814 \c ADC reg16,r/m16 ; o16 13 /r [8086]
6815 \c ADC reg32,r/m32 ; o32 13 /r [386]
6817 \c ADC r/m8,imm8 ; 80 /2 ib [8086]
6818 \c ADC r/m16,imm16 ; o16 81 /2 iw [8086]
6819 \c ADC r/m32,imm32 ; o32 81 /2 id [386]
6821 \c ADC r/m16,imm8 ; o16 83 /2 ib [8086]
6822 \c ADC r/m32,imm8 ; o32 83 /2 ib [386]
6824 \c ADC AL,imm8 ; 14 ib [8086]
6825 \c ADC AX,imm16 ; o16 15 iw [8086]
6826 \c ADC EAX,imm32 ; o32 15 id [386]
6828 \c{ADC} performs integer addition: it adds its two operands
6829 together, plus the value of the carry flag, and leaves the result in
6830 its destination (first) operand. The destination operand can be a
6831 register or a memory location. The source operand can be a register,
6832 a memory location or an immediate value.
6834 The flags are set according to the result of the operation: in
6835 particular, the carry flag is affected and can be used by a
6836 subsequent \c{ADC} instruction.
6838 In the forms with an 8-bit immediate second operand and a longer
6839 first operand, the second operand is considered to be signed, and is
6840 sign-extended to the length of the first operand. In these cases,
6841 the \c{BYTE} qualifier is necessary to force NASM to generate this
6842 form of the instruction.
6844 To add two numbers without also adding the contents of the carry
6845 flag, use \c{ADD} (\k{insADD}).
6848 \S{insADD} \i\c{ADD}: Add Integers
6850 \c ADD r/m8,reg8 ; 00 /r [8086]
6851 \c ADD r/m16,reg16 ; o16 01 /r [8086]
6852 \c ADD r/m32,reg32 ; o32 01 /r [386]
6854 \c ADD reg8,r/m8 ; 02 /r [8086]
6855 \c ADD reg16,r/m16 ; o16 03 /r [8086]
6856 \c ADD reg32,r/m32 ; o32 03 /r [386]
6858 \c ADD r/m8,imm8 ; 80 /0 ib [8086]
6859 \c ADD r/m16,imm16 ; o16 81 /0 iw [8086]
6860 \c ADD r/m32,imm32 ; o32 81 /0 id [386]
6862 \c ADD r/m16,imm8 ; o16 83 /0 ib [8086]
6863 \c ADD r/m32,imm8 ; o32 83 /0 ib [386]
6865 \c ADD AL,imm8 ; 04 ib [8086]
6866 \c ADD AX,imm16 ; o16 05 iw [8086]
6867 \c ADD EAX,imm32 ; o32 05 id [386]
6869 \c{ADD} performs integer addition: it adds its two operands
6870 together, and leaves the result in its destination (first) operand.
6871 The destination operand can be a register or a memory location.
6872 The source operand can be a register, a memory location or an
6875 The flags are set according to the result of the operation: in
6876 particular, the carry flag is affected and can be used by a
6877 subsequent \c{ADC} instruction.
6879 In the forms with an 8-bit immediate second operand and a longer
6880 first operand, the second operand is considered to be signed, and is
6881 sign-extended to the length of the first operand. In these cases,
6882 the \c{BYTE} qualifier is necessary to force NASM to generate this
6883 form of the instruction.
6886 \S{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values
6888 \c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2]
6890 \c{ADDPD} performs addition on each of two packed double-precision
6893 \c dst[0-63] := dst[0-63] + src[0-63],
6894 \c dst[64-127] := dst[64-127] + src[64-127].
6896 The destination is an \c{XMM} register. The source operand can be
6897 either an \c{XMM} register or a 128-bit memory location.
6900 \S{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values
6902 \c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE]
6904 \c{ADDPS} performs addition on each of four packed single-precision
6907 \c dst[0-31] := dst[0-31] + src[0-31],
6908 \c dst[32-63] := dst[32-63] + src[32-63],
6909 \c dst[64-95] := dst[64-95] + src[64-95],
6910 \c dst[96-127] := dst[96-127] + src[96-127].
6912 The destination is an \c{XMM} register. The source operand can be
6913 either an \c{XMM} register or a 128-bit memory location.
6916 \S{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values
6918 \c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE]
6920 \c{ADDSD} adds the low double-precision FP values from the source
6921 and destination operands and stores the double-precision FP result
6922 in the destination operand.
6924 \c dst[0-63] := dst[0-63] + src[0-63],
6925 \c dst[64-127) remains unchanged.
6927 The destination is an \c{XMM} register. The source operand can be
6928 either an \c{XMM} register or a 64-bit memory location.
6931 \S{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values
6933 \c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2]
6935 \c{ADDSS} adds the low single-precision FP values from the source
6936 and destination operands and stores the single-precision FP result
6937 in the destination operand.
6939 \c dst[0-31] := dst[0-31] + src[0-31],
6940 \c dst[32-127] remains unchanged.
6942 The destination is an \c{XMM} register. The source operand can be
6943 either an \c{XMM} register or a 32-bit memory location.
6946 \S{insAND} \i\c{AND}: Bitwise AND
6948 \c AND r/m8,reg8 ; 20 /r [8086]
6949 \c AND r/m16,reg16 ; o16 21 /r [8086]
6950 \c AND r/m32,reg32 ; o32 21 /r [386]
6952 \c AND reg8,r/m8 ; 22 /r [8086]
6953 \c AND reg16,r/m16 ; o16 23 /r [8086]
6954 \c AND reg32,r/m32 ; o32 23 /r [386]
6956 \c AND r/m8,imm8 ; 80 /4 ib [8086]
6957 \c AND r/m16,imm16 ; o16 81 /4 iw [8086]
6958 \c AND r/m32,imm32 ; o32 81 /4 id [386]
6960 \c AND r/m16,imm8 ; o16 83 /4 ib [8086]
6961 \c AND r/m32,imm8 ; o32 83 /4 ib [386]
6963 \c AND AL,imm8 ; 24 ib [8086]
6964 \c AND AX,imm16 ; o16 25 iw [8086]
6965 \c AND EAX,imm32 ; o32 25 id [386]
6967 \c{AND} performs a bitwise AND operation between its two operands
6968 (i.e. each bit of the result is 1 if and only if the corresponding
6969 bits of the two inputs were both 1), and stores the result in the
6970 destination (first) operand. The destination operand can be a
6971 register or a memory location. The source operand can be a register,
6972 a memory location or an immediate value.
6974 In the forms with an 8-bit immediate second operand and a longer
6975 first operand, the second operand is considered to be signed, and is
6976 sign-extended to the length of the first operand. In these cases,
6977 the \c{BYTE} qualifier is necessary to force NASM to generate this
6978 form of the instruction.
6980 The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same
6981 operation on the 64-bit \c{MMX} registers.
6984 \S{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of
6985 Packed Double-Precision FP Values
6987 \c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2]
6989 \c{ANDNPD} inverts the bits of the two double-precision
6990 floating-point values in the destination register, and then
6991 performs a logical AND between the two double-precision
6992 floating-point values in the source operand and the temporary
6993 inverted result, storing the result in the destination register.
6995 \c dst[0-63] := src[0-63] AND NOT dst[0-63],
6996 \c dst[64-127] := src[64-127] AND NOT dst[64-127].
6998 The destination is an \c{XMM} register. The source operand can be
6999 either an \c{XMM} register or a 128-bit memory location.
7002 \S{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of
7003 Packed Single-Precision FP Values
7005 \c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE]
7007 \c{ANDNPS} inverts the bits of the four single-precision
7008 floating-point values in the destination register, and then
7009 performs a logical AND between the four single-precision
7010 floating-point values in the source operand and the temporary
7011 inverted result, storing the result in the destination register.
7013 \c dst[0-31] := src[0-31] AND NOT dst[0-31],
7014 \c dst[32-63] := src[32-63] AND NOT dst[32-63],
7015 \c dst[64-95] := src[64-95] AND NOT dst[64-95],
7016 \c dst[96-127] := src[96-127] AND NOT dst[96-127].
7018 The destination is an \c{XMM} register. The source operand can be
7019 either an \c{XMM} register or a 128-bit memory location.
7022 \S{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP
7024 \c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2]
7026 \c{ANDPD} performs a bitwise logical AND of the two double-precision
7027 floating point values in the source and destination operand, and
7028 stores the result in the destination register.
7030 \c dst[0-63] := src[0-63] AND dst[0-63],
7031 \c dst[64-127] := src[64-127] AND dst[64-127].
7033 The destination is an \c{XMM} register. The source operand can be
7034 either an \c{XMM} register or a 128-bit memory location.
7037 \S{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP
7039 \c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE]
7041 \c{ANDPS} performs a bitwise logical AND of the four single-precision
7042 floating point values in the source and destination operand, and
7043 stores the result in the destination register.
7045 \c dst[0-31] := src[0-31] AND dst[0-31],
7046 \c dst[32-63] := src[32-63] AND dst[32-63],
7047 \c dst[64-95] := src[64-95] AND dst[64-95],
7048 \c dst[96-127] := src[96-127] AND dst[96-127].
7050 The destination is an \c{XMM} register. The source operand can be
7051 either an \c{XMM} register or a 128-bit memory location.
7054 \S{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector
7056 \c ARPL r/m16,reg16 ; 63 /r [286,PRIV]
7058 \c{ARPL} expects its two word operands to be segment selectors. It
7059 adjusts the \i\c{RPL} (requested privilege level - stored in the bottom
7060 two bits of the selector) field of the destination (first) operand
7061 to ensure that it is no less (i.e. no more privileged than) the \c{RPL}
7062 field of the source operand. The zero flag is set if and only if a
7063 change had to be made.
7066 \S{insBOUND} \i\c{BOUND}: Check Array Index against Bounds
7068 \c BOUND reg16,mem ; o16 62 /r [186]
7069 \c BOUND reg32,mem ; o32 62 /r [386]
7071 \c{BOUND} expects its second operand to point to an area of memory
7072 containing two signed values of the same size as its first operand
7073 (i.e. two words for the 16-bit form; two doublewords for the 32-bit
7074 form). It performs two signed comparisons: if the value in the
7075 register passed as its first operand is less than the first of the
7076 in-memory values, or is greater than or equal to the second, it
7077 throws a \c{BR} exception. Otherwise, it does nothing.
7080 \S{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan
7082 \c BSF reg16,r/m16 ; o16 0F BC /r [386]
7083 \c BSF reg32,r/m32 ; o32 0F BC /r [386]
7085 \c BSR reg16,r/m16 ; o16 0F BD /r [386]
7086 \c BSR reg32,r/m32 ; o32 0F BD /r [386]
7088 \b \c{BSF} searches for the least significant set bit in its source
7089 (second) operand, and if it finds one, stores the index in
7090 its destination (first) operand. If no set bit is found, the
7091 contents of the destination operand are undefined. If the source
7092 operand is zero, the zero flag is set.
7094 \b \c{BSR} performs the same function, but searches from the top
7095 instead, so it finds the most significant set bit.
7097 Bit indices are from 0 (least significant) to 15 or 31 (most
7098 significant). The destination operand can only be a register.
7099 The source operand can be a register or a memory location.
7102 \S{insBSWAP} \i\c{BSWAP}: Byte Swap
7104 \c BSWAP reg32 ; o32 0F C8+r [486]
7106 \c{BSWAP} swaps the order of the four bytes of a 32-bit register:
7107 bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with
7108 bits 16-23. There is no explicit 16-bit equivalent: to byte-swap
7109 \c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP}
7110 is used with a 16-bit register, the result is undefined.
7113 \S{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test
7115 \c BT r/m16,reg16 ; o16 0F A3 /r [386]
7116 \c BT r/m32,reg32 ; o32 0F A3 /r [386]
7117 \c BT r/m16,imm8 ; o16 0F BA /4 ib [386]
7118 \c BT r/m32,imm8 ; o32 0F BA /4 ib [386]
7120 \c BTC r/m16,reg16 ; o16 0F BB /r [386]
7121 \c BTC r/m32,reg32 ; o32 0F BB /r [386]
7122 \c BTC r/m16,imm8 ; o16 0F BA /7 ib [386]
7123 \c BTC r/m32,imm8 ; o32 0F BA /7 ib [386]
7125 \c BTR r/m16,reg16 ; o16 0F B3 /r [386]
7126 \c BTR r/m32,reg32 ; o32 0F B3 /r [386]
7127 \c BTR r/m16,imm8 ; o16 0F BA /6 ib [386]
7128 \c BTR r/m32,imm8 ; o32 0F BA /6 ib [386]
7130 \c BTS r/m16,reg16 ; o16 0F AB /r [386]
7131 \c BTS r/m32,reg32 ; o32 0F AB /r [386]
7132 \c BTS r/m16,imm ; o16 0F BA /5 ib [386]
7133 \c BTS r/m32,imm ; o32 0F BA /5 ib [386]
7135 These instructions all test one bit of their first operand, whose
7136 index is given by the second operand, and store the value of that
7137 bit into the carry flag. Bit indices are from 0 (least significant)
7138 to 15 or 31 (most significant).
7140 In addition to storing the original value of the bit into the carry
7141 flag, \c{BTR} also resets (clears) the bit in the operand itself.
7142 \c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does
7143 not modify its operands.
7145 The destination can be a register or a memory location. The source can
7146 be a register or an immediate value.
7148 If the destination operand is a register, the bit offset should be
7149 in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands).
7150 An immediate value outside these ranges will be taken modulo 16/32
7153 If the destination operand is a memory location, then an immediate
7154 bit offset follows the same rules as for a register. If the bit offset
7155 is in a register, then it can be anything within the signed range of
7156 the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1)
7159 \S{insCALL} \i\c{CALL}: Call Subroutine
7161 \c CALL imm ; E8 rw/rd [8086]
7162 \c CALL imm:imm16 ; o16 9A iw iw [8086]
7163 \c CALL imm:imm32 ; o32 9A id iw [386]
7164 \c CALL FAR mem16 ; o16 FF /3 [8086]
7165 \c CALL FAR mem32 ; o32 FF /3 [386]
7166 \c CALL r/m16 ; o16 FF /2 [8086]
7167 \c CALL r/m32 ; o32 FF /2 [386]
7169 \c{CALL} calls a subroutine, by means of pushing the current
7170 instruction pointer (\c{IP}) and optionally \c{CS} as well on the
7171 stack, and then jumping to a given address.
7173 \c{CS} is pushed as well as \c{IP} if and only if the call is a far
7174 call, i.e. a destination segment address is specified in the
7175 instruction. The forms involving two colon-separated arguments are
7176 far calls; so are the \c{CALL FAR mem} forms.
7178 The immediate \i{near call} takes one of two forms (\c{call imm16/imm32},
7179 determined by the current segment size limit. For 16-bit operands,
7180 you would use \c{CALL 0x1234}, and for 32-bit operands you would use
7181 \c{CALL 0x12345678}. The value passed as an operand is a relative offset.
7183 You can choose between the two immediate \i{far call} forms
7184 (\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords:
7185 \c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}.
7187 The \c{CALL FAR mem} forms execute a far call by loading the
7188 destination address out of memory. The address loaded consists of 16
7189 or 32 bits of offset (depending on the operand size), and 16 bits of
7190 segment. The operand size may be overridden using \c{CALL WORD FAR
7191 mem} or \c{CALL DWORD FAR mem}.
7193 The \c{CALL r/m} forms execute a \i{near call} (within the same
7194 segment), loading the destination address out of memory or out of a
7195 register. The keyword \c{NEAR} may be specified, for clarity, in
7196 these forms, but is not necessary. Again, operand size can be
7197 overridden using \c{CALL WORD mem} or \c{CALL DWORD mem}.
7199 As a convenience, NASM does not require you to call a far procedure
7200 symbol by coding the cumbersome \c{CALL SEG routine:routine}, but
7201 instead allows the easier synonym \c{CALL FAR routine}.
7203 The \c{CALL r/m} forms given above are near calls; NASM will accept
7204 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
7205 is not strictly necessary.
7208 \S{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions
7210 \c CBW ; o16 98 [8086]
7211 \c CWDE ; o32 98 [386]
7213 \c CWD ; o16 99 [8086]
7214 \c CDQ ; o32 99 [386]
7216 All these instructions sign-extend a short value into a longer one,
7217 by replicating the top bit of the original value to fill the
7220 \c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of
7221 \c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into
7222 \c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating
7223 the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends
7224 \c{EAX} into \c{EDX:EAX}.
7227 \S{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags
7232 \c CLTS ; 0F 06 [286,PRIV]
7234 These instructions clear various flags. \c{CLC} clears the carry
7235 flag; \c{CLD} clears the direction flag; \c{CLI} clears the
7236 interrupt flag (thus disabling interrupts); and \c{CLTS} clears the
7237 task-switched (\c{TS}) flag in \c{CR0}.
7239 To set the carry, direction, or interrupt flags, use the \c{STC},
7240 \c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry
7241 flag, use \c{CMC} (\k{insCMC}).
7244 \S{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line
7246 \c CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2]
7248 \c{CLFLUSH} invalidates the cache line that contains the linear address
7249 specified by the source operand from all levels of the processor cache
7250 hierarchy (data and instruction). If, at any level of the cache
7251 hierarchy, the line is inconsistent with memory (dirty) it is written
7252 to memory before invalidation. The source operand points to a
7253 byte-sized memory location.
7255 Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be
7256 present on all processors which have \c{SSE2} support, and it may be
7257 supported on other processors; the \c{CPUID} instruction (\k{insCPUID})
7258 will return a bit which indicates support for the \c{CLFLUSH} instruction.
7261 \S{insCMC} \i\c{CMC}: Complement Carry Flag
7265 \c{CMC} changes the value of the carry flag: if it was 0, it sets it
7266 to 1, and vice versa.
7269 \S{insCMOVcc} \i\c{CMOVcc}: Conditional Move
7271 \c CMOVcc reg16,r/m16 ; o16 0F 40+cc /r [P6]
7272 \c CMOVcc reg32,r/m32 ; o32 0F 40+cc /r [P6]
7274 \c{CMOV} moves its source (second) operand into its destination
7275 (first) operand if the given condition code is satisfied; otherwise
7278 For a list of condition codes, see \k{iref-cc}.
7280 Although the \c{CMOV} instructions are flagged \c{P6} and above, they
7281 may not be supported by all Pentium Pro processors; the \c{CPUID}
7282 instruction (\k{insCPUID}) will return a bit which indicates whether
7283 conditional moves are supported.
7286 \S{insCMP} \i\c{CMP}: Compare Integers
7288 \c CMP r/m8,reg8 ; 38 /r [8086]
7289 \c CMP r/m16,reg16 ; o16 39 /r [8086]
7290 \c CMP r/m32,reg32 ; o32 39 /r [386]
7292 \c CMP reg8,r/m8 ; 3A /r [8086]
7293 \c CMP reg16,r/m16 ; o16 3B /r [8086]
7294 \c CMP reg32,r/m32 ; o32 3B /r [386]
7296 \c CMP r/m8,imm8 ; 80 /0 ib [8086]
7297 \c CMP r/m16,imm16 ; o16 81 /0 iw [8086]
7298 \c CMP r/m32,imm32 ; o32 81 /0 id [386]
7300 \c CMP r/m16,imm8 ; o16 83 /0 ib [8086]
7301 \c CMP r/m32,imm8 ; o32 83 /0 ib [386]
7303 \c CMP AL,imm8 ; 3C ib [8086]
7304 \c CMP AX,imm16 ; o16 3D iw [8086]
7305 \c CMP EAX,imm32 ; o32 3D id [386]
7307 \c{CMP} performs a `mental' subtraction of its second operand from
7308 its first operand, and affects the flags as if the subtraction had
7309 taken place, but does not store the result of the subtraction
7312 In the forms with an 8-bit immediate second operand and a longer
7313 first operand, the second operand is considered to be signed, and is
7314 sign-extended to the length of the first operand. In these cases,
7315 the \c{BYTE} qualifier is necessary to force NASM to generate this
7316 form of the instruction.
7318 The destination operand can be a register or a memory location. The
7319 source can be a register, memory location or an immediate value of
7320 the same size as the destination.
7323 \S{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare
7324 \I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD}
7325 \I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD}
7327 \c CMPPD xmm1,xmm2/mem128,imm8 ; 66 0F C2 /r ib [WILLAMETTE,SSE2]
7329 \c CMPEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 00 [WILLAMETTE,SSE2]
7330 \c CMPLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 01 [WILLAMETTE,SSE2]
7331 \c CMPLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 02 [WILLAMETTE,SSE2]
7332 \c CMPUNORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 03 [WILLAMETTE,SSE2]
7333 \c CMPNEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 04 [WILLAMETTE,SSE2]
7334 \c CMPNLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 05 [WILLAMETTE,SSE2]
7335 \c CMPNLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 06 [WILLAMETTE,SSE2]
7336 \c CMPORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 07 [WILLAMETTE,SSE2]
7338 The \c{CMPccPD} instructions compare the two packed double-precision
7339 FP values in the source and destination operands, and returns the
7340 result of the comparison in the destination register. The result of
7341 each comparison is a quadword mask of all 1s (comparison true) or
7342 all 0s (comparison false).
7344 The destination is an \c{XMM} register. The source can be either an
7345 \c{XMM} register or a 128-bit memory location.
7347 The third operand is an 8-bit immediate value, of which the low 3
7348 bits define the type of comparison. For ease of programming, the
7349 8 two-operand pseudo-instructions are provided, with the third
7350 operand already filled in. The \I{Condition Predicates}
7351 \c{Condition Predicates} are:
7355 \c LE 2 Less-than-or-equal
7356 \c UNORD 3 Unordered
7358 \c NLT 5 Not-less-than
7359 \c NLE 6 Not-less-than-or-equal
7362 For more details of the comparison predicates, and details of how
7363 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7366 \S{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare
7367 \I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS}
7368 \I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS}
7370 \c CMPPS xmm1,xmm2/mem128,imm8 ; 0F C2 /r ib [KATMAI,SSE]
7372 \c CMPEQPS xmm1,xmm2/mem128 ; 0F C2 /r 00 [KATMAI,SSE]
7373 \c CMPLTPS xmm1,xmm2/mem128 ; 0F C2 /r 01 [KATMAI,SSE]
7374 \c CMPLEPS xmm1,xmm2/mem128 ; 0F C2 /r 02 [KATMAI,SSE]
7375 \c CMPUNORDPS xmm1,xmm2/mem128 ; 0F C2 /r 03 [KATMAI,SSE]
7376 \c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE]
7377 \c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE]
7378 \c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE]
7379 \c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE]
7381 The \c{CMPccPS} instructions compare the two packed single-precision
7382 FP values in the source and destination operands, and returns the
7383 result of the comparison in the destination register. The result of
7384 each comparison is a doubleword mask of all 1s (comparison true) or
7385 all 0s (comparison false).
7387 The destination is an \c{XMM} register. The source can be either an
7388 \c{XMM} register or a 128-bit memory location.
7390 The third operand is an 8-bit immediate value, of which the low 3
7391 bits define the type of comparison. For ease of programming, the
7392 8 two-operand pseudo-instructions are provided, with the third
7393 operand already filled in. The \I{Condition Predicates}
7394 \c{Condition Predicates} are:
7398 \c LE 2 Less-than-or-equal
7399 \c UNORD 3 Unordered
7401 \c NLT 5 Not-less-than
7402 \c NLE 6 Not-less-than-or-equal
7405 For more details of the comparison predicates, and details of how
7406 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7409 \S{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings
7411 \c CMPSB ; A6 [8086]
7412 \c CMPSW ; o16 A7 [8086]
7413 \c CMPSD ; o32 A7 [386]
7415 \c{CMPSB} compares the byte at \c{[DS:SI]} or \c{[DS:ESI]} with the
7416 byte at \c{[ES:DI]} or \c{[ES:EDI]}, and sets the flags accordingly.
7417 It then increments or decrements (depending on the direction flag:
7418 increments if the flag is clear, decrements if it is set) \c{SI} and
7419 \c{DI} (or \c{ESI} and \c{EDI}).
7421 The registers used are \c{SI} and \c{DI} if the address size is 16
7422 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
7423 an address size not equal to the current \c{BITS} setting, you can
7424 use an explicit \i\c{a16} or \i\c{a32} prefix.
7426 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
7427 overridden by using a segment register name as a prefix (for
7428 example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]}
7429 or \c{[EDI]} cannot be overridden.
7431 \c{CMPSW} and \c{CMPSD} work in the same way, but they compare a
7432 word or a doubleword instead of a byte, and increment or decrement
7433 the addressing registers by 2 or 4 instead of 1.
7435 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
7436 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
7437 \c{ECX} - again, the address size chooses which) times until the
7438 first unequal or equal byte is found.
7441 \S{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare
7442 \I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD}
7443 \I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD}
7445 \c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2]
7447 \c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2]
7448 \c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2]
7449 \c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2]
7450 \c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2]
7451 \c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2]
7452 \c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2]
7453 \c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2]
7454 \c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2]
7456 The \c{CMPccSD} instructions compare the low-order double-precision
7457 FP values in the source and destination operands, and returns the
7458 result of the comparison in the destination register. The result of
7459 each comparison is a quadword mask of all 1s (comparison true) or
7460 all 0s (comparison false).
7462 The destination is an \c{XMM} register. The source can be either an
7463 \c{XMM} register or a 128-bit memory location.
7465 The third operand is an 8-bit immediate value, of which the low 3
7466 bits define the type of comparison. For ease of programming, the
7467 8 two-operand pseudo-instructions are provided, with the third
7468 operand already filled in. The \I{Condition Predicates}
7469 \c{Condition Predicates} are:
7473 \c LE 2 Less-than-or-equal
7474 \c UNORD 3 Unordered
7476 \c NLT 5 Not-less-than
7477 \c NLE 6 Not-less-than-or-equal
7480 For more details of the comparison predicates, and details of how
7481 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7484 \S{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare
7485 \I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS}
7486 \I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS}
7488 \c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE]
7490 \c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE]
7491 \c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE]
7492 \c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE]
7493 \c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE]
7494 \c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE]
7495 \c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE]
7496 \c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE]
7497 \c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE]
7499 The \c{CMPccSS} instructions compare the low-order single-precision
7500 FP values in the source and destination operands, and returns the
7501 result of the comparison in the destination register. The result of
7502 each comparison is a doubleword mask of all 1s (comparison true) or
7503 all 0s (comparison false).
7505 The destination is an \c{XMM} register. The source can be either an
7506 \c{XMM} register or a 128-bit memory location.
7508 The third operand is an 8-bit immediate value, of which the low 3
7509 bits define the type of comparison. For ease of programming, the
7510 8 two-operand pseudo-instructions are provided, with the third
7511 operand already filled in. The \I{Condition Predicates}
7512 \c{Condition Predicates} are:
7516 \c LE 2 Less-than-or-equal
7517 \c UNORD 3 Unordered
7519 \c NLT 5 Not-less-than
7520 \c NLE 6 Not-less-than-or-equal
7523 For more details of the comparison predicates, and details of how
7524 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7527 \S{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange
7529 \c CMPXCHG r/m8,reg8 ; 0F B0 /r [PENT]
7530 \c CMPXCHG r/m16,reg16 ; o16 0F B1 /r [PENT]
7531 \c CMPXCHG r/m32,reg32 ; o32 0F B1 /r [PENT]
7533 \c CMPXCHG486 r/m8,reg8 ; 0F A6 /r [486,UNDOC]
7534 \c CMPXCHG486 r/m16,reg16 ; o16 0F A7 /r [486,UNDOC]
7535 \c CMPXCHG486 r/m32,reg32 ; o32 0F A7 /r [486,UNDOC]
7537 These two instructions perform exactly the same operation; however,
7538 apparently some (not all) 486 processors support it under a
7539 non-standard opcode, so NASM provides the undocumented
7540 \c{CMPXCHG486} form to generate the non-standard opcode.
7542 \c{CMPXCHG} compares its destination (first) operand to the value in
7543 \c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the
7544 instruction). If they are equal, it copies its source (second)
7545 operand into the destination and sets the zero flag. Otherwise, it
7546 clears the zero flag and copies the destination register to AL, AX or EAX.
7548 The destination can be either a register or a memory location. The
7549 source is a register.
7551 \c{CMPXCHG} is intended to be used for atomic operations in
7552 multitasking or multiprocessor environments. To safely update a
7553 value in shared memory, for example, you might load the value into
7554 \c{EAX}, load the updated value into \c{EBX}, and then execute the
7555 instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not
7556 changed since being loaded, it is updated with your desired new
7557 value, and the zero flag is set to let you know it has worked. (The
7558 \c{LOCK} prefix prevents another processor doing anything in the
7559 middle of this operation: it guarantees atomicity.) However, if
7560 another processor has modified the value in between your load and
7561 your attempted store, the store does not happen, and you are
7562 notified of the failure by a cleared zero flag, so you can go round
7566 \S{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes
7568 \c CMPXCHG8B mem ; 0F C7 /1 [PENT]
7570 This is a larger and more unwieldy version of \c{CMPXCHG}: it
7571 compares the 64-bit (eight-byte) value stored at \c{[mem]} with the
7572 value in \c{EDX:EAX}. If they are equal, it sets the zero flag and
7573 stores \c{ECX:EBX} into the memory area. If they are unequal, it
7574 clears the zero flag and stores the memory contents into \c{EDX:EAX}.
7576 \c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic
7577 execution. This is useful in multi-processor and multi-tasking
7581 \S{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
7583 \c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2]
7585 \c{COMISD} compares the low-order double-precision FP value in the
7586 two source operands. ZF, PF and CF are set according to the result.
7587 OF, AF and AF are cleared. The unordered result is returned if either
7588 source is a NaN (QNaN or SNaN).
7590 The destination operand is an \c{XMM} register. The source can be either
7591 an \c{XMM} register or a memory location.
7593 The flags are set according to the following rules:
7595 \c Result Flags Values
7597 \c UNORDERED: ZF,PF,CF <-- 111;
7598 \c GREATER_THAN: ZF,PF,CF <-- 000;
7599 \c LESS_THAN: ZF,PF,CF <-- 001;
7600 \c EQUAL: ZF,PF,CF <-- 100;
7603 \S{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
7605 \c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE]
7607 \c{COMISS} compares the low-order single-precision FP value in the
7608 two source operands. ZF, PF and CF are set according to the result.
7609 OF, AF and AF are cleared. The unordered result is returned if either
7610 source is a NaN (QNaN or SNaN).
7612 The destination operand is an \c{XMM} register. The source can be either
7613 an \c{XMM} register or a memory location.
7615 The flags are set according to the following rules:
7617 \c Result Flags Values
7619 \c UNORDERED: ZF,PF,CF <-- 111;
7620 \c GREATER_THAN: ZF,PF,CF <-- 000;
7621 \c LESS_THAN: ZF,PF,CF <-- 001;
7622 \c EQUAL: ZF,PF,CF <-- 100;
7625 \S{insCPUID} \i\c{CPUID}: Get CPU Identification Code
7627 \c CPUID ; 0F A2 [PENT]
7629 \c{CPUID} returns various information about the processor it is
7630 being executed on. It fills the four registers \c{EAX}, \c{EBX},
7631 \c{ECX} and \c{EDX} with information, which varies depending on the
7632 input contents of \c{EAX}.
7634 \c{CPUID} also acts as a barrier to serialise instruction execution:
7635 executing the \c{CPUID} instruction guarantees that all the effects
7636 (memory modification, flag modification, register modification) of
7637 previous instructions have been completed before the next
7638 instruction gets fetched.
7640 The information returned is as follows:
7642 \b If \c{EAX} is zero on input, \c{EAX} on output holds the maximum
7643 acceptable input value of \c{EAX}, and \c{EBX:EDX:ECX} contain the
7644 string \c{"GenuineIntel"} (or not, if you have a clone processor).
7645 That is to say, \c{EBX} contains \c{"Genu"} (in NASM's own sense of
7646 character constants, described in \k{chrconst}), \c{EDX} contains
7647 \c{"ineI"} and \c{ECX} contains \c{"ntel"}.
7649 \b If \c{EAX} is one on input, \c{EAX} on output contains version
7650 information about the processor, and \c{EDX} contains a set of
7651 feature flags, showing the presence and absence of various features.
7652 For example, bit 8 is set if the \c{CMPXCHG8B} instruction
7653 (\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional
7654 move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported,
7655 and bit 23 is set if \c{MMX} instructions are supported.
7657 \b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX}
7658 all contain information about caches and TLBs (Translation Lookahead
7661 For more information on the data returned from \c{CPUID}, see the
7662 documentation from Intel and other processor manufacturers.
7665 \S{insCVTDQ2PD} \i\c{CVTDQ2PD}:
7666 Packed Signed INT32 to Packed Double-Precision FP Conversion
7668 \c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2]
7670 \c{CVTDQ2PD} converts two packed signed doublewords from the source
7671 operand to two packed double-precision FP values in the destination
7674 The destination operand is an \c{XMM} register. The source can be
7675 either an \c{XMM} register or a 64-bit memory location. If the
7676 source is a register, the packed integers are in the low quadword.
7679 \S{insCVTDQ2PS} \i\c{CVTDQ2PS}:
7680 Packed Signed INT32 to Packed Single-Precision FP Conversion
7682 \c CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2]
7684 \c{CVTDQ2PS} converts four packed signed doublewords from the source
7685 operand to four packed single-precision FP values in the destination
7688 The destination operand is an \c{XMM} register. The source can be
7689 either an \c{XMM} register or a 128-bit memory location.
7691 For more details of this instruction, see the Intel Processor manuals.
7694 \S{insCVTPD2DQ} \i\c{CVTPD2DQ}:
7695 Packed Double-Precision FP to Packed Signed INT32 Conversion
7697 \c CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2]
7699 \c{CVTPD2DQ} converts two packed double-precision FP values from the
7700 source operand to two packed signed doublewords in the low quadword
7701 of the destination operand. The high quadword of the destination is
7704 The destination operand is an \c{XMM} register. The source can be
7705 either an \c{XMM} register or a 128-bit memory location.
7707 For more details of this instruction, see the Intel Processor manuals.
7710 \S{insCVTPD2PI} \i\c{CVTPD2PI}:
7711 Packed Double-Precision FP to Packed Signed INT32 Conversion
7713 \c CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2]
7715 \c{CVTPD2PI} converts two packed double-precision FP values from the
7716 source operand to two packed signed doublewords in the destination
7719 The destination operand is an \c{MMX} register. The source can be
7720 either an \c{XMM} register or a 128-bit memory location.
7722 For more details of this instruction, see the Intel Processor manuals.
7725 \S{insCVTPD2PS} \i\c{CVTPD2PS}:
7726 Packed Double-Precision FP to Packed Single-Precision FP Conversion
7728 \c CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2]
7730 \c{CVTPD2PS} converts two packed double-precision FP values from the
7731 source operand to two packed single-precision FP values in the low
7732 quadword of the destination operand. The high quadword of the
7733 destination is set to all 0s.
7735 The destination operand is an \c{XMM} register. The source can be
7736 either an \c{XMM} register or a 128-bit memory location.
7738 For more details of this instruction, see the Intel Processor manuals.
7741 \S{insCVTPI2PD} \i\c{CVTPI2PD}:
7742 Packed Signed INT32 to Packed Double-Precision FP Conversion
7744 \c CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2]
7746 \c{CVTPI2PD} converts two packed signed doublewords from the source
7747 operand to two packed double-precision FP values in the destination
7750 The destination operand is an \c{XMM} register. The source can be
7751 either an \c{MMX} register or a 64-bit memory location.
7753 For more details of this instruction, see the Intel Processor manuals.
7756 \S{insCVTPI2PS} \i\c{CVTPI2PS}:
7757 Packed Signed INT32 to Packed Single-FP Conversion
7759 \c CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE]
7761 \c{CVTPI2PS} converts two packed signed doublewords from the source
7762 operand to two packed single-precision FP values in the low quadword
7763 of the destination operand. The high quadword of the destination
7766 The destination operand is an \c{XMM} register. The source can be
7767 either an \c{MMX} register or a 64-bit memory location.
7769 For more details of this instruction, see the Intel Processor manuals.
7772 \S{insCVTPS2DQ} \i\c{CVTPS2DQ}:
7773 Packed Single-Precision FP to Packed Signed INT32 Conversion
7775 \c CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2]
7777 \c{CVTPS2DQ} converts four packed single-precision FP values from the
7778 source operand to four packed signed doublewords in the destination operand.
7780 The destination operand is an \c{XMM} register. The source can be
7781 either an \c{XMM} register or a 128-bit memory location.
7783 For more details of this instruction, see the Intel Processor manuals.
7786 \S{insCVTPS2PD} \i\c{CVTPS2PD}:
7787 Packed Single-Precision FP to Packed Double-Precision FP Conversion
7789 \c CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2]
7791 \c{CVTPS2PD} converts two packed single-precision FP values from the
7792 source operand to two packed double-precision FP values in the destination
7795 The destination operand is an \c{XMM} register. The source can be
7796 either an \c{XMM} register or a 64-bit memory location. If the source
7797 is a register, the input values are in the low quadword.
7799 For more details of this instruction, see the Intel Processor manuals.
7802 \S{insCVTPS2PI} \i\c{CVTPS2PI}:
7803 Packed Single-Precision FP to Packed Signed INT32 Conversion
7805 \c CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE]
7807 \c{CVTPS2PI} converts two packed single-precision FP values from
7808 the source operand to two packed signed doublewords in the destination
7811 The destination operand is an \c{MMX} register. The source can be
7812 either an \c{XMM} register or a 64-bit memory location. If the
7813 source is a register, the input values are in the low quadword.
7815 For more details of this instruction, see the Intel Processor manuals.
7818 \S{insCVTSD2SI} \i\c{CVTSD2SI}:
7819 Scalar Double-Precision FP to Signed INT32 Conversion
7821 \c CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2]
7823 \c{CVTSD2SI} converts a double-precision FP value from the source
7824 operand to a signed doubleword in the destination operand.
7826 The destination operand is a general purpose register. The source can be
7827 either an \c{XMM} register or a 64-bit memory location. If the
7828 source is a register, the input value is in the low quadword.
7830 For more details of this instruction, see the Intel Processor manuals.
7833 \S{insCVTSD2SS} \i\c{CVTSD2SS}:
7834 Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
7836 \c CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE]
7838 \c{CVTSD2SS} converts a double-precision FP value from the source
7839 operand to a single-precision FP value in the low doubleword of the
7840 destination operand. The upper 3 doublewords are left unchanged.
7842 The destination operand is an \c{XMM} register. The source can be
7843 either an \c{XMM} register or a 64-bit memory location. If the
7844 source is a register, the input value is in the low quadword.
7846 For more details of this instruction, see the Intel Processor manuals.
7849 \S{insCVTSI2SD} \i\c{CVTSI2SD}:
7850 Signed INT32 to Scalar Double-Precision FP Conversion
7852 \c CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2]
7854 \c{CVTSI2SD} converts a signed doubleword from the source operand to
7855 a double-precision FP value in the low quadword of the destination
7856 operand. The high quadword is left unchanged.
7858 The destination operand is an \c{XMM} register. The source can be either
7859 a general purpose register or a 32-bit memory location.
7861 For more details of this instruction, see the Intel Processor manuals.
7864 \S{insCVTSI2SS} \i\c{CVTSI2SS}:
7865 Signed INT32 to Scalar Single-Precision FP Conversion
7867 \c CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE]
7869 \c{CVTSI2SS} converts a signed doubleword from the source operand to a
7870 single-precision FP value in the low doubleword of the destination operand.
7871 The upper 3 doublewords are left unchanged.
7873 The destination operand is an \c{XMM} register. The source can be either
7874 a general purpose register or a 32-bit memory location.
7876 For more details of this instruction, see the Intel Processor manuals.
7879 \S{insCVTSS2SD} \i\c{CVTSS2SD}:
7880 Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
7882 \c CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2]
7884 \c{CVTSS2SD} converts a single-precision FP value from the source operand
7885 to a double-precision FP value in the low quadword of the destination
7886 operand. The upper quadword is left unchanged.
7888 The destination operand is an \c{XMM} register. The source can be either
7889 an \c{XMM} register or a 32-bit memory location. If the source is a
7890 register, the input value is contained in the low doubleword.
7892 For more details of this instruction, see the Intel Processor manuals.
7895 \S{insCVTSS2SI} \i\c{CVTSS2SI}:
7896 Scalar Single-Precision FP to Signed INT32 Conversion
7898 \c CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE]
7900 \c{CVTSS2SI} converts a single-precision FP value from the source
7901 operand to a signed doubleword in the destination operand.
7903 The destination operand is a general purpose register. The source can be
7904 either an \c{XMM} register or a 32-bit memory location. If the
7905 source is a register, the input value is in the low doubleword.
7907 For more details of this instruction, see the Intel Processor manuals.
7910 \S{insCVTTPD2DQ} \i\c{CVTTPD2DQ}:
7911 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7913 \c CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2]
7915 \c{CVTTPD2DQ} converts two packed double-precision FP values in the source
7916 operand to two packed single-precision FP values in the destination operand.
7917 If the result is inexact, it is truncated (rounded toward zero). The high
7918 quadword is set to all 0s.
7920 The destination operand is an \c{XMM} register. The source can be
7921 either an \c{XMM} register or a 128-bit memory location.
7923 For more details of this instruction, see the Intel Processor manuals.
7926 \S{insCVTTPD2PI} \i\c{CVTTPD2PI}:
7927 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7929 \c CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2]
7931 \c{CVTTPD2PI} converts two packed double-precision FP values in the source
7932 operand to two packed single-precision FP values in the destination operand.
7933 If the result is inexact, it is truncated (rounded toward zero).
7935 The destination operand is an \c{MMX} register. The source can be
7936 either an \c{XMM} register or a 128-bit memory location.
7938 For more details of this instruction, see the Intel Processor manuals.
7941 \S{insCVTTPS2DQ} \i\c{CVTTPS2DQ}:
7942 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7944 \c CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2]
7946 \c{CVTTPS2DQ} converts four packed single-precision FP values in the source
7947 operand to four packed signed doublewords in the destination operand.
7948 If the result is inexact, it is truncated (rounded toward zero).
7950 The destination operand is an \c{XMM} register. The source can be
7951 either an \c{XMM} register or a 128-bit memory location.
7953 For more details of this instruction, see the Intel Processor manuals.
7956 \S{insCVTTPS2PI} \i\c{CVTTPS2PI}:
7957 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7959 \c CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE]
7961 \c{CVTTPS2PI} converts two packed single-precision FP values in the source
7962 operand to two packed signed doublewords in the destination operand.
7963 If the result is inexact, it is truncated (rounded toward zero). If
7964 the source is a register, the input values are in the low quadword.
7966 The destination operand is an \c{MMX} register. The source can be
7967 either an \c{XMM} register or a 64-bit memory location. If the source
7968 is a register, the input value is in the low quadword.
7970 For more details of this instruction, see the Intel Processor manuals.
7973 \S{insCVTTSD2SI} \i\c{CVTTSD2SI}:
7974 Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
7976 \c CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2]
7978 \c{CVTTSD2SI} converts a double-precision FP value in the source operand
7979 to a signed doubleword in the destination operand. If the result is
7980 inexact, it is truncated (rounded toward zero).
7982 The destination operand is a general purpose register. The source can be
7983 either an \c{XMM} register or a 64-bit memory location. If the source is a
7984 register, the input value is in the low quadword.
7986 For more details of this instruction, see the Intel Processor manuals.
7989 \S{insCVTTSS2SI} \i\c{CVTTSS2SI}:
7990 Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
7992 \c CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE]
7994 \c{CVTTSS2SI} converts a single-precision FP value in the source operand
7995 to a signed doubleword in the destination operand. If the result is
7996 inexact, it is truncated (rounded toward zero).
7998 The destination operand is a general purpose register. The source can be
7999 either an \c{XMM} register or a 32-bit memory location. If the source is a
8000 register, the input value is in the low doubleword.
8002 For more details of this instruction, see the Intel Processor manuals.
8005 \S{insDAA} \i\c{DAA}, \i\c{DAS}: Decimal Adjustments
8010 These instructions are used in conjunction with the add and subtract
8011 instructions to perform binary-coded decimal arithmetic in
8012 \e{packed} (one BCD digit per nibble) form. For the unpacked
8013 equivalents, see \k{insAAA}.
8015 \c{DAA} should be used after a one-byte \c{ADD} instruction whose
8016 destination was the \c{AL} register: by means of examining the value
8017 in the \c{AL} and also the auxiliary carry flag \c{AF}, it
8018 determines whether either digit of the addition has overflowed, and
8019 adjusts it (and sets the carry and auxiliary-carry flags) if so. You
8020 can add long BCD strings together by doing \c{ADD}/\c{DAA} on the
8021 low two digits, then doing \c{ADC}/\c{DAA} on each subsequent pair
8024 \c{DAS} works similarly to \c{DAA}, but is for use after \c{SUB}
8025 instructions rather than \c{ADD}.
8028 \S{insDEC} \i\c{DEC}: Decrement Integer
8030 \c DEC reg16 ; o16 48+r [8086]
8031 \c DEC reg32 ; o32 48+r [386]
8032 \c DEC r/m8 ; FE /1 [8086]
8033 \c DEC r/m16 ; o16 FF /1 [8086]
8034 \c DEC r/m32 ; o32 FF /1 [386]
8036 \c{DEC} subtracts 1 from its operand. It does \e{not} affect the
8037 carry flag: to affect the carry flag, use \c{SUB something,1} (see
8038 \k{insSUB}). \c{DEC} affects all the other flags according to the result.
8040 This instruction can be used with a \c{LOCK} prefix to allow atomic
8043 See also \c{INC} (\k{insINC}).
8046 \S{insDIV} \i\c{DIV}: Unsigned Integer Divide
8048 \c DIV r/m8 ; F6 /6 [8086]
8049 \c DIV r/m16 ; o16 F7 /6 [8086]
8050 \c DIV r/m32 ; o32 F7 /6 [386]
8052 \c{DIV} performs unsigned integer division. The explicit operand
8053 provided is the divisor; the dividend and destination operands are
8054 implicit, in the following way:
8056 \b For \c{DIV r/m8}, \c{AX} is divided by the given operand; the
8057 quotient is stored in \c{AL} and the remainder in \c{AH}.
8059 \b For \c{DIV r/m16}, \c{DX:AX} is divided by the given operand; the
8060 quotient is stored in \c{AX} and the remainder in \c{DX}.
8062 \b For \c{DIV r/m32}, \c{EDX:EAX} is divided by the given operand;
8063 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
8065 Signed integer division is performed by the \c{IDIV} instruction:
8069 \S{insDIVPD} \i\c{DIVPD}: Packed Double-Precision FP Divide
8071 \c DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2]
8073 \c{DIVPD} divides the two packed double-precision FP values in
8074 the destination operand by the two packed double-precision FP
8075 values in the source operand, and stores the packed double-precision
8076 results in the destination register.
8078 The destination is an \c{XMM} register. The source operand can be
8079 either an \c{XMM} register or a 128-bit memory location.
8081 \c dst[0-63] := dst[0-63] / src[0-63],
8082 \c dst[64-127] := dst[64-127] / src[64-127].
8085 \S{insDIVPS} \i\c{DIVPS}: Packed Single-Precision FP Divide
8087 \c DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE]
8089 \c{DIVPS} divides the four packed single-precision FP values in
8090 the destination operand by the four packed single-precision FP
8091 values in the source operand, and stores the packed single-precision
8092 results in the destination register.
8094 The destination is an \c{XMM} register. The source operand can be
8095 either an \c{XMM} register or a 128-bit memory location.
8097 \c dst[0-31] := dst[0-31] / src[0-31],
8098 \c dst[32-63] := dst[32-63] / src[32-63],
8099 \c dst[64-95] := dst[64-95] / src[64-95],
8100 \c dst[96-127] := dst[96-127] / src[96-127].
8103 \S{insDIVSD} \i\c{DIVSD}: Scalar Double-Precision FP Divide
8105 \c DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2]
8107 \c{DIVSD} divides the low-order double-precision FP value in the
8108 destination operand by the low-order double-precision FP value in
8109 the source operand, and stores the double-precision result in the
8110 destination register.
8112 The destination is an \c{XMM} register. The source operand can be
8113 either an \c{XMM} register or a 64-bit memory location.
8115 \c dst[0-63] := dst[0-63] / src[0-63],
8116 \c dst[64-127] remains unchanged.
8119 \S{insDIVSS} \i\c{DIVSS}: Scalar Single-Precision FP Divide
8121 \c DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE]
8123 \c{DIVSS} divides the low-order single-precision FP value in the
8124 destination operand by the low-order single-precision FP value in
8125 the source operand, and stores the single-precision result in the
8126 destination register.
8128 The destination is an \c{XMM} register. The source operand can be
8129 either an \c{XMM} register or a 32-bit memory location.
8131 \c dst[0-31] := dst[0-31] / src[0-31],
8132 \c dst[32-127] remains unchanged.
8135 \S{insEMMS} \i\c{EMMS}: Empty MMX State
8137 \c EMMS ; 0F 77 [PENT,MMX]
8139 \c{EMMS} sets the FPU tag word (marking which floating-point registers
8140 are available) to all ones, meaning all registers are available for
8141 the FPU to use. It should be used after executing \c{MMX} instructions
8142 and before executing any subsequent floating-point operations.
8145 \S{insENTER} \i\c{ENTER}: Create Stack Frame
8147 \c ENTER imm,imm ; C8 iw ib [186]
8149 \c{ENTER} constructs a \i\c{stack frame} for a high-level language
8150 procedure call. The first operand (the \c{iw} in the opcode
8151 definition above refers to the first operand) gives the amount of
8152 stack space to allocate for local variables; the second (the \c{ib}
8153 above) gives the nesting level of the procedure (for languages like
8154 Pascal, with nested procedures).
8156 The function of \c{ENTER}, with a nesting level of zero, is
8159 \c PUSH EBP ; or PUSH BP in 16 bits
8160 \c MOV EBP,ESP ; or MOV BP,SP in 16 bits
8161 \c SUB ESP,operand1 ; or SUB SP,operand1 in 16 bits
8163 This creates a stack frame with the procedure parameters accessible
8164 upwards from \c{EBP}, and local variables accessible downwards from
8167 With a nesting level of one, the stack frame created is 4 (or 2)
8168 bytes bigger, and the value of the final frame pointer \c{EBP} is
8169 accessible in memory at \c{[EBP-4]}.
8171 This allows \c{ENTER}, when called with a nesting level of two, to
8172 look at the stack frame described by the \e{previous} value of
8173 \c{EBP}, find the frame pointer at offset -4 from that, and push it
8174 along with its new frame pointer, so that when a level-two procedure
8175 is called from within a level-one procedure, \c{[EBP-4]} holds the
8176 frame pointer of the most recent level-one procedure call and
8177 \c{[EBP-8]} holds that of the most recent level-two call. And so on,
8178 for nesting levels up to 31.
8180 Stack frames created by \c{ENTER} can be destroyed by the \c{LEAVE}
8181 instruction: see \k{insLEAVE}.
8184 \S{insF2XM1} \i\c{F2XM1}: Calculate 2**X-1
8186 \c F2XM1 ; D9 F0 [8086,FPU]
8188 \c{F2XM1} raises 2 to the power of \c{ST0}, subtracts one, and
8189 stores the result back into \c{ST0}. The initial contents of \c{ST0}
8190 must be a number in the range -1.0 to +1.0.
8193 \S{insFABS} \i\c{FABS}: Floating-Point Absolute Value
8195 \c FABS ; D9 E1 [8086,FPU]
8197 \c{FABS} computes the absolute value of \c{ST0},by clearing the sign
8198 bit, and stores the result back in \c{ST0}.
8201 \S{insFADD} \i\c{FADD}, \i\c{FADDP}: Floating-Point Addition
8203 \c FADD mem32 ; D8 /0 [8086,FPU]
8204 \c FADD mem64 ; DC /0 [8086,FPU]
8206 \c FADD fpureg ; D8 C0+r [8086,FPU]
8207 \c FADD ST0,fpureg ; D8 C0+r [8086,FPU]
8209 \c FADD TO fpureg ; DC C0+r [8086,FPU]
8210 \c FADD fpureg,ST0 ; DC C0+r [8086,FPU]
8212 \c FADDP fpureg ; DE C0+r [8086,FPU]
8213 \c FADDP fpureg,ST0 ; DE C0+r [8086,FPU]
8215 \b \c{FADD}, given one operand, adds the operand to \c{ST0} and stores
8216 the result back in \c{ST0}. If the operand has the \c{TO} modifier,
8217 the result is stored in the register given rather than in \c{ST0}.
8219 \b \c{FADDP} performs the same function as \c{FADD TO}, but pops the
8220 register stack after storing the result.
8222 The given two-operand forms are synonyms for the one-operand forms.
8224 To add an integer value to \c{ST0}, use the c{FIADD} instruction
8228 \S{insFBLD} \i\c{FBLD}, \i\c{FBSTP}: BCD Floating-Point Load and Store
8230 \c FBLD mem80 ; DF /4 [8086,FPU]
8231 \c FBSTP mem80 ; DF /6 [8086,FPU]
8233 \c{FBLD} loads an 80-bit (ten-byte) packed binary-coded decimal
8234 number from the given memory address, converts it to a real, and
8235 pushes it on the register stack. \c{FBSTP} stores the value of
8236 \c{ST0}, in packed BCD, at the given address and then pops the
8240 \S{insFCHS} \i\c{FCHS}: Floating-Point Change Sign
8242 \c FCHS ; D9 E0 [8086,FPU]
8244 \c{FCHS} negates the number in \c{ST0}, by inverting the sign bit:
8245 negative numbers become positive, and vice versa.
8248 \S{insFCLEX} \i\c{FCLEX}, \c{FNCLEX}: Clear Floating-Point Exceptions
8250 \c FCLEX ; 9B DB E2 [8086,FPU]
8251 \c FNCLEX ; DB E2 [8086,FPU]
8253 \c{FCLEX} clears any floating-point exceptions which may be pending.
8254 \c{FNCLEX} does the same thing but doesn't wait for previous
8255 floating-point operations (including the \e{handling} of pending
8256 exceptions) to finish first.
8259 \S{insFCMOVB} \i\c{FCMOVcc}: Floating-Point Conditional Move
8261 \c FCMOVB fpureg ; DA C0+r [P6,FPU]
8262 \c FCMOVB ST0,fpureg ; DA C0+r [P6,FPU]
8264 \c FCMOVE fpureg ; DA C8+r [P6,FPU]
8265 \c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU]
8267 \c FCMOVBE fpureg ; DA D0+r [P6,FPU]
8268 \c FCMOVBE ST0,fpureg ; DA D0+r [P6,FPU]
8270 \c FCMOVU fpureg ; DA D8+r [P6,FPU]
8271 \c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU]
8273 \c FCMOVNB fpureg ; DB C0+r [P6,FPU]
8274 \c FCMOVNB ST0,fpureg ; DB C0+r [P6,FPU]
8276 \c FCMOVNE fpureg ; DB C8+r [P6,FPU]
8277 \c FCMOVNE ST0,fpureg ; DB C8+r [P6,FPU]
8279 \c FCMOVNBE fpureg ; DB D0+r [P6,FPU]
8280 \c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU]
8282 \c FCMOVNU fpureg ; DB D8+r [P6,FPU]
8283 \c FCMOVNU ST0,fpureg ; DB D8+r [P6,FPU]
8285 The \c{FCMOV} instructions perform conditional move operations: each
8286 of them moves the contents of the given register into \c{ST0} if its
8287 condition is satisfied, and does nothing if not.
8289 The conditions are not the same as the standard condition codes used
8290 with conditional jump instructions. The conditions \c{B}, \c{BE},
8291 \c{NB}, \c{NBE}, \c{E} and \c{NE} are exactly as normal, but none of
8292 the other standard ones are supported. Instead, the condition \c{U}
8293 and its counterpart \c{NU} are provided; the \c{U} condition is
8294 satisfied if the last two floating-point numbers compared were
8295 \e{unordered}, i.e. they were not equal but neither one could be
8296 said to be greater than the other, for example if they were NaNs.
8297 (The flag state which signals this is the setting of the parity
8298 flag: so the \c{U} condition is notionally equivalent to \c{PE}, and
8299 \c{NU} is equivalent to \c{PO}.)
8301 The \c{FCMOV} conditions test the main processor's status flags, not
8302 the FPU status flags, so using \c{FCMOV} directly after \c{FCOM}
8303 will not work. Instead, you should either use \c{FCOMI} which writes
8304 directly to the main CPU flags word, or use \c{FSTSW} to extract the
8307 Although the \c{FCMOV} instructions are flagged \c{P6} above, they
8308 may not be supported by all Pentium Pro processors; the \c{CPUID}
8309 instruction (\k{insCPUID}) will return a bit which indicates whether
8310 conditional moves are supported.
8313 \S{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI},
8314 \i\c{FCOMIP}: Floating-Point Compare
8316 \c FCOM mem32 ; D8 /2 [8086,FPU]
8317 \c FCOM mem64 ; DC /2 [8086,FPU]
8318 \c FCOM fpureg ; D8 D0+r [8086,FPU]
8319 \c FCOM ST0,fpureg ; D8 D0+r [8086,FPU]
8321 \c FCOMP mem32 ; D8 /3 [8086,FPU]
8322 \c FCOMP mem64 ; DC /3 [8086,FPU]
8323 \c FCOMP fpureg ; D8 D8+r [8086,FPU]
8324 \c FCOMP ST0,fpureg ; D8 D8+r [8086,FPU]
8326 \c FCOMPP ; DE D9 [8086,FPU]
8328 \c FCOMI fpureg ; DB F0+r [P6,FPU]
8329 \c FCOMI ST0,fpureg ; DB F0+r [P6,FPU]
8331 \c FCOMIP fpureg ; DF F0+r [P6,FPU]
8332 \c FCOMIP ST0,fpureg ; DF F0+r [P6,FPU]
8334 \c{FCOM} compares \c{ST0} with the given operand, and sets the FPU
8335 flags accordingly. \c{ST0} is treated as the left-hand side of the
8336 comparison, so that the carry flag is set (for a `less-than' result)
8337 if \c{ST0} is less than the given operand.
8339 \c{FCOMP} does the same as \c{FCOM}, but pops the register stack
8340 afterwards. \c{FCOMPP} compares \c{ST0} with \c{ST1} and then pops
8341 the register stack twice.
8343 \c{FCOMI} and \c{FCOMIP} work like the corresponding forms of
8344 \c{FCOM} and \c{FCOMP}, but write their results directly to the CPU
8345 flags register rather than the FPU status word, so they can be
8346 immediately followed by conditional jump or conditional move
8349 The \c{FCOM} instructions differ from the \c{FUCOM} instructions
8350 (\k{insFUCOM}) only in the way they handle quiet NaNs: \c{FUCOM}
8351 will handle them silently and set the condition code flags to an
8352 `unordered' result, whereas \c{FCOM} will generate an exception.
8355 \S{insFCOS} \i\c{FCOS}: Cosine
8357 \c FCOS ; D9 FF [386,FPU]
8359 \c{FCOS} computes the cosine of \c{ST0} (in radians), and stores the
8360 result in \c{ST0}. The absolute value of \c{ST0} must be less than 2**63.
8362 See also \c{FSINCOS} (\k{insFSIN}).
8365 \S{insFDECSTP} \i\c{FDECSTP}: Decrement Floating-Point Stack Pointer
8367 \c FDECSTP ; D9 F6 [8086,FPU]
8369 \c{FDECSTP} decrements the `top' field in the floating-point status
8370 word. This has the effect of rotating the FPU register stack by one,
8371 as if the contents of \c{ST7} had been pushed on the stack. See also
8372 \c{FINCSTP} (\k{insFINCSTP}).
8375 \S{insFDISI} \i\c{FxDISI}, \i\c{FxENI}: Disable and Enable Floating-Point Interrupts
8377 \c FDISI ; 9B DB E1 [8086,FPU]
8378 \c FNDISI ; DB E1 [8086,FPU]
8380 \c FENI ; 9B DB E0 [8086,FPU]
8381 \c FNENI ; DB E0 [8086,FPU]
8383 \c{FDISI} and \c{FENI} disable and enable floating-point interrupts.
8384 These instructions are only meaningful on original 8087 processors:
8385 the 287 and above treat them as no-operation instructions.
8387 \c{FNDISI} and \c{FNENI} do the same thing as \c{FDISI} and \c{FENI}
8388 respectively, but without waiting for the floating-point processor
8389 to finish what it was doing first.
8392 \S{insFDIV} \i\c{FDIV}, \i\c{FDIVP}, \i\c{FDIVR}, \i\c{FDIVRP}: Floating-Point Division
8394 \c FDIV mem32 ; D8 /6 [8086,FPU]
8395 \c FDIV mem64 ; DC /6 [8086,FPU]
8397 \c FDIV fpureg ; D8 F0+r [8086,FPU]
8398 \c FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
8400 \c FDIV TO fpureg ; DC F8+r [8086,FPU]
8401 \c FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
8403 \c FDIVR mem32 ; D8 /0 [8086,FPU]
8404 \c FDIVR mem64 ; DC /0 [8086,FPU]
8406 \c FDIVR fpureg ; D8 F8+r [8086,FPU]
8407 \c FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
8409 \c FDIVR TO fpureg ; DC F0+r [8086,FPU]
8410 \c FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
8412 \c FDIVP fpureg ; DE F8+r [8086,FPU]
8413 \c FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
8415 \c FDIVRP fpureg ; DE F0+r [8086,FPU]
8416 \c FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
8418 \b \c{FDIV} divides \c{ST0} by the given operand and stores the result
8419 back in \c{ST0}, unless the \c{TO} qualifier is given, in which case
8420 it divides the given operand by \c{ST0} and stores the result in the
8423 \b \c{FDIVR} does the same thing, but does the division the other way
8424 up: so if \c{TO} is not given, it divides the given operand by
8425 \c{ST0} and stores the result in \c{ST0}, whereas if \c{TO} is given
8426 it divides \c{ST0} by its operand and stores the result in the
8429 \b \c{FDIVP} operates like \c{FDIV TO}, but pops the register stack
8430 once it has finished.
8432 \b \c{FDIVRP} operates like \c{FDIVR TO}, but pops the register stack
8433 once it has finished.
8435 For FP/Integer divisions, see \c{FIDIV} (\k{insFIDIV}).
8438 \S{insFEMMS} \i\c{FEMMS}: Faster Enter/Exit of the MMX or floating-point state
8440 \c FEMMS ; 0F 0E [PENT,3DNOW]
8442 \c{FEMMS} can be used in place of the \c{EMMS} instruction on
8443 processors which support the 3DNow! instruction set. Following
8444 execution of \c{FEMMS}, the state of the \c{MMX/FP} registers
8445 is undefined, and this allows a faster context switch between
8446 \c{FP} and \c{MMX} instructions. The \c{FEMMS} instruction can
8447 also be used \e{before} executing \c{MMX} instructions
8450 \S{insFFREE} \i\c{FFREE}: Flag Floating-Point Register as Unused
8452 \c FFREE fpureg ; DD C0+r [8086,FPU]
8453 \c FFREEP fpureg ; DF C0+r [286,FPU,UNDOC]
8455 \c{FFREE} marks the given register as being empty.
8457 \c{FFREEP} marks the given register as being empty, and then
8458 pops the register stack.
8461 \S{insFIADD} \i\c{FIADD}: Floating-Point/Integer Addition
8463 \c FIADD mem16 ; DE /0 [8086,FPU]
8464 \c FIADD mem32 ; DA /0 [8086,FPU]
8466 \c{FIADD} adds the 16-bit or 32-bit integer stored in the given
8467 memory location to \c{ST0}, storing the result in \c{ST0}.
8470 \S{insFICOM} \i\c{FICOM}, \i\c{FICOMP}: Floating-Point/Integer Compare
8472 \c FICOM mem16 ; DE /2 [8086,FPU]
8473 \c FICOM mem32 ; DA /2 [8086,FPU]
8475 \c FICOMP mem16 ; DE /3 [8086,FPU]
8476 \c FICOMP mem32 ; DA /3 [8086,FPU]
8478 \c{FICOM} compares \c{ST0} with the 16-bit or 32-bit integer stored
8479 in the given memory location, and sets the FPU flags accordingly.
8480 \c{FICOMP} does the same, but pops the register stack afterwards.
8483 \S{insFIDIV} \i\c{FIDIV}, \i\c{FIDIVR}: Floating-Point/Integer Division
8485 \c FIDIV mem16 ; DE /6 [8086,FPU]
8486 \c FIDIV mem32 ; DA /6 [8086,FPU]
8488 \c FIDIVR mem16 ; DE /7 [8086,FPU]
8489 \c FIDIVR mem32 ; DA /7 [8086,FPU]
8491 \c{FIDIV} divides \c{ST0} by the 16-bit or 32-bit integer stored in
8492 the given memory location, and stores the result in \c{ST0}.
8493 \c{FIDIVR} does the division the other way up: it divides the
8494 integer by \c{ST0}, but still stores the result in \c{ST0}.
8497 \S{insFILD} \i\c{FILD}, \i\c{FIST}, \i\c{FISTP}: Floating-Point/Integer Conversion
8499 \c FILD mem16 ; DF /0 [8086,FPU]
8500 \c FILD mem32 ; DB /0 [8086,FPU]
8501 \c FILD mem64 ; DF /5 [8086,FPU]
8503 \c FIST mem16 ; DF /2 [8086,FPU]
8504 \c FIST mem32 ; DB /2 [8086,FPU]
8506 \c FISTP mem16 ; DF /3 [8086,FPU]
8507 \c FISTP mem32 ; DB /3 [8086,FPU]
8508 \c FISTP mem64 ; DF /7 [8086,FPU]
8510 \c{FILD} loads an integer out of a memory location, converts it to a
8511 real, and pushes it on the FPU register stack. \c{FIST} converts
8512 \c{ST0} to an integer and stores that in memory; \c{FISTP} does the
8513 same as \c{FIST}, but pops the register stack afterwards.
8516 \S{insFIMUL} \i\c{FIMUL}: Floating-Point/Integer Multiplication
8518 \c FIMUL mem16 ; DE /1 [8086,FPU]
8519 \c FIMUL mem32 ; DA /1 [8086,FPU]
8521 \c{FIMUL} multiplies \c{ST0} by the 16-bit or 32-bit integer stored
8522 in the given memory location, and stores the result in \c{ST0}.
8525 \S{insFINCSTP} \i\c{FINCSTP}: Increment Floating-Point Stack Pointer
8527 \c FINCSTP ; D9 F7 [8086,FPU]
8529 \c{FINCSTP} increments the `top' field in the floating-point status
8530 word. This has the effect of rotating the FPU register stack by one,
8531 as if the register stack had been popped; however, unlike the
8532 popping of the stack performed by many FPU instructions, it does not
8533 flag the new \c{ST7} (previously \c{ST0}) as empty. See also
8534 \c{FDECSTP} (\k{insFDECSTP}).
8537 \S{insFINIT} \i\c{FINIT}, \i\c{FNINIT}: Initialise Floating-Point Unit
8539 \c FINIT ; 9B DB E3 [8086,FPU]
8540 \c FNINIT ; DB E3 [8086,FPU]
8542 \c{FINIT} initialises the FPU to its default state. It flags all
8543 registers as empty, without actually change their values, clears
8544 the top of stack pointer. \c{FNINIT} does the same, without first
8545 waiting for pending exceptions to clear.
8548 \S{insFISUB} \i\c{FISUB}: Floating-Point/Integer Subtraction
8550 \c FISUB mem16 ; DE /4 [8086,FPU]
8551 \c FISUB mem32 ; DA /4 [8086,FPU]
8553 \c FISUBR mem16 ; DE /5 [8086,FPU]
8554 \c FISUBR mem32 ; DA /5 [8086,FPU]
8556 \c{FISUB} subtracts the 16-bit or 32-bit integer stored in the given
8557 memory location from \c{ST0}, and stores the result in \c{ST0}.
8558 \c{FISUBR} does the subtraction the other way round, i.e. it
8559 subtracts \c{ST0} from the given integer, but still stores the
8563 \S{insFLD} \i\c{FLD}: Floating-Point Load
8565 \c FLD mem32 ; D9 /0 [8086,FPU]
8566 \c FLD mem64 ; DD /0 [8086,FPU]
8567 \c FLD mem80 ; DB /5 [8086,FPU]
8568 \c FLD fpureg ; D9 C0+r [8086,FPU]
8570 \c{FLD} loads a floating-point value out of the given register or
8571 memory location, and pushes it on the FPU register stack.
8574 \S{insFLD1} \i\c{FLDxx}: Floating-Point Load Constants
8576 \c FLD1 ; D9 E8 [8086,FPU]
8577 \c FLDL2E ; D9 EA [8086,FPU]
8578 \c FLDL2T ; D9 E9 [8086,FPU]
8579 \c FLDLG2 ; D9 EC [8086,FPU]
8580 \c FLDLN2 ; D9 ED [8086,FPU]
8581 \c FLDPI ; D9 EB [8086,FPU]
8582 \c FLDZ ; D9 EE [8086,FPU]
8584 These instructions push specific standard constants on the FPU
8587 \c Instruction Constant pushed
8590 \c FLDL2E base-2 logarithm of e
8591 \c FLDL2T base-2 log of 10
8592 \c FLDLG2 base-10 log of 2
8593 \c FLDLN2 base-e log of 2
8598 \S{insFLDCW} \i\c{FLDCW}: Load Floating-Point Control Word
8600 \c FLDCW mem16 ; D9 /5 [8086,FPU]
8602 \c{FLDCW} loads a 16-bit value out of memory and stores it into the
8603 FPU control word (governing things like the rounding mode, the
8604 precision, and the exception masks). See also \c{FSTCW}
8605 (\k{insFSTCW}). If exceptions are enabled and you don't want to
8606 generate one, use \c{FCLEX} or \c{FNCLEX} (\k{insFCLEX}) before
8607 loading the new control word.
8610 \S{insFLDENV} \i\c{FLDENV}: Load Floating-Point Environment
8612 \c FLDENV mem ; D9 /4 [8086,FPU]
8614 \c{FLDENV} loads the FPU operating environment (control word, status
8615 word, tag word, instruction pointer, data pointer and last opcode)
8616 from memory. The memory area is 14 or 28 bytes long, depending on
8617 the CPU mode at the time. See also \c{FSTENV} (\k{insFSTENV}).
8620 \S{insFMUL} \i\c{FMUL}, \i\c{FMULP}: Floating-Point Multiply
8622 \c FMUL mem32 ; D8 /1 [8086,FPU]
8623 \c FMUL mem64 ; DC /1 [8086,FPU]
8625 \c FMUL fpureg ; D8 C8+r [8086,FPU]
8626 \c FMUL ST0,fpureg ; D8 C8+r [8086,FPU]
8628 \c FMUL TO fpureg ; DC C8+r [8086,FPU]
8629 \c FMUL fpureg,ST0 ; DC C8+r [8086,FPU]
8631 \c FMULP fpureg ; DE C8+r [8086,FPU]
8632 \c FMULP fpureg,ST0 ; DE C8+r [8086,FPU]
8634 \c{FMUL} multiplies \c{ST0} by the given operand, and stores the
8635 result in \c{ST0}, unless the \c{TO} qualifier is used in which case
8636 it stores the result in the operand. \c{FMULP} performs the same
8637 operation as \c{FMUL TO}, and then pops the register stack.
8640 \S{insFNOP} \i\c{FNOP}: Floating-Point No Operation
8642 \c FNOP ; D9 D0 [8086,FPU]
8644 \c{FNOP} does nothing.
8647 \S{insFPATAN} \i\c{FPATAN}, \i\c{FPTAN}: Arctangent and Tangent
8649 \c FPATAN ; D9 F3 [8086,FPU]
8650 \c FPTAN ; D9 F2 [8086,FPU]
8652 \c{FPATAN} computes the arctangent, in radians, of the result of
8653 dividing \c{ST1} by \c{ST0}, stores the result in \c{ST1}, and pops
8654 the register stack. It works like the C \c{atan2} function, in that
8655 changing the sign of both \c{ST0} and \c{ST1} changes the output
8656 value by pi (so it performs true rectangular-to-polar coordinate
8657 conversion, with \c{ST1} being the Y coordinate and \c{ST0} being
8658 the X coordinate, not merely an arctangent).
8660 \c{FPTAN} computes the tangent of the value in \c{ST0} (in radians),
8661 and stores the result back into \c{ST0}.
8663 The absolute value of \c{ST0} must be less than 2**63.
8666 \S{insFPREM} \i\c{FPREM}, \i\c{FPREM1}: Floating-Point Partial Remainder
8668 \c FPREM ; D9 F8 [8086,FPU]
8669 \c FPREM1 ; D9 F5 [386,FPU]
8671 These instructions both produce the remainder obtained by dividing
8672 \c{ST0} by \c{ST1}. This is calculated, notionally, by dividing
8673 \c{ST0} by \c{ST1}, rounding the result to an integer, multiplying
8674 by \c{ST1} again, and computing the value which would need to be
8675 added back on to the result to get back to the original value in
8678 The two instructions differ in the way the notional round-to-integer
8679 operation is performed. \c{FPREM} does it by rounding towards zero,
8680 so that the remainder it returns always has the same sign as the
8681 original value in \c{ST0}; \c{FPREM1} does it by rounding to the
8682 nearest integer, so that the remainder always has at most half the
8683 magnitude of \c{ST1}.
8685 Both instructions calculate \e{partial} remainders, meaning that
8686 they may not manage to provide the final result, but might leave
8687 intermediate results in \c{ST0} instead. If this happens, they will
8688 set the C2 flag in the FPU status word; therefore, to calculate a
8689 remainder, you should repeatedly execute \c{FPREM} or \c{FPREM1}
8690 until C2 becomes clear.
8693 \S{insFRNDINT} \i\c{FRNDINT}: Floating-Point Round to Integer
8695 \c FRNDINT ; D9 FC [8086,FPU]
8697 \c{FRNDINT} rounds the contents of \c{ST0} to an integer, according
8698 to the current rounding mode set in the FPU control word, and stores
8699 the result back in \c{ST0}.
8702 \S{insFRSTOR} \i\c{FSAVE}, \i\c{FRSTOR}: Save/Restore Floating-Point State
8704 \c FSAVE mem ; 9B DD /6 [8086,FPU]
8705 \c FNSAVE mem ; DD /6 [8086,FPU]
8707 \c FRSTOR mem ; DD /4 [8086,FPU]
8709 \c{FSAVE} saves the entire floating-point unit state, including all
8710 the information saved by \c{FSTENV} (\k{insFSTENV}) plus the
8711 contents of all the registers, to a 94 or 108 byte area of memory
8712 (depending on the CPU mode). \c{FRSTOR} restores the floating-point
8713 state from the same area of memory.
8715 \c{FNSAVE} does the same as \c{FSAVE}, without first waiting for
8716 pending floating-point exceptions to clear.
8719 \S{insFSCALE} \i\c{FSCALE}: Scale Floating-Point Value by Power of Two
8721 \c FSCALE ; D9 FD [8086,FPU]
8723 \c{FSCALE} scales a number by a power of two: it rounds \c{ST1}
8724 towards zero to obtain an integer, then multiplies \c{ST0} by two to
8725 the power of that integer, and stores the result in \c{ST0}.
8728 \S{insFSETPM} \i\c{FSETPM}: Set Protected Mode
8730 \c FSETPM ; DB E4 [286,FPU]
8732 This instruction initialises protected mode on the 287 floating-point
8733 coprocessor. It is only meaningful on that processor: the 387 and
8734 above treat the instruction as a no-operation.
8737 \S{insFSIN} \i\c{FSIN}, \i\c{FSINCOS}: Sine and Cosine
8739 \c FSIN ; D9 FE [386,FPU]
8740 \c FSINCOS ; D9 FB [386,FPU]
8742 \c{FSIN} calculates the sine of \c{ST0} (in radians) and stores the
8743 result in \c{ST0}. \c{FSINCOS} does the same, but then pushes the
8744 cosine of the same value on the register stack, so that the sine
8745 ends up in \c{ST1} and the cosine in \c{ST0}. \c{FSINCOS} is faster
8746 than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in succession.
8748 The absolute value of \c{ST0} must be less than 2**63.
8751 \S{insFSQRT} \i\c{FSQRT}: Floating-Point Square Root
8753 \c FSQRT ; D9 FA [8086,FPU]
8755 \c{FSQRT} calculates the square root of \c{ST0} and stores the
8759 \S{insFST} \i\c{FST}, \i\c{FSTP}: Floating-Point Store
8761 \c FST mem32 ; D9 /2 [8086,FPU]
8762 \c FST mem64 ; DD /2 [8086,FPU]
8763 \c FST fpureg ; DD D0+r [8086,FPU]
8765 \c FSTP mem32 ; D9 /3 [8086,FPU]
8766 \c FSTP mem64 ; DD /3 [8086,FPU]
8767 \c FSTP mem80 ; DB /7 [8086,FPU]
8768 \c FSTP fpureg ; DD D8+r [8086,FPU]
8770 \c{FST} stores the value in \c{ST0} into the given memory location
8771 or other FPU register. \c{FSTP} does the same, but then pops the
8775 \S{insFSTCW} \i\c{FSTCW}: Store Floating-Point Control Word
8777 \c FSTCW mem16 ; 9B D9 /7 [8086,FPU]
8778 \c FNSTCW mem16 ; D9 /7 [8086,FPU]
8780 \c{FSTCW} stores the \c{FPU} control word (governing things like the
8781 rounding mode, the precision, and the exception masks) into a 2-byte
8782 memory area. See also \c{FLDCW} (\k{insFLDCW}).
8784 \c{FNSTCW} does the same thing as \c{FSTCW}, without first waiting
8785 for pending floating-point exceptions to clear.
8788 \S{insFSTENV} \i\c{FSTENV}: Store Floating-Point Environment
8790 \c FSTENV mem ; 9B D9 /6 [8086,FPU]
8791 \c FNSTENV mem ; D9 /6 [8086,FPU]
8793 \c{FSTENV} stores the \c{FPU} operating environment (control word,
8794 status word, tag word, instruction pointer, data pointer and last
8795 opcode) into memory. The memory area is 14 or 28 bytes long,
8796 depending on the CPU mode at the time. See also \c{FLDENV}
8799 \c{FNSTENV} does the same thing as \c{FSTENV}, without first waiting
8800 for pending floating-point exceptions to clear.
8803 \S{insFSTSW} \i\c{FSTSW}: Store Floating-Point Status Word
8805 \c FSTSW mem16 ; 9B DD /7 [8086,FPU]
8806 \c FSTSW AX ; 9B DF E0 [286,FPU]
8808 \c FNSTSW mem16 ; DD /7 [8086,FPU]
8809 \c FNSTSW AX ; DF E0 [286,FPU]
8811 \c{FSTSW} stores the \c{FPU} status word into \c{AX} or into a 2-byte
8814 \c{FNSTSW} does the same thing as \c{FSTSW}, without first waiting
8815 for pending floating-point exceptions to clear.
8818 \S{insFSUB} \i\c{FSUB}, \i\c{FSUBP}, \i\c{FSUBR}, \i\c{FSUBRP}: Floating-Point Subtract
8820 \c FSUB mem32 ; D8 /4 [8086,FPU]
8821 \c FSUB mem64 ; DC /4 [8086,FPU]
8823 \c FSUB fpureg ; D8 E0+r [8086,FPU]
8824 \c FSUB ST0,fpureg ; D8 E0+r [8086,FPU]
8826 \c FSUB TO fpureg ; DC E8+r [8086,FPU]
8827 \c FSUB fpureg,ST0 ; DC E8+r [8086,FPU]
8829 \c FSUBR mem32 ; D8 /5 [8086,FPU]
8830 \c FSUBR mem64 ; DC /5 [8086,FPU]
8832 \c FSUBR fpureg ; D8 E8+r [8086,FPU]
8833 \c FSUBR ST0,fpureg ; D8 E8+r [8086,FPU]
8835 \c FSUBR TO fpureg ; DC E0+r [8086,FPU]
8836 \c FSUBR fpureg,ST0 ; DC E0+r [8086,FPU]
8838 \c FSUBP fpureg ; DE E8+r [8086,FPU]
8839 \c FSUBP fpureg,ST0 ; DE E8+r [8086,FPU]
8841 \c FSUBRP fpureg ; DE E0+r [8086,FPU]
8842 \c FSUBRP fpureg,ST0 ; DE E0+r [8086,FPU]
8844 \b \c{FSUB} subtracts the given operand from \c{ST0} and stores the
8845 result back in \c{ST0}, unless the \c{TO} qualifier is given, in
8846 which case it subtracts \c{ST0} from the given operand and stores
8847 the result in the operand.
8849 \b \c{FSUBR} does the same thing, but does the subtraction the other
8850 way up: so if \c{TO} is not given, it subtracts \c{ST0} from the given
8851 operand and stores the result in \c{ST0}, whereas if \c{TO} is given
8852 it subtracts its operand from \c{ST0} and stores the result in the
8855 \b \c{FSUBP} operates like \c{FSUB TO}, but pops the register stack
8856 once it has finished.
8858 \b \c{FSUBRP} operates like \c{FSUBR TO}, but pops the register stack
8859 once it has finished.
8862 \S{insFTST} \i\c{FTST}: Test \c{ST0} Against Zero
8864 \c FTST ; D9 E4 [8086,FPU]
8866 \c{FTST} compares \c{ST0} with zero and sets the FPU flags
8867 accordingly. \c{ST0} is treated as the left-hand side of the
8868 comparison, so that a `less-than' result is generated if \c{ST0} is
8872 \S{insFUCOM} \i\c{FUCOMxx}: Floating-Point Unordered Compare
8874 \c FUCOM fpureg ; DD E0+r [386,FPU]
8875 \c FUCOM ST0,fpureg ; DD E0+r [386,FPU]
8877 \c FUCOMP fpureg ; DD E8+r [386,FPU]
8878 \c FUCOMP ST0,fpureg ; DD E8+r [386,FPU]
8880 \c FUCOMPP ; DA E9 [386,FPU]
8882 \c FUCOMI fpureg ; DB E8+r [P6,FPU]
8883 \c FUCOMI ST0,fpureg ; DB E8+r [P6,FPU]
8885 \c FUCOMIP fpureg ; DF E8+r [P6,FPU]
8886 \c FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU]
8888 \b \c{FUCOM} compares \c{ST0} with the given operand, and sets the
8889 FPU flags accordingly. \c{ST0} is treated as the left-hand side of
8890 the comparison, so that the carry flag is set (for a `less-than'
8891 result) if \c{ST0} is less than the given operand.
8893 \b \c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack
8894 afterwards. \c{FUCOMPP} compares \c{ST0} with \c{ST1} and then pops
8895 the register stack twice.
8897 \b \c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of
8898 \c{FUCOM} and \c{FUCOMP}, but write their results directly to the CPU
8899 flags register rather than the FPU status word, so they can be
8900 immediately followed by conditional jump or conditional move
8903 The \c{FUCOM} instructions differ from the \c{FCOM} instructions
8904 (\k{insFCOM}) only in the way they handle quiet NaNs: \c{FUCOM} will
8905 handle them silently and set the condition code flags to an
8906 `unordered' result, whereas \c{FCOM} will generate an exception.
8909 \S{insFXAM} \i\c{FXAM}: Examine Class of Value in \c{ST0}
8911 \c FXAM ; D9 E5 [8086,FPU]
8913 \c{FXAM} sets the FPU flags \c{C3}, \c{C2} and \c{C0} depending on
8914 the type of value stored in \c{ST0}:
8916 \c Register contents Flags
8918 \c Unsupported format 000
8920 \c Finite number 010
8923 \c Empty register 101
8926 Additionally, the \c{C1} flag is set to the sign of the number.
8929 \S{insFXCH} \i\c{FXCH}: Floating-Point Exchange
8931 \c FXCH ; D9 C9 [8086,FPU]
8932 \c FXCH fpureg ; D9 C8+r [8086,FPU]
8933 \c FXCH fpureg,ST0 ; D9 C8+r [8086,FPU]
8934 \c FXCH ST0,fpureg ; D9 C8+r [8086,FPU]
8936 \c{FXCH} exchanges \c{ST0} with a given FPU register. The no-operand
8937 form exchanges \c{ST0} with \c{ST1}.
8940 \S{insFXRSTOR} \i\c{FXRSTOR}: Restore \c{FP}, \c{MMX} and \c{SSE} State
8942 \c FXRSTOR memory ; 0F AE /1 [P6,SSE,FPU]
8944 The \c{FXRSTOR} instruction reloads the \c{FPU}, \c{MMX} and \c{SSE}
8945 state (environment and registers), from the 512 byte memory area defined
8946 by the source operand. This data should have been written by a previous
8950 \S{insFXSAVE} \i\c{FXSAVE}: Store \c{FP}, \c{MMX} and \c{SSE} State
8952 \c FXSAVE memory ; 0F AE /0 [P6,SSE,FPU]
8954 \c{FXSAVE}The FXSAVE instruction writes the current \c{FPU}, \c{MMX}
8955 and \c{SSE} technology states (environment and registers), to the
8956 512 byte memory area defined by the destination operand. It does this
8957 without checking for pending unmasked floating-point exceptions
8958 (similar to the operation of \c{FNSAVE}).
8960 Unlike the \c{FSAVE/FNSAVE} instructions, the processor retains the
8961 contents of the \c{FPU}, \c{MMX} and \c{SSE} state in the processor
8962 after the state has been saved. This instruction has been optimised
8963 to maximize floating-point save performance.
8966 \S{insFXTRACT} \i\c{FXTRACT}: Extract Exponent and Significand
8968 \c FXTRACT ; D9 F4 [8086,FPU]
8970 \c{FXTRACT} separates the number in \c{ST0} into its exponent and
8971 significand (mantissa), stores the exponent back into \c{ST0}, and
8972 then pushes the significand on the register stack (so that the
8973 significand ends up in \c{ST0}, and the exponent in \c{ST1}).
8976 \S{insFYL2X} \i\c{FYL2X}, \i\c{FYL2XP1}: Compute Y times Log2(X) or Log2(X+1)
8978 \c FYL2X ; D9 F1 [8086,FPU]
8979 \c FYL2XP1 ; D9 F9 [8086,FPU]
8981 \c{FYL2X} multiplies \c{ST1} by the base-2 logarithm of \c{ST0},
8982 stores the result in \c{ST1}, and pops the register stack (so that
8983 the result ends up in \c{ST0}). \c{ST0} must be non-zero and
8986 \c{FYL2XP1} works the same way, but replacing the base-2 log of
8987 \c{ST0} with that of \c{ST0} plus one. This time, \c{ST0} must have
8988 magnitude no greater than 1 minus half the square root of two.
8991 \S{insHLT} \i\c{HLT}: Halt Processor
8993 \c HLT ; F4 [8086,PRIV]
8995 \c{HLT} puts the processor into a halted state, where it will
8996 perform no more operations until restarted by an interrupt or a
8999 On the 286 and later processors, this is a privileged instruction.
9002 \S{insIBTS} \i\c{IBTS}: Insert Bit String
9004 \c IBTS r/m16,reg16 ; o16 0F A7 /r [386,UNDOC]
9005 \c IBTS r/m32,reg32 ; o32 0F A7 /r [386,UNDOC]
9007 The implied operation of this instruction is:
9009 \c IBTS r/m16,AX,CL,reg16
9010 \c IBTS r/m32,EAX,CL,reg32
9012 Writes a bit string from the source operand to the destination.
9013 \c{CL} indicates the number of bits to be copied, from the low bits
9014 of the source. \c{(E)AX} indicates the low order bit offset in the
9015 destination that is written to. For example, if \c{CL} is set to 4
9016 and \c{AX} (for 16-bit code) is set to 5, bits 0-3 of \c{src} will
9017 be copied to bits 5-8 of \c{dst}. This instruction is very poorly
9018 documented, and I have been unable to find any official source of
9019 documentation on it.
9021 \c{IBTS} is supported only on the early Intel 386s, and conflicts
9022 with the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM
9023 supports it only for completeness. Its counterpart is \c{XBTS}
9027 \S{insIDIV} \i\c{IDIV}: Signed Integer Divide
9029 \c IDIV r/m8 ; F6 /7 [8086]
9030 \c IDIV r/m16 ; o16 F7 /7 [8086]
9031 \c IDIV r/m32 ; o32 F7 /7 [386]
9033 \c{IDIV} performs signed integer division. The explicit operand
9034 provided is the divisor; the dividend and destination operands
9035 are implicit, in the following way:
9037 \b For \c{IDIV r/m8}, \c{AX} is divided by the given operand;
9038 the quotient is stored in \c{AL} and the remainder in \c{AH}.
9040 \b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand;
9041 the quotient is stored in \c{AX} and the remainder in \c{DX}.
9043 \b For \c{IDIV r/m32}, \c{EDX:EAX} is divided by the given operand;
9044 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
9046 Unsigned integer division is performed by the \c{DIV} instruction:
9050 \S{insIMUL} \i\c{IMUL}: Signed Integer Multiply
9052 \c IMUL r/m8 ; F6 /5 [8086]
9053 \c IMUL r/m16 ; o16 F7 /5 [8086]
9054 \c IMUL r/m32 ; o32 F7 /5 [386]
9056 \c IMUL reg16,r/m16 ; o16 0F AF /r [386]
9057 \c IMUL reg32,r/m32 ; o32 0F AF /r [386]
9059 \c IMUL reg16,imm8 ; o16 6B /r ib [186]
9060 \c IMUL reg16,imm16 ; o16 69 /r iw [186]
9061 \c IMUL reg32,imm8 ; o32 6B /r ib [386]
9062 \c IMUL reg32,imm32 ; o32 69 /r id [386]
9064 \c IMUL reg16,r/m16,imm8 ; o16 6B /r ib [186]
9065 \c IMUL reg16,r/m16,imm16 ; o16 69 /r iw [186]
9066 \c IMUL reg32,r/m32,imm8 ; o32 6B /r ib [386]
9067 \c IMUL reg32,r/m32,imm32 ; o32 69 /r id [386]
9069 \c{IMUL} performs signed integer multiplication. For the
9070 single-operand form, the other operand and destination are
9071 implicit, in the following way:
9073 \b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand;
9074 the product is stored in \c{AX}.
9076 \b For \c{IMUL r/m16}, \c{AX} is multiplied by the given operand;
9077 the product is stored in \c{DX:AX}.
9079 \b For \c{IMUL r/m32}, \c{EAX} is multiplied by the given operand;
9080 the product is stored in \c{EDX:EAX}.
9082 The two-operand form multiplies its two operands and stores the
9083 result in the destination (first) operand. The three-operand
9084 form multiplies its last two operands and stores the result in
9087 The two-operand form with an immediate second operand is in
9088 fact a shorthand for the three-operand form, as can be seen by
9089 examining the opcode descriptions: in the two-operand form, the
9090 code \c{/r} takes both its register and \c{r/m} parts from the
9091 same operand (the first one).
9093 In the forms with an 8-bit immediate operand and another longer
9094 source operand, the immediate operand is considered to be signed,
9095 and is sign-extended to the length of the other source operand.
9096 In these cases, the \c{BYTE} qualifier is necessary to force
9097 NASM to generate this form of the instruction.
9099 Unsigned integer multiplication is performed by the \c{MUL}
9100 instruction: see \k{insMUL}.
9103 \S{insIN} \i\c{IN}: Input from I/O Port
9105 \c IN AL,imm8 ; E4 ib [8086]
9106 \c IN AX,imm8 ; o16 E5 ib [8086]
9107 \c IN EAX,imm8 ; o32 E5 ib [386]
9108 \c IN AL,DX ; EC [8086]
9109 \c IN AX,DX ; o16 ED [8086]
9110 \c IN EAX,DX ; o32 ED [386]
9112 \c{IN} reads a byte, word or doubleword from the specified I/O port,
9113 and stores it in the given destination register. The port number may
9114 be specified as an immediate value if it is between 0 and 255, and
9115 otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}).
9118 \S{insINC} \i\c{INC}: Increment Integer
9120 \c INC reg16 ; o16 40+r [8086]
9121 \c INC reg32 ; o32 40+r [386]
9122 \c INC r/m8 ; FE /0 [8086]
9123 \c INC r/m16 ; o16 FF /0 [8086]
9124 \c INC r/m32 ; o32 FF /0 [386]
9126 \c{INC} adds 1 to its operand. It does \e{not} affect the carry
9127 flag: to affect the carry flag, use \c{ADD something,1} (see
9128 \k{insADD}). \c{INC} affects all the other flags according to the result.
9130 This instruction can be used with a \c{LOCK} prefix to allow atomic execution.
9132 See also \c{DEC} (\k{insDEC}).
9135 \S{insINSB} \i\c{INSB}, \i\c{INSW}, \i\c{INSD}: Input String from I/O Port
9138 \c INSW ; o16 6D [186]
9139 \c INSD ; o32 6D [386]
9141 \c{INSB} inputs a byte from the I/O port specified in \c{DX} and
9142 stores it at \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or
9143 decrements (depending on the direction flag: increments if the flag
9144 is clear, decrements if it is set) \c{DI} or \c{EDI}.
9146 The register used is \c{DI} if the address size is 16 bits, and
9147 \c{EDI} if it is 32 bits. If you need to use an address size not
9148 equal to the current \c{BITS} setting, you can use an explicit
9149 \i\c{a16} or \i\c{a32} prefix.
9151 Segment override prefixes have no effect for this instruction: the
9152 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
9155 \c{INSW} and \c{INSD} work in the same way, but they input a word or
9156 a doubleword instead of a byte, and increment or decrement the
9157 addressing register by 2 or 4 instead of 1.
9159 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
9160 \c{ECX} - again, the address size chooses which) times.
9162 See also \c{OUTSB}, \c{OUTSW} and \c{OUTSD} (\k{insOUTSB}).
9165 \S{insINT} \i\c{INT}: Software Interrupt
9167 \c INT imm8 ; CD ib [8086]
9169 \c{INT} causes a software interrupt through a specified vector
9170 number from 0 to 255.
9172 The code generated by the \c{INT} instruction is always two bytes
9173 long: although there are short forms for some \c{INT} instructions,
9174 NASM does not generate them when it sees the \c{INT} mnemonic. In
9175 order to generate single-byte breakpoint instructions, use the
9176 \c{INT3} or \c{INT1} instructions (see \k{insINT1}) instead.
9179 \S{insINT1} \i\c{INT3}, \i\c{INT1}, \i\c{ICEBP}, \i\c{INT01}: Breakpoints
9186 \c INT03 ; CC [8086]
9188 \c{INT1} and \c{INT3} are short one-byte forms of the instructions
9189 \c{INT 1} and \c{INT 3} (see \k{insINT}). They perform a similar
9190 function to their longer counterparts, but take up less code space.
9191 They are used as breakpoints by debuggers.
9193 \b \c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is
9194 an instruction used by in-circuit emulators (ICEs). It is present,
9195 though not documented, on some processors down to the 286, but is
9196 only documented for the Pentium Pro. \c{INT3} is the instruction
9197 normally used as a breakpoint by debuggers.
9199 \b \c{INT3}, and its synonym \c{INT03}, is not precisely equivalent to
9200 \c{INT 3}: the short form, since it is designed to be used as a
9201 breakpoint, bypasses the normal \c{IOPL} checks in virtual-8086 mode,
9202 and also does not go through interrupt redirection.
9205 \S{insINTO} \i\c{INTO}: Interrupt if Overflow
9209 \c{INTO} performs an \c{INT 4} software interrupt (see \k{insINT})
9210 if and only if the overflow flag is set.
9213 \S{insINVD} \i\c{INVD}: Invalidate Internal Caches
9215 \c INVD ; 0F 08 [486]
9217 \c{INVD} invalidates and empties the processor's internal caches,
9218 and causes the processor to instruct external caches to do the same.
9219 It does not write the contents of the caches back to memory first:
9220 any modified data held in the caches will be lost. To write the data
9221 back first, use \c{WBINVD} (\k{insWBINVD}).
9224 \S{insINVLPG} \i\c{INVLPG}: Invalidate TLB Entry
9226 \c INVLPG mem ; 0F 01 /7 [486]
9228 \c{INVLPG} invalidates the translation lookahead buffer (TLB) entry
9229 associated with the supplied memory address.
9232 \S{insIRET} \i\c{IRET}, \i\c{IRETW}, \i\c{IRETD}: Return from Interrupt
9235 \c IRETW ; o16 CF [8086]
9236 \c IRETD ; o32 CF [386]
9238 \c{IRET} returns from an interrupt (hardware or software) by means
9239 of popping \c{IP} (or \c{EIP}), \c{CS} and the flags off the stack
9240 and then continuing execution from the new \c{CS:IP}.
9242 \c{IRETW} pops \c{IP}, \c{CS} and the flags as 2 bytes each, taking
9243 6 bytes off the stack in total. \c{IRETD} pops \c{EIP} as 4 bytes,
9244 pops a further 4 bytes of which the top two are discarded and the
9245 bottom two go into \c{CS}, and pops the flags as 4 bytes as well,
9246 taking 12 bytes off the stack.
9248 \c{IRET} is a shorthand for either \c{IRETW} or \c{IRETD}, depending
9249 on the default \c{BITS} setting at the time.
9252 \S{insJcc} \i\c{Jcc}: Conditional Branch
9254 \c Jcc imm ; 70+cc rb [8086]
9255 \c Jcc NEAR imm ; 0F 80+cc rw/rd [386]
9257 The \i{conditional jump} instructions execute a near (same segment)
9258 jump if and only if their conditions are satisfied. For example,
9259 \c{JNZ} jumps only if the zero flag is not set.
9261 The ordinary form of the instructions has only a 128-byte range; the
9262 \c{NEAR} form is a 386 extension to the instruction set, and can
9263 span the full size of a segment. NASM will not override your choice
9264 of jump instruction: if you want \c{Jcc NEAR}, you have to use the
9267 The \c{SHORT} keyword is allowed on the first form of the
9268 instruction, for clarity, but is not necessary.
9270 For details of the condition codes, see \k{iref-cc}.
9273 \S{insJCXZ} \i\c{JCXZ}, \i\c{JECXZ}: Jump if CX/ECX Zero
9275 \c JCXZ imm ; a16 E3 rb [8086]
9276 \c JECXZ imm ; a32 E3 rb [386]
9278 \c{JCXZ} performs a short jump (with maximum range 128 bytes) if and
9279 only if the contents of the \c{CX} register is 0. \c{JECXZ} does the
9280 same thing, but with \c{ECX}.
9283 \S{insJMP} \i\c{JMP}: Jump
9285 \c JMP imm ; E9 rw/rd [8086]
9286 \c JMP SHORT imm ; EB rb [8086]
9287 \c JMP imm:imm16 ; o16 EA iw iw [8086]
9288 \c JMP imm:imm32 ; o32 EA id iw [386]
9289 \c JMP FAR mem ; o16 FF /5 [8086]
9290 \c JMP FAR mem32 ; o32 FF /5 [386]
9291 \c JMP r/m16 ; o16 FF /4 [8086]
9292 \c JMP r/m32 ; o32 FF /4 [386]
9294 \c{JMP} jumps to a given address. The address may be specified as an
9295 absolute segment and offset, or as a relative jump within the
9298 \c{JMP SHORT imm} has a maximum range of 128 bytes, since the
9299 displacement is specified as only 8 bits, but takes up less code
9300 space. NASM does not choose when to generate \c{JMP SHORT} for you:
9301 you must explicitly code \c{SHORT} every time you want a short jump.
9303 You can choose between the two immediate \i{far jump} forms (\c{JMP
9304 imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: \c{JMP
9305 WORD 0x1234:0x5678}) or \c{JMP DWORD 0x1234:0x56789abc}.
9307 The \c{JMP FAR mem} forms execute a far jump by loading the
9308 destination address out of memory. The address loaded consists of 16
9309 or 32 bits of offset (depending on the operand size), and 16 bits of
9310 segment. The operand size may be overridden using \c{JMP WORD FAR
9311 mem} or \c{JMP DWORD FAR mem}.
9313 The \c{JMP r/m} forms execute a \i{near jump} (within the same
9314 segment), loading the destination address out of memory or out of a
9315 register. The keyword \c{NEAR} may be specified, for clarity, in
9316 these forms, but is not necessary. Again, operand size can be
9317 overridden using \c{JMP WORD mem} or \c{JMP DWORD mem}.
9319 As a convenience, NASM does not require you to jump to a far symbol
9320 by coding the cumbersome \c{JMP SEG routine:routine}, but instead
9321 allows the easier synonym \c{JMP FAR routine}.
9323 The \c{CALL r/m} forms given above are near calls; NASM will accept
9324 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
9325 is not strictly necessary.
9328 \S{insLAHF} \i\c{LAHF}: Load AH from Flags
9332 \c{LAHF} sets the \c{AH} register according to the contents of the
9333 low byte of the flags word.
9335 The operation of \c{LAHF} is:
9337 \c AH <-- SF:ZF:0:AF:0:PF:1:CF
9339 See also \c{SAHF} (\k{insSAHF}).
9342 \S{insLAR} \i\c{LAR}: Load Access Rights
9344 \c LAR reg16,r/m16 ; o16 0F 02 /r [286,PRIV]
9345 \c LAR reg32,r/m32 ; o32 0F 02 /r [286,PRIV]
9347 \c{LAR} takes the segment selector specified by its source (second)
9348 operand, finds the corresponding segment descriptor in the GDT or
9349 LDT, and loads the access-rights byte of the descriptor into its
9350 destination (first) operand.
9353 \S{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension
9356 \c LDMXCSR mem32 ; 0F AE /2 [KATMAI,SSE]
9358 \c{LDMXCSR} loads 32-bits of data from the specified memory location
9359 into the \c{MXCSR} control/status register. \c{MXCSR} is used to
9360 enable masked/unmasked exception handling, to set rounding modes,
9361 to set flush-to-zero mode, and to view exception status flags.
9363 For details of the \c{MXCSR} register, see the Intel processor docs.
9365 See also \c{STMXCSR} (\k{insSTMXCSR}
9368 \S{insLDS} \i\c{LDS}, \i\c{LES}, \i\c{LFS}, \i\c{LGS}, \i\c{LSS}: Load Far Pointer
9370 \c LDS reg16,mem ; o16 C5 /r [8086]
9371 \c LDS reg32,mem ; o32 C5 /r [386]
9373 \c LES reg16,mem ; o16 C4 /r [8086]
9374 \c LES reg32,mem ; o32 C4 /r [386]
9376 \c LFS reg16,mem ; o16 0F B4 /r [386]
9377 \c LFS reg32,mem ; o32 0F B4 /r [386]
9379 \c LGS reg16,mem ; o16 0F B5 /r [386]
9380 \c LGS reg32,mem ; o32 0F B5 /r [386]
9382 \c LSS reg16,mem ; o16 0F B2 /r [386]
9383 \c LSS reg32,mem ; o32 0F B2 /r [386]
9385 These instructions load an entire far pointer (16 or 32 bits of
9386 offset, plus 16 bits of segment) out of memory in one go. \c{LDS},
9387 for example, loads 16 or 32 bits from the given memory address into
9388 the given register (depending on the size of the register), then
9389 loads the \e{next} 16 bits from memory into \c{DS}. \c{LES},
9390 \c{LFS}, \c{LGS} and \c{LSS} work in the same way but use the other
9394 \S{insLEA} \i\c{LEA}: Load Effective Address
9396 \c LEA reg16,mem ; o16 8D /r [8086]
9397 \c LEA reg32,mem ; o32 8D /r [386]
9399 \c{LEA}, despite its syntax, does not access memory. It calculates
9400 the effective address specified by its second operand as if it were
9401 going to load or store data from it, but instead it stores the
9402 calculated address into the register specified by its first operand.
9403 This can be used to perform quite complex calculations (e.g. \c{LEA
9404 EAX,[EBX+ECX*4+100]}) in one instruction.
9406 \c{LEA}, despite being a purely arithmetic instruction which
9407 accesses no memory, still requires square brackets around its second
9408 operand, as if it were a memory reference.
9410 The size of the calculation is the current \e{address} size, and the
9411 size that the result is stored as is the current \e{operand} size.
9412 If the address and operand size are not the same, then if the
9413 addressing mode was 32-bits, the low 16-bits are stored, and if the
9414 address was 16-bits, it is zero-extended to 32-bits before storing.
9417 \S{insLEAVE} \i\c{LEAVE}: Destroy Stack Frame
9421 \c{LEAVE} destroys a stack frame of the form created by the
9422 \c{ENTER} instruction (see \k{insENTER}). It is functionally
9423 equivalent to \c{MOV ESP,EBP} followed by \c{POP EBP} (or \c{MOV
9424 SP,BP} followed by \c{POP BP} in 16-bit mode).
9427 \S{insLFENCE} \i\c{LFENCE}: Load Fence
9429 \c LFENCE ; 0F AE /5 [WILLAMETTE,SSE2]
9431 \c{LFENCE} performs a serialising operation on all loads from memory
9432 that were issued before the \c{LFENCE} instruction. This guarantees that
9433 all memory reads before the \c{LFENCE} instruction are visible before any
9434 reads after the \c{LFENCE} instruction.
9436 \c{LFENCE} is ordered respective to other \c{LFENCE} instruction, \c{MFENCE},
9437 any memory read and any other serialising instruction (such as \c{CPUID}).
9439 Weakly ordered memory types can be used to achieve higher processor
9440 performance through such techniques as out-of-order issue and
9441 speculative reads. The degree to which a consumer of data recognizes
9442 or knows that the data is weakly ordered varies among applications
9443 and may be unknown to the producer of this data. The \c{LFENCE}
9444 instruction provides a performance-efficient way of ensuring load
9445 ordering between routines that produce weakly-ordered results and
9446 routines that consume that data.
9448 \c{LFENCE} uses the following ModRM encoding:
9451 \c Reg/Opcode (5:3) = 101B
9454 All other ModRM encodings are defined to be reserved, and use
9455 of these encodings risks incompatibility with future processors.
9457 See also \c{SFENCE} (\k{insSFENCE}) and \c{MFENCE} (\k{insMFENCE}).
9460 \S{insLGDT} \i\c{LGDT}, \i\c{LIDT}, \i\c{LLDT}: Load Descriptor Tables
9462 \c LGDT mem ; 0F 01 /2 [286,PRIV]
9463 \c LIDT mem ; 0F 01 /3 [286,PRIV]
9464 \c LLDT r/m16 ; 0F 00 /2 [286,PRIV]
9466 \c{LGDT} and \c{LIDT} both take a 6-byte memory area as an operand:
9467 they load a 32-bit linear address and a 16-bit size limit from that
9468 area (in the opposite order) into the \c{GDTR} (global descriptor table
9469 register) or \c{IDTR} (interrupt descriptor table register). These are
9470 the only instructions which directly use \e{linear} addresses, rather
9471 than segment/offset pairs.
9473 \c{LLDT} takes a segment selector as an operand. The processor looks
9474 up that selector in the GDT and stores the limit and base address
9475 given there into the \c{LDTR} (local descriptor table register).
9477 See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}).
9480 \S{insLMSW} \i\c{LMSW}: Load/Store Machine Status Word
9482 \c LMSW r/m16 ; 0F 01 /6 [286,PRIV]
9484 \c{LMSW} loads the bottom four bits of the source operand into the
9485 bottom four bits of the \c{CR0} control register (or the Machine
9486 Status Word, on 286 processors). See also \c{SMSW} (\k{insSMSW}).
9489 \S{insLOADALL} \i\c{LOADALL}, \i\c{LOADALL286}: Load Processor State
9491 \c LOADALL ; 0F 07 [386,UNDOC]
9492 \c LOADALL286 ; 0F 05 [286,UNDOC]
9494 This instruction, in its two different-opcode forms, is apparently
9495 supported on most 286 processors, some 386 and possibly some 486.
9496 The opcode differs between the 286 and the 386.
9498 The function of the instruction is to load all information relating
9499 to the state of the processor out of a block of memory: on the 286,
9500 this block is located implicitly at absolute address \c{0x800}, and
9501 on the 386 and 486 it is at \c{[ES:EDI]}.
9504 \S{insLODSB} \i\c{LODSB}, \i\c{LODSW}, \i\c{LODSD}: Load from String
9506 \c LODSB ; AC [8086]
9507 \c LODSW ; o16 AD [8086]
9508 \c LODSD ; o32 AD [386]
9510 \c{LODSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} into \c{AL}.
9511 It then increments or decrements (depending on the direction flag:
9512 increments if the flag is clear, decrements if it is set) \c{SI} or
9515 The register used is \c{SI} if the address size is 16 bits, and
9516 \c{ESI} if it is 32 bits. If you need to use an address size not
9517 equal to the current \c{BITS} setting, you can use an explicit
9518 \i\c{a16} or \i\c{a32} prefix.
9520 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
9521 overridden by using a segment register name as a prefix (for
9522 example, \c{ES LODSB}).
9524 \c{LODSW} and \c{LODSD} work in the same way, but they load a
9525 word or a doubleword instead of a byte, and increment or decrement
9526 the addressing registers by 2 or 4 instead of 1.
9529 \S{insLOOP} \i\c{LOOP}, \i\c{LOOPE}, \i\c{LOOPZ}, \i\c{LOOPNE}, \i\c{LOOPNZ}: Loop with Counter
9531 \c LOOP imm ; E2 rb [8086]
9532 \c LOOP imm,CX ; a16 E2 rb [8086]
9533 \c LOOP imm,ECX ; a32 E2 rb [386]
9535 \c LOOPE imm ; E1 rb [8086]
9536 \c LOOPE imm,CX ; a16 E1 rb [8086]
9537 \c LOOPE imm,ECX ; a32 E1 rb [386]
9538 \c LOOPZ imm ; E1 rb [8086]
9539 \c LOOPZ imm,CX ; a16 E1 rb [8086]
9540 \c LOOPZ imm,ECX ; a32 E1 rb [386]
9542 \c LOOPNE imm ; E0 rb [8086]
9543 \c LOOPNE imm,CX ; a16 E0 rb [8086]
9544 \c LOOPNE imm,ECX ; a32 E0 rb [386]
9545 \c LOOPNZ imm ; E0 rb [8086]
9546 \c LOOPNZ imm,CX ; a16 E0 rb [8086]
9547 \c LOOPNZ imm,ECX ; a32 E0 rb [386]
9549 \c{LOOP} decrements its counter register (either \c{CX} or \c{ECX} -
9550 if one is not specified explicitly, the \c{BITS} setting dictates
9551 which is used) by one, and if the counter does not become zero as a
9552 result of this operation, it jumps to the given label. The jump has
9553 a range of 128 bytes.
9555 \c{LOOPE} (or its synonym \c{LOOPZ}) adds the additional condition
9556 that it only jumps if the counter is nonzero \e{and} the zero flag
9557 is set. Similarly, \c{LOOPNE} (and \c{LOOPNZ}) jumps only if the
9558 counter is nonzero and the zero flag is clear.
9561 \S{insLSL} \i\c{LSL}: Load Segment Limit
9563 \c LSL reg16,r/m16 ; o16 0F 03 /r [286,PRIV]
9564 \c LSL reg32,r/m32 ; o32 0F 03 /r [286,PRIV]
9566 \c{LSL} is given a segment selector in its source (second) operand;
9567 it computes the segment limit value by loading the segment limit
9568 field from the associated segment descriptor in the \c{GDT} or \c{LDT}.
9569 (This involves shifting left by 12 bits if the segment limit is
9570 page-granular, and not if it is byte-granular; so you end up with a
9571 byte limit in either case.) The segment limit obtained is then
9572 loaded into the destination (first) operand.
9575 \S{insLTR} \i\c{LTR}: Load Task Register
9577 \c LTR r/m16 ; 0F 00 /3 [286,PRIV]
9579 \c{LTR} looks up the segment base and limit in the GDT or LDT
9580 descriptor specified by the segment selector given as its operand,
9581 and loads them into the Task Register.
9584 \S{insMASKMOVDQU} \i\c{MASKMOVDQU}: Byte Mask Write
9586 \c MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2]
9588 \c{MASKMOVDQU} stores data from xmm1 to the location specified by
9589 \c{ES:(E)DI}. The size of the store depends on the address-size
9590 attribute. The most significant bit in each byte of the mask
9591 register xmm2 is used to selectively write the data (0 = no write,
9592 1 = write) on a per-byte basis.
9595 \S{insMASKMOVQ} \i\c{MASKMOVQ}: Byte Mask Write
9597 \c MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX]
9599 \c{MASKMOVQ} stores data from mm1 to the location specified by
9600 \c{ES:(E)DI}. The size of the store depends on the address-size
9601 attribute. The most significant bit in each byte of the mask
9602 register mm2 is used to selectively write the data (0 = no write,
9603 1 = write) on a per-byte basis.
9606 \S{insMAXPD} \i\c{MAXPD}: Return Packed Double-Precision FP Maximum
9608 \c MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2]
9610 \c{MAXPD} performs a SIMD compare of the packed double-precision
9611 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9612 of each pair of values in xmm1. If the values being compared are
9613 both zeroes, source2 (xmm2/m128) would be returned. If source2
9614 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9615 destination (i.e., a QNaN version of the SNaN is not returned).
9618 \S{insMAXPS} \i\c{MAXPS}: Return Packed Single-Precision FP Maximum
9620 \c MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE]
9622 \c{MAXPS} performs a SIMD compare of the packed single-precision
9623 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9624 of each pair of values in xmm1. If the values being compared are
9625 both zeroes, source2 (xmm2/m128) would be returned. If source2
9626 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9627 destination (i.e., a QNaN version of the SNaN is not returned).
9630 \S{insMAXSD} \i\c{MAXSD}: Return Scalar Double-Precision FP Maximum
9632 \c MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2]
9634 \c{MAXSD} compares the low-order double-precision FP numbers from
9635 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9636 values being compared are both zeroes, source2 (xmm2/m64) would
9637 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9638 forwarded unchanged to the destination (i.e., a QNaN version of
9639 the SNaN is not returned). The high quadword of the destination
9643 \S{insMAXSS} \i\c{MAXSS}: Return Scalar Single-Precision FP Maximum
9645 \c MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE]
9647 \c{MAXSS} compares the low-order single-precision FP numbers from
9648 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9649 values being compared are both zeroes, source2 (xmm2/m32) would
9650 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9651 forwarded unchanged to the destination (i.e., a QNaN version of
9652 the SNaN is not returned). The high three doublewords of the
9653 destination are left unchanged.
9656 \S{insMFENCE} \i\c{MFENCE}: Memory Fence
9658 \c MFENCE ; 0F AE /6 [WILLAMETTE,SSE2]
9660 \c{MFENCE} performs a serialising operation on all loads from memory
9661 and writes to memory that were issued before the \c{MFENCE} instruction.
9662 This guarantees that all memory reads and writes before the \c{MFENCE}
9663 instruction are completed before any reads and writes after the
9664 \c{MFENCE} instruction.
9666 \c{MFENCE} is ordered respective to other \c{MFENCE} instructions,
9667 \c{LFENCE}, \c{SFENCE}, any memory read and any other serialising
9668 instruction (such as \c{CPUID}).
9670 Weakly ordered memory types can be used to achieve higher processor
9671 performance through such techniques as out-of-order issue, speculative
9672 reads, write-combining, and write-collapsing. The degree to which a
9673 consumer of data recognizes or knows that the data is weakly ordered
9674 varies among applications and may be unknown to the producer of this
9675 data. The \c{MFENCE} instruction provides a performance-efficient way
9676 of ensuring load and store ordering between routines that produce
9677 weakly-ordered results and routines that consume that data.
9679 \c{MFENCE} uses the following ModRM encoding:
9682 \c Reg/Opcode (5:3) = 110B
9685 All other ModRM encodings are defined to be reserved, and use
9686 of these encodings risks incompatibility with future processors.
9688 See also \c{LFENCE} (\k{insLFENCE}) and \c{SFENCE} (\k{insSFENCE}).
9691 \S{insMINPD} \i\c{MINPD}: Return Packed Double-Precision FP Minimum
9693 \c MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2]
9695 \c{MINPD} performs a SIMD compare of the packed double-precision
9696 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9697 of each pair of values in xmm1. If the values being compared are
9698 both zeroes, source2 (xmm2/m128) would be returned. If source2
9699 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9700 destination (i.e., a QNaN version of the SNaN is not returned).
9703 \S{insMINPS} \i\c{MINPS}: Return Packed Single-Precision FP Minimum
9705 \c MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE]
9707 \c{MINPS} performs a SIMD compare of the packed single-precision
9708 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9709 of each pair of values in xmm1. If the values being compared are
9710 both zeroes, source2 (xmm2/m128) would be returned. If source2
9711 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9712 destination (i.e., a QNaN version of the SNaN is not returned).
9715 \S{insMINSD} \i\c{MINSD}: Return Scalar Double-Precision FP Minimum
9717 \c MINSD xmm1,xmm2/m64 ; F2 0F 5D /r [WILLAMETTE,SSE2]
9719 \c{MINSD} compares the low-order double-precision FP numbers from
9720 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9721 values being compared are both zeroes, source2 (xmm2/m64) would
9722 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9723 forwarded unchanged to the destination (i.e., a QNaN version of
9724 the SNaN is not returned). The high quadword of the destination
9728 \S{insMINSS} \i\c{MINSS}: Return Scalar Single-Precision FP Minimum
9730 \c MINSS xmm1,xmm2/m32 ; F3 0F 5D /r [KATMAI,SSE]
9732 \c{MINSS} compares the low-order single-precision FP numbers from
9733 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9734 values being compared are both zeroes, source2 (xmm2/m32) would
9735 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9736 forwarded unchanged to the destination (i.e., a QNaN version of
9737 the SNaN is not returned). The high three doublewords of the
9738 destination are left unchanged.
9741 \S{insMOV} \i\c{MOV}: Move Data
9743 \c MOV r/m8,reg8 ; 88 /r [8086]
9744 \c MOV r/m16,reg16 ; o16 89 /r [8086]
9745 \c MOV r/m32,reg32 ; o32 89 /r [386]
9746 \c MOV reg8,r/m8 ; 8A /r [8086]
9747 \c MOV reg16,r/m16 ; o16 8B /r [8086]
9748 \c MOV reg32,r/m32 ; o32 8B /r [386]
9750 \c MOV reg8,imm8 ; B0+r ib [8086]
9751 \c MOV reg16,imm16 ; o16 B8+r iw [8086]
9752 \c MOV reg32,imm32 ; o32 B8+r id [386]
9753 \c MOV r/m8,imm8 ; C6 /0 ib [8086]
9754 \c MOV r/m16,imm16 ; o16 C7 /0 iw [8086]
9755 \c MOV r/m32,imm32 ; o32 C7 /0 id [386]
9757 \c MOV AL,memoffs8 ; A0 ow/od [8086]
9758 \c MOV AX,memoffs16 ; o16 A1 ow/od [8086]
9759 \c MOV EAX,memoffs32 ; o32 A1 ow/od [386]
9760 \c MOV memoffs8,AL ; A2 ow/od [8086]
9761 \c MOV memoffs16,AX ; o16 A3 ow/od [8086]
9762 \c MOV memoffs32,EAX ; o32 A3 ow/od [386]
9764 \c MOV r/m16,segreg ; o16 8C /r [8086]
9765 \c MOV r/m32,segreg ; o32 8C /r [386]
9766 \c MOV segreg,r/m16 ; o16 8E /r [8086]
9767 \c MOV segreg,r/m32 ; o32 8E /r [386]
9769 \c MOV reg32,CR0/2/3/4 ; 0F 20 /r [386]
9770 \c MOV reg32,DR0/1/2/3/6/7 ; 0F 21 /r [386]
9771 \c MOV reg32,TR3/4/5/6/7 ; 0F 24 /r [386]
9772 \c MOV CR0/2/3/4,reg32 ; 0F 22 /r [386]
9773 \c MOV DR0/1/2/3/6/7,reg32 ; 0F 23 /r [386]
9774 \c MOV TR3/4/5/6/7,reg32 ; 0F 26 /r [386]
9776 \c{MOV} copies the contents of its source (second) operand into its
9777 destination (first) operand.
9779 In all forms of the \c{MOV} instruction, the two operands are the
9780 same size, except for moving between a segment register and an
9781 \c{r/m32} operand. These instructions are treated exactly like the
9782 corresponding 16-bit equivalent (so that, for example, \c{MOV
9783 DS,EAX} functions identically to \c{MOV DS,AX} but saves a prefix
9784 when in 32-bit mode), except that when a segment register is moved
9785 into a 32-bit destination, the top two bytes of the result are
9788 \c{MOV} may not use \c{CS} as a destination.
9790 \c{CR4} is only a supported register on the Pentium and above.
9792 Test registers are supported on 386/486 processors and on some
9793 non-Intel Pentium class processors.
9796 \S{insMOVAPD} \i\c{MOVAPD}: Move Aligned Packed Double-Precision FP Values
9798 \c MOVAPD xmm1,xmm2/mem128 ; 66 0F 28 /r [WILLAMETTE,SSE2]
9799 \c MOVAPD xmm1/mem128,xmm2 ; 66 0F 29 /r [WILLAMETTE,SSE2]
9801 \c{MOVAPD} moves a double quadword containing 2 packed double-precision
9802 FP values from the source operand to the destination. When the source
9803 or destination operand is a memory location, it must be aligned on a
9806 To move data in and out of memory locations that are not known to be on
9807 16-byte boundaries, use the \c{MOVUPD} instruction (\k{insMOVUPD}).
9810 \S{insMOVAPS} \i\c{MOVAPS}: Move Aligned Packed Single-Precision FP Values
9812 \c MOVAPS xmm1,xmm2/mem128 ; 0F 28 /r [KATMAI,SSE]
9813 \c MOVAPS xmm1/mem128,xmm2 ; 0F 29 /r [KATMAI,SSE]
9815 \c{MOVAPS} moves a double quadword containing 4 packed single-precision
9816 FP values from the source operand to the destination. When the source
9817 or destination operand is a memory location, it must be aligned on a
9820 To move data in and out of memory locations that are not known to be on
9821 16-byte boundaries, use the \c{MOVUPS} instruction (\k{insMOVUPS}).
9824 \S{insMOVD} \i\c{MOVD}: Move Doubleword to/from MMX Register
9826 \c MOVD mm,r/m32 ; 0F 6E /r [PENT,MMX]
9827 \c MOVD r/m32,mm ; 0F 7E /r [PENT,MMX]
9828 \c MOVD xmm,r/m32 ; 66 0F 6E /r [WILLAMETTE,SSE2]
9829 \c MOVD r/m32,xmm ; 66 0F 7E /r [WILLAMETTE,SSE2]
9831 \c{MOVD} copies 32 bits from its source (second) operand into its
9832 destination (first) operand. When the destination is a 64-bit \c{MMX}
9833 register or a 128-bit \c{XMM} register, the input value is zero-extended
9834 to fill the destination register.
9837 \S{insMOVDQ2Q} \i\c{MOVDQ2Q}: Move Quadword from XMM to MMX register.
9839 \c MOVDQ2Q mm,xmm ; F2 OF D6 /r [WILLAMETTE,SSE2]
9841 \c{MOVDQ2Q} moves the low quadword from the source operand to the
9842 destination operand.
9845 \S{insMOVDQA} \i\c{MOVDQA}: Move Aligned Double Quadword
9847 \c MOVDQA xmm1,xmm2/m128 ; 66 OF 6F /r [WILLAMETTE,SSE2]
9848 \c MOVDQA xmm1/m128,xmm2 ; 66 OF 7F /r [WILLAMETTE,SSE2]
9850 \c{MOVDQA} moves a double quadword from the source operand to the
9851 destination operand. When the source or destination operand is a
9852 memory location, it must be aligned to a 16-byte boundary.
9854 To move a double quadword to or from unaligned memory locations,
9855 use the \c{MOVDQU} instruction (\k{insMOVDQU}).
9858 \S{insMOVDQU} \i\c{MOVDQU}: Move Unaligned Double Quadword
9860 \c MOVDQU xmm1,xmm2/m128 ; F3 OF 6F /r [WILLAMETTE,SSE2]
9861 \c MOVDQU xmm1/m128,xmm2 ; F3 OF 7F /r [WILLAMETTE,SSE2]
9863 \c{MOVDQU} moves a double quadword from the source operand to the
9864 destination operand. When the source or destination operand is a
9865 memory location, the memory may be unaligned.
9867 To move a double quadword to or from known aligned memory locations,
9868 use the \c{MOVDQA} instruction (\k{insMOVDQA}).
9871 \S{insMOVHLPS} \i\c{MOVHLPS}: Move Packed Single-Precision FP High to Low
9873 \c MOVHLPS xmm1,xmm2 ; OF 12 /r [KATMAI,SSE]
9875 \c{MOVHLPS} moves the two packed single-precision FP values from the
9876 high quadword of the source register xmm2 to the low quadword of the
9877 destination register, xmm2. The upper quadword of xmm1 is left unchanged.
9879 The operation of this instruction is:
9881 \c dst[0-63] := src[64-127],
9882 \c dst[64-127] remains unchanged.
9885 \S{insMOVHPD} \i\c{MOVHPD}: Move High Packed Double-Precision FP
9887 \c MOVHPD xmm,m64 ; 66 OF 16 /r [WILLAMETTE,SSE2]
9888 \c MOVHPD m64,xmm ; 66 OF 17 /r [WILLAMETTE,SSE2]
9890 \c{MOVHPD} moves a double-precision FP value between the source and
9891 destination operands. One of the operands is a 64-bit memory location,
9892 the other is the high quadword of an \c{XMM} register.
9894 The operation of this instruction is:
9896 \c mem[0-63] := xmm[64-127];
9900 \c xmm[0-63] remains unchanged;
9901 \c xmm[64-127] := mem[0-63].
9904 \S{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-Precision FP
9906 \c MOVHPS xmm,m64 ; 0F 16 /r [KATMAI,SSE]
9907 \c MOVHPS m64,xmm ; 0F 17 /r [KATMAI,SSE]
9909 \c{MOVHPS} moves two packed single-precision FP values between the source
9910 and destination operands. One of the operands is a 64-bit memory location,
9911 the other is the high quadword of an \c{XMM} register.
9913 The operation of this instruction is:
9915 \c mem[0-63] := xmm[64-127];
9919 \c xmm[0-63] remains unchanged;
9920 \c xmm[64-127] := mem[0-63].
9923 \S{insMOVLHPS} \i\c{MOVLHPS}: Move Packed Single-Precision FP Low to High
9925 \c MOVLHPS xmm1,xmm2 ; OF 16 /r [KATMAI,SSE]
9927 \c{MOVLHPS} moves the two packed single-precision FP values from the
9928 low quadword of the source register xmm2 to the high quadword of the
9929 destination register, xmm2. The low quadword of xmm1 is left unchanged.
9931 The operation of this instruction is:
9933 \c dst[0-63] remains unchanged;
9934 \c dst[64-127] := src[0-63].
9936 \S{insMOVLPD} \i\c{MOVLPD}: Move Low Packed Double-Precision FP
9938 \c MOVLPD xmm,m64 ; 66 OF 12 /r [WILLAMETTE,SSE2]
9939 \c MOVLPD m64,xmm ; 66 OF 13 /r [WILLAMETTE,SSE2]
9941 \c{MOVLPD} moves a double-precision FP value between the source and
9942 destination operands. One of the operands is a 64-bit memory location,
9943 the other is the low quadword of an \c{XMM} register.
9945 The operation of this instruction is:
9947 \c mem(0-63) := xmm(0-63);
9951 \c xmm(0-63) := mem(0-63);
9952 \c xmm(64-127) remains unchanged.
9954 \S{insMOVLPS} \i\c{MOVLPS}: Move Low Packed Single-Precision FP
9956 \c MOVLPS xmm,m64 ; OF 12 /r [KATMAI,SSE]
9957 \c MOVLPS m64,xmm ; OF 13 /r [KATMAI,SSE]
9959 \c{MOVLPS} moves two packed single-precision FP values between the source
9960 and destination operands. One of the operands is a 64-bit memory location,
9961 the other is the low quadword of an \c{XMM} register.
9963 The operation of this instruction is:
9965 \c mem(0-63) := xmm(0-63);
9969 \c xmm(0-63) := mem(0-63);
9970 \c xmm(64-127) remains unchanged.
9973 \S{insMOVMSKPD} \i\c{MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask
9975 \c MOVMSKPD reg32,xmm ; 66 0F 50 /r [WILLAMETTE,SSE2]
9977 \c{MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant
9978 bits of each double-precision FP number of the source operand.
9981 \S{insMOVMSKPS} \i\c{MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask
9983 \c MOVMSKPS reg32,xmm ; 0F 50 /r [KATMAI,SSE]
9985 \c{MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant
9986 bits of each single-precision FP number of the source operand.
9989 \S{insMOVNTDQ} \i\c{MOVNTDQ}: Move Double Quadword Non Temporal
9991 \c MOVNTDQ m128,xmm ; 66 0F E7 /r [WILLAMETTE,SSE2]
9993 \c{MOVNTDQ} moves the double quadword from the \c{XMM} source
9994 register to the destination memory location, using a non-temporal
9995 hint. This store instruction minimizes cache pollution.
9998 \S{insMOVNTI} \i\c{MOVNTI}: Move Doubleword Non Temporal
10000 \c MOVNTI m32,reg32 ; 0F C3 /r [WILLAMETTE,SSE2]
10002 \c{MOVNTI} moves the doubleword in the source register
10003 to the destination memory location, using a non-temporal
10004 hint. This store instruction minimizes cache pollution.
10007 \S{insMOVNTPD} \i\c{MOVNTPD}: Move Aligned Four Packed Single-Precision
10008 FP Values Non Temporal
10010 \c MOVNTPD m128,xmm ; 66 0F 2B /r [WILLAMETTE,SSE2]
10012 \c{MOVNTPD} moves the double quadword from the \c{XMM} source
10013 register to the destination memory location, using a non-temporal
10014 hint. This store instruction minimizes cache pollution. The memory
10015 location must be aligned to a 16-byte boundary.
10018 \S{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-Precision
10019 FP Values Non Temporal
10021 \c MOVNTPS m128,xmm ; 0F 2B /r [KATMAI,SSE]
10023 \c{MOVNTPS} moves the double quadword from the \c{XMM} source
10024 register to the destination memory location, using a non-temporal
10025 hint. This store instruction minimizes cache pollution. The memory
10026 location must be aligned to a 16-byte boundary.
10029 \S{insMOVNTQ} \i\c{MOVNTQ}: Move Quadword Non Temporal
10031 \c MOVNTQ m64,mm ; 0F E7 /r [KATMAI,MMX]
10033 \c{MOVNTQ} moves the quadword in the \c{MMX} source register
10034 to the destination memory location, using a non-temporal
10035 hint. This store instruction minimizes cache pollution.
10038 \S{insMOVQ} \i\c{MOVQ}: Move Quadword to/from MMX Register
10040 \c MOVQ mm1,mm2/m64 ; 0F 6F /r [PENT,MMX]
10041 \c MOVQ mm1/m64,mm2 ; 0F 7F /r [PENT,MMX]
10043 \c MOVQ xmm1,xmm2/m64 ; F3 0F 7E /r [WILLAMETTE,SSE2]
10044 \c MOVQ xmm1/m64,xmm2 ; 66 0F D6 /r [WILLAMETTE,SSE2]
10046 \c{MOVQ} copies 64 bits from its source (second) operand into its
10047 destination (first) operand. When the source is an \c{XMM} register,
10048 the low quadword is moved. When the destination is an \c{XMM} register,
10049 the destination is the low quadword, and the high quadword is cleared.
10052 \S{insMOVQ2DQ} \i\c{MOVQ2DQ}: Move Quadword from MMX to XMM register.
10054 \c MOVQ2DQ xmm,mm ; F3 OF D6 /r [WILLAMETTE,SSE2]
10056 \c{MOVQ2DQ} moves the quadword from the source operand to the low
10057 quadword of the destination operand, and clears the high quadword.
10060 \S{insMOVSB} \i\c{MOVSB}, \i\c{MOVSW}, \i\c{MOVSD}: Move String
10062 \c MOVSB ; A4 [8086]
10063 \c MOVSW ; o16 A5 [8086]
10064 \c MOVSD ; o32 A5 [386]
10066 \c{MOVSB} copies the byte at \c{[DS:SI]} or \c{[DS:ESI]} to
10067 \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or decrements
10068 (depending on the direction flag: increments if the flag is clear,
10069 decrements if it is set) \c{SI} and \c{DI} (or \c{ESI} and \c{EDI}).
10071 The registers used are \c{SI} and \c{DI} if the address size is 16
10072 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
10073 an address size not equal to the current \c{BITS} setting, you can
10074 use an explicit \i\c{a16} or \i\c{a32} prefix.
10076 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
10077 overridden by using a segment register name as a prefix (for
10078 example, \c{es movsb}). The use of \c{ES} for the store to \c{[DI]}
10079 or \c{[EDI]} cannot be overridden.
10081 \c{MOVSW} and \c{MOVSD} work in the same way, but they copy a word
10082 or a doubleword instead of a byte, and increment or decrement the
10083 addressing registers by 2 or 4 instead of 1.
10085 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
10086 \c{ECX} - again, the address size chooses which) times.
10089 \S{insMOVSD} \i\c{MOVSD}: Move Scalar Double-Precision FP Value
10091 \c MOVSD xmm1,xmm2/m64 ; F2 0F 10 /r [WILLAMETTE,SSE2]
10092 \c MOVSD xmm1/m64,xmm2 ; F2 0F 11 /r [WILLAMETTE,SSE2]
10094 \c{MOVSD} moves a double-precision FP value from the source operand
10095 to the destination operand. When the source or destination is a
10096 register, the low-order FP value is read or written.
10099 \S{insMOVSS} \i\c{MOVSS}: Move Scalar Single-Precision FP Value
10101 \c MOVSS xmm1,xmm2/m32 ; F3 0F 10 /r [KATMAI,SSE]
10102 \c MOVSS xmm1/m32,xmm2 ; F3 0F 11 /r [KATMAI,SSE]
10104 \c{MOVSS} moves a single-precision FP value from the source operand
10105 to the destination operand. When the source or destination is a
10106 register, the low-order FP value is read or written.
10109 \S{insMOVSX} \i\c{MOVSX}, \i\c{MOVZX}: Move Data with Sign or Zero Extend
10111 \c MOVSX reg16,r/m8 ; o16 0F BE /r [386]
10112 \c MOVSX reg32,r/m8 ; o32 0F BE /r [386]
10113 \c MOVSX reg32,r/m16 ; o32 0F BF /r [386]
10115 \c MOVZX reg16,r/m8 ; o16 0F B6 /r [386]
10116 \c MOVZX reg32,r/m8 ; o32 0F B6 /r [386]
10117 \c MOVZX reg32,r/m16 ; o32 0F B7 /r [386]
10119 \c{MOVSX} sign-extends its source (second) operand to the length of
10120 its destination (first) operand, and copies the result into the
10121 destination operand. \c{MOVZX} does the same, but zero-extends
10122 rather than sign-extending.
10125 \S{insMOVUPD} \i\c{MOVUPD}: Move Unaligned Packed Double-Precision FP Values
10127 \c MOVUPD xmm1,xmm2/mem128 ; 66 0F 10 /r [WILLAMETTE,SSE2]
10128 \c MOVUPD xmm1/mem128,xmm2 ; 66 0F 11 /r [WILLAMETTE,SSE2]
10130 \c{MOVUPD} moves a double quadword containing 2 packed double-precision
10131 FP values from the source operand to the destination. This instruction
10132 makes no assumptions about alignment of memory operands.
10134 To move data in and out of memory locations that are known to be on 16-byte
10135 boundaries, use the \c{MOVAPD} instruction (\k{insMOVAPD}).
10138 \S{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Packed Single-Precision FP Values
10140 \c MOVUPS xmm1,xmm2/mem128 ; 0F 10 /r [KATMAI,SSE]
10141 \c MOVUPS xmm1/mem128,xmm2 ; 0F 11 /r [KATMAI,SSE]
10143 \c{MOVUPS} moves a double quadword containing 4 packed single-precision
10144 FP values from the source operand to the destination. This instruction
10145 makes no assumptions about alignment of memory operands.
10147 To move data in and out of memory locations that are known to be on 16-byte
10148 boundaries, use the \c{MOVAPS} instruction (\k{insMOVAPS}).
10151 \S{insMUL} \i\c{MUL}: Unsigned Integer Multiply
10153 \c MUL r/m8 ; F6 /4 [8086]
10154 \c MUL r/m16 ; o16 F7 /4 [8086]
10155 \c MUL r/m32 ; o32 F7 /4 [386]
10157 \c{MUL} performs unsigned integer multiplication. The other operand
10158 to the multiplication, and the destination operand, are implicit, in
10161 \b For \c{MUL r/m8}, \c{AL} is multiplied by the given operand; the
10162 product is stored in \c{AX}.
10164 \b For \c{MUL r/m16}, \c{AX} is multiplied by the given operand;
10165 the product is stored in \c{DX:AX}.
10167 \b For \c{MUL r/m32}, \c{EAX} is multiplied by the given operand;
10168 the product is stored in \c{EDX:EAX}.
10170 Signed integer multiplication is performed by the \c{IMUL}
10171 instruction: see \k{insIMUL}.
10174 \S{insMULPD} \i\c{MULPD}: Packed Single-FP Multiply
10176 \c MULPD xmm1,xmm2/mem128 ; 66 0F 59 /r [WILLAMETTE,SSE2]
10178 \c{MULPD} performs a SIMD multiply of the packed double-precision FP
10179 values in both operands, and stores the results in the destination register.
10182 \S{insMULPS} \i\c{MULPS}: Packed Single-FP Multiply
10184 \c MULPS xmm1,xmm2/mem128 ; 0F 59 /r [KATMAI,SSE]
10186 \c{MULPS} performs a SIMD multiply of the packed single-precision FP
10187 values in both operands, and stores the results in the destination register.
10190 \S{insMULSD} \i\c{MULSD}: Scalar Single-FP Multiply
10192 \c MULSD xmm1,xmm2/mem32 ; F2 0F 59 /r [WILLAMETTE,SSE2]
10194 \c{MULSD} multiplies the lowest double-precision FP values of both
10195 operands, and stores the result in the low quadword of xmm1.
10198 \S{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply
10200 \c MULSS xmm1,xmm2/mem32 ; F3 0F 59 /r [KATMAI,SSE]
10202 \c{MULSS} multiplies the lowest single-precision FP values of both
10203 operands, and stores the result in the low doubleword of xmm1.
10206 \S{insNEG} \i\c{NEG}, \i\c{NOT}: Two's and One's Complement
10208 \c NEG r/m8 ; F6 /3 [8086]
10209 \c NEG r/m16 ; o16 F7 /3 [8086]
10210 \c NEG r/m32 ; o32 F7 /3 [386]
10212 \c NOT r/m8 ; F6 /2 [8086]
10213 \c NOT r/m16 ; o16 F7 /2 [8086]
10214 \c NOT r/m32 ; o32 F7 /2 [386]
10216 \c{NEG} replaces the contents of its operand by the two's complement
10217 negation (invert all the bits and then add one) of the original
10218 value. \c{NOT}, similarly, performs one's complement (inverts all
10222 \S{insNOP} \i\c{NOP}: No Operation
10226 \c{NOP} performs no operation. Its opcode is the same as that
10227 generated by \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the
10228 processor mode; see \k{insXCHG}).
10231 \S{insOR} \i\c{OR}: Bitwise OR
10233 \c OR r/m8,reg8 ; 08 /r [8086]
10234 \c OR r/m16,reg16 ; o16 09 /r [8086]
10235 \c OR r/m32,reg32 ; o32 09 /r [386]
10237 \c OR reg8,r/m8 ; 0A /r [8086]
10238 \c OR reg16,r/m16 ; o16 0B /r [8086]
10239 \c OR reg32,r/m32 ; o32 0B /r [386]
10241 \c OR r/m8,imm8 ; 80 /1 ib [8086]
10242 \c OR r/m16,imm16 ; o16 81 /1 iw [8086]
10243 \c OR r/m32,imm32 ; o32 81 /1 id [386]
10245 \c OR r/m16,imm8 ; o16 83 /1 ib [8086]
10246 \c OR r/m32,imm8 ; o32 83 /1 ib [386]
10248 \c OR AL,imm8 ; 0C ib [8086]
10249 \c OR AX,imm16 ; o16 0D iw [8086]
10250 \c OR EAX,imm32 ; o32 0D id [386]
10252 \c{OR} performs a bitwise OR operation between its two operands
10253 (i.e. each bit of the result is 1 if and only if at least one of the
10254 corresponding bits of the two inputs was 1), and stores the result
10255 in the destination (first) operand.
10257 In the forms with an 8-bit immediate second operand and a longer
10258 first operand, the second operand is considered to be signed, and is
10259 sign-extended to the length of the first operand. In these cases,
10260 the \c{BYTE} qualifier is necessary to force NASM to generate this
10261 form of the instruction.
10263 The MMX instruction \c{POR} (see \k{insPOR}) performs the same
10264 operation on the 64-bit MMX registers.
10267 \S{insORPD} \i\c{ORPD}: Bit-wise Logical OR of Double-Precision FP Data
10269 \c ORPD xmm1,xmm2/m128 ; 66 0F 56 /r [WILLAMETTE,SSE2]
10271 \c{ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem,
10272 and stores the result in xmm1. If the source operand is a memory
10273 location, it must be aligned to a 16-byte boundary.
10276 \S{insORPS} \i\c{ORPS}: Bit-wise Logical OR of Single-Precision FP Data
10278 \c ORPS xmm1,xmm2/m128 ; 0F 56 /r [KATMAI,SSE]
10280 \c{ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem,
10281 and stores the result in xmm1. If the source operand is a memory
10282 location, it must be aligned to a 16-byte boundary.
10285 \S{insOUT} \i\c{OUT}: Output Data to I/O Port
10287 \c OUT imm8,AL ; E6 ib [8086]
10288 \c OUT imm8,AX ; o16 E7 ib [8086]
10289 \c OUT imm8,EAX ; o32 E7 ib [386]
10290 \c OUT DX,AL ; EE [8086]
10291 \c OUT DX,AX ; o16 EF [8086]
10292 \c OUT DX,EAX ; o32 EF [386]
10294 \c{OUT} writes the contents of the given source register to the
10295 specified I/O port. The port number may be specified as an immediate
10296 value if it is between 0 and 255, and otherwise must be stored in
10297 \c{DX}. See also \c{IN} (\k{insIN}).
10300 \S{insOUTSB} \i\c{OUTSB}, \i\c{OUTSW}, \i\c{OUTSD}: Output String to I/O Port
10302 \c OUTSB ; 6E [186]
10303 \c OUTSW ; o16 6F [186]
10304 \c OUTSD ; o32 6F [386]
10306 \c{OUTSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} and writes
10307 it to the I/O port specified in \c{DX}. It then increments or
10308 decrements (depending on the direction flag: increments if the flag
10309 is clear, decrements if it is set) \c{SI} or \c{ESI}.
10311 The register used is \c{SI} if the address size is 16 bits, and
10312 \c{ESI} if it is 32 bits. If you need to use an address size not
10313 equal to the current \c{BITS} setting, you can use an explicit
10314 \i\c{a16} or \i\c{a32} prefix.
10316 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
10317 overridden by using a segment register name as a prefix (for
10318 example, \c{es outsb}).
10320 \c{OUTSW} and \c{OUTSD} work in the same way, but they output a
10321 word or a doubleword instead of a byte, and increment or decrement
10322 the addressing registers by 2 or 4 instead of 1.
10324 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
10325 \c{ECX} - again, the address size chooses which) times.
10328 \S{insPACKSSDW} \i\c{PACKSSDW}, \i\c{PACKSSWB}, \i\c{PACKUSWB}: Pack Data
10330 \c PACKSSDW mm1,mm2/m64 ; 0F 6B /r [PENT,MMX]
10331 \c PACKSSWB mm1,mm2/m64 ; 0F 63 /r [PENT,MMX]
10332 \c PACKUSWB mm1,mm2/m64 ; 0F 67 /r [PENT,MMX]
10334 \c PACKSSDW xmm1,xmm2/m128 ; 66 0F 6B /r [WILLAMETTE,SSE2]
10335 \c PACKSSWB xmm1,xmm2/m128 ; 66 0F 63 /r [WILLAMETTE,SSE2]
10336 \c PACKUSWB xmm1,xmm2/m128 ; 66 0F 67 /r [WILLAMETTE,SSE2]
10338 All these instructions start by combining the source and destination
10339 operands, and then splitting the result in smaller sections which it
10340 then packs into the destination register. The \c{MMX} versions pack
10341 two 64-bit operands into one 64-bit register, while the \c{SSE}
10342 versions pack two 128-bit operands into one 128-bit register.
10344 \b \c{PACKSSWB} splits the combined value into words, and then reduces
10345 the words to bytes, using signed saturation. It then packs the bytes
10346 into the destination register in the same order the words were in.
10348 \b \c{PACKSSDW} performs the same operation as \c{PACKSSWB}, except that
10349 it reduces doublewords to words, then packs them into the destination
10352 \b \c{PACKUSWB} performs the same operation as \c{PACKSSWB}, except that
10353 it uses unsigned saturation when reducing the size of the elements.
10355 To perform signed saturation on a number, it is replaced by the largest
10356 signed number (\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too
10357 small it is replaced by the smallest signed number (\c{8000h} or
10358 \c{80h}) that will fit. To perform unsigned saturation, the input is
10359 treated as unsigned, and the input is replaced by the largest unsigned
10360 number that will fit.
10363 \S{insPADDB} \i\c{PADDB}, \i\c{PADDW}, \i\c{PADDD}: Add Packed Integers
10365 \c PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX]
10366 \c PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX]
10367 \c PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX]
10369 \c PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2]
10370 \c PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2]
10371 \c PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2]
10373 \c{PADDx} performs packed addition of the two operands, storing the
10374 result in the destination (first) operand.
10376 \b \c{PADDB} treats the operands as packed bytes, and adds each byte
10379 \b \c{PADDW} treats the operands as packed words;
10381 \b \c{PADDD} treats its operands as packed doublewords.
10383 When an individual result is too large to fit in its destination, it
10384 is wrapped around and the low bits are stored, with the carry bit
10388 \S{insPADDQ} \i\c{PADDQ}: Add Packed Quadword Integers
10390 \c PADDQ mm1,mm2/m64 ; 0F D4 /r [PENT,MMX]
10392 \c PADDQ xmm1,xmm2/m128 ; 66 0F D4 /r [WILLAMETTE,SSE2]
10394 \c{PADDQ} adds the quadwords in the source and destination operands, and
10395 stores the result in the destination register.
10397 When an individual result is too large to fit in its destination, it
10398 is wrapped around and the low bits are stored, with the carry bit
10402 \S{insPADDSB} \i\c{PADDSB}, \i\c{PADDSW}: Add Packed Signed Integers With Saturation
10404 \c PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX]
10405 \c PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX]
10407 \c PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2]
10408 \c PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2]
10410 \c{PADDSx} performs packed addition of the two operands, storing the
10411 result in the destination (first) operand.
10412 \c{PADDSB} treats the operands as packed bytes, and adds each byte
10413 individually; and \c{PADDSW} treats the operands as packed words.
10415 When an individual result is too large to fit in its destination, a
10416 saturated value is stored. The resulting value is the value with the
10417 largest magnitude of the same sign as the result which will fit in
10418 the available space.
10421 \S{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit Destination
10423 \c PADDSIW mmxreg,r/m64 ; 0F 51 /r [CYRIX,MMX]
10425 \c{PADDSIW}, specific to the Cyrix extensions to the MMX instruction
10426 set, performs the same function as \c{PADDSW}, except that the result
10427 is placed in an implied register.
10429 To work out the implied register, invert the lowest bit in the register
10430 number. So \c{PADDSIW MM0,MM2} would put the result in \c{MM1}, but
10431 \c{PADDSIW MM1,MM2} would put the result in \c{MM0}.
10434 \S{insPADDUSB} \i\c{PADDUSB}, \i\c{PADDUSW}: Add Packed Unsigned Integers With Saturation
10436 \c PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX]
10437 \c PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX]
10439 \c PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2]
10440 \c PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2]
10442 \c{PADDUSx} performs packed addition of the two operands, storing the
10443 result in the destination (first) operand.
10444 \c{PADDUSB} treats the operands as packed bytes, and adds each byte
10445 individually; and \c{PADDUSW} treats the operands as packed words.
10447 When an individual result is too large to fit in its destination, a
10448 saturated value is stored. The resulting value is the maximum value
10449 that will fit in the available space.
10452 \S{insPAND} \i\c{PAND}, \i\c{PANDN}: MMX Bitwise AND and AND-NOT
10454 \c PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX]
10455 \c PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX]
10457 \c PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2]
10458 \c PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2]
10461 \c{PAND} performs a bitwise AND operation between its two operands
10462 (i.e. each bit of the result is 1 if and only if the corresponding
10463 bits of the two inputs were both 1), and stores the result in the
10464 destination (first) operand.
10466 \c{PANDN} performs the same operation, but performs a one's
10467 complement operation on the destination (first) operand first.
10470 \S{insPAUSE} \i\c{PAUSE}: Spin Loop Hint
10472 \c PAUSE ; F3 90 [WILLAMETTE,SSE2]
10474 \c{PAUSE} provides a hint to the processor that the following code
10475 is a spin loop. This improves processor performance by bypassing
10476 possible memory order violations. On older processors, this instruction
10477 operates as a \c{NOP}.
10480 \S{insPAVEB} \i\c{PAVEB}: MMX Packed Average
10482 \c PAVEB mmxreg,r/m64 ; 0F 50 /r [CYRIX,MMX]
10484 \c{PAVEB}, specific to the Cyrix MMX extensions, treats its two
10485 operands as vectors of eight unsigned bytes, and calculates the
10486 average of the corresponding bytes in the operands. The resulting
10487 vector of eight averages is stored in the first operand.
10489 This opcode maps to \c{MOVMSKPS r32, xmm} on processors that support
10490 the SSE instruction set.
10493 \S{insPAVGB} \i\c{PAVGB} \i\c{PAVGW}: Average Packed Integers
10495 \c PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX]
10496 \c PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM]
10498 \c PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2]
10499 \c PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2]
10501 \c{PAVGB} and \c{PAVGW} add the unsigned data elements of the source
10502 operand to the unsigned data elements of the destination register,
10503 then adds 1 to the temporary results. The results of the add are then
10504 each independently right-shifted by one bit position. The high order
10505 bits of each element are filled with the carry bits of the corresponding
10508 \b \c{PAVGB} operates on packed unsigned bytes, and
10510 \b \c{PAVGW} operates on packed unsigned words.
10513 \S{insPAVGUSB} \i\c{PAVGUSB}: Average of unsigned packed 8-bit values
10515 \c PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW]
10517 \c{PAVGUSB} adds the unsigned data elements of the source operand to
10518 the unsigned data elements of the destination register, then adds 1
10519 to the temporary results. The results of the add are then each
10520 independently right-shifted by one bit position. The high order bits
10521 of each element are filled with the carry bits of the corresponding
10524 This instruction performs exactly the same operations as the \c{PAVGB}
10525 \c{MMX} instruction (\k{insPAVGB}).
10528 \S{insPCMPEQB} \i\c{PCMPxx}: Compare Packed Integers.
10530 \c PCMPEQB mm1,mm2/m64 ; 0F 74 /r [PENT,MMX]
10531 \c PCMPEQW mm1,mm2/m64 ; 0F 75 /r [PENT,MMX]
10532 \c PCMPEQD mm1,mm2/m64 ; 0F 76 /r [PENT,MMX]
10534 \c PCMPGTB mm1,mm2/m64 ; 0F 64 /r [PENT,MMX]
10535 \c PCMPGTW mm1,mm2/m64 ; 0F 65 /r [PENT,MMX]
10536 \c PCMPGTD mm1,mm2/m64 ; 0F 66 /r [PENT,MMX]
10538 \c PCMPEQB xmm1,xmm2/m128 ; 66 0F 74 /r [WILLAMETTE,SSE2]
10539 \c PCMPEQW xmm1,xmm2/m128 ; 66 0F 75 /r [WILLAMETTE,SSE2]
10540 \c PCMPEQD xmm1,xmm2/m128 ; 66 0F 76 /r [WILLAMETTE,SSE2]
10542 \c PCMPGTB xmm1,xmm2/m128 ; 66 0F 64 /r [WILLAMETTE,SSE2]
10543 \c PCMPGTW xmm1,xmm2/m128 ; 66 0F 65 /r [WILLAMETTE,SSE2]
10544 \c PCMPGTD xmm1,xmm2/m128 ; 66 0F 66 /r [WILLAMETTE,SSE2]
10546 The \c{PCMPxx} instructions all treat their operands as vectors of
10547 bytes, words, or doublewords; corresponding elements of the source
10548 and destination are compared, and the corresponding element of the
10549 destination (first) operand is set to all zeros or all ones
10550 depending on the result of the comparison.
10552 \b \c{PCMPxxB} treats the operands as vectors of bytes;
10554 \b \c{PCMPxxW} treats the operands as vectors of words;
10556 \b \c{PCMPxxD} treats the operands as vectors of doublewords;
10558 \b \c{PCMPEQx} sets the corresponding element of the destination
10559 operand to all ones if the two elements compared are equal;
10561 \b \c{PCMPGTx} sets the destination element to all ones if the element
10562 of the first (destination) operand is greater (treated as a signed
10563 integer) than that of the second (source) operand.
10566 \S{insPDISTIB} \i\c{PDISTIB}: MMX Packed Distance and Accumulate
10567 with Implied Register
10569 \c PDISTIB mm,m64 ; 0F 54 /r [CYRIX,MMX]
10571 \c{PDISTIB}, specific to the Cyrix MMX extensions, treats its two
10572 input operands as vectors of eight unsigned bytes. For each byte
10573 position, it finds the absolute difference between the bytes in that
10574 position in the two input operands, and adds that value to the byte
10575 in the same position in the implied output register. The addition is
10576 saturated to an unsigned byte in the same way as \c{PADDUSB}.
10578 To work out the implied register, invert the lowest bit in the register
10579 number. So \c{PDISTIB MM0,M64} would put the result in \c{MM1}, but
10580 \c{PDISTIB MM1,M64} would put the result in \c{MM0}.
10582 Note that \c{PDISTIB} cannot take a register as its second source
10587 \c dstI[0-7] := dstI[0-7] + ABS(src0[0-7] - src1[0-7]),
10588 \c dstI[8-15] := dstI[8-15] + ABS(src0[8-15] - src1[8-15]),
10591 \c dstI[56-63] := dstI[56-63] + ABS(src0[56-63] - src1[56-63]).
10594 \S{insPEXTRW} \i\c{PEXTRW}: Extract Word
10596 \c PEXTRW reg32,mm,imm8 ; 0F C5 /r ib [KATMAI,MMX]
10597 \c PEXTRW reg32,xmm,imm8 ; 66 0F C5 /r ib [WILLAMETTE,SSE2]
10599 \c{PEXTRW} moves the word in the source register (second operand)
10600 that is pointed to by the count operand (third operand), into the
10601 lower half of a 32-bit general purpose register. The upper half of
10602 the register is cleared to all 0s.
10604 When the source operand is an \c{MMX} register, the two least
10605 significant bits of the count specify the source word. When it is
10606 an \c{SSE} register, the three least significant bits specify the
10610 \S{insPF2ID} \i\c{PF2ID}: Packed Single-Precision FP to Integer Convert
10612 \c PF2ID mm1,mm2/m64 ; 0F 0F /r 1D [PENT,3DNOW]
10614 \c{PF2ID} converts two single-precision FP values in the source operand
10615 to signed 32-bit integers, using truncation, and stores them in the
10616 destination operand. Source values that are outside the range supported
10617 by the destination are saturated to the largest absolute value of the
10621 \S{insPF2IW} \i\c{PF2IW}: Packed Single-Precision FP to Integer Word Convert
10623 \c PF2IW mm1,mm2/m64 ; 0F 0F /r 1C [PENT,3DNOW]
10625 \c{PF2IW} converts two single-precision FP values in the source operand
10626 to signed 16-bit integers, using truncation, and stores them in the
10627 destination operand. Source values that are outside the range supported
10628 by the destination are saturated to the largest absolute value of the
10631 \b In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits
10634 \b In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended
10635 to 32-bits before storing.
10638 \S{insPFACC} \i\c{PFACC}: Packed Single-Precision FP Accumulate
10640 \c PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW]
10642 \c{PFACC} adds the two single-precision FP values from the destination
10643 operand together, then adds the two single-precision FP values from the
10644 source operand, and places the results in the low and high doublewords
10645 of the destination operand.
10649 \c dst[0-31] := dst[0-31] + dst[32-63],
10650 \c dst[32-63] := src[0-31] + src[32-63].
10653 \S{insPFADD} \i\c{PFADD}: Packed Single-Precision FP Addition
10655 \c PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW]
10657 \c{PFADD} performs addition on each of two packed single-precision
10660 \c dst[0-31] := dst[0-31] + src[0-31],
10661 \c dst[32-63] := dst[32-63] + src[32-63].
10664 \S{insPFCMP} \i\c{PFCMPxx}: Packed Single-Precision FP Compare
10665 \I\c{PFCMPEQ} \I\c{PFCMPGE} \I\c{PFCMPGT}
10667 \c PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW]
10668 \c PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW]
10669 \c PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW]
10671 The \c{PFCMPxx} instructions compare the packed single-point FP values
10672 in the source and destination operands, and set the destination
10673 according to the result. If the condition is true, the destination is
10674 set to all 1s, otherwise it's set to all 0s.
10676 \b \c{PFCMPEQ} tests whether dst == src;
10678 \b \c{PFCMPGE} tests whether dst >= src;
10680 \b \c{PFCMPGT} tests whether dst > src.
10683 \S{insPFMAX} \i\c{PFMAX}: Packed Single-Precision FP Maximum
10685 \c PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW]
10687 \c{PFMAX} returns the higher of each pair of single-precision FP values.
10688 If the higher value is zero, it is returned as positive zero.
10691 \S{insPFMIN} \i\c{PFMIN}: Packed Single-Precision FP Minimum
10693 \c PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW]
10695 \c{PFMIN} returns the lower of each pair of single-precision FP values.
10696 If the lower value is zero, it is returned as positive zero.
10699 \S{insPFMUL} \i\c{PFMUL}: Packed Single-Precision FP Multiply
10701 \c PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW]
10703 \c{PFMUL} returns the product of each pair of single-precision FP values.
10705 \c dst[0-31] := dst[0-31] * src[0-31],
10706 \c dst[32-63] := dst[32-63] * src[32-63].
10709 \S{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Negative Accumulate
10711 \c PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW]
10713 \c{PFNACC} performs a negative accumulate of the two single-precision
10714 FP values in the source and destination registers. The result of the
10715 accumulate from the destination register is stored in the low doubleword
10716 of the destination, and the result of the source accumulate is stored in
10717 the high doubleword of the destination register.
10721 \c dst[0-31] := dst[0-31] - dst[32-63],
10722 \c dst[32-63] := src[0-31] - src[32-63].
10725 \S{insPFPNACC} \i\c{PFPNACC}: Packed Single-Precision FP Mixed Accumulate
10727 \c PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW]
10729 \c{PFPNACC} performs a positive accumulate of the two single-precision
10730 FP values in the source register and a negative accumulate of the
10731 destination register. The result of the accumulate from the destination
10732 register is stored in the low doubleword of the destination, and the
10733 result of the source accumulate is stored in the high doubleword of the
10734 destination register.
10738 \c dst[0-31] := dst[0-31] - dst[32-63],
10739 \c dst[32-63] := src[0-31] + src[32-63].
10742 \S{insPFRCP} \i\c{PFRCP}: Packed Single-Precision FP Reciprocal Approximation
10744 \c PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW]
10746 \c{PFRCP} performs a low precision estimate of the reciprocal of the
10747 low-order single-precision FP value in the source operand, storing the
10748 result in both halves of the destination register. The result is accurate
10751 For higher precision reciprocals, this instruction should be followed by
10752 two more instructions: \c{PFRCPIT1} (\k{insPFRCPIT1}) and \c{PFRCPIT2}
10753 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10754 see the AMD 3DNow! technology manual.
10757 \S{insPFRCPIT1} \i\c{PFRCPIT1}: Packed Single-Precision FP Reciprocal,
10758 First Iteration Step
10760 \c PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW]
10762 \c{PFRCPIT1} performs the first intermediate step in the calculation of
10763 the reciprocal of a single-precision FP value. The first source value
10764 (\c{mm1} is the original value, and the second source value (\c{mm2/m64}
10765 is the result of a \c{PFRCP} instruction.
10767 For the final step in a reciprocal, returning the full 24-bit accuracy
10768 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10769 more details, see the AMD 3DNow! technology manual.
10772 \S{insPFRCPIT2} \i\c{PFRCPIT2}: Packed Single-Precision FP
10773 Reciprocal/ Reciprocal Square Root, Second Iteration Step
10775 \c PFRCPIT2 mm1,mm2/m64 ; 0F 0F /r B6 [PENT,3DNOW]
10777 \c{PFRCPIT2} performs the second and final intermediate step in the
10778 calculation of a reciprocal or reciprocal square root, refining the
10779 values returned by the \c{PFRCP} and \c{PFRSQRT} instructions,
10782 The first source value (\c{mm1}) is the output of either a \c{PFRCPIT1}
10783 or a \c{PFRSQIT1} instruction, and the second source is the output of
10784 either the \c{PFRCP} or the \c{PFRSQRT} instruction. For more details,
10785 see the AMD 3DNow! technology manual.
10788 \S{insPFRSQIT1} \i\c{PFRSQIT1}: Packed Single-Precision FP Reciprocal
10789 Square Root, First Iteration Step
10791 \c PFRSQIT1 mm1,mm2/m64 ; 0F 0F /r A7 [PENT,3DNOW]
10793 \c{PFRSQIT1} performs the first intermediate step in the calculation of
10794 the reciprocal square root of a single-precision FP value. The first
10795 source value (\c{mm1} is the square of the result of a \c{PFRSQRT}
10796 instruction, and the second source value (\c{mm2/m64} is the original
10799 For the final step in a calculation, returning the full 24-bit accuracy
10800 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10801 more details, see the AMD 3DNow! technology manual.
10804 \S{insPFRSQRT} \i\c{PFRSQRT}: Packed Single-Precision FP Reciprocal
10805 Square Root Approximation
10807 \c PFRSQRT mm1,mm2/m64 ; 0F 0F /r 97 [PENT,3DNOW]
10809 \c{PFRSQRT} performs a low precision estimate of the reciprocal square
10810 root of the low-order single-precision FP value in the source operand,
10811 storing the result in both halves of the destination register. The result
10812 is accurate to 15 bits.
10814 For higher precision reciprocals, this instruction should be followed by
10815 two more instructions: \c{PFRSQIT1} (\k{insPFRSQIT1}) and \c{PFRCPIT2}
10816 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10817 see the AMD 3DNow! technology manual.
10820 \S{insPFSUB} \i\c{PFSUB}: Packed Single-Precision FP Subtract
10822 \c PFSUB mm1,mm2/m64 ; 0F 0F /r 9A [PENT,3DNOW]
10824 \c{PFSUB} subtracts the single-precision FP values in the source from
10825 those in the destination, and stores the result in the destination
10828 \c dst[0-31] := dst[0-31] - src[0-31],
10829 \c dst[32-63] := dst[32-63] - src[32-63].
10832 \S{insPFSUBR} \i\c{PFSUBR}: Packed Single-Precision FP Reverse Subtract
10834 \c PFSUBR mm1,mm2/m64 ; 0F 0F /r AA [PENT,3DNOW]
10836 \c{PFSUBR} subtracts the single-precision FP values in the destination
10837 from those in the source, and stores the result in the destination
10840 \c dst[0-31] := src[0-31] - dst[0-31],
10841 \c dst[32-63] := src[32-63] - dst[32-63].
10844 \S{insPI2FD} \i\c{PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert
10846 \c PI2FD mm1,mm2/m64 ; 0F 0F /r 0D [PENT,3DNOW]
10848 \c{PF2ID} converts two signed 32-bit integers in the source operand
10849 to single-precision FP values, using truncation of significant digits,
10850 and stores them in the destination operand.
10853 \S{insPF2IW} \i\c{PF2IW}: Packed Word Integer to Single-Precision FP Convert
10855 \c PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW]
10857 \c{PF2IW} converts two signed 16-bit integers in the source operand
10858 to single-precision FP values, and stores them in the destination
10859 operand. The input values are in the low word of each doubleword.
10862 \S{insPINSRW} \i\c{PINSRW}: Insert Word
10864 \c PINSRW mm,r16/r32/m16,imm8 ;0F C4 /r ib [KATMAI,MMX]
10865 \c PINSRW xmm,r16/r32/m16,imm8 ;66 0F C4 /r ib [WILLAMETTE,SSE2]
10867 \c{PINSRW} loads a word from a 16-bit register (or the low half of a
10868 32-bit register), or from memory, and loads it to the word position
10869 in the destination register, pointed at by the count operand (third
10870 operand). If the destination is an \c{MMX} register, the low two bits
10871 of the count byte are used, if it is an \c{XMM} register the low 3
10872 bits are used. The insertion is done in such a way that the other
10873 words from the destination register are left untouched.
10876 \S{insPMACHRIW} \i\c{PMACHRIW}: Packed Multiply and Accumulate with Rounding
10878 \c PMACHRIW mm,m64 ; 0F 5E /r [CYRIX,MMX]
10880 \c{PMACHRIW} takes two packed 16-bit integer inputs, multiplies the
10881 values in the inputs, rounds on bit 15 of each result, then adds bits
10882 15-30 of each result to the corresponding position of the \e{implied}
10883 destination register.
10885 The operation of this instruction is:
10887 \c dstI[0-15] := dstI[0-15] + (mm[0-15] *m64[0-15]
10888 \c + 0x00004000)[15-30],
10889 \c dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31]
10890 \c + 0x00004000)[15-30],
10891 \c dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47]
10892 \c + 0x00004000)[15-30],
10893 \c dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63]
10894 \c + 0x00004000)[15-30].
10896 Note that \c{PMACHRIW} cannot take a register as its second source
10900 \S{insPMADDWD} \i\c{PMADDWD}: MMX Packed Multiply and Add
10902 \c PMADDWD mm1,mm2/m64 ; 0F F5 /r [PENT,MMX]
10903 \c PMADDWD xmm1,xmm2/m128 ; 66 0F F5 /r [WILLAMETTE,SSE2]
10905 \c{PMADDWD} treats its two inputs as vectors of signed words. It
10906 multiplies corresponding elements of the two operands, giving doubleword
10907 results. These are then added together in pairs and stored in the
10908 destination operand.
10910 The operation of this instruction is:
10912 \c dst[0-31] := (dst[0-15] * src[0-15])
10913 \c + (dst[16-31] * src[16-31]);
10914 \c dst[32-63] := (dst[32-47] * src[32-47])
10915 \c + (dst[48-63] * src[48-63]);
10917 The following apply to the \c{SSE} version of the instruction:
10919 \c dst[64-95] := (dst[64-79] * src[64-79])
10920 \c + (dst[80-95] * src[80-95]);
10921 \c dst[96-127] := (dst[96-111] * src[96-111])
10922 \c + (dst[112-127] * src[112-127]).
10925 \S{insPMAGW} \i\c{PMAGW}: MMX Packed Magnitude
10927 \c PMAGW mm1,mm2/m64 ; 0F 52 /r [CYRIX,MMX]
10929 \c{PMAGW}, specific to the Cyrix MMX extensions, treats both its
10930 operands as vectors of four signed words. It compares the absolute
10931 values of the words in corresponding positions, and sets each word
10932 of the destination (first) operand to whichever of the two words in
10933 that position had the larger absolute value.
10936 \S{insPMAXSW} \i\c{PMAXSW}: Packed Signed Integer Word Maximum
10938 \c PMAXSW mm1,mm2/m64 ; 0F EE /r [KATMAI,MMX]
10939 \c PMAXSW xmm1,xmm2/m128 ; 66 0F EE /r [WILLAMETTE,SSE2]
10941 \c{PMAXSW} compares each pair of words in the two source operands, and
10942 for each pair it stores the maximum value in the destination register.
10945 \S{insPMAXUB} \i\c{PMAXUB}: Packed Unsigned Integer Byte Maximum
10947 \c PMAXUB mm1,mm2/m64 ; 0F DE /r [KATMAI,MMX]
10948 \c PMAXUB xmm1,xmm2/m128 ; 66 0F DE /r [WILLAMETTE,SSE2]
10950 \c{PMAXUB} compares each pair of bytes in the two source operands, and
10951 for each pair it stores the maximum value in the destination register.
10954 \S{insPMINSW} \i\c{PMINSW}: Packed Signed Integer Word Minimum
10956 \c PMINSW mm1,mm2/m64 ; 0F EA /r [KATMAI,MMX]
10957 \c PMINSW xmm1,xmm2/m128 ; 66 0F EA /r [WILLAMETTE,SSE2]
10959 \c{PMINSW} compares each pair of words in the two source operands, and
10960 for each pair it stores the minimum value in the destination register.
10963 \S{insPMINUB} \i\c{PMINUB}: Packed Unsigned Integer Byte Minimum
10965 \c PMINUB mm1,mm2/m64 ; 0F DA /r [KATMAI,MMX]
10966 \c PMINUB xmm1,xmm2/m128 ; 66 0F DA /r [WILLAMETTE,SSE2]
10968 \c{PMINUB} compares each pair of bytes in the two source operands, and
10969 for each pair it stores the minimum value in the destination register.
10972 \S{insPMOVMSKB} \i\c{PMOVMSKB}: Move Byte Mask To Integer
10974 \c PMOVMSKB reg32,mm ; 0F D7 /r [KATMAI,MMX]
10975 \c PMOVMSKB reg32,xmm ; 66 0F D7 /r [WILLAMETTE,SSE2]
10977 \c{PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most
10978 significant bits of each byte of source operand (8-bits for an
10979 \c{MMX} register, 16-bits for an \c{XMM} register).
10982 \S{insPMULHRW} \i\c{PMULHRWC}, \i\c{PMULHRIW}: Multiply Packed 16-bit Integers
10983 With Rounding, and Store High Word
10985 \c PMULHRWC mm1,mm2/m64 ; 0F 59 /r [CYRIX,MMX]
10986 \c PMULHRIW mm1,mm2/m64 ; 0F 5D /r [CYRIX,MMX]
10988 These instructions take two packed 16-bit integer inputs, multiply the
10989 values in the inputs, round on bit 15 of each result, then store bits
10990 15-30 of each result to the corresponding position of the destination
10993 \b For \c{PMULHRWC}, the destination is the first source operand.
10995 \b For \c{PMULHRIW}, the destination is an implied register (worked out
10996 as described for \c{PADDSIW} (\k{insPADDSIW})).
10998 The operation of this instruction is:
11000 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00004000)[15-30]
11001 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30]
11002 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30]
11003 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30]
11005 See also \c{PMULHRWA} (\k{insPMULHRWA}) for a 3DNow! version of this
11009 \S{insPMULHRWA} \i\c{PMULHRWA}: Multiply Packed 16-bit Integers
11010 With Rounding, and Store High Word
11012 \c PMULHRWA mm1,mm2/m64 ; 0F 0F /r B7 [PENT,3DNOW]
11014 \c{PMULHRWA} takes two packed 16-bit integer inputs, multiplies
11015 the values in the inputs, rounds on bit 16 of each result, then
11016 stores bits 16-31 of each result to the corresponding position
11017 of the destination register.
11019 The operation of this instruction is:
11021 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00008000)[16-31];
11022 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31];
11023 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31];
11024 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31].
11026 See also \c{PMULHRWC} (\k{insPMULHRW}) for a Cyrix version of this
11030 \S{insPMULHUW} \i\c{PMULHUW}: Multiply Packed 16-bit Integers,
11031 and Store High Word
11033 \c PMULHUW mm1,mm2/m64 ; 0F E4 /r [KATMAI,MMX]
11034 \c PMULHUW xmm1,xmm2/m128 ; 66 0F E4 /r [WILLAMETTE,SSE2]
11036 \c{PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies
11037 the values in the inputs, then stores bits 16-31 of each result to the
11038 corresponding position of the destination register.
11041 \S{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: Multiply Packed 16-bit Integers,
11044 \c PMULHW mm1,mm2/m64 ; 0F E5 /r [PENT,MMX]
11045 \c PMULLW mm1,mm2/m64 ; 0F D5 /r [PENT,MMX]
11047 \c PMULHW xmm1,xmm2/m128 ; 66 0F E5 /r [WILLAMETTE,SSE2]
11048 \c PMULLW xmm1,xmm2/m128 ; 66 0F D5 /r [WILLAMETTE,SSE2]
11050 \c{PMULxW} takes two packed unsigned 16-bit integer inputs, and
11051 multiplies the values in the inputs, forming doubleword results.
11053 \b \c{PMULHW} then stores the top 16 bits of each doubleword in the
11054 destination (first) operand;
11056 \b \c{PMULLW} stores the bottom 16 bits of each doubleword in the
11057 destination operand.
11060 \S{insPMULUDQ} \i\c{PMULUDQ}: Multiply Packed Unsigned
11061 32-bit Integers, and Store.
11063 \c PMULUDQ mm1,mm2/m64 ; 0F F4 /r [WILLAMETTE,SSE2]
11064 \c PMULUDQ xmm1,xmm2/m128 ; 66 0F F4 /r [WILLAMETTE,SSE2]
11066 \c{PMULUDQ} takes two packed unsigned 32-bit integer inputs, and
11067 multiplies the values in the inputs, forming quadword results. The
11068 source is either an unsigned doubleword in the low doubleword of a
11069 64-bit operand, or it's two unsigned doublewords in the first and
11070 third doublewords of a 128-bit operand. This produces either one or
11071 two 64-bit results, which are stored in the respective quadword
11072 locations of the destination register.
11076 \c dst[0-63] := dst[0-31] * src[0-31];
11077 \c dst[64-127] := dst[64-95] * src[64-95].
11080 \S{insPMVccZB} \i\c{PMVccZB}: MMX Packed Conditional Move
11082 \c PMVZB mmxreg,mem64 ; 0F 58 /r [CYRIX,MMX]
11083 \c PMVNZB mmxreg,mem64 ; 0F 5A /r [CYRIX,MMX]
11084 \c PMVLZB mmxreg,mem64 ; 0F 5B /r [CYRIX,MMX]
11085 \c PMVGEZB mmxreg,mem64 ; 0F 5C /r [CYRIX,MMX]
11087 These instructions, specific to the Cyrix MMX extensions, perform
11088 parallel conditional moves. The two input operands are treated as
11089 vectors of eight bytes. Each byte of the destination (first) operand
11090 is either written from the corresponding byte of the source (second)
11091 operand, or left alone, depending on the value of the byte in the
11092 \e{implied} operand (specified in the same way as \c{PADDSIW}, in
11095 \b \c{PMVZB} performs each move if the corresponding byte in the
11096 implied operand is zero;
11098 \b \c{PMVNZB} moves if the byte is non-zero;
11100 \b \c{PMVLZB} moves if the byte is less than zero;
11102 \b \c{PMVGEZB} moves if the byte is greater than or equal to zero.
11104 Note that these instructions cannot take a register as their second
11108 \S{insPOP} \i\c{POP}: Pop Data from Stack
11110 \c POP reg16 ; o16 58+r [8086]
11111 \c POP reg32 ; o32 58+r [386]
11113 \c POP r/m16 ; o16 8F /0 [8086]
11114 \c POP r/m32 ; o32 8F /0 [386]
11116 \c POP CS ; 0F [8086,UNDOC]
11117 \c POP DS ; 1F [8086]
11118 \c POP ES ; 07 [8086]
11119 \c POP SS ; 17 [8086]
11120 \c POP FS ; 0F A1 [386]
11121 \c POP GS ; 0F A9 [386]
11123 \c{POP} loads a value from the stack (from \c{[SS:SP]} or
11124 \c{[SS:ESP]}) and then increments the stack pointer.
11126 The address-size attribute of the instruction determines whether
11127 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11128 override the default given by the \c{BITS} setting, you can use an
11129 \i\c{a16} or \i\c{a32} prefix.
11131 The operand-size attribute of the instruction determines whether the
11132 stack pointer is incremented by 2 or 4: this means that segment
11133 register pops in \c{BITS 32} mode will pop 4 bytes off the stack and
11134 discard the upper two of them. If you need to override that, you can
11135 use an \i\c{o16} or \i\c{o32} prefix.
11137 The above opcode listings give two forms for general-purpose
11138 register pop instructions: for example, \c{POP BX} has the two forms
11139 \c{5B} and \c{8F C3}. NASM will always generate the shorter form
11140 when given \c{POP BX}. NDISASM will disassemble both.
11142 \c{POP CS} is not a documented instruction, and is not supported on
11143 any processor above the 8086 (since they use \c{0Fh} as an opcode
11144 prefix for instruction set extensions). However, at least some 8086
11145 processors do support it, and so NASM generates it for completeness.
11148 \S{insPOPA} \i\c{POPAx}: Pop All General-Purpose Registers
11151 \c POPAW ; o16 61 [186]
11152 \c POPAD ; o32 61 [386]
11154 \b \c{POPAW} pops a word from the stack into each of, successively,
11155 \c{DI}, \c{SI}, \c{BP}, nothing (it discards a word from the stack
11156 which was a placeholder for \c{SP}), \c{BX}, \c{DX}, \c{CX} and
11157 \c{AX}. It is intended to reverse the operation of \c{PUSHAW} (see
11158 \k{insPUSHA}), but it ignores the value for \c{SP} that was pushed
11159 on the stack by \c{PUSHAW}.
11161 \b \c{POPAD} pops twice as much data, and places the results in
11162 \c{EDI}, \c{ESI}, \c{EBP}, nothing (placeholder for \c{ESP}),
11163 \c{EBX}, \c{EDX}, \c{ECX} and \c{EAX}. It reverses the operation of
11166 \c{POPA} is an alias mnemonic for either \c{POPAW} or \c{POPAD},
11167 depending on the current \c{BITS} setting.
11169 Note that the registers are popped in reverse order of their numeric
11170 values in opcodes (see \k{iref-rv}).
11173 \S{insPOPF} \i\c{POPFx}: Pop Flags Register
11175 \c POPF ; 9D [8086]
11176 \c POPFW ; o16 9D [8086]
11177 \c POPFD ; o32 9D [386]
11179 \b \c{POPFW} pops a word from the stack and stores it in the bottom 16
11180 bits of the flags register (or the whole flags register, on
11181 processors below a 386).
11183 \b \c{POPFD} pops a doubleword and stores it in the entire flags register.
11185 \c{POPF} is an alias mnemonic for either \c{POPFW} or \c{POPFD},
11186 depending on the current \c{BITS} setting.
11188 See also \c{PUSHF} (\k{insPUSHF}).
11191 \S{insPOR} \i\c{POR}: MMX Bitwise OR
11193 \c POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX]
11194 \c POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2]
11196 \c{POR} performs a bitwise OR operation between its two operands
11197 (i.e. each bit of the result is 1 if and only if at least one of the
11198 corresponding bits of the two inputs was 1), and stores the result
11199 in the destination (first) operand.
11202 \S{insPREFETCH} \i\c{PREFETCH}: Prefetch Data Into Caches
11204 \c PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW]
11205 \c PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW]
11207 \c{PREFETCH} and \c{PREFETCHW} fetch the line of data from memory that
11208 contains the specified byte. \c{PREFETCHW} performs differently on the
11209 Athlon to earlier processors.
11211 For more details, see the 3DNow! Technology Manual.
11214 \S{insPREFETCHh} \i\c{PREFETCHh}: Prefetch Data Into Caches
11215 \I\c{PREFETCHNTA} \I\c{PREFETCHT0} \I\c{PREFETCHT1} \I\c{PREFETCHT2}
11217 \c PREFETCHNTA m8 ; 0F 18 /0 [KATMAI]
11218 \c PREFETCHT0 m8 ; 0F 18 /1 [KATMAI]
11219 \c PREFETCHT1 m8 ; 0F 18 /2 [KATMAI]
11220 \c PREFETCHT2 m8 ; 0F 18 /3 [KATMAI]
11222 The \c{PREFETCHh} instructions fetch the line of data from memory
11223 that contains the specified byte. It is placed in the cache
11224 according to rules specified by locality hints \c{h}:
11228 \b \c{T0} (temporal data) - prefetch data into all levels of the
11231 \b \c{T1} (temporal data with respect to first level cache) -
11232 prefetch data into level 2 cache and higher.
11234 \b \c{T2} (temporal data with respect to second level cache) -
11235 prefetch data into level 2 cache and higher.
11237 \b \c{NTA} (non-temporal data with respect to all cache levels) -
11238 prefetch data into non-temporal cache structure and into a
11239 location close to the processor, minimizing cache pollution.
11241 Note that this group of instructions doesn't provide a guarantee
11242 that the data will be in the cache when it is needed. For more
11243 details, see the Intel IA32 Software Developer Manual, Volume 2.
11246 \S{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences
11248 \c PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX]
11249 \c PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2]
11251 \c{PSADBW} The PSADBW instruction computes the absolute value of the
11252 difference of the packed unsigned bytes in the two source operands.
11253 These differences are then summed to produce a word result in the lower
11254 16-bit field of the destination register; the rest of the register is
11255 cleared. The destination operand is an \c{MMX} or an \c{XMM} register.
11256 The source operand can either be a register or a memory operand.
11259 \S{insPSHUFD} \i\c{PSHUFD}: Shuffle Packed Doublewords
11261 \c PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2]
11263 \c{PSHUFD} shuffles the doublewords in the source (second) operand
11264 according to the encoding specified by imm8, and stores the result
11265 in the destination (first) operand.
11267 Bits 0 and 1 of imm8 encode the source position of the doubleword to
11268 be copied to position 0 in the destination operand. Bits 2 and 3
11269 encode for position 1, bits 4 and 5 encode for position 2, and bits
11270 6 and 7 encode for position 3. For example, an encoding of 10 in
11271 bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of
11272 the source operand will be copied to bits 0-31 of the destination.
11275 \S{insPSHUFHW} \i\c{PSHUFHW}: Shuffle Packed High Words
11277 \c PSHUFHW xmm1,xmm2/m128,imm8 ; F3 0F 70 /r ib [WILLAMETTE,SSE2]
11279 \c{PSHUFW} shuffles the words in the high quadword of the source
11280 (second) operand according to the encoding specified by imm8, and
11281 stores the result in the high quadword of the destination (first)
11284 The operation of this instruction is similar to the \c{PSHUFW}
11285 instruction, except that the source and destination are the top
11286 quadword of a 128-bit operand, instead of being 64-bit operands.
11287 The low quadword is copied from the source to the destination
11288 without any changes.
11291 \S{insPSHUFLW} \i\c{PSHUFLW}: Shuffle Packed Low Words
11293 \c PSHUFLW xmm1,xmm2/m128,imm8 ; F2 0F 70 /r ib [WILLAMETTE,SSE2]
11295 \c{PSHUFLW} shuffles the words in the low quadword of the source
11296 (second) operand according to the encoding specified by imm8, and
11297 stores the result in the low quadword of the destination (first)
11300 The operation of this instruction is similar to the \c{PSHUFW}
11301 instruction, except that the source and destination are the low
11302 quadword of a 128-bit operand, instead of being 64-bit operands.
11303 The high quadword is copied from the source to the destination
11304 without any changes.
11307 \S{insPSHUFW} \i\c{PSHUFW}: Shuffle Packed Words
11309 \c PSHUFW mm1,mm2/m64,imm8 ; 0F 70 /r ib [KATMAI,MMX]
11311 \c{PSHUFW} shuffles the words in the source (second) operand
11312 according to the encoding specified by imm8, and stores the result
11313 in the destination (first) operand.
11315 Bits 0 and 1 of imm8 encode the source position of the word to be
11316 copied to position 0 in the destination operand. Bits 2 and 3 encode
11317 for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7
11318 encode for position 3. For example, an encoding of 10 in bits 0 and 1
11319 of imm8 indicates that the word at bits 32-47 of the source operand
11320 will be copied to bits 0-15 of the destination.
11323 \S{insPSLLD} \i\c{PSLLx}: Packed Data Bit Shift Left Logical
11325 \c PSLLW mm1,mm2/m64 ; 0F F1 /r [PENT,MMX]
11326 \c PSLLW mm,imm8 ; 0F 71 /6 ib [PENT,MMX]
11328 \c PSLLW xmm1,xmm2/m128 ; 66 0F F1 /r [WILLAMETTE,SSE2]
11329 \c PSLLW xmm,imm8 ; 66 0F 71 /6 ib [WILLAMETTE,SSE2]
11331 \c PSLLD mm1,mm2/m64 ; 0F F2 /r [PENT,MMX]
11332 \c PSLLD mm,imm8 ; 0F 72 /6 ib [PENT,MMX]
11334 \c PSLLD xmm1,xmm2/m128 ; 66 0F F2 /r [WILLAMETTE,SSE2]
11335 \c PSLLD xmm,imm8 ; 66 0F 72 /6 ib [WILLAMETTE,SSE2]
11337 \c PSLLQ mm1,mm2/m64 ; 0F F3 /r [PENT,MMX]
11338 \c PSLLQ mm,imm8 ; 0F 73 /6 ib [PENT,MMX]
11340 \c PSLLQ xmm1,xmm2/m128 ; 66 0F F3 /r [WILLAMETTE,SSE2]
11341 \c PSLLQ xmm,imm8 ; 66 0F 73 /6 ib [WILLAMETTE,SSE2]
11343 \c PSLLDQ xmm1,imm8 ; 66 0F 73 /7 ib [PENT,MMX]
11345 \c{PSLLx} performs logical left shifts of the data elements in the
11346 destination (first) operand, moving each bit in the separate elements
11347 left by the number of bits specified in the source (second) operand,
11348 clearing the low-order bits as they are vacated.
11350 \b \c{PSLLW} shifts word sized elements.
11352 \b \c{PSLLD} shifts doubleword sized elements.
11354 \b \c{PSLLQ} shifts quadword sized elements.
11356 \b \c{PSLLDQ} shifts double quadword sized elements.
11359 \S{insPSRAD} \i\c{PSRAx}: Packed Data Bit Shift Right Arithmetic
11361 \c PSRAW mm1,mm2/m64 ; 0F E1 /r [PENT,MMX]
11362 \c PSRAW mm,imm8 ; 0F 71 /4 ib [PENT,MMX]
11364 \c PSRAW xmm1,xmm2/m128 ; 66 0F E1 /r [WILLAMETTE,SSE2]
11365 \c PSRAW xmm,imm8 ; 66 0F 71 /4 ib [WILLAMETTE,SSE2]
11367 \c PSRAD mm1,mm2/m64 ; 0F E2 /r [PENT,MMX]
11368 \c PSRAD mm,imm8 ; 0F 72 /4 ib [PENT,MMX]
11370 \c PSRAD xmm1,xmm2/m128 ; 66 0F E2 /r [WILLAMETTE,SSE2]
11371 \c PSRAD xmm,imm8 ; 66 0F 72 /4 ib [WILLAMETTE,SSE2]
11373 \c{PSRAx} performs arithmetic right shifts of the data elements in the
11374 destination (first) operand, moving each bit in the separate elements
11375 right by the number of bits specified in the source (second) operand,
11376 setting the high-order bits to the value of the original sign bit.
11378 \b \c{PSRAW} shifts word sized elements.
11380 \b \c{PSRAD} shifts doubleword sized elements.
11383 \S{insPSRLD} \i\c{PSRLx}: Packed Data Bit Shift Right Logical
11385 \c PSRLW mm1,mm2/m64 ; 0F D1 /r [PENT,MMX]
11386 \c PSRLW mm,imm8 ; 0F 71 /2 ib [PENT,MMX]
11388 \c PSRLW xmm1,xmm2/m128 ; 66 0F D1 /r [WILLAMETTE,SSE2]
11389 \c PSRLW xmm,imm8 ; 66 0F 71 /2 ib [WILLAMETTE,SSE2]
11391 \c PSRLD mm1,mm2/m64 ; 0F D2 /r [PENT,MMX]
11392 \c PSRLD mm,imm8 ; 0F 72 /2 ib [PENT,MMX]
11394 \c PSRLD xmm1,xmm2/m128 ; 66 0F D2 /r [WILLAMETTE,SSE2]
11395 \c PSRLD xmm,imm8 ; 66 0F 72 /2 ib [WILLAMETTE,SSE2]
11397 \c PSRLQ mm1,mm2/m64 ; 0F D3 /r [PENT,MMX]
11398 \c PSRLQ mm,imm8 ; 0F 73 /2 ib [PENT,MMX]
11400 \c PSRLQ xmm1,xmm2/m128 ; 66 0F D3 /r [WILLAMETTE,SSE2]
11401 \c PSRLQ xmm,imm8 ; 66 0F 73 /2 ib [WILLAMETTE,SSE2]
11403 \c PSRLDQ xmm1,imm8 ; 66 0F 73 /3 ib [WILLAMETTE,SSE2]
11405 \c{PSRLx} performs logical right shifts of the data elements in the
11406 destination (first) operand, moving each bit in the separate elements
11407 right by the number of bits specified in the source (second) operand,
11408 clearing the high-order bits as they are vacated.
11410 \b \c{PSRLW} shifts word sized elements.
11412 \b \c{PSRLD} shifts doubleword sized elements.
11414 \b \c{PSRLQ} shifts quadword sized elements.
11416 \b \c{PSRLDQ} shifts double quadword sized elements.
11419 \S{insPSUBB} \i\c{PSUBx}: Subtract Packed Integers
11421 \c PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX]
11422 \c PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX]
11423 \c PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX]
11424 \c PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2]
11426 \c PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2]
11427 \c PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2]
11428 \c PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2]
11429 \c PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2]
11431 \c{PSUBx} subtracts packed integers in the source operand from those
11432 in the destination operand. It doesn't differentiate between signed
11433 and unsigned integers, and doesn't set any of the flags.
11435 \b \c{PSUBB} operates on byte sized elements.
11437 \b \c{PSUBW} operates on word sized elements.
11439 \b \c{PSUBD} operates on doubleword sized elements.
11441 \b \c{PSUBQ} operates on quadword sized elements.
11444 \S{insPSUBSB} \i\c{PSUBSxx}, \i\c{PSUBUSx}: Subtract Packed Integers With Saturation
11446 \c PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX]
11447 \c PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX]
11449 \c PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2]
11450 \c PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2]
11452 \c PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX]
11453 \c PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX]
11455 \c PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2]
11456 \c PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2]
11458 \c{PSUBSx} and \c{PSUBUSx} subtracts packed integers in the source
11459 operand from those in the destination operand, and use saturation for
11460 results that are outside the range supported by the destination operand.
11462 \b \c{PSUBSB} operates on signed bytes, and uses signed saturation on the
11465 \b \c{PSUBSW} operates on signed words, and uses signed saturation on the
11468 \b \c{PSUBUSB} operates on unsigned bytes, and uses signed saturation on
11471 \b \c{PSUBUSW} operates on unsigned words, and uses signed saturation on
11475 \S{insPSUBSIW} \i\c{PSUBSIW}: MMX Packed Subtract with Saturation to
11476 Implied Destination
11478 \c PSUBSIW mm1,mm2/m64 ; 0F 55 /r [CYRIX,MMX]
11480 \c{PSUBSIW}, specific to the Cyrix extensions to the MMX instruction
11481 set, performs the same function as \c{PSUBSW}, except that the
11482 result is not placed in the register specified by the first operand,
11483 but instead in the implied destination register, specified as for
11484 \c{PADDSIW} (\k{insPADDSIW}).
11487 \S{insPSWAPD} \i\c{PSWAPD}: Swap Packed Data
11490 \c PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW]
11492 \c{PSWAPD} swaps the packed doublewords in the source operand, and
11493 stores the result in the destination operand.
11495 In the \c{K6-2} and \c{K6-III} processors, this opcode uses the
11496 mnemonic \c{PSWAPW}, and it swaps the order of words when copying
11497 from the source to the destination.
11499 The operation in the \c{K6-2} and \c{K6-III} processors is
11501 \c dst[0-15] = src[48-63];
11502 \c dst[16-31] = src[32-47];
11503 \c dst[32-47] = src[16-31];
11504 \c dst[48-63] = src[0-15].
11506 The operation in the \c{K6-x+}, \c{ATHLON} and later processors is:
11508 \c dst[0-31] = src[32-63];
11509 \c dst[32-63] = src[0-31].
11512 \S{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack and Interleave Data
11514 \c PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX]
11515 \c PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX]
11516 \c PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX]
11518 \c PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2]
11519 \c PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2]
11520 \c PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2]
11521 \c PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2]
11523 \c PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX]
11524 \c PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX]
11525 \c PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX]
11527 \c PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2]
11528 \c PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2]
11529 \c PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2]
11530 \c PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2]
11532 \c{PUNPCKxx} all treat their operands as vectors, and produce a new
11533 vector generated by interleaving elements from the two inputs. The
11534 \c{PUNPCKHxx} instructions start by throwing away the bottom half of
11535 each input operand, and the \c{PUNPCKLxx} instructions throw away
11538 The remaining elements, are then interleaved into the destination,
11539 alternating elements from the second (source) operand and the first
11540 (destination) operand: so the leftmost part of each element in the
11541 result always comes from the second operand, and the rightmost from
11544 \b \c{PUNPCKxBW} works a byte at a time, producing word sized output
11547 \b \c{PUNPCKxWD} works a word at a time, producing doubleword sized
11550 \b \c{PUNPCKxDQ} works a doubleword at a time, producing quadword sized
11553 \b \c{PUNPCKxQDQ} works a quadword at a time, producing double quadword
11554 sized output elements.
11556 So, for example, for \c{MMX} operands, if the first operand held
11557 \c{0x7A6A5A4A3A2A1A0A} and the second held \c{0x7B6B5B4B3B2B1B0B},
11560 \b \c{PUNPCKHBW} would return \c{0x7B7A6B6A5B5A4B4A}.
11562 \b \c{PUNPCKHWD} would return \c{0x7B6B7A6A5B4B5A4A}.
11564 \b \c{PUNPCKHDQ} would return \c{0x7B6B5B4B7A6A5A4A}.
11566 \b \c{PUNPCKLBW} would return \c{0x3B3A2B2A1B1A0B0A}.
11568 \b \c{PUNPCKLWD} would return \c{0x3B2B3A2A1B0B1A0A}.
11570 \b \c{PUNPCKLDQ} would return \c{0x3B2B1B0B3A2A1A0A}.
11573 \S{insPUSH} \i\c{PUSH}: Push Data on Stack
11575 \c PUSH reg16 ; o16 50+r [8086]
11576 \c PUSH reg32 ; o32 50+r [386]
11578 \c PUSH r/m16 ; o16 FF /6 [8086]
11579 \c PUSH r/m32 ; o32 FF /6 [386]
11581 \c PUSH CS ; 0E [8086]
11582 \c PUSH DS ; 1E [8086]
11583 \c PUSH ES ; 06 [8086]
11584 \c PUSH SS ; 16 [8086]
11585 \c PUSH FS ; 0F A0 [386]
11586 \c PUSH GS ; 0F A8 [386]
11588 \c PUSH imm8 ; 6A ib [186]
11589 \c PUSH imm16 ; o16 68 iw [186]
11590 \c PUSH imm32 ; o32 68 id [386]
11592 \c{PUSH} decrements the stack pointer (\c{SP} or \c{ESP}) by 2 or 4,
11593 and then stores the given value at \c{[SS:SP]} or \c{[SS:ESP]}.
11595 The address-size attribute of the instruction determines whether
11596 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11597 override the default given by the \c{BITS} setting, you can use an
11598 \i\c{a16} or \i\c{a32} prefix.
11600 The operand-size attribute of the instruction determines whether the
11601 stack pointer is decremented by 2 or 4: this means that segment
11602 register pushes in \c{BITS 32} mode will push 4 bytes on the stack,
11603 of which the upper two are undefined. If you need to override that,
11604 you can use an \i\c{o16} or \i\c{o32} prefix.
11606 The above opcode listings give two forms for general-purpose
11607 \i{register push} instructions: for example, \c{PUSH BX} has the two
11608 forms \c{53} and \c{FF F3}. NASM will always generate the shorter
11609 form when given \c{PUSH BX}. NDISASM will disassemble both.
11611 Unlike the undocumented and barely supported \c{POP CS}, \c{PUSH CS}
11612 is a perfectly valid and sensible instruction, supported on all
11615 The instruction \c{PUSH SP} may be used to distinguish an 8086 from
11616 later processors: on an 8086, the value of \c{SP} stored is the
11617 value it has \e{after} the push instruction, whereas on later
11618 processors it is the value \e{before} the push instruction.
11621 \S{insPUSHA} \i\c{PUSHAx}: Push All General-Purpose Registers
11623 \c PUSHA ; 60 [186]
11624 \c PUSHAD ; o32 60 [386]
11625 \c PUSHAW ; o16 60 [186]
11627 \c{PUSHAW} pushes, in succession, \c{AX}, \c{CX}, \c{DX}, \c{BX},
11628 \c{SP}, \c{BP}, \c{SI} and \c{DI} on the stack, decrementing the
11629 stack pointer by a total of 16.
11631 \c{PUSHAD} pushes, in succession, \c{EAX}, \c{ECX}, \c{EDX},
11632 \c{EBX}, \c{ESP}, \c{EBP}, \c{ESI} and \c{EDI} on the stack,
11633 decrementing the stack pointer by a total of 32.
11635 In both cases, the value of \c{SP} or \c{ESP} pushed is its
11636 \e{original} value, as it had before the instruction was executed.
11638 \c{PUSHA} is an alias mnemonic for either \c{PUSHAW} or \c{PUSHAD},
11639 depending on the current \c{BITS} setting.
11641 Note that the registers are pushed in order of their numeric values
11642 in opcodes (see \k{iref-rv}).
11644 See also \c{POPA} (\k{insPOPA}).
11647 \S{insPUSHF} \i\c{PUSHFx}: Push Flags Register
11649 \c PUSHF ; 9C [8086]
11650 \c PUSHFD ; o32 9C [386]
11651 \c PUSHFW ; o16 9C [8086]
11653 \b \c{PUSHFW} pops a word from the stack and stores it in the
11654 bottom 16 bits of the flags register (or the whole flags register,
11655 on processors below a 386).
11657 \b \c{PUSHFD} pops a doubleword and stores it in the entire flags
11660 \c{PUSHF} is an alias mnemonic for either \c{PUSHFW} or \c{PUSHFD},
11661 depending on the current \c{BITS} setting.
11663 See also \c{POPF} (\k{insPOPF}).
11666 \S{insPXOR} \i\c{PXOR}: MMX Bitwise XOR
11668 \c PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX]
11669 \c PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2]
11671 \c{PXOR} performs a bitwise XOR operation between its two operands
11672 (i.e. each bit of the result is 1 if and only if exactly one of the
11673 corresponding bits of the two inputs was 1), and stores the result
11674 in the destination (first) operand.
11677 \S{insRCL} \i\c{RCL}, \i\c{RCR}: Bitwise Rotate through Carry Bit
11679 \c RCL r/m8,1 ; D0 /2 [8086]
11680 \c RCL r/m8,CL ; D2 /2 [8086]
11681 \c RCL r/m8,imm8 ; C0 /2 ib [186]
11682 \c RCL r/m16,1 ; o16 D1 /2 [8086]
11683 \c RCL r/m16,CL ; o16 D3 /2 [8086]
11684 \c RCL r/m16,imm8 ; o16 C1 /2 ib [186]
11685 \c RCL r/m32,1 ; o32 D1 /2 [386]
11686 \c RCL r/m32,CL ; o32 D3 /2 [386]
11687 \c RCL r/m32,imm8 ; o32 C1 /2 ib [386]
11689 \c RCR r/m8,1 ; D0 /3 [8086]
11690 \c RCR r/m8,CL ; D2 /3 [8086]
11691 \c RCR r/m8,imm8 ; C0 /3 ib [186]
11692 \c RCR r/m16,1 ; o16 D1 /3 [8086]
11693 \c RCR r/m16,CL ; o16 D3 /3 [8086]
11694 \c RCR r/m16,imm8 ; o16 C1 /3 ib [186]
11695 \c RCR r/m32,1 ; o32 D1 /3 [386]
11696 \c RCR r/m32,CL ; o32 D3 /3 [386]
11697 \c RCR r/m32,imm8 ; o32 C1 /3 ib [386]
11699 \c{RCL} and \c{RCR} perform a 9-bit, 17-bit or 33-bit bitwise
11700 rotation operation, involving the given source/destination (first)
11701 operand and the carry bit. Thus, for example, in the operation
11702 \c{RCL AL,1}, a 9-bit rotation is performed in which \c{AL} is
11703 shifted left by 1, the top bit of \c{AL} moves into the carry flag,
11704 and the original value of the carry flag is placed in the low bit of
11707 The number of bits to rotate by is given by the second operand. Only
11708 the bottom five bits of the rotation count are considered by
11709 processors above the 8086.
11711 You can force the longer (286 and upwards, beginning with a \c{C1}
11712 byte) form of \c{RCL foo,1} by using a \c{BYTE} prefix: \c{RCL
11713 foo,BYTE 1}. Similarly with \c{RCR}.
11716 \S{insRCPPS} \i\c{RCPPS}: Packed Single-Precision FP Reciprocal
11718 \c RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE]
11720 \c{RCPPS} returns an approximation of the reciprocal of the packed
11721 single-precision FP values from xmm2/m128. The maximum error for this
11722 approximation is: |Error| <= 1.5 x 2^-12
11725 \S{insRCPSS} \i\c{RCPSS}: Scalar Single-Precision FP Reciprocal
11727 \c RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE]
11729 \c{RCPSS} returns an approximation of the reciprocal of the lower
11730 single-precision FP value from xmm2/m32; the upper three fields are
11731 passed through from xmm1. The maximum error for this approximation is:
11732 |Error| <= 1.5 x 2^-12
11735 \S{insRDMSR} \i\c{RDMSR}: Read Model-Specific Registers
11737 \c RDMSR ; 0F 32 [PENT,PRIV]
11739 \c{RDMSR} reads the processor Model-Specific Register (MSR) whose
11740 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11741 See also \c{WRMSR} (\k{insWRMSR}).
11744 \S{insRDPMC} \i\c{RDPMC}: Read Performance-Monitoring Counters
11746 \c RDPMC ; 0F 33 [P6]
11748 \c{RDPMC} reads the processor performance-monitoring counter whose
11749 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11751 This instruction is available on P6 and later processors and on MMX
11755 \S{insRDSHR} \i\c{RDSHR}: Read SMM Header Pointer Register
11757 \c RDSHR r/m32 ; 0F 36 /0 [386,CYRIX,SMM]
11759 \c{RDSHR} reads the contents of the SMM header pointer register and
11760 saves it to the destination operand, which can be either a 32 bit
11761 memory location or a 32 bit register.
11763 See also \c{WRSHR} (\k{insWRSHR}).
11766 \S{insRDTSC} \i\c{RDTSC}: Read Time-Stamp Counter
11768 \c RDTSC ; 0F 31 [PENT]
11770 \c{RDTSC} reads the processor's time-stamp counter into \c{EDX:EAX}.
11773 \S{insRET} \i\c{RET}, \i\c{RETF}, \i\c{RETN}: Return from Procedure Call
11776 \c RET imm16 ; C2 iw [8086]
11778 \c RETF ; CB [8086]
11779 \c RETF imm16 ; CA iw [8086]
11781 \c RETN ; C3 [8086]
11782 \c RETN imm16 ; C2 iw [8086]
11784 \b \c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from
11785 the stack and transfer control to the new address. Optionally, if a
11786 numeric second operand is provided, they increment the stack pointer
11787 by a further \c{imm16} bytes after popping the return address.
11789 \b \c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it
11790 then pops \c{CS}, and \e{then} increments the stack pointer by the
11791 optional argument if present.
11794 \S{insROL} \i\c{ROL}, \i\c{ROR}: Bitwise Rotate
11796 \c ROL r/m8,1 ; D0 /0 [8086]
11797 \c ROL r/m8,CL ; D2 /0 [8086]
11798 \c ROL r/m8,imm8 ; C0 /0 ib [186]
11799 \c ROL r/m16,1 ; o16 D1 /0 [8086]
11800 \c ROL r/m16,CL ; o16 D3 /0 [8086]
11801 \c ROL r/m16,imm8 ; o16 C1 /0 ib [186]
11802 \c ROL r/m32,1 ; o32 D1 /0 [386]
11803 \c ROL r/m32,CL ; o32 D3 /0 [386]
11804 \c ROL r/m32,imm8 ; o32 C1 /0 ib [386]
11806 \c ROR r/m8,1 ; D0 /1 [8086]
11807 \c ROR r/m8,CL ; D2 /1 [8086]
11808 \c ROR r/m8,imm8 ; C0 /1 ib [186]
11809 \c ROR r/m16,1 ; o16 D1 /1 [8086]
11810 \c ROR r/m16,CL ; o16 D3 /1 [8086]
11811 \c ROR r/m16,imm8 ; o16 C1 /1 ib [186]
11812 \c ROR r/m32,1 ; o32 D1 /1 [386]
11813 \c ROR r/m32,CL ; o32 D3 /1 [386]
11814 \c ROR r/m32,imm8 ; o32 C1 /1 ib [386]
11816 \c{ROL} and \c{ROR} perform a bitwise rotation operation on the given
11817 source/destination (first) operand. Thus, for example, in the
11818 operation \c{ROL AL,1}, an 8-bit rotation is performed in which
11819 \c{AL} is shifted left by 1 and the original top bit of \c{AL} moves
11820 round into the low bit.
11822 The number of bits to rotate by is given by the second operand. Only
11823 the bottom five bits of the rotation count are considered by processors
11826 You can force the longer (286 and upwards, beginning with a \c{C1}
11827 byte) form of \c{ROL foo,1} by using a \c{BYTE} prefix: \c{ROL
11828 foo,BYTE 1}. Similarly with \c{ROR}.
11831 \S{insRSDC} \i\c{RSDC}: Restore Segment Register and Descriptor
11833 \c RSDC segreg,m80 ; 0F 79 /r [486,CYRIX,SMM]
11835 \c{RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80,
11836 and sets up its descriptor.
11839 \S{insRSLDT} \i\c{RSLDT}: Restore Segment Register and Descriptor
11841 \c RSLDT m80 ; 0F 7B /0 [486,CYRIX,SMM]
11843 \c{RSLDT} restores the Local Descriptor Table (LDTR) from mem80.
11846 \S{insRSM} \i\c{RSM}: Resume from System-Management Mode
11848 \c RSM ; 0F AA [PENT]
11850 \c{RSM} returns the processor to its normal operating mode when it
11851 was in System-Management Mode.
11854 \S{insRSQRTPS} \i\c{RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal
11856 \c RSQRTPS xmm1,xmm2/m128 ; 0F 52 /r [KATMAI,SSE]
11858 \c{RSQRTPS} computes the approximate reciprocals of the square
11859 roots of the packed single-precision floating-point values in the
11860 source and stores the results in xmm1. The maximum error for this
11861 approximation is: |Error| <= 1.5 x 2^-12
11864 \S{insRSQRTSS} \i\c{RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal
11866 \c RSQRTSS xmm1,xmm2/m128 ; F3 0F 52 /r [KATMAI,SSE]
11868 \c{RSQRTSS} returns an approximation of the reciprocal of the
11869 square root of the lowest order single-precision FP value from
11870 the source, and stores it in the low doubleword of the destination
11871 register. The upper three fields of xmm1 are preserved. The maximum
11872 error for this approximation is: |Error| <= 1.5 x 2^-12
11875 \S{insRSTS} \i\c{RSTS}: Restore TSR and Descriptor
11877 \c RSTS m80 ; 0F 7D /0 [486,CYRIX,SMM]
11879 \c{RSTS} restores Task State Register (TSR) from mem80.
11882 \S{insSAHF} \i\c{SAHF}: Store AH to Flags
11884 \c SAHF ; 9E [8086]
11886 \c{SAHF} sets the low byte of the flags word according to the
11887 contents of the \c{AH} register.
11889 The operation of \c{SAHF} is:
11891 \c AH --> SF:ZF:0:AF:0:PF:1:CF
11893 See also \c{LAHF} (\k{insLAHF}).
11896 \S{insSAL} \i\c{SAL}, \i\c{SAR}: Bitwise Arithmetic Shifts
11898 \c SAL r/m8,1 ; D0 /4 [8086]
11899 \c SAL r/m8,CL ; D2 /4 [8086]
11900 \c SAL r/m8,imm8 ; C0 /4 ib [186]
11901 \c SAL r/m16,1 ; o16 D1 /4 [8086]
11902 \c SAL r/m16,CL ; o16 D3 /4 [8086]
11903 \c SAL r/m16,imm8 ; o16 C1 /4 ib [186]
11904 \c SAL r/m32,1 ; o32 D1 /4 [386]
11905 \c SAL r/m32,CL ; o32 D3 /4 [386]
11906 \c SAL r/m32,imm8 ; o32 C1 /4 ib [386]
11908 \c SAR r/m8,1 ; D0 /7 [8086]
11909 \c SAR r/m8,CL ; D2 /7 [8086]
11910 \c SAR r/m8,imm8 ; C0 /7 ib [186]
11911 \c SAR r/m16,1 ; o16 D1 /7 [8086]
11912 \c SAR r/m16,CL ; o16 D3 /7 [8086]
11913 \c SAR r/m16,imm8 ; o16 C1 /7 ib [186]
11914 \c SAR r/m32,1 ; o32 D1 /7 [386]
11915 \c SAR r/m32,CL ; o32 D3 /7 [386]
11916 \c SAR r/m32,imm8 ; o32 C1 /7 ib [386]
11918 \c{SAL} and \c{SAR} perform an arithmetic shift operation on the given
11919 source/destination (first) operand. The vacated bits are filled with
11920 zero for \c{SAL}, and with copies of the original high bit of the
11921 source operand for \c{SAR}.
11923 \c{SAL} is a synonym for \c{SHL} (see \k{insSHL}). NASM will
11924 assemble either one to the same code, but NDISASM will always
11925 disassemble that code as \c{SHL}.
11927 The number of bits to shift by is given by the second operand. Only
11928 the bottom five bits of the shift count are considered by processors
11931 You can force the longer (286 and upwards, beginning with a \c{C1}
11932 byte) form of \c{SAL foo,1} by using a \c{BYTE} prefix: \c{SAL
11933 foo,BYTE 1}. Similarly with \c{SAR}.
11936 \S{insSALC} \i\c{SALC}: Set AL from Carry Flag
11938 \c SALC ; D6 [8086,UNDOC]
11940 \c{SALC} is an early undocumented instruction similar in concept to
11941 \c{SETcc} (\k{insSETcc}). Its function is to set \c{AL} to zero if
11942 the carry flag is clear, or to \c{0xFF} if it is set.
11945 \S{insSBB} \i\c{SBB}: Subtract with Borrow
11947 \c SBB r/m8,reg8 ; 18 /r [8086]
11948 \c SBB r/m16,reg16 ; o16 19 /r [8086]
11949 \c SBB r/m32,reg32 ; o32 19 /r [386]
11951 \c SBB reg8,r/m8 ; 1A /r [8086]
11952 \c SBB reg16,r/m16 ; o16 1B /r [8086]
11953 \c SBB reg32,r/m32 ; o32 1B /r [386]
11955 \c SBB r/m8,imm8 ; 80 /3 ib [8086]
11956 \c SBB r/m16,imm16 ; o16 81 /3 iw [8086]
11957 \c SBB r/m32,imm32 ; o32 81 /3 id [386]
11959 \c SBB r/m16,imm8 ; o16 83 /3 ib [8086]
11960 \c SBB r/m32,imm8 ; o32 83 /3 ib [386]
11962 \c SBB AL,imm8 ; 1C ib [8086]
11963 \c SBB AX,imm16 ; o16 1D iw [8086]
11964 \c SBB EAX,imm32 ; o32 1D id [386]
11966 \c{SBB} performs integer subtraction: it subtracts its second
11967 operand, plus the value of the carry flag, from its first, and
11968 leaves the result in its destination (first) operand. The flags are
11969 set according to the result of the operation: in particular, the
11970 carry flag is affected and can be used by a subsequent \c{SBB}
11973 In the forms with an 8-bit immediate second operand and a longer
11974 first operand, the second operand is considered to be signed, and is
11975 sign-extended to the length of the first operand. In these cases,
11976 the \c{BYTE} qualifier is necessary to force NASM to generate this
11977 form of the instruction.
11979 To subtract one number from another without also subtracting the
11980 contents of the carry flag, use \c{SUB} (\k{insSUB}).
11983 \S{insSCASB} \i\c{SCASB}, \i\c{SCASW}, \i\c{SCASD}: Scan String
11985 \c SCASB ; AE [8086]
11986 \c SCASW ; o16 AF [8086]
11987 \c SCASD ; o32 AF [386]
11989 \c{SCASB} compares the byte in \c{AL} with the byte at \c{[ES:DI]}
11990 or \c{[ES:EDI]}, and sets the flags accordingly. It then increments
11991 or decrements (depending on the direction flag: increments if the
11992 flag is clear, decrements if it is set) \c{DI} (or \c{EDI}).
11994 The register used is \c{DI} if the address size is 16 bits, and
11995 \c{EDI} if it is 32 bits. If you need to use an address size not
11996 equal to the current \c{BITS} setting, you can use an explicit
11997 \i\c{a16} or \i\c{a32} prefix.
11999 Segment override prefixes have no effect for this instruction: the
12000 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
12003 \c{SCASW} and \c{SCASD} work in the same way, but they compare a
12004 word to \c{AX} or a doubleword to \c{EAX} instead of a byte to
12005 \c{AL}, and increment or decrement the addressing registers by 2 or
12008 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
12009 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
12010 \c{ECX} - again, the address size chooses which) times until the
12011 first unequal or equal byte is found.
12014 \S{insSETcc} \i\c{SETcc}: Set Register from Condition
12016 \c SETcc r/m8 ; 0F 90+cc /2 [386]
12018 \c{SETcc} sets the given 8-bit operand to zero if its condition is
12019 not satisfied, and to 1 if it is.
12022 \S{insSFENCE} \i\c{SFENCE}: Store Fence
12024 \c SFENCE ; 0F AE /7 [KATMAI]
12026 \c{SFENCE} performs a serialising operation on all writes to memory
12027 that were issued before the \c{SFENCE} instruction. This guarantees that
12028 all memory writes before the \c{SFENCE} instruction are visible before any
12029 writes after the \c{SFENCE} instruction.
12031 \c{SFENCE} is ordered respective to other \c{SFENCE} instruction, \c{MFENCE},
12032 any memory write and any other serialising instruction (such as \c{CPUID}).
12034 Weakly ordered memory types can be used to achieve higher processor
12035 performance through such techniques as out-of-order issue,
12036 write-combining, and write-collapsing. The degree to which a consumer
12037 of data recognizes or knows that the data is weakly ordered varies
12038 among applications and may be unknown to the producer of this data.
12039 The \c{SFENCE} instruction provides a performance-efficient way of
12040 insuring store ordering between routines that produce weakly-ordered
12041 results and routines that consume this data.
12043 \c{SFENCE} uses the following ModRM encoding:
12046 \c Reg/Opcode (5:3) = 111B
12047 \c R/M (2:0) = 000B
12049 All other ModRM encodings are defined to be reserved, and use
12050 of these encodings risks incompatibility with future processors.
12052 See also \c{LFENCE} (\k{insLFENCE}) and \c{MFENCE} (\k{insMFENCE}).
12055 \S{insSGDT} \i\c{SGDT}, \i\c{SIDT}, \i\c{SLDT}: Store Descriptor Table Pointers
12057 \c SGDT mem ; 0F 01 /0 [286,PRIV]
12058 \c SIDT mem ; 0F 01 /1 [286,PRIV]
12059 \c SLDT r/m16 ; 0F 00 /0 [286,PRIV]
12061 \c{SGDT} and \c{SIDT} both take a 6-byte memory area as an operand:
12062 they store the contents of the GDTR (global descriptor table
12063 register) or IDTR (interrupt descriptor table register) into that
12064 area as a 32-bit linear address and a 16-bit size limit from that
12065 area (in that order). These are the only instructions which directly
12066 use \e{linear} addresses, rather than segment/offset pairs.
12068 \c{SLDT} stores the segment selector corresponding to the LDT (local
12069 descriptor table) into the given operand.
12071 See also \c{LGDT}, \c{LIDT} and \c{LLDT} (\k{insLGDT}).
12074 \S{insSHL} \i\c{SHL}, \i\c{SHR}: Bitwise Logical Shifts
12076 \c SHL r/m8,1 ; D0 /4 [8086]
12077 \c SHL r/m8,CL ; D2 /4 [8086]
12078 \c SHL r/m8,imm8 ; C0 /4 ib [186]
12079 \c SHL r/m16,1 ; o16 D1 /4 [8086]
12080 \c SHL r/m16,CL ; o16 D3 /4 [8086]
12081 \c SHL r/m16,imm8 ; o16 C1 /4 ib [186]
12082 \c SHL r/m32,1 ; o32 D1 /4 [386]
12083 \c SHL r/m32,CL ; o32 D3 /4 [386]
12084 \c SHL r/m32,imm8 ; o32 C1 /4 ib [386]
12086 \c SHR r/m8,1 ; D0 /5 [8086]
12087 \c SHR r/m8,CL ; D2 /5 [8086]
12088 \c SHR r/m8,imm8 ; C0 /5 ib [186]
12089 \c SHR r/m16,1 ; o16 D1 /5 [8086]
12090 \c SHR r/m16,CL ; o16 D3 /5 [8086]
12091 \c SHR r/m16,imm8 ; o16 C1 /5 ib [186]
12092 \c SHR r/m32,1 ; o32 D1 /5 [386]
12093 \c SHR r/m32,CL ; o32 D3 /5 [386]
12094 \c SHR r/m32,imm8 ; o32 C1 /5 ib [386]
12096 \c{SHL} and \c{SHR} perform a logical shift operation on the given
12097 source/destination (first) operand. The vacated bits are filled with
12100 A synonym for \c{SHL} is \c{SAL} (see \k{insSAL}). NASM will
12101 assemble either one to the same code, but NDISASM will always
12102 disassemble that code as \c{SHL}.
12104 The number of bits to shift by is given by the second operand. Only
12105 the bottom five bits of the shift count are considered by processors
12108 You can force the longer (286 and upwards, beginning with a \c{C1}
12109 byte) form of \c{SHL foo,1} by using a \c{BYTE} prefix: \c{SHL
12110 foo,BYTE 1}. Similarly with \c{SHR}.
12113 \S{insSHLD} \i\c{SHLD}, \i\c{SHRD}: Bitwise Double-Precision Shifts
12115 \c SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386]
12116 \c SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386]
12117 \c SHLD r/m16,reg16,CL ; o16 0F A5 /r [386]
12118 \c SHLD r/m16,reg32,CL ; o32 0F A5 /r [386]
12120 \c SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386]
12121 \c SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386]
12122 \c SHRD r/m16,reg16,CL ; o16 0F AD /r [386]
12123 \c SHRD r/m32,reg32,CL ; o32 0F AD /r [386]
12125 \b \c{SHLD} performs a double-precision left shift. It notionally
12126 places its second operand to the right of its first, then shifts
12127 the entire bit string thus generated to the left by a number of
12128 bits specified in the third operand. It then updates only the
12129 \e{first} operand according to the result of this. The second
12130 operand is not modified.
12132 \b \c{SHRD} performs the corresponding right shift: it notionally
12133 places the second operand to the \e{left} of the first, shifts the
12134 whole bit string right, and updates only the first operand.
12136 For example, if \c{EAX} holds \c{0x01234567} and \c{EBX} holds
12137 \c{0x89ABCDEF}, then the instruction \c{SHLD EAX,EBX,4} would update
12138 \c{EAX} to hold \c{0x12345678}. Under the same conditions, \c{SHRD
12139 EAX,EBX,4} would update \c{EAX} to hold \c{0xF0123456}.
12141 The number of bits to shift by is given by the third operand. Only
12142 the bottom five bits of the shift count are considered.
12145 \S{insSHUFPD} \i\c{SHUFPD}: Shuffle Packed Double-Precision FP Values
12147 \c SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2]
12149 \c{SHUFPD} moves one of the packed double-precision FP values from
12150 the destination operand into the low quadword of the destination
12151 operand; the upper quadword is generated by moving one of the
12152 double-precision FP values from the source operand into the
12153 destination. The select (third) operand selects which of the values
12154 are moved to the destination register.
12156 The select operand is an 8-bit immediate: bit 0 selects which value
12157 is moved from the destination operand to the result (where 0 selects
12158 the low quadword and 1 selects the high quadword) and bit 1 selects
12159 which value is moved from the source operand to the result.
12160 Bits 2 through 7 of the shuffle operand are reserved.
12163 \S{insSHUFPS} \i\c{SHUFPS}: Shuffle Packed Single-Precision FP Values
12165 \c SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE]
12167 \c{SHUFPS} moves two of the packed single-precision FP values from
12168 the destination operand into the low quadword of the destination
12169 operand; the upper quadword is generated by moving two of the
12170 single-precision FP values from the source operand into the
12171 destination. The select (third) operand selects which of the
12172 values are moved to the destination register.
12174 The select operand is an 8-bit immediate: bits 0 and 1 select the
12175 value to be moved from the destination operand the low doubleword of
12176 the result, bits 2 and 3 select the value to be moved from the
12177 destination operand the second doubleword of the result, bits 4 and
12178 5 select the value to be moved from the source operand the third
12179 doubleword of the result, and bits 6 and 7 select the value to be
12180 moved from the source operand to the high doubleword of the result.
12183 \S{insSMI} \i\c{SMI}: System Management Interrupt
12185 \c SMI ; F1 [386,UNDOC]
12187 \c{SMI} puts some AMD processors into SMM mode. It is available on some
12188 386 and 486 processors, and is only available when DR7 bit 12 is set,
12189 otherwise it generates an Int 1.
12192 \S{insSMINT} \i\c{SMINT}, \i\c{SMINTOLD}: Software SMM Entry (CYRIX)
12194 \c SMINT ; 0F 38 [PENT,CYRIX]
12195 \c SMINTOLD ; 0F 7E [486,CYRIX]
12197 \c{SMINT} puts the processor into SMM mode. The CPU state information is
12198 saved in the SMM memory header, and then execution begins at the SMM base
12201 \c{SMINTOLD} is the same as \c{SMINT}, but was the opcode used on the 486.
12203 This pair of opcodes are specific to the Cyrix and compatible range of
12204 processors (Cyrix, IBM, Via).
12207 \S{insSMSW} \i\c{SMSW}: Store Machine Status Word
12209 \c SMSW r/m16 ; 0F 01 /4 [286,PRIV]
12211 \c{SMSW} stores the bottom half of the \c{CR0} control register (or
12212 the Machine Status Word, on 286 processors) into the destination
12213 operand. See also \c{LMSW} (\k{insLMSW}).
12215 For 32-bit code, this would use the low 16-bits of the specified
12216 register (or a 16bit memory location), without needing an operand
12217 size override byte.
12220 \S{insSQRTPD} \i\c{SQRTPD}: Packed Double-Precision FP Square Root
12222 \c SQRTPD xmm1,xmm2/m128 ; 66 0F 51 /r [WILLAMETTE,SSE2]
12224 \c{SQRTPD} calculates the square root of the packed double-precision
12225 FP value from the source operand, and stores the double-precision
12226 results in the destination register.
12229 \S{insSQRTPS} \i\c{SQRTPS}: Packed Single-Precision FP Square Root
12231 \c SQRTPS xmm1,xmm2/m128 ; 0F 51 /r [KATMAI,SSE]
12233 \c{SQRTPS} calculates the square root of the packed single-precision
12234 FP value from the source operand, and stores the single-precision
12235 results in the destination register.
12238 \S{insSQRTSD} \i\c{SQRTSD}: Scalar Double-Precision FP Square Root
12240 \c SQRTSD xmm1,xmm2/m128 ; F2 0F 51 /r [WILLAMETTE,SSE2]
12242 \c{SQRTSD} calculates the square root of the low-order double-precision
12243 FP value from the source operand, and stores the double-precision
12244 result in the destination register. The high-quadword remains unchanged.
12247 \S{insSQRTSS} \i\c{SQRTSS}: Scalar Single-Precision FP Square Root
12249 \c SQRTSS xmm1,xmm2/m128 ; F3 0F 51 /r [KATMAI,SSE]
12251 \c{SQRTSS} calculates the square root of the low-order single-precision
12252 FP value from the source operand, and stores the single-precision
12253 result in the destination register. The three high doublewords remain
12257 \S{insSTC} \i\c{STC}, \i\c{STD}, \i\c{STI}: Set Flags
12263 These instructions set various flags. \c{STC} sets the carry flag;
12264 \c{STD} sets the direction flag; and \c{STI} sets the interrupt flag
12265 (thus enabling interrupts).
12267 To clear the carry, direction, or interrupt flags, use the \c{CLC},
12268 \c{CLD} and \c{CLI} instructions (\k{insCLC}). To invert the carry
12269 flag, use \c{CMC} (\k{insCMC}).
12272 \S{insSTMXCSR} \i\c{STMXCSR}: Store Streaming SIMD Extension
12275 \c STMXCSR m32 ; 0F AE /3 [KATMAI,SSE]
12277 \c{STMXCSR} stores the contents of the \c{MXCSR} control/status
12278 register to the specified memory location. \c{MXCSR} is used to
12279 enable masked/unmasked exception handling, to set rounding modes,
12280 to set flush-to-zero mode, and to view exception status flags.
12281 The reserved bits in the \c{MXCSR} register are stored as 0s.
12283 For details of the \c{MXCSR} register, see the Intel processor docs.
12285 See also \c{LDMXCSR} (\k{insLDMXCSR}).
12288 \S{insSTOSB} \i\c{STOSB}, \i\c{STOSW}, \i\c{STOSD}: Store Byte to String
12290 \c STOSB ; AA [8086]
12291 \c STOSW ; o16 AB [8086]
12292 \c STOSD ; o32 AB [386]
12294 \c{STOSB} stores the byte in \c{AL} at \c{[ES:DI]} or \c{[ES:EDI]},
12295 and sets the flags accordingly. It then increments or decrements
12296 (depending on the direction flag: increments if the flag is clear,
12297 decrements if it is set) \c{DI} (or \c{EDI}).
12299 The register used is \c{DI} if the address size is 16 bits, and
12300 \c{EDI} if it is 32 bits. If you need to use an address size not
12301 equal to the current \c{BITS} setting, you can use an explicit
12302 \i\c{a16} or \i\c{a32} prefix.
12304 Segment override prefixes have no effect for this instruction: the
12305 use of \c{ES} for the store to \c{[DI]} or \c{[EDI]} cannot be
12308 \c{STOSW} and \c{STOSD} work in the same way, but they store the
12309 word in \c{AX} or the doubleword in \c{EAX} instead of the byte in
12310 \c{AL}, and increment or decrement the addressing registers by 2 or
12313 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
12314 \c{ECX} - again, the address size chooses which) times.
12317 \S{insSTR} \i\c{STR}: Store Task Register
12319 \c STR r/m16 ; 0F 00 /1 [286,PRIV]
12321 \c{STR} stores the segment selector corresponding to the contents of
12322 the Task Register into its operand. When the operand size is a 16-bit
12323 register, the upper 16-bits are cleared to 0s. When the destination
12324 operand is a memory location, 16 bits are written regardless of the
12328 \S{insSUB} \i\c{SUB}: Subtract Integers
12330 \c SUB r/m8,reg8 ; 28 /r [8086]
12331 \c SUB r/m16,reg16 ; o16 29 /r [8086]
12332 \c SUB r/m32,reg32 ; o32 29 /r [386]
12334 \c SUB reg8,r/m8 ; 2A /r [8086]
12335 \c SUB reg16,r/m16 ; o16 2B /r [8086]
12336 \c SUB reg32,r/m32 ; o32 2B /r [386]
12338 \c SUB r/m8,imm8 ; 80 /5 ib [8086]
12339 \c SUB r/m16,imm16 ; o16 81 /5 iw [8086]
12340 \c SUB r/m32,imm32 ; o32 81 /5 id [386]
12342 \c SUB r/m16,imm8 ; o16 83 /5 ib [8086]
12343 \c SUB r/m32,imm8 ; o32 83 /5 ib [386]
12345 \c SUB AL,imm8 ; 2C ib [8086]
12346 \c SUB AX,imm16 ; o16 2D iw [8086]
12347 \c SUB EAX,imm32 ; o32 2D id [386]
12349 \c{SUB} performs integer subtraction: it subtracts its second
12350 operand from its first, and leaves the result in its destination
12351 (first) operand. The flags are set according to the result of the
12352 operation: in particular, the carry flag is affected and can be used
12353 by a subsequent \c{SBB} instruction (\k{insSBB}).
12355 In the forms with an 8-bit immediate second operand and a longer
12356 first operand, the second operand is considered to be signed, and is
12357 sign-extended to the length of the first operand. In these cases,
12358 the \c{BYTE} qualifier is necessary to force NASM to generate this
12359 form of the instruction.
12362 \S{insSUBPD} \i\c{SUBPD}: Packed Double-Precision FP Subtract
12364 \c SUBPD xmm1,xmm2/m128 ; 66 0F 5C /r [WILLAMETTE,SSE2]
12366 \c{SUBPD} subtracts the packed double-precision FP values of
12367 the source operand from those of the destination operand, and
12368 stores the result in the destination operation.
12371 \S{insSUBPS} \i\c{SUBPS}: Packed Single-Precision FP Subtract
12373 \c SUBPS xmm1,xmm2/m128 ; 0F 5C /r [KATMAI,SSE]
12375 \c{SUBPS} subtracts the packed single-precision FP values of
12376 the source operand from those of the destination operand, and
12377 stores the result in the destination operation.
12380 \S{insSUBSD} \i\c{SUBSD}: Scalar Single-FP Subtract
12382 \c SUBSD xmm1,xmm2/m128 ; F2 0F 5C /r [WILLAMETTE,SSE2]
12384 \c{SUBSD} subtracts the low-order double-precision FP value of
12385 the source operand from that of the destination operand, and
12386 stores the result in the destination operation. The high
12387 quadword is unchanged.
12390 \S{insSUBSS} \i\c{SUBSS}: Scalar Single-FP Subtract
12392 \c SUBSS xmm1,xmm2/m128 ; F3 0F 5C /r [KATMAI,SSE]
12394 \c{SUBSS} subtracts the low-order single-precision FP value of
12395 the source operand from that of the destination operand, and
12396 stores the result in the destination operation. The three high
12397 doublewords are unchanged.
12400 \S{insSVDC} \i\c{SVDC}: Save Segment Register and Descriptor
12402 \c SVDC m80,segreg ; 0F 78 /r [486,CYRIX,SMM]
12404 \c{SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its
12405 descriptor to mem80.
12408 \S{insSVLDT} \i\c{SVLDT}: Save LDTR and Descriptor
12410 \c SVLDT m80 ; 0F 7A /0 [486,CYRIX,SMM]
12412 \c{SVLDT} saves the Local Descriptor Table (LDTR) to mem80.
12415 \S{insSVTS} \i\c{SVTS}: Save TSR and Descriptor
12417 \c SVTS m80 ; 0F 7C /0 [486,CYRIX,SMM]
12419 \c{SVTS} saves the Task State Register (TSR) to mem80.
12422 \S{insSYSCALL} \i\c{SYSCALL}: Call Operating System
12424 \c SYSCALL ; 0F 05 [P6,AMD]
12426 \c{SYSCALL} provides a fast method of transferring control to a fixed
12427 entry point in an operating system.
12429 \b The \c{EIP} register is copied into the \c{ECX} register.
12431 \b Bits [31-0] of the 64-bit SYSCALL/SYSRET Target Address Register
12432 (\c{STAR}) are copied into the \c{EIP} register.
12434 \b Bits [47-32] of the \c{STAR} register specify the selector that is
12435 copied into the \c{CS} register.
12437 \b Bits [47-32]+1000b of the \c{STAR} register specify the selector that
12438 is copied into the SS register.
12440 The \c{CS} and \c{SS} registers should not be modified by the operating
12441 system between the execution of the \c{SYSCALL} instruction and its
12442 corresponding \c{SYSRET} instruction.
12444 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12445 (AMD document number 21086.pdf).
12448 \S{insSYSENTER} \i\c{SYSENTER}: Fast System Call
12450 \c SYSENTER ; 0F 34 [P6]
12452 \c{SYSENTER} executes a fast call to a level 0 system procedure or
12453 routine. Before using this instruction, various MSRs need to be set
12456 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12457 privilege level 0 code segment. (This value is also used to compute
12458 the segment selector of the privilege level 0 stack segment.)
12460 \b \c{SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege
12461 level 0 code segment to the first instruction of the selected operating
12462 procedure or routine.
12464 \b \c{SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the
12465 privilege level 0 stack.
12467 \c{SYSENTER} performs the following sequence of operations:
12469 \b Loads the segment selector from the \c{SYSENTER_CS_MSR} into the
12472 \b Loads the instruction pointer from the \c{SYSENTER_EIP_MSR} into
12473 the \c{EIP} register.
12475 \b Adds 8 to the value in \c{SYSENTER_CS_MSR} and loads it into the
12478 \b Loads the stack pointer from the \c{SYSENTER_ESP_MSR} into the
12481 \b Switches to privilege level 0.
12483 \b Clears the \c{VM} flag in the \c{EFLAGS} register, if the flag
12486 \b Begins executing the selected system procedure.
12488 In particular, note that this instruction des not save the values of
12489 \c{CS} or \c{(E)IP}. If you need to return to the calling code, you
12490 need to write your code to cater for this.
12492 For more information, see the Intel Architecture Software Developer's
12496 \S{insSYSEXIT} \i\c{SYSEXIT}: Fast Return From System Call
12498 \c SYSEXIT ; 0F 35 [P6,PRIV]
12500 \c{SYSEXIT} executes a fast return to privilege level 3 user code.
12501 This instruction is a companion instruction to the \c{SYSENTER}
12502 instruction, and can only be executed by privilege level 0 code.
12503 Various registers need to be set up before calling this instruction:
12505 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12506 privilege level 0 code segment in which the processor is currently
12507 executing. (This value is used to compute the segment selectors for
12508 the privilege level 3 code and stack segments.)
12510 \b \c{EDX} contains the 32-bit offset into the privilege level 3 code
12511 segment to the first instruction to be executed in the user code.
12513 \b \c{ECX} contains the 32-bit stack pointer for the privilege level 3
12516 \c{SYSEXIT} performs the following sequence of operations:
12518 \b Adds 16 to the value in \c{SYSENTER_CS_MSR} and loads the sum into
12519 the \c{CS} selector register.
12521 \b Loads the instruction pointer from the \c{EDX} register into the
12524 \b Adds 24 to the value in \c{SYSENTER_CS_MSR} and loads the sum
12525 into the \c{SS} selector register.
12527 \b Loads the stack pointer from the \c{ECX} register into the \c{ESP}
12530 \b Switches to privilege level 3.
12532 \b Begins executing the user code at the \c{EIP} address.
12534 For more information on the use of the \c{SYSENTER} and \c{SYSEXIT}
12535 instructions, see the Intel Architecture Software Developer's
12539 \S{insSYSRET} \i\c{SYSRET}: Return From Operating System
12541 \c SYSRET ; 0F 07 [P6,AMD,PRIV]
12543 \c{SYSRET} is the return instruction used in conjunction with the
12544 \c{SYSCALL} instruction to provide fast entry/exit to an operating system.
12546 \b The \c{ECX} register, which points to the next sequential instruction
12547 after the corresponding \c{SYSCALL} instruction, is copied into the \c{EIP}
12550 \b Bits [63-48] of the \c{STAR} register specify the selector that is copied
12551 into the \c{CS} register.
12553 \b Bits [63-48]+1000b of the \c{STAR} register specify the selector that is
12554 copied into the \c{SS} register.
12556 \b Bits [1-0] of the \c{SS} register are set to 11b (RPL of 3) regardless of
12557 the value of bits [49-48] of the \c{STAR} register.
12559 The \c{CS} and \c{SS} registers should not be modified by the operating
12560 system between the execution of the \c{SYSCALL} instruction and its
12561 corresponding \c{SYSRET} instruction.
12563 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12564 (AMD document number 21086.pdf).
12567 \S{insTEST} \i\c{TEST}: Test Bits (notional bitwise AND)
12569 \c TEST r/m8,reg8 ; 84 /r [8086]
12570 \c TEST r/m16,reg16 ; o16 85 /r [8086]
12571 \c TEST r/m32,reg32 ; o32 85 /r [386]
12573 \c TEST r/m8,imm8 ; F6 /0 ib [8086]
12574 \c TEST r/m16,imm16 ; o16 F7 /0 iw [8086]
12575 \c TEST r/m32,imm32 ; o32 F7 /0 id [386]
12577 \c TEST AL,imm8 ; A8 ib [8086]
12578 \c TEST AX,imm16 ; o16 A9 iw [8086]
12579 \c TEST EAX,imm32 ; o32 A9 id [386]
12581 \c{TEST} performs a `mental' bitwise AND of its two operands, and
12582 affects the flags as if the operation had taken place, but does not
12583 store the result of the operation anywhere.
12586 \S{insUCOMISD} \i\c{UCOMISD}: Unordered Scalar Double-Precision FP
12587 compare and set EFLAGS
12589 \c UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2]
12591 \c{UCOMISD} compares the low-order double-precision FP numbers in the
12592 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12593 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12594 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12595 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12596 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12599 \S{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-Precision FP
12600 compare and set EFLAGS
12602 \c UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE]
12604 \c{UCOMISS} compares the low-order single-precision FP numbers in the
12605 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12606 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12607 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12608 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12609 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12612 \S{insUD2} \i\c{UD0}, \i\c{UD1}, \i\c{UD2}: Undefined Instruction
12614 \c UD0 ; 0F FF [186,UNDOC]
12615 \c UD1 ; 0F B9 [186,UNDOC]
12616 \c UD2 ; 0F 0B [186]
12618 \c{UDx} can be used to generate an invalid opcode exception, for testing
12621 \c{UD0} is specifically documented by AMD as being reserved for this
12624 \c{UD1} is documented by Intel as being available for this purpose.
12626 \c{UD2} is specifically documented by Intel as being reserved for this
12627 purpose. Intel document this as the preferred method of generating an
12628 invalid opcode exception.
12630 All these opcodes can be used to generate invalid opcode exceptions on
12631 all currently available processors.
12634 \S{insUMOV} \i\c{UMOV}: User Move Data
12636 \c UMOV r/m8,reg8 ; 0F 10 /r [386,UNDOC]
12637 \c UMOV r/m16,reg16 ; o16 0F 11 /r [386,UNDOC]
12638 \c UMOV r/m32,reg32 ; o32 0F 11 /r [386,UNDOC]
12640 \c UMOV reg8,r/m8 ; 0F 12 /r [386,UNDOC]
12641 \c UMOV reg16,r/m16 ; o16 0F 13 /r [386,UNDOC]
12642 \c UMOV reg32,r/m32 ; o32 0F 13 /r [386,UNDOC]
12644 This undocumented instruction is used by in-circuit emulators to
12645 access user memory (as opposed to host memory). It is used just like
12646 an ordinary memory/register or register/register \c{MOV}
12647 instruction, but accesses user space.
12649 This instruction is only available on some AMD and IBM 386 and 486
12653 \S{insUNPCKHPD} \i\c{UNPCKHPD}: Unpack and Interleave High Packed
12654 Double-Precision FP Values
12656 \c UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2]
12658 \c{UNPCKHPD} performs an interleaved unpack of the high-order data
12659 elements of the source and destination operands, saving the result
12660 in \c{xmm1}. It ignores the lower half of the sources.
12662 The operation of this instruction is:
12664 \c dst[63-0] := dst[127-64];
12665 \c dst[127-64] := src[127-64].
12668 \S{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack and Interleave High Packed
12669 Single-Precision FP Values
12671 \c UNPCKHPS xmm1,xmm2/m128 ; 0F 15 /r [KATMAI,SSE]
12673 \c{UNPCKHPS} performs an interleaved unpack of the high-order data
12674 elements of the source and destination operands, saving the result
12675 in \c{xmm1}. It ignores the lower half of the sources.
12677 The operation of this instruction is:
12679 \c dst[31-0] := dst[95-64];
12680 \c dst[63-32] := src[95-64];
12681 \c dst[95-64] := dst[127-96];
12682 \c dst[127-96] := src[127-96].
12685 \S{insUNPCKLPD} \i\c{UNPCKLPD}: Unpack and Interleave Low Packed
12686 Double-Precision FP Data
12688 \c UNPCKLPD xmm1,xmm2/m128 ; 66 0F 14 /r [WILLAMETTE,SSE2]
12690 \c{UNPCKLPD} performs an interleaved unpack of the low-order data
12691 elements of the source and destination operands, saving the result
12692 in \c{xmm1}. It ignores the lower half of the sources.
12694 The operation of this instruction is:
12696 \c dst[63-0] := dst[63-0];
12697 \c dst[127-64] := src[63-0].
12700 \S{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack and Interleave Low Packed
12701 Single-Precision FP Data
12703 \c UNPCKLPS xmm1,xmm2/m128 ; 0F 14 /r [KATMAI,SSE]
12705 \c{UNPCKLPS} performs an interleaved unpack of the low-order data
12706 elements of the source and destination operands, saving the result
12707 in \c{xmm1}. It ignores the lower half of the sources.
12709 The operation of this instruction is:
12711 \c dst[31-0] := dst[31-0];
12712 \c dst[63-32] := src[31-0];
12713 \c dst[95-64] := dst[63-32];
12714 \c dst[127-96] := src[63-32].
12717 \S{insVERR} \i\c{VERR}, \i\c{VERW}: Verify Segment Readability/Writability
12719 \c VERR r/m16 ; 0F 00 /4 [286,PRIV]
12721 \c VERW r/m16 ; 0F 00 /5 [286,PRIV]
12723 \b \c{VERR} sets the zero flag if the segment specified by the selector
12724 in its operand can be read from at the current privilege level.
12725 Otherwise it is cleared.
12727 \b \c{VERW} sets the zero flag if the segment can be written.
12730 \S{insWAIT} \i\c{WAIT}: Wait for Floating-Point Processor
12732 \c WAIT ; 9B [8086]
12733 \c FWAIT ; 9B [8086]
12735 \c{WAIT}, on 8086 systems with a separate 8087 FPU, waits for the
12736 FPU to have finished any operation it is engaged in before
12737 continuing main processor operations, so that (for example) an FPU
12738 store to main memory can be guaranteed to have completed before the
12739 CPU tries to read the result back out.
12741 On higher processors, \c{WAIT} is unnecessary for this purpose, and
12742 it has the alternative purpose of ensuring that any pending unmasked
12743 FPU exceptions have happened before execution continues.
12746 \S{insWBINVD} \i\c{WBINVD}: Write Back and Invalidate Cache
12748 \c WBINVD ; 0F 09 [486]
12750 \c{WBINVD} invalidates and empties the processor's internal caches,
12751 and causes the processor to instruct external caches to do the same.
12752 It writes the contents of the caches back to memory first, so no
12753 data is lost. To flush the caches quickly without bothering to write
12754 the data back first, use \c{INVD} (\k{insINVD}).
12757 \S{insWRMSR} \i\c{WRMSR}: Write Model-Specific Registers
12759 \c WRMSR ; 0F 30 [PENT]
12761 \c{WRMSR} writes the value in \c{EDX:EAX} to the processor
12762 Model-Specific Register (MSR) whose index is stored in \c{ECX}.
12763 See also \c{RDMSR} (\k{insRDMSR}).
12766 \S{insWRSHR} \i\c{WRSHR}: Write SMM Header Pointer Register
12768 \c WRSHR r/m32 ; 0F 37 /0 [386,CYRIX,SMM]
12770 \c{WRSHR} loads the contents of either a 32-bit memory location or a
12771 32-bit register into the SMM header pointer register.
12773 See also \c{RDSHR} (\k{insRDSHR}).
12776 \S{insXADD} \i\c{XADD}: Exchange and Add
12778 \c XADD r/m8,reg8 ; 0F C0 /r [486]
12779 \c XADD r/m16,reg16 ; o16 0F C1 /r [486]
12780 \c XADD r/m32,reg32 ; o32 0F C1 /r [486]
12782 \c{XADD} exchanges the values in its two operands, and then adds
12783 them together and writes the result into the destination (first)
12784 operand. This instruction can be used with a \c{LOCK} prefix for
12785 multi-processor synchronisation purposes.
12788 \S{insXBTS} \i\c{XBTS}: Extract Bit String
12790 \c XBTS reg16,r/m16 ; o16 0F A6 /r [386,UNDOC]
12791 \c XBTS reg32,r/m32 ; o32 0F A6 /r [386,UNDOC]
12793 The implied operation of this instruction is:
12795 \c XBTS r/m16,reg16,AX,CL
12796 \c XBTS r/m32,reg32,EAX,CL
12798 Writes a bit string from the source operand to the destination. \c{CL}
12799 indicates the number of bits to be copied, and \c{(E)AX} indicates the
12800 low order bit offset in the source. The bits are written to the low
12801 order bits of the destination register. For example, if \c{CL} is set
12802 to 4 and \c{AX} (for 16-bit code) is set to 5, bits 5-8 of \c{src} will
12803 be copied to bits 0-3 of \c{dst}. This instruction is very poorly
12804 documented, and I have been unable to find any official source of
12805 documentation on it.
12807 \c{XBTS} is supported only on the early Intel 386s, and conflicts with
12808 the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM supports it
12809 only for completeness. Its counterpart is \c{IBTS} (see \k{insIBTS}).
12812 \S{insXCHG} \i\c{XCHG}: Exchange
12814 \c XCHG reg8,r/m8 ; 86 /r [8086]
12815 \c XCHG reg16,r/m8 ; o16 87 /r [8086]
12816 \c XCHG reg32,r/m32 ; o32 87 /r [386]
12818 \c XCHG r/m8,reg8 ; 86 /r [8086]
12819 \c XCHG r/m16,reg16 ; o16 87 /r [8086]
12820 \c XCHG r/m32,reg32 ; o32 87 /r [386]
12822 \c XCHG AX,reg16 ; o16 90+r [8086]
12823 \c XCHG EAX,reg32 ; o32 90+r [386]
12824 \c XCHG reg16,AX ; o16 90+r [8086]
12825 \c XCHG reg32,EAX ; o32 90+r [386]
12827 \c{XCHG} exchanges the values in its two operands. It can be used
12828 with a \c{LOCK} prefix for purposes of multi-processor
12831 \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the \c{BITS}
12832 setting) generates the opcode \c{90h}, and so is a synonym for
12833 \c{NOP} (\k{insNOP}).
12836 \S{insXLATB} \i\c{XLATB}: Translate Byte in Lookup Table
12838 \c XLAT ; D7 [8086]
12839 \c XLATB ; D7 [8086]
12841 \c{XLATB} adds the value in \c{AL}, treated as an unsigned byte, to
12842 \c{BX} or \c{EBX}, and loads the byte from the resulting address (in
12843 the segment specified by \c{DS}) back into \c{AL}.
12845 The base register used is \c{BX} if the address size is 16 bits, and
12846 \c{EBX} if it is 32 bits. If you need to use an address size not
12847 equal to the current \c{BITS} setting, you can use an explicit
12848 \i\c{a16} or \i\c{a32} prefix.
12850 The segment register used to load from \c{[BX+AL]} or \c{[EBX+AL]}
12851 can be overridden by using a segment register name as a prefix (for
12852 example, \c{es xlatb}).
12855 \S{insXOR} \i\c{XOR}: Bitwise Exclusive OR
12857 \c XOR r/m8,reg8 ; 30 /r [8086]
12858 \c XOR r/m16,reg16 ; o16 31 /r [8086]
12859 \c XOR r/m32,reg32 ; o32 31 /r [386]
12861 \c XOR reg8,r/m8 ; 32 /r [8086]
12862 \c XOR reg16,r/m16 ; o16 33 /r [8086]
12863 \c XOR reg32,r/m32 ; o32 33 /r [386]
12865 \c XOR r/m8,imm8 ; 80 /6 ib [8086]
12866 \c XOR r/m16,imm16 ; o16 81 /6 iw [8086]
12867 \c XOR r/m32,imm32 ; o32 81 /6 id [386]
12869 \c XOR r/m16,imm8 ; o16 83 /6 ib [8086]
12870 \c XOR r/m32,imm8 ; o32 83 /6 ib [386]
12872 \c XOR AL,imm8 ; 34 ib [8086]
12873 \c XOR AX,imm16 ; o16 35 iw [8086]
12874 \c XOR EAX,imm32 ; o32 35 id [386]
12876 \c{XOR} performs a bitwise XOR operation between its two operands
12877 (i.e. each bit of the result is 1 if and only if exactly one of the
12878 corresponding bits of the two inputs was 1), and stores the result
12879 in the destination (first) operand.
12881 In the forms with an 8-bit immediate second operand and a longer
12882 first operand, the second operand is considered to be signed, and is
12883 sign-extended to the length of the first operand. In these cases,
12884 the \c{BYTE} qualifier is necessary to force NASM to generate this
12885 form of the instruction.
12887 The \c{MMX} instruction \c{PXOR} (see \k{insPXOR}) performs the same
12888 operation on the 64-bit \c{MMX} registers.
12891 \S{insXORPD} \i\c{XORPD}: Bitwise Logical XOR of Double-Precision FP Values
12893 \c XORPD xmm1,xmm2/m128 ; 66 0F 57 /r [WILLAMETTE,SSE2]
12895 \c{XORPD} returns a bit-wise logical XOR between the source and
12896 destination operands, storing the result in the destination operand.
12899 \S{insXORPS} \i\c{XORPS}: Bitwise Logical XOR of Single-Precision FP Values
12901 \c XORPS xmm1,xmm2/m128 ; 0F 57 /r [KATMAI,SSE]
12903 \c{XORPS} returns a bit-wise logical XOR between the source and
12904 destination operands, storing the result in the destination operand.