3 \# Source code to NASM documentation
5 \M{category}{Programming}
6 \M{title}{NASM - The Netwide Assembler}
8 \M{author}{The NASM Development Team}
9 \M{license}{All rights reserved. This document is redistributable under the licence given in the file "COPYING" distributed in the NASM archive.}
10 \M{summary}{This file documents NASM, the Netwide Assembler: an assembler targetting the Intel x86 series of processors, with portable source.}
13 \M{infotitle}{The Netwide Assembler for x86}
14 \M{epslogo}{nasmlogo.eps}
20 \IR{-On} \c{-On} option
36 \IR{!=} \c{!=} operator
37 \IR{$, here} \c{$}, Here token
38 \IR{$, prefix} \c{$}, prefix
41 \IR{%%} \c{%%} operator
42 \IR{%+1} \c{%+1} and \c{%-1} syntax
44 \IR{%0} \c{%0} parameter count
46 \IR{&&} \c{&&} operator
48 \IR{..@} \c{..@} symbol prefix
50 \IR{//} \c{//} operator
52 \IR{<<} \c{<<} operator
53 \IR{<=} \c{<=} operator
54 \IR{<>} \c{<>} operator
56 \IR{==} \c{==} operator
58 \IR{>=} \c{>=} operator
59 \IR{>>} \c{>>} operator
60 \IR{?} \c{?} MASM syntax
62 \IR{^^} \c{^^} operator
64 \IR{||} \c{||} operator
66 \IR{%$} \c{%$} and \c{%$$} prefixes
68 \IR{+ opaddition} \c{+} operator, binary
69 \IR{+ opunary} \c{+} operator, unary
70 \IR{+ modifier} \c{+} modifier
71 \IR{- opsubtraction} \c{-} operator, binary
72 \IR{- opunary} \c{-} operator, unary
73 \IR{alignment, in bin sections} alignment, in \c{bin} sections
74 \IR{alignment, in elf sections} alignment, in \c{elf} sections
75 \IR{alignment, in win32 sections} alignment, in \c{win32} sections
76 \IR{alignment, of elf common variables} alignment, of \c{elf} common
78 \IR{alignment, in obj sections} alignment, in \c{obj} sections
79 \IR{a.out, bsd version} \c{a.out}, BSD version
80 \IR{a.out, linux version} \c{a.out}, Linux version
81 \IR{autoconf} Autoconf
83 \IR{bitwise and} bitwise AND
84 \IR{bitwise or} bitwise OR
85 \IR{bitwise xor} bitwise XOR
86 \IR{block ifs} block IFs
87 \IR{borland pascal} Borland, Pascal
88 \IR{borland's win32 compilers} Borland, Win32 compilers
89 \IR{braces, after % sign} braces, after \c{%} sign
91 \IR{c calling convention} C calling convention
92 \IR{c symbol names} C symbol names
93 \IA{critical expressions}{critical expression}
94 \IA{command line}{command-line}
95 \IA{case sensitivity}{case sensitive}
96 \IA{case-sensitive}{case sensitive}
97 \IA{case-insensitive}{case sensitive}
98 \IA{character constants}{character constant}
99 \IR{common object file format} Common Object File Format
100 \IR{common variables, alignment in elf} common variables, alignment
102 \IR{common, elf extensions to} \c{COMMON}, \c{elf} extensions to
103 \IR{common, obj extensions to} \c{COMMON}, \c{obj} extensions to
104 \IR{declaring structure} declaring structures
105 \IR{default-wrt mechanism} default-\c{WRT} mechanism
108 \IR{dll symbols, exporting} DLL symbols, exporting
109 \IR{dll symbols, importing} DLL symbols, importing
111 \IR{dos archive} DOS archive
112 \IR{dos source archive} DOS source archive
113 \IA{effective address}{effective addresses}
114 \IA{effective-address}{effective addresses}
116 \IR{elf, 16-bit code and} ELF, 16-bit code and
117 \IR{elf shared libraries} ELF, shared libraries
118 \IR{executable and linkable format} Executable and Linkable Format
119 \IR{extern, obj extensions to} \c{EXTERN}, \c{obj} extensions to
121 \IR{freelink} FreeLink
122 \IR{functions, c calling convention} functions, C calling convention
123 \IR{functions, pascal calling convention} functions, Pascal calling
125 \IR{global, aoutb extensions to} \c{GLOBAL}, \c{aoutb} extensions to
126 \IR{global, elf extensions to} \c{GLOBAL}, \c{elf} extensions to
127 \IR{global, rdf extensions to} \c{GLOBAL}, \c{rdf} extensions to
129 \IR{got relocations} \c{GOT} relocations
130 \IR{gotoff relocation} \c{GOTOFF} relocations
131 \IR{gotpc relocation} \c{GOTPC} relocations
132 \IR{intel number formats} Intel number formats
133 \IR{linux, elf} Linux, ELF
134 \IR{linux, a.out} Linux, \c{a.out}
135 \IR{linux, as86} Linux, \c{as86}
136 \IR{logical and} logical AND
137 \IR{logical or} logical OR
138 \IR{logical xor} logical XOR
140 \IA{memory reference}{memory references}
142 \IA{misc directory}{misc subdirectory}
143 \IR{misc subdirectory} \c{misc} subdirectory
144 \IR{microsoft omf} Microsoft OMF
145 \IR{mmx registers} MMX registers
146 \IA{modr/m}{modr/m byte}
147 \IR{modr/m byte} ModR/M byte
149 \IR{ms-dos device drivers} MS-DOS device drivers
150 \IR{multipush} \c{multipush} macro
151 \IR{nasm version} NASM version
155 \IR{operating system} operating system
157 \IR{pascal calling convention}Pascal calling convention
158 \IR{passes} passes, assembly
163 \IR{plt} \c{PLT} relocations
164 \IA{pre-defining macros}{pre-define}
165 \IA{preprocessor expressions}{preprocessor, expressions}
166 \IA{preprocessor loops}{preprocessor, loops}
167 \IA{preprocessor variables}{preprocessor, variables}
168 \IA{rdoff subdirectory}{rdoff}
169 \IR{rdoff} \c{rdoff} subdirectory
170 \IR{relocatable dynamic object file format} Relocatable Dynamic
172 \IR{relocations, pic-specific} relocations, PIC-specific
173 \IA{repeating}{repeating code}
174 \IR{section alignment, in elf} section alignment, in \c{elf}
175 \IR{section alignment, in bin} section alignment, in \c{bin}
176 \IR{section alignment, in obj} section alignment, in \c{obj}
177 \IR{section alignment, in win32} section alignment, in \c{win32}
178 \IR{section, elf extensions to} \c{SECTION}, \c{elf} extensions to
179 \IR{section, win32 extensions to} \c{SECTION}, \c{win32} extensions to
180 \IR{segment alignment, in bin} segment alignment, in \c{bin}
181 \IR{segment alignment, in obj} segment alignment, in \c{obj}
182 \IR{segment, obj extensions to} \c{SEGMENT}, \c{elf} extensions to
183 \IR{segment names, borland pascal} segment names, Borland Pascal
184 \IR{shift command} \c{shift} command
186 \IR{sib byte} SIB byte
187 \IR{solaris x86} Solaris x86
188 \IA{standard section names}{standardised section names}
189 \IR{symbols, exporting from dlls} symbols, exporting from DLLs
190 \IR{symbols, importing from dlls} symbols, importing from DLLs
191 \IR{test subdirectory} \c{test} subdirectory
193 \IR{underscore, in c symbols} underscore, in C symbols
195 \IA{sco unix}{unix, sco}
196 \IR{unix, sco} Unix, SCO
197 \IA{unix source archive}{unix, source archive}
198 \IR{unix, source archive} Unix, source archive
199 \IA{unix system v}{unix, system v}
200 \IR{unix, system v} Unix, System V
201 \IR{unixware} UnixWare
203 \IR{version number of nasm} version number of NASM
204 \IR{visual c++} Visual C++
205 \IR{www page} WWW page
208 \IR{windows 95} Windows 95
209 \IR{windows nt} Windows NT
210 \# \IC{program entry point}{entry point, program}
211 \# \IC{program entry point}{start point, program}
212 \# \IC{MS-DOS device drivers}{device drivers, MS-DOS}
213 \# \IC{16-bit mode, versus 32-bit mode}{32-bit mode, versus 16-bit mode}
214 \# \IC{c symbol names}{symbol names, in C}
217 \C{intro} Introduction
219 \H{whatsnasm} What Is NASM?
221 The Netwide Assembler, NASM, is an 80x86 assembler designed for
222 portability and modularity. It supports a range of object file
223 formats, including Linux and \c{NetBSD/FreeBSD} \c{a.out}, \c{ELF},
224 \c{COFF}, Microsoft 16-bit \c{OBJ} and \c{Win32}. It will also output
225 plain binary files. Its syntax is designed to be simple and easy to
226 understand, similar to Intel's but less complex. It supports \c{Pentium},
227 \c{P6}, \c{MMX}, \c{3DNow!}, \c{SSE} and \c{SSE2} opcodes, and has
231 \S{yaasm} Why Yet Another Assembler?
233 The Netwide Assembler grew out of an idea on \i\c{comp.lang.asm.x86}
234 (or possibly \i\c{alt.lang.asm} - I forget which), which was
235 essentially that there didn't seem to be a good \e{free} x86-series
236 assembler around, and that maybe someone ought to write one.
238 \b \i\c{a86} is good, but not free, and in particular you don't get any
239 32-bit capability until you pay. It's DOS only, too.
241 \b \i\c{gas} is free, and ports over DOS and Unix, but it's not
242 very good, since it's designed to be a back end to \i\c{gcc}, which
243 always feeds it correct code. So its error checking is minimal. Also,
244 its syntax is horrible, from the point of view of anyone trying to
245 actually \e{write} anything in it. Plus you can't write 16-bit code in
248 \b \i\c{as86} is Minix- and Linux-specific, and (my version at least)
249 doesn't seem to have much (or any) documentation.
251 \b \i\c{MASM} isn't very good, and it's expensive, and it runs only under
254 \b \i\c{TASM} is better, but still strives for MASM compatibility,
255 which means millions of directives and tons of red tape. And its syntax
256 is essentially MASM's, with the contradictions and quirks that
257 entails (although it sorts out some of those by means of Ideal mode).
258 It's expensive too. And it's DOS-only.
260 So here, for your coding pleasure, is NASM. At present it's
261 still in prototype stage - we don't promise that it can outperform
262 any of these assemblers. But please, \e{please} send us bug reports,
263 fixes, helpful information, and anything else you can get your hands
264 on (and thanks to the many people who've done this already! You all
265 know who you are), and we'll improve it out of all recognition.
269 \S{legal} Licence Conditions
271 Please see the file \c{Licence}, supplied as part of any NASM
272 distribution archive, for the \i{licence} conditions under which you
276 \H{contact} Contact Information
278 The current version of NASM (since about 0.98.08) are maintained by a
279 team of developers, accessible through the \c{nasm-devel} mailing list
280 (see below for the link).
281 If you want to report a bug, please read \k{bugs} first.
283 NASM has a \i{WWW page} at
284 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm},
285 and another, with additional information, at
286 \W{http://nasm.2y.net/}\c{http://nasm.2y.net/}
288 The original authors are \i{e\-mail}able as
289 \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} and
290 \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}.
291 The latter is no longer involved in the development team.
293 \i{New releases} of NASM are uploaded to the official sites
294 \W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm}
296 \W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org}
298 \W{ftp://ibiblio.org/pub/Linux/devel/lang/assemblers/}\i\c{ibiblio.org}.
300 Announcements are posted to
301 \W{news:comp.lang.asm.x86}\i\c{comp.lang.asm.x86},
302 \W{news:alt.lang.asm}\i\c{alt.lang.asm} and
303 \W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce}
305 If you want information about NASM beta releases, and the current
306 development status, please subscribe to the \i\c{nasm-devel} email list
308 \W{http://groups.yahoo.com/group/nasm-devel}\c{http://groups.yahoo.com/group/nasm-devel},
309 \W{http://www.pairlist.net/mailman/listinfo/nasm-devel}\c{http://www.pairlist.net/mailman/listinfo/nasm-devel}
311 \W{http://sourceforge.net/projects/nasm}\c{http://sourceforge.net/projects/nasm}.
313 The preferred list is the list at Sourceforge, which is also the home to
314 the latest nasm source code and releases. The other lists are open, but
315 may not continue to be supported in the long term.
318 \H{install} Installation
320 \S{instdos} \i{Installing} NASM under MS-\i{DOS} or Windows
322 Once you've obtained the \i{DOS archive} for NASM, \i\c{nasmXXX.zip}
323 (where \c{XXX} denotes the version number of NASM contained in the
324 archive), unpack it into its own directory (for example \c{c:\\nasm}).
326 The archive will contain four executable files: the NASM executable
327 files \i\c{nasm.exe} and \i\c{nasmw.exe}, and the NDISASM executable
328 files \i\c{ndisasm.exe} and \i\c{ndisasmw.exe}. In each case, the
329 file whose name ends in \c{w} is a \I{Win32}\c{Win32} executable,
330 designed to run under \I{Windows 95}\c{Windows 95} or \I{Windows NT}
331 \c{Windows NT} Intel, and the other one is a 16-bit \I{DOS}\c{DOS}
334 The only file NASM needs to run is its own executable, so copy
335 (at least) one of \c{nasm.exe} and \c{nasmw.exe} to a directory on
336 your PATH, or alternatively edit \i\c{autoexec.bat} to add the
337 \c{nasm} directory to your \i\c{PATH}. (If you're only installing the
338 \c{Win32} version, you may wish to rename it to \c{nasm.exe}.)
340 That's it - NASM is installed. You don't need the nasm directory
341 to be present to run NASM (unless you've added it to your \c{PATH}),
342 so you can delete it if you need to save space; however, you may
343 want to keep the documentation or test programs.
345 If you've downloaded the \i{DOS source archive}, \i\c{nasmXXXs.zip},
346 the \c{nasm} directory will also contain the full NASM \i{source
347 code}, and a selection of \i{Makefiles} you can (hopefully) use to
348 rebuild your copy of NASM from scratch.
350 Note that the source files \c{insnsa.c}, \c{insnsd.c}, \c{insnsi.h}
351 and \c{insnsn.c} are automatically generated from the master
352 instruction table \c{insns.dat} by a Perl script; the file
353 \c{macros.c} is generated from \c{standard.mac} by another Perl
354 script. Although the NASM 0.98 distribution includes these generated
355 files, you will need to rebuild them (and hence, will need a Perl
356 interpreter) if you change insns.dat, standard.mac or the
357 documentation. It is possible future source distributions may not
358 include these files at all. Ports of \i{Perl} for a variety of
359 platforms, including DOS and Windows, are available from
360 \W{http://www.cpan.org/ports/}\i{www.cpan.org}.
363 \S{instdos} Installing NASM under \i{Unix}
365 Once you've obtained the \i{Unix source archive} for NASM,
366 \i\c{nasm-X.XX.tar.gz} (where \c{X.XX} denotes the version number of
367 NASM contained in the archive), unpack it into a directory such
368 as \c{/usr/local/src}. The archive, when unpacked, will create its
369 own subdirectory \c{nasm-X.XX}.
371 NASM is an \I{Autoconf}\I\c{configure}auto-configuring package: once
372 you've unpacked it, \c{cd} to the directory it's been unpacked into
373 and type \c{./configure}. This shell script will find the best C
374 compiler to use for building NASM and set up \i{Makefiles}
377 Once NASM has auto-configured, you can type \i\c{make} to build the
378 \c{nasm} and \c{ndisasm} binaries, and then \c{make install} to
379 install them in \c{/usr/local/bin} and install the \i{man pages}
380 \i\c{nasm.1} and \i\c{ndisasm.1} in \c{/usr/local/man/man1}.
381 Alternatively, you can give options such as \c{--prefix} to the
382 configure script (see the file \i\c{INSTALL} for more details), or
383 install the programs yourself.
385 NASM also comes with a set of utilities for handling the \c{RDOFF}
386 custom object-file format, which are in the \i\c{rdoff} subdirectory
387 of the NASM archive. You can build these with \c{make rdf} and
388 install them with \c{make rdf_install}, if you want them.
390 If NASM fails to auto-configure, you may still be able to make it
391 compile by using the fall-back Unix makefile \i\c{Makefile.unx}.
392 Copy or rename that file to \c{Makefile} and try typing \c{make}.
393 There is also a Makefile.unx file in the \c{rdoff} subdirectory.
396 \C{running} Running NASM
398 \H{syntax} NASM \i{Command-Line} Syntax
400 To assemble a file, you issue a command of the form
402 \c nasm -f <format> <filename> [-o <output>]
406 \c nasm -f elf myfile.asm
408 will assemble \c{myfile.asm} into an \c{ELF} object file \c{myfile.o}. And
410 \c nasm -f bin myfile.asm -o myfile.com
412 will assemble \c{myfile.asm} into a raw binary file \c{myfile.com}.
414 To produce a listing file, with the hex codes output from NASM
415 displayed on the left of the original sources, use the \c{-l} option
416 to give a listing file name, for example:
418 \c nasm -f coff myfile.asm -l myfile.lst
420 To get further usage instructions from NASM, try typing
424 This will also list the available output file formats, and what they
427 If you use Linux but aren't sure whether your system is \c{a.out}
432 (in the directory in which you put the NASM binary when you
433 installed it). If it says something like
435 \c nasm: ELF 32-bit LSB executable i386 (386 and up) Version 1
437 then your system is \c{ELF}, and you should use the option \c{-f elf}
438 when you want NASM to produce Linux object files. If it says
440 \c nasm: Linux/i386 demand-paged executable (QMAGIC)
442 or something similar, your system is \c{a.out}, and you should use
443 \c{-f aout} instead (Linux \c{a.out} systems have long been obsolete,
444 and are rare these days.)
446 Like Unix compilers and assemblers, NASM is silent unless it
447 goes wrong: you won't see any output at all, unless it gives error
451 \S{opt-o} The \i\c{-o} Option: Specifying the Output File Name
453 NASM will normally choose the name of your output file for you;
454 precisely how it does this is dependent on the object file format.
455 For Microsoft object file formats (\i\c{obj} and \i\c{win32}), it
456 will remove the \c{.asm} \i{extension} (or whatever extension you
457 like to use - NASM doesn't care) from your source file name and
458 substitute \c{.obj}. For Unix object file formats (\i\c{aout},
459 \i\c{coff}, \i\c{elf} and \i\c{as86}) it will substitute \c{.o}. For
460 \i\c{rdf}, it will use \c{.rdf}, and for the \i\c{bin} format it
461 will simply remove the extension, so that \c{myfile.asm} produces
462 the output file \c{myfile}.
464 If the output file already exists, NASM will overwrite it, unless it
465 has the same name as the input file, in which case it will give a
466 warning and use \i\c{nasm.out} as the output file name instead.
468 For situations in which this behaviour is unacceptable, NASM
469 provides the \c{-o} command-line option, which allows you to specify
470 your desired output file name. You invoke \c{-o} by following it
471 with the name you wish for the output file, either with or without
472 an intervening space. For example:
474 \c nasm -f bin program.asm -o program.com
475 \c nasm -f bin driver.asm -odriver.sys
477 Note that this is a small o, and is different from a capital O , which
478 is used to specify the number of optimisation passes required. See \k{opt-On}.
481 \S{opt-f} The \i\c{-f} Option: Specifying the \i{Output File Format}
483 If you do not supply the \c{-f} option to NASM, it will choose an
484 output file format for you itself. In the distribution versions of
485 NASM, the default is always \i\c{bin}; if you've compiled your own
486 copy of NASM, you can redefine \i\c{OF_DEFAULT} at compile time and
487 choose what you want the default to be.
489 Like \c{-o}, the intervening space between \c{-f} and the output
490 file format is optional; so \c{-f elf} and \c{-felf} are both valid.
492 A complete list of the available output file formats can be given by
493 issuing the command \i\c{nasm -hf}.
496 \S{opt-l} The \i\c{-l} Option: Generating a \i{Listing File}
498 If you supply the \c{-l} option to NASM, followed (with the usual
499 optional space) by a file name, NASM will generate a
500 \i{source-listing file} for you, in which addresses and generated
501 code are listed on the left, and the actual source code, with
502 expansions of multi-line macros (except those which specifically
503 request no expansion in source listings: see \k{nolist}) on the
506 \c nasm -f elf myfile.asm -l myfile.lst
509 \S{opt-M} The \i\c{-M} Option: Generate \i{Makefile Dependencies}.
511 This option can be used to generate makefile dependencies on stdout.
512 This can be redirected to a file for further processing. For example:
514 \c NASM -M myfile.asm > myfile.dep
517 \S{opt-F} The \i\c{-F} Option: Selecting a \i{Debugging Format}
519 This option can be used to select a debugging format for the output file.
520 The syntax is the same as for the -f option, except that it produces
521 output in a debugging format.
523 A complete list of the available debug file formats for an output format
524 can be seen by issuing the command \i\c{nasm -f <format> -y}.
526 This option is not built into NASM by default. For information on how
527 to enable it when building from the sources, see \k{dbgfmt}
530 \S{opt-g} The \i\c{-g} Option: Enabling \i{Debug Information}.
532 This option can be used to generate debugging information in the specified
535 See \k{opt-F} for more information.
538 \S{opt-E} The \i\c{-E} Option: Send Errors to a File
540 Under \I{DOS}\c{MS-DOS} it can be difficult (though there are ways) to
541 redirect the standard-error output of a program to a file. Since
542 NASM usually produces its warning and \i{error messages} on
543 \i\c{stderr}, this can make it hard to capture the errors if (for
544 example) you want to load them into an editor.
546 NASM therefore provides the \c{-E} option, taking a filename argument
547 which causes errors to be sent to the specified files rather than
548 standard error. Therefore you can \I{redirecting errors}redirect
549 the errors into a file by typing
551 \c nasm -E myfile.err -f obj myfile.asm
554 \S{opt-s} The \i\c{-s} Option: Send Errors to \i\c{stdout}
556 The \c{-s} option redirects \i{error messages} to \c{stdout} rather
557 than \c{stderr}, so it can be redirected under \I{DOS}\c{MS-DOS}. To
558 assemble the file \c{myfile.asm} and pipe its output to the \c{more}
559 program, you can type:
561 \c nasm -s -f obj myfile.asm | more
563 See also the \c{-E} option, \k{opt-E}.
566 \S{opt-i} The \i\c{-i}\I\c{-I} Option: Include File Search Directories
568 When NASM sees the \i\c{%include} directive in a source file (see
569 \k{include}), it will search for the given file not only in the
570 current directory, but also in any directories specified on the
571 command line by the use of the \c{-i} option. Therefore you can
572 include files from a \i{macro library}, for example, by typing
574 \c nasm -ic:\macrolib\ -f obj myfile.asm
576 (As usual, a space between \c{-i} and the path name is allowed, and
579 NASM, in the interests of complete source-code portability, does not
580 understand the file naming conventions of the OS it is running on;
581 the string you provide as an argument to the \c{-i} option will be
582 prepended exactly as written to the name of the include file.
583 Therefore the trailing backslash in the above example is necessary.
584 Under Unix, a trailing forward slash is similarly necessary.
586 (You can use this to your advantage, if you're really \i{perverse},
587 by noting that the option \c{-ifoo} will cause \c{%include "bar.i"}
588 to search for the file \c{foobar.i}...)
590 If you want to define a \e{standard} \i{include search path},
591 similar to \c{/usr/include} on Unix systems, you should place one or
592 more \c{-i} directives in the \c{NASMENV} environment variable (see
595 For Makefile compatibility with many C compilers, this option can also
596 be specified as \c{-I}.
599 \S{opt-p} The \i\c{-p}\I\c{-P} Option: \I{pre-including files}Pre-Include a File
601 \I\c{%include}NASM allows you to specify files to be
602 \e{pre-included} into your source file, by the use of the \c{-p}
605 \c nasm myfile.asm -p myinc.inc
607 is equivalent to running \c{nasm myfile.asm} and placing the
608 directive \c{%include "myinc.inc"} at the start of the file.
610 For consistency with the \c{-I}, \c{-D} and \c{-U} options, this
611 option can also be specified as \c{-P}.
614 \S{opt-d} The \i\c{-d}\I\c{-D} Option: \I{pre-defining macros}Pre-Define a Macro
616 \I\c{%define}Just as the \c{-p} option gives an alternative to placing
617 \c{%include} directives at the start of a source file, the \c{-d}
618 option gives an alternative to placing a \c{%define} directive. You
621 \c nasm myfile.asm -dFOO=100
623 as an alternative to placing the directive
627 at the start of the file. You can miss off the macro value, as well:
628 the option \c{-dFOO} is equivalent to coding \c{%define FOO}. This
629 form of the directive may be useful for selecting \i{assembly-time
630 options} which are then tested using \c{%ifdef}, for example
633 For Makefile compatibility with many C compilers, this option can also
634 be specified as \c{-D}.
637 \S{opt-u} The \i\c{-u}\I\c{-U} Option: \I{Undefining macros}Undefine a Macro
639 \I\c{%undef}The \c{-u} option undefines a macro that would otherwise
640 have been pre-defined, either automatically or by a \c{-p} or \c{-d}
641 option specified earlier on the command lines.
643 For example, the following command line:
645 \c nasm myfile.asm -dFOO=100 -uFOO
647 would result in \c{FOO} \e{not} being a predefined macro in the
648 program. This is useful to override options specified at a different
651 For Makefile compatibility with many C compilers, this option can also
652 be specified as \c{-U}.
655 \S{opt-e} The \i\c{-e} Option: Preprocess Only
657 NASM allows the \i{preprocessor} to be run on its own, up to a
658 point. Using the \c{-e} option (which requires no arguments) will
659 cause NASM to preprocess its input file, expand all the macro
660 references, remove all the comments and preprocessor directives, and
661 print the resulting file on standard output (or save it to a file,
662 if the \c{-o} option is also used).
664 This option cannot be applied to programs which require the
665 preprocessor to evaluate \I{preprocessor expressions}\i{expressions}
666 which depend on the values of symbols: so code such as
668 \c %assign tablesize ($-tablestart)
670 will cause an error in \i{preprocess-only mode}.
673 \S{opt-a} The \i\c{-a} Option: Don't Preprocess At All
675 If NASM is being used as the back end to a compiler, it might be
676 desirable to \I{suppressing preprocessing}suppress preprocessing
677 completely and assume the compiler has already done it, to save time
678 and increase compilation speeds. The \c{-a} option, requiring no
679 argument, instructs NASM to replace its powerful \i{preprocessor}
680 with a \i{stub preprocessor} which does nothing.
683 \S{opt-On} The \i\c{-On} Option: Specifying \i{Multipass Optimization}.
685 NASM defaults to being a two pass assembler. This means that if you
686 have a complex source file which needs more than 2 passes to assemble
687 correctly, you have to tell it.
689 Using the \c{-O} option, you can tell NASM to carry out multiple passes.
692 \b \c{-O0} strict two-pass assembly, JMP and Jcc are handled more
693 like v0.98, except that backward JMPs are short, if possible.
694 Immediate operands take their long forms if a short form is
697 \b \c{-O1} strict two-pass assembly, but forward branches are assembled
698 with code guaranteed to reach; may produce larger code than
699 -O0, but will produce successful assembly more often if
700 branch offset sizes are not specified.
701 Additionally, immediate operands which will fit in a signed byte
702 are optimised, unless the long form is specified.
704 \b \c{-On} multi-pass optimization, minimize branch offsets; also will
705 minimize signed immediate bytes, overriding size specification
706 when the \c{strict} keyword hasn't been used (see \k{strict}).
707 If 2 <= n <= 3, then there are 5 * n passes, otherwise there
711 Note that this is a capital O, and is different from a small o, which
712 is used to specify the output format. See \k{opt-o}.
715 \S{opt-t} The \i\c{-t} option: Enable TASM Compatibility Mode
717 NASM includes a limited form of compatibility with Borland's \i\c{TASM}.
718 When NASM's \c{-t} option is used, the following changes are made:
720 \b local labels may be prefixed with \c{@@} instead of \c{.}
722 \b TASM-style response files beginning with \c{@} may be specified on
723 the command line. This is different from the \c{-@resp} style that NASM
726 \b size override is supported within brackets. In TASM compatible mode,
727 a size override inside square brackets changes the size of the operand,
728 and not the address type of the operand as it does in NASM syntax. E.g.
729 \c{mov eax,[DWORD val]} is valid syntax in TASM compatibility mode.
730 Note that you lose the ability to override the default address type for
733 \b \c{%arg} preprocessor directive is supported which is similar to
734 TASM's \c{ARG} directive.
736 \b \c{%local} preprocessor directive
738 \b \c{%stacksize} preprocessor directive
740 \b unprefixed forms of some directives supported (\c{arg}, \c{elif},
741 \c{else}, \c{endif}, \c{if}, \c{ifdef}, \c{ifdifi}, \c{ifndef},
742 \c{include}, \c{local})
746 For more information on the directives, see the section on TASM
747 Compatiblity preprocessor directives in \k{tasmcompat}.
750 \S{opt-w} The \i\c{-w} Option: Enable or Disable Assembly \i{Warnings}
752 NASM can observe many conditions during the course of assembly which
753 are worth mentioning to the user, but not a sufficiently severe
754 error to justify NASM refusing to generate an output file. These
755 conditions are reported like errors, but come up with the word
756 `warning' before the message. Warnings do not prevent NASM from
757 generating an output file and returning a success status to the
760 Some conditions are even less severe than that: they are only
761 sometimes worth mentioning to the user. Therefore NASM supports the
762 \c{-w} command-line option, which enables or disables certain
763 classes of assembly warning. Such warning classes are described by a
764 name, for example \c{orphan-labels}; you can enable warnings of
765 this class by the command-line option \c{-w+orphan-labels} and
766 disable it by \c{-w-orphan-labels}.
768 The \i{suppressible warning} classes are:
770 \b \i\c{macro-params} covers warnings about \i{multi-line macros}
771 being invoked with the wrong number of parameters. This warning
772 class is enabled by default; see \k{mlmacover} for an example of why
773 you might want to disable it.
775 \b \i\c{orphan-labels} covers warnings about source lines which
776 contain no instruction but define a label without a trailing colon.
777 NASM does not warn about this somewhat obscure condition by default;
778 see \k{syntax} for an example of why you might want it to.
780 \b \i\c{number-overflow} covers warnings about numeric constants which
781 don't fit in 32 bits (for example, it's easy to type one too many Fs
782 and produce \c{0x7ffffffff} by mistake). This warning class is
786 \S{opt-v} The \i\c{-v} Option: Display \i{Version} Info
788 Typing \c{NASM -v} will display the version of NASM which you are using,
789 and the date on which it was compiled.
791 You will need the version number if you report a bug.
794 \S{nasmenv} The \c{NASMENV} \i{Environment} Variable
796 If you define an environment variable called \c{NASMENV}, the program
797 will interpret it as a list of extra command-line options, which are
798 processed before the real command line. You can use this to define
799 standard search directories for include files, by putting \c{-i}
800 options in the \c{NASMENV} variable.
802 The value of the variable is split up at white space, so that the
803 value \c{-s -ic:\\nasmlib} will be treated as two separate options.
804 However, that means that the value \c{-dNAME="my name"} won't do
805 what you might want, because it will be split at the space and the
806 NASM command-line processing will get confused by the two
807 nonsensical words \c{-dNAME="my} and \c{name"}.
809 To get round this, NASM provides a feature whereby, if you begin the
810 \c{NASMENV} environment variable with some character that isn't a minus
811 sign, then NASM will treat this character as the \i{separator
812 character} for options. So setting the \c{NASMENV} variable to the
813 value \c{!-s!-ic:\\nasmlib} is equivalent to setting it to \c{-s
814 -ic:\\nasmlib}, but \c{!-dNAME="my name"} will work.
816 This environment variable was previously called \c{NASM}. This was
817 changed with version 0.98.31.
820 \H{qstart} \i{Quick Start} for \i{MASM} Users
822 If you're used to writing programs with MASM, or with \i{TASM} in
823 MASM-compatible (non-Ideal) mode, or with \i\c{a86}, this section
824 attempts to outline the major differences between MASM's syntax and
825 NASM's. If you're not already used to MASM, it's probably worth
826 skipping this section.
829 \S{qscs} NASM Is \I{case sensitivity}Case-Sensitive
831 One simple difference is that NASM is case-sensitive. It makes a
832 difference whether you call your label \c{foo}, \c{Foo} or \c{FOO}.
833 If you're assembling to \c{DOS} or \c{OS/2} \c{.OBJ} files, you can
834 invoke the \i\c{UPPERCASE} directive (documented in \k{objfmt}) to
835 ensure that all symbols exported to other code modules are forced
836 to be upper case; but even then, \e{within} a single module, NASM
837 will distinguish between labels differing only in case.
840 \S{qsbrackets} NASM Requires \i{Square Brackets} For \i{Memory References}
842 NASM was designed with simplicity of syntax in mind. One of the
843 \i{design goals} of NASM is that it should be possible, as far as is
844 practical, for the user to look at a single line of NASM code
845 and tell what opcode is generated by it. You can't do this in MASM:
846 if you declare, for example,
851 then the two lines of code
856 generate completely different opcodes, despite having
857 identical-looking syntaxes.
859 NASM avoids this undesirable situation by having a much simpler
860 syntax for memory references. The rule is simply that any access to
861 the \e{contents} of a memory location requires square brackets
862 around the address, and any access to the \e{address} of a variable
863 doesn't. So an instruction of the form \c{mov ax,foo} will
864 \e{always} refer to a compile-time constant, whether it's an \c{EQU}
865 or the address of a variable; and to access the \e{contents} of the
866 variable \c{bar}, you must code \c{mov ax,[bar]}.
868 This also means that NASM has no need for MASM's \i\c{OFFSET}
869 keyword, since the MASM code \c{mov ax,offset bar} means exactly the
870 same thing as NASM's \c{mov ax,bar}. If you're trying to get
871 large amounts of MASM code to assemble sensibly under NASM, you
872 can always code \c{%idefine offset} to make the preprocessor treat
873 the \c{OFFSET} keyword as a no-op.
875 This issue is even more confusing in \i\c{a86}, where declaring a
876 label with a trailing colon defines it to be a `label' as opposed to
877 a `variable' and causes \c{a86} to adopt NASM-style semantics; so in
878 \c{a86}, \c{mov ax,var} has different behaviour depending on whether
879 \c{var} was declared as \c{var: dw 0} (a label) or \c{var dw 0} (a
880 word-size variable). NASM is very simple by comparison:
881 \e{everything} is a label.
883 NASM, in the interests of simplicity, also does not support the
884 \i{hybrid syntaxes} supported by MASM and its clones, such as
885 \c{mov ax,table[bx]}, where a memory reference is denoted by one
886 portion outside square brackets and another portion inside. The
887 correct syntax for the above is \c{mov ax,[table+bx]}. Likewise,
888 \c{mov ax,es:[di]} is wrong and \c{mov ax,[es:di]} is right.
891 \S{qstypes} NASM Doesn't Store \i{Variable Types}
893 NASM, by design, chooses not to remember the types of variables you
894 declare. Whereas MASM will remember, on seeing \c{var dw 0}, that
895 you declared \c{var} as a word-size variable, and will then be able
896 to fill in the \i{ambiguity} in the size of the instruction \c{mov
897 var,2}, NASM will deliberately remember nothing about the symbol
898 \c{var} except where it begins, and so you must explicitly code
899 \c{mov word [var],2}.
901 For this reason, NASM doesn't support the \c{LODS}, \c{MOVS},
902 \c{STOS}, \c{SCAS}, \c{CMPS}, \c{INS}, or \c{OUTS} instructions,
903 but only supports the forms such as \c{LODSB}, \c{MOVSW}, and
904 \c{SCASD}, which explicitly specify the size of the components of
905 the strings being manipulated.
908 \S{qsassume} NASM Doesn't \i\c{ASSUME}
910 As part of NASM's drive for simplicity, it also does not support the
911 \c{ASSUME} directive. NASM will not keep track of what values you
912 choose to put in your segment registers, and will never
913 \e{automatically} generate a \i{segment override} prefix.
916 \S{qsmodel} NASM Doesn't Support \i{Memory Models}
918 NASM also does not have any directives to support different 16-bit
919 memory models. The programmer has to keep track of which functions
920 are supposed to be called with a \i{far call} and which with a
921 \i{near call}, and is responsible for putting the correct form of
922 \c{RET} instruction (\c{RETN} or \c{RETF}; NASM accepts \c{RET}
923 itself as an alternate form for \c{RETN}); in addition, the
924 programmer is responsible for coding CALL FAR instructions where
925 necessary when calling \e{external} functions, and must also keep
926 track of which external variable definitions are far and which are
930 \S{qsfpu} \i{Floating-Point} Differences
932 NASM uses different names to refer to floating-point registers from
933 MASM: where MASM would call them \c{ST(0)}, \c{ST(1)} and so on, and
934 \i\c{a86} would call them simply \c{0}, \c{1} and so on, NASM
935 chooses to call them \c{st0}, \c{st1} etc.
937 As of version 0.96, NASM now treats the instructions with
938 \i{`nowait'} forms in the same way as MASM-compatible assemblers.
939 The idiosyncratic treatment employed by 0.95 and earlier was based
940 on a misunderstanding by the authors.
943 \S{qsother} Other Differences
945 For historical reasons, NASM uses the keyword \i\c{TWORD} where MASM
946 and compatible assemblers use \i\c{TBYTE}.
948 NASM does not declare \i{uninitialised storage} in the same way as
949 MASM: where a MASM programmer might use \c{stack db 64 dup (?)},
950 NASM requires \c{stack resb 64}, intended to be read as `reserve 64
951 bytes'. For a limited amount of compatibility, since NASM treats
952 \c{?} as a valid character in symbol names, you can code \c{? equ 0}
953 and then writing \c{dw ?} will at least do something vaguely useful.
954 \I\c{RESB}\i\c{DUP} is still not a supported syntax, however.
956 In addition to all of this, macros and directives work completely
957 differently to MASM. See \k{preproc} and \k{directive} for further
961 \C{lang} The NASM Language
963 \H{syntax} Layout of a NASM Source Line
965 Like most assemblers, each NASM source line contains (unless it
966 is a macro, a preprocessor directive or an assembler directive: see
967 \k{preproc} and \k{directive}) some combination of the four fields
969 \c label: instruction operands ; comment
971 As usual, most of these fields are optional; the presence or absence
972 of any combination of a label, an instruction and a comment is allowed.
973 Of course, the operand field is either required or forbidden by the
974 presence and nature of the instruction field.
976 NASM uses backslash (\\) as the line continuation character; if a line
977 ends with backslash, the next line is considered to be a part of the
978 backslash-ended line.
980 NASM places no restrictions on white space within a line: labels may
981 have white space before them, or instructions may have no space
982 before them, or anything. The \i{colon} after a label is also
983 optional. (Note that this means that if you intend to code \c{lodsb}
984 alone on a line, and type \c{lodab} by accident, then that's still a
985 valid source line which does nothing but define a label. Running
986 NASM with the command-line option
987 \I{orphan-labels}\c{-w+orphan-labels} will cause it to warn you if
988 you define a label alone on a line without a \i{trailing colon}.)
990 \i{Valid characters} in labels are letters, numbers, \c{_}, \c{$},
991 \c{#}, \c{@}, \c{~}, \c{.}, and \c{?}. The only characters which may
992 be used as the \e{first} character of an identifier are letters,
993 \c{.} (with special meaning: see \k{locallab}), \c{_} and \c{?}.
994 An identifier may also be prefixed with a \I{$, prefix}\c{$} to
995 indicate that it is intended to be read as an identifier and not a
996 reserved word; thus, if some other module you are linking with
997 defines a symbol called \c{eax}, you can refer to \c{$eax} in NASM
998 code to distinguish the symbol from the register.
1000 The instruction field may contain any machine instruction: Pentium
1001 and P6 instructions, FPU instructions, MMX instructions and even
1002 undocumented instructions are all supported. The instruction may be
1003 prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or
1004 \c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size
1005 prefixes}address-size and \i{operand-size prefixes} \c{A16},
1006 \c{A32}, \c{O16} and \c{O32} are provided - one example of their use
1007 is given in \k{mixsize}. You can also use the name of a \I{segment
1008 override}segment register as an instruction prefix: coding
1009 \c{es mov [bx],ax} is equivalent to coding \c{mov [es:bx],ax}. We
1010 recommend the latter syntax, since it is consistent with other
1011 syntactic features of the language, but for instructions such as
1012 \c{LODSB}, which has no operands and yet can require a segment
1013 override, there is no clean syntactic way to proceed apart from
1016 An instruction is not required to use a prefix: prefixes such as
1017 \c{CS}, \c{A32}, \c{LOCK} or \c{REPE} can appear on a line by
1018 themselves, and NASM will just generate the prefix bytes.
1020 In addition to actual machine instructions, NASM also supports a
1021 number of pseudo-instructions, described in \k{pseudop}.
1023 Instruction \i{operands} may take a number of forms: they can be
1024 registers, described simply by the register name (e.g. \c{ax},
1025 \c{bp}, \c{ebx}, \c{cr0}: NASM does not use the \c{gas}-style
1026 syntax in which register names must be prefixed by a \c{%} sign), or
1027 they can be \i{effective addresses} (see \k{effaddr}), constants
1028 (\k{const}) or expressions (\k{expr}).
1030 For \i{floating-point} instructions, NASM accepts a wide range of
1031 syntaxes: you can use two-operand forms like MASM supports, or you
1032 can use NASM's native single-operand forms in most cases. Details of
1033 all forms of each supported instruction are given in
1034 \k{iref}. For example, you can code:
1036 \c fadd st1 ; this sets st0 := st0 + st1
1037 \c fadd st0,st1 ; so does this
1039 \c fadd st1,st0 ; this sets st1 := st1 + st0
1040 \c fadd to st1 ; so does this
1042 Almost any floating-point instruction that references memory must
1043 use one of the prefixes \i\c{DWORD}, \i\c{QWORD} or \i\c{TWORD} to
1044 indicate what size of \i{memory operand} it refers to.
1047 \H{pseudop} \i{Pseudo-Instructions}
1049 Pseudo-instructions are things which, though not real x86 machine
1050 instructions, are used in the instruction field anyway because
1051 that's the most convenient place to put them. The current
1052 pseudo-instructions are \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and
1053 \i\c{DT}, their \i{uninitialised} counterparts \i\c{RESB},
1054 \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST}, the \i\c{INCBIN}
1055 command, the \i\c{EQU} command, and the \i\c{TIMES} prefix.
1058 \S{db} \c{DB} and friends: Declaring Initialised Data
1060 \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and \i\c{DT} are used, much
1061 as in MASM, to declare initialised data in the output file. They can
1062 be invoked in a wide range of ways:
1063 \I{floating-point}\I{character constant}\I{string constant}
1065 \c db 0x55 ; just the byte 0x55
1066 \c db 0x55,0x56,0x57 ; three bytes in succession
1067 \c db 'a',0x55 ; character constants are OK
1068 \c db 'hello',13,10,'$' ; so are string constants
1069 \c dw 0x1234 ; 0x34 0x12
1070 \c dw 'a' ; 0x41 0x00 (it's just a number)
1071 \c dw 'ab' ; 0x41 0x42 (character constant)
1072 \c dw 'abc' ; 0x41 0x42 0x43 0x00 (string)
1073 \c dd 0x12345678 ; 0x78 0x56 0x34 0x12
1074 \c dd 1.234567e20 ; floating-point constant
1075 \c dq 1.234567e20 ; double-precision float
1076 \c dt 1.234567e20 ; extended-precision float
1078 \c{DQ} and \c{DT} do not accept \i{numeric constants} or string
1079 constants as operands.
1082 \S{resb} \c{RESB} and friends: Declaring \i{Uninitialised} Data
1084 \i\c{RESB}, \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST} are
1085 designed to be used in the BSS section of a module: they declare
1086 \e{uninitialised} storage space. Each takes a single operand, which
1087 is the number of bytes, words, doublewords or whatever to reserve.
1088 As stated in \k{qsother}, NASM does not support the MASM/TASM syntax
1089 of reserving uninitialised space by writing \I\c{?}\c{DW ?} or
1090 similar things: this is what it does instead. The operand to a
1091 \c{RESB}-type pseudo-instruction is a \i\e{critical expression}: see
1096 \c buffer: resb 64 ; reserve 64 bytes
1097 \c wordvar: resw 1 ; reserve a word
1098 \c realarray resq 10 ; array of ten reals
1101 \S{incbin} \i\c{INCBIN}: Including External \i{Binary Files}
1103 \c{INCBIN} is borrowed from the old Amiga assembler \i{DevPac}: it
1104 includes a binary file verbatim into the output file. This can be
1105 handy for (for example) including \i{graphics} and \i{sound} data
1106 directly into a game executable file. It can be called in one of
1109 \c incbin "file.dat" ; include the whole file
1110 \c incbin "file.dat",1024 ; skip the first 1024 bytes
1111 \c incbin "file.dat",1024,512 ; skip the first 1024, and
1112 \c ; actually include at most 512
1115 \S{equ} \i\c{EQU}: Defining Constants
1117 \c{EQU} defines a symbol to a given constant value: when \c{EQU} is
1118 used, the source line must contain a label. The action of \c{EQU} is
1119 to define the given label name to the value of its (only) operand.
1120 This definition is absolute, and cannot change later. So, for
1123 \c message db 'hello, world'
1124 \c msglen equ $-message
1126 defines \c{msglen} to be the constant 12. \c{msglen} may not then be
1127 redefined later. This is not a \i{preprocessor} definition either:
1128 the value of \c{msglen} is evaluated \e{once}, using the value of
1129 \c{$} (see \k{expr} for an explanation of \c{$}) at the point of
1130 definition, rather than being evaluated wherever it is referenced
1131 and using the value of \c{$} at the point of reference. Note that
1132 the operand to an \c{EQU} is also a \i{critical expression}
1136 \S{times} \i\c{TIMES}: \i{Repeating} Instructions or Data
1138 The \c{TIMES} prefix causes the instruction to be assembled multiple
1139 times. This is partly present as NASM's equivalent of the \i\c{DUP}
1140 syntax supported by \i{MASM}-compatible assemblers, in that you can
1143 \c zerobuf: times 64 db 0
1145 or similar things; but \c{TIMES} is more versatile than that. The
1146 argument to \c{TIMES} is not just a numeric constant, but a numeric
1147 \e{expression}, so you can do things like
1149 \c buffer: db 'hello, world'
1150 \c times 64-$+buffer db ' '
1152 which will store exactly enough spaces to make the total length of
1153 \c{buffer} up to 64. Finally, \c{TIMES} can be applied to ordinary
1154 instructions, so you can code trivial \i{unrolled loops} in it:
1158 Note that there is no effective difference between \c{times 100 resb
1159 1} and \c{resb 100}, except that the latter will be assembled about
1160 100 times faster due to the internal structure of the assembler.
1162 The operand to \c{TIMES}, like that of \c{EQU} and those of \c{RESB}
1163 and friends, is a critical expression (\k{crit}).
1165 Note also that \c{TIMES} can't be applied to \i{macros}: the reason
1166 for this is that \c{TIMES} is processed after the macro phase, which
1167 allows the argument to \c{TIMES} to contain expressions such as
1168 \c{64-$+buffer} as above. To repeat more than one line of code, or a
1169 complex macro, use the preprocessor \i\c{%rep} directive.
1172 \H{effaddr} Effective Addresses
1174 An \i{effective address} is any operand to an instruction which
1175 \I{memory reference}references memory. Effective addresses, in NASM,
1176 have a very simple syntax: they consist of an expression evaluating
1177 to the desired address, enclosed in \i{square brackets}. For
1182 \c mov ax,[wordvar+1]
1183 \c mov ax,[es:wordvar+bx]
1185 Anything not conforming to this simple system is not a valid memory
1186 reference in NASM, for example \c{es:wordvar[bx]}.
1188 More complicated effective addresses, such as those involving more
1189 than one register, work in exactly the same way:
1191 \c mov eax,[ebx*2+ecx+offset]
1194 NASM is capable of doing \i{algebra} on these effective addresses,
1195 so that things which don't necessarily \e{look} legal are perfectly
1198 \c mov eax,[ebx*5] ; assembles as [ebx*4+ebx]
1199 \c mov eax,[label1*2-label2] ; ie [label1+(label1-label2)]
1201 Some forms of effective address have more than one assembled form;
1202 in most such cases NASM will generate the smallest form it can. For
1203 example, there are distinct assembled forms for the 32-bit effective
1204 addresses \c{[eax*2+0]} and \c{[eax+eax]}, and NASM will generally
1205 generate the latter on the grounds that the former requires four
1206 bytes to store a zero offset.
1208 NASM has a hinting mechanism which will cause \c{[eax+ebx]} and
1209 \c{[ebx+eax]} to generate different opcodes; this is occasionally
1210 useful because \c{[esi+ebp]} and \c{[ebp+esi]} have different
1211 default segment registers.
1213 However, you can force NASM to generate an effective address in a
1214 particular form by the use of the keywords \c{BYTE}, \c{WORD},
1215 \c{DWORD} and \c{NOSPLIT}. If you need \c{[eax+3]} to be assembled
1216 using a double-word offset field instead of the one byte NASM will
1217 normally generate, you can code \c{[dword eax+3]}. Similarly, you
1218 can force NASM to use a byte offset for a small value which it
1219 hasn't seen on the first pass (see \k{crit} for an example of such a
1220 code fragment) by using \c{[byte eax+offset]}. As special cases,
1221 \c{[byte eax]} will code \c{[eax+0]} with a byte offset of zero, and
1222 \c{[dword eax]} will code it with a double-word offset of zero. The
1223 normal form, \c{[eax]}, will be coded with no offset field.
1225 The form described in the previous paragraph is also useful if you
1226 are trying to access data in a 32-bit segment from within 16 bit code.
1227 For more information on this see the section on mixed-size addressing
1228 (\k{mixaddr}). In particular, if you need to access data with a known
1229 offset that is larger than will fit in a 16-bit value, if you don't
1230 specify that it is a dword offset, nasm will cause the high word of
1231 the offset to be lost.
1233 Similarly, NASM will split \c{[eax*2]} into \c{[eax+eax]} because
1234 that allows the offset field to be absent and space to be saved; in
1235 fact, it will also split \c{[eax*2+offset]} into
1236 \c{[eax+eax+offset]}. You can combat this behaviour by the use of
1237 the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force
1238 \c{[eax*2+0]} to be generated literally.
1241 \H{const} \i{Constants}
1243 NASM understands four different types of constant: numeric,
1244 character, string and floating-point.
1247 \S{numconst} \i{Numeric Constants}
1249 A numeric constant is simply a number. NASM allows you to specify
1250 numbers in a variety of number bases, in a variety of ways: you can
1251 suffix \c{H}, \c{Q} and \c{B} for \i{hex}, \i{octal} and \i{binary},
1252 or you can prefix \c{0x} for hex in the style of C, or you can
1253 prefix \c{$} for hex in the style of Borland Pascal. Note, though,
1254 that the \I{$, prefix}\c{$} prefix does double duty as a prefix on
1255 identifiers (see \k{syntax}), so a hex number prefixed with a \c{$}
1256 sign must have a digit after the \c{$} rather than a letter.
1260 \c mov ax,100 ; decimal
1261 \c mov ax,0a2h ; hex
1262 \c mov ax,$0a2 ; hex again: the 0 is required
1263 \c mov ax,0xa2 ; hex yet again
1264 \c mov ax,777q ; octal
1265 \c mov ax,10010011b ; binary
1268 \S{chrconst} \i{Character Constants}
1270 A character constant consists of up to four characters enclosed in
1271 either single or double quotes. The type of quote makes no
1272 difference to NASM, except of course that surrounding the constant
1273 with single quotes allows double quotes to appear within it and vice
1276 A character constant with more than one character will be arranged
1277 with \i{little-endian} order in mind: if you code
1281 then the constant generated is not \c{0x61626364}, but
1282 \c{0x64636261}, so that if you were then to store the value into
1283 memory, it would read \c{abcd} rather than \c{dcba}. This is also
1284 the sense of character constants understood by the Pentium's
1285 \i\c{CPUID} instruction (see \k{insCPUID}).
1288 \S{strconst} String Constants
1290 String constants are only acceptable to some pseudo-instructions,
1291 namely the \I\c{DW}\I\c{DD}\I\c{DQ}\I\c{DT}\i\c{DB} family and
1294 A string constant looks like a character constant, only longer. It
1295 is treated as a concatenation of maximum-size character constants
1296 for the conditions. So the following are equivalent:
1298 \c db 'hello' ; string constant
1299 \c db 'h','e','l','l','o' ; equivalent character constants
1301 And the following are also equivalent:
1303 \c dd 'ninechars' ; doubleword string constant
1304 \c dd 'nine','char','s' ; becomes three doublewords
1305 \c db 'ninechars',0,0,0 ; and really looks like this
1307 Note that when used as an operand to \c{db}, a constant like
1308 \c{'ab'} is treated as a string constant despite being short enough
1309 to be a character constant, because otherwise \c{db 'ab'} would have
1310 the same effect as \c{db 'a'}, which would be silly. Similarly,
1311 three-character or four-character constants are treated as strings
1312 when they are operands to \c{dw}.
1315 \S{fltconst} \I{floating-point, constants}Floating-Point Constants
1317 \i{Floating-point} constants are acceptable only as arguments to
1318 \i\c{DD}, \i\c{DQ} and \i\c{DT}. They are expressed in the
1319 traditional form: digits, then a period, then optionally more
1320 digits, then optionally an \c{E} followed by an exponent. The period
1321 is mandatory, so that NASM can distinguish between \c{dd 1}, which
1322 declares an integer constant, and \c{dd 1.0} which declares a
1323 floating-point constant.
1327 \c dd 1.2 ; an easy one
1328 \c dq 1.e10 ; 10,000,000,000
1329 \c dq 1.e+10 ; synonymous with 1.e10
1330 \c dq 1.e-10 ; 0.000 000 000 1
1331 \c dt 3.141592653589793238462 ; pi
1333 NASM cannot do compile-time arithmetic on floating-point constants.
1334 This is because NASM is designed to be portable - although it always
1335 generates code to run on x86 processors, the assembler itself can
1336 run on any system with an ANSI C compiler. Therefore, the assembler
1337 cannot guarantee the presence of a floating-point unit capable of
1338 handling the \i{Intel number formats}, and so for NASM to be able to
1339 do floating arithmetic it would have to include its own complete set
1340 of floating-point routines, which would significantly increase the
1341 size of the assembler for very little benefit.
1344 \H{expr} \i{Expressions}
1346 Expressions in NASM are similar in syntax to those in C.
1348 NASM does not guarantee the size of the integers used to evaluate
1349 expressions at compile time: since NASM can compile and run on
1350 64-bit systems quite happily, don't assume that expressions are
1351 evaluated in 32-bit registers and so try to make deliberate use of
1352 \i{integer overflow}. It might not always work. The only thing NASM
1353 will guarantee is what's guaranteed by ANSI C: you always have \e{at
1354 least} 32 bits to work in.
1356 NASM supports two special tokens in expressions, allowing
1357 calculations to involve the current assembly position: the
1358 \I{$, here}\c{$} and \i\c{$$} tokens. \c{$} evaluates to the assembly
1359 position at the beginning of the line containing the expression; so
1360 you can code an \i{infinite loop} using \c{JMP $}. \c{$$} evaluates
1361 to the beginning of the current section; so you can tell how far
1362 into the section you are by using \c{($-$$)}.
1364 The arithmetic \i{operators} provided by NASM are listed here, in
1365 increasing order of \i{precedence}.
1368 \S{expor} \i\c{|}: \i{Bitwise OR} Operator
1370 The \c{|} operator gives a bitwise OR, exactly as performed by the
1371 \c{OR} machine instruction. Bitwise OR is the lowest-priority
1372 arithmetic operator supported by NASM.
1375 \S{expxor} \i\c{^}: \i{Bitwise XOR} Operator
1377 \c{^} provides the bitwise XOR operation.
1380 \S{expand} \i\c{&}: \i{Bitwise AND} Operator
1382 \c{&} provides the bitwise AND operation.
1385 \S{expshift} \i\c{<<} and \i\c{>>}: \i{Bit Shift} Operators
1387 \c{<<} gives a bit-shift to the left, just as it does in C. So \c{5<<3}
1388 evaluates to 5 times 8, or 40. \c{>>} gives a bit-shift to the
1389 right; in NASM, such a shift is \e{always} unsigned, so that
1390 the bits shifted in from the left-hand end are filled with zero
1391 rather than a sign-extension of the previous highest bit.
1394 \S{expplmi} \I{+ opaddition}\c{+} and \I{- opsubtraction}\c{-}:
1395 \i{Addition} and \i{Subtraction} Operators
1397 The \c{+} and \c{-} operators do perfectly ordinary addition and
1401 \S{expmul} \i\c{*}, \i\c{/}, \i\c{//}, \i\c{%} and \i\c{%%}:
1402 \i{Multiplication} and \i{Division}
1404 \c{*} is the multiplication operator. \c{/} and \c{//} are both
1405 division operators: \c{/} is \i{unsigned division} and \c{//} is
1406 \i{signed division}. Similarly, \c{%} and \c{%%} provide \I{unsigned
1407 modulo}\I{modulo operators}unsigned and
1408 \i{signed modulo} operators respectively.
1410 NASM, like ANSI C, provides no guarantees about the sensible
1411 operation of the signed modulo operator.
1413 Since the \c{%} character is used extensively by the macro
1414 \i{preprocessor}, you should ensure that both the signed and unsigned
1415 modulo operators are followed by white space wherever they appear.
1418 \S{expmul} \i{Unary Operators}: \I{+ opunary}\c{+}, \I{- opunary}\c{-},
1419 \i\c{~} and \i\c{SEG}
1421 The highest-priority operators in NASM's expression grammar are
1422 those which only apply to one argument. \c{-} negates its operand,
1423 \c{+} does nothing (it's provided for symmetry with \c{-}), \c{~}
1424 computes the \i{one's complement} of its operand, and \c{SEG}
1425 provides the \i{segment address} of its operand (explained in more
1426 detail in \k{segwrt}).
1429 \H{segwrt} \i\c{SEG} and \i\c{WRT}
1431 When writing large 16-bit programs, which must be split into
1432 multiple \i{segments}, it is often necessary to be able to refer to
1433 the \I{segment address}segment part of the address of a symbol. NASM
1434 supports the \c{SEG} operator to perform this function.
1436 The \c{SEG} operator returns the \i\e{preferred} segment base of a
1437 symbol, defined as the segment base relative to which the offset of
1438 the symbol makes sense. So the code
1440 \c mov ax,seg symbol
1444 will load \c{ES:BX} with a valid pointer to the symbol \c{symbol}.
1446 Things can be more complex than this: since 16-bit segments and
1447 \i{groups} may \I{overlapping segments}overlap, you might occasionally
1448 want to refer to some symbol using a different segment base from the
1449 preferred one. NASM lets you do this, by the use of the \c{WRT}
1450 (With Reference To) keyword. So you can do things like
1452 \c mov ax,weird_seg ; weird_seg is a segment base
1454 \c mov bx,symbol wrt weird_seg
1456 to load \c{ES:BX} with a different, but functionally equivalent,
1457 pointer to the symbol \c{symbol}.
1459 NASM supports far (inter-segment) calls and jumps by means of the
1460 syntax \c{call segment:offset}, where \c{segment} and \c{offset}
1461 both represent immediate values. So to call a far procedure, you
1462 could code either of
1464 \c call (seg procedure):procedure
1465 \c call weird_seg:(procedure wrt weird_seg)
1467 (The parentheses are included for clarity, to show the intended
1468 parsing of the above instructions. They are not necessary in
1471 NASM supports the syntax \I\c{CALL FAR}\c{call far procedure} as a
1472 synonym for the first of the above usages. \c{JMP} works identically
1473 to \c{CALL} in these examples.
1475 To declare a \i{far pointer} to a data item in a data segment, you
1478 \c dw symbol, seg symbol
1480 NASM supports no convenient synonym for this, though you can always
1481 invent one using the macro processor.
1484 \H{strict} \i\c{STRICT}: Inhibiting Optimization
1486 When assembling with the optimizer set to level 2 or higher (see
1487 \k{opt-On}), NASM will usee size specifiers (\c{BYTE}, \c{WORD},
1488 \c{DWORD}, \c{QWORD}, or \c{TWORD}), but will give them the smallest
1489 possible size. The keyword \c{STRICT} can be used to inhibit
1490 optimization and force a particular operand to be emitted in the
1491 specified size. For example, with the optimizer on, and in
1496 is encoded in three bytes \c{66 6A 21}, whereas
1498 \c push strict dword 33
1500 is encoded in six bytes, with a full dword immediate operand \c{66 68
1503 With the optimizer off, the same code (six bytes) is generated whether
1504 the \c{STRICT} keyword was used or not.
1507 \H{crit} \i{Critical Expressions}
1509 A limitation of NASM is that it is a \i{two-pass assembler}; unlike
1510 TASM and others, it will always do exactly two \I{passes}\i{assembly
1511 passes}. Therefore it is unable to cope with source files that are
1512 complex enough to require three or more passes.
1514 The first pass is used to determine the size of all the assembled
1515 code and data, so that the second pass, when generating all the
1516 code, knows all the symbol addresses the code refers to. So one
1517 thing NASM can't handle is code whose size depends on the value of a
1518 symbol declared after the code in question. For example,
1520 \c times (label-$) db 0
1521 \c label: db 'Where am I?'
1523 The argument to \i\c{TIMES} in this case could equally legally
1524 evaluate to anything at all; NASM will reject this example because
1525 it cannot tell the size of the \c{TIMES} line when it first sees it.
1526 It will just as firmly reject the slightly \I{paradox}paradoxical
1529 \c times (label-$+1) db 0
1530 \c label: db 'NOW where am I?'
1532 in which \e{any} value for the \c{TIMES} argument is by definition
1535 NASM rejects these examples by means of a concept called a
1536 \e{critical expression}, which is defined to be an expression whose
1537 value is required to be computable in the first pass, and which must
1538 therefore depend only on symbols defined before it. The argument to
1539 the \c{TIMES} prefix is a critical expression; for the same reason,
1540 the arguments to the \i\c{RESB} family of pseudo-instructions are
1541 also critical expressions.
1543 Critical expressions can crop up in other contexts as well: consider
1547 \c symbol1 equ symbol2
1550 On the first pass, NASM cannot determine the value of \c{symbol1},
1551 because \c{symbol1} is defined to be equal to \c{symbol2} which NASM
1552 hasn't seen yet. On the second pass, therefore, when it encounters
1553 the line \c{mov ax,symbol1}, it is unable to generate the code for
1554 it because it still doesn't know the value of \c{symbol1}. On the
1555 next line, it would see the \i\c{EQU} again and be able to determine
1556 the value of \c{symbol1}, but by then it would be too late.
1558 NASM avoids this problem by defining the right-hand side of an
1559 \c{EQU} statement to be a critical expression, so the definition of
1560 \c{symbol1} would be rejected in the first pass.
1562 There is a related issue involving \i{forward references}: consider
1565 \c mov eax,[ebx+offset]
1568 NASM, on pass one, must calculate the size of the instruction \c{mov
1569 eax,[ebx+offset]} without knowing the value of \c{offset}. It has no
1570 way of knowing that \c{offset} is small enough to fit into a
1571 one-byte offset field and that it could therefore get away with
1572 generating a shorter form of the \i{effective-address} encoding; for
1573 all it knows, in pass one, \c{offset} could be a symbol in the code
1574 segment, and it might need the full four-byte form. So it is forced
1575 to compute the size of the instruction to accommodate a four-byte
1576 address part. In pass two, having made this decision, it is now
1577 forced to honour it and keep the instruction large, so the code
1578 generated in this case is not as small as it could have been. This
1579 problem can be solved by defining \c{offset} before using it, or by
1580 forcing byte size in the effective address by coding \c{[byte
1584 \H{locallab} \i{Local Labels}
1586 NASM gives special treatment to symbols beginning with a \i{period}.
1587 A label beginning with a single period is treated as a \e{local}
1588 label, which means that it is associated with the previous non-local
1589 label. So, for example:
1591 \c label1 ; some code
1599 \c label2 ; some code
1607 In the above code fragment, each \c{JNE} instruction jumps to the
1608 line immediately before it, because the two definitions of \c{.loop}
1609 are kept separate by virtue of each being associated with the
1610 previous non-local label.
1612 This form of local label handling is borrowed from the old Amiga
1613 assembler \i{DevPac}; however, NASM goes one step further, in
1614 allowing access to local labels from other parts of the code. This
1615 is achieved by means of \e{defining} a local label in terms of the
1616 previous non-local label: the first definition of \c{.loop} above is
1617 really defining a symbol called \c{label1.loop}, and the second
1618 defines a symbol called \c{label2.loop}. So, if you really needed
1621 \c label3 ; some more code
1626 Sometimes it is useful - in a macro, for instance - to be able to
1627 define a label which can be referenced from anywhere but which
1628 doesn't interfere with the normal local-label mechanism. Such a
1629 label can't be non-local because it would interfere with subsequent
1630 definitions of, and references to, local labels; and it can't be
1631 local because the macro that defined it wouldn't know the label's
1632 full name. NASM therefore introduces a third type of label, which is
1633 probably only useful in macro definitions: if a label begins with
1634 the \I{label prefix}special prefix \i\c{..@}, then it does nothing
1635 to the local label mechanism. So you could code
1637 \c label1: ; a non-local label
1638 \c .local: ; this is really label1.local
1639 \c ..@foo: ; this is a special symbol
1640 \c label2: ; another non-local label
1641 \c .local: ; this is really label2.local
1643 \c jmp ..@foo ; this will jump three lines up
1645 NASM has the capacity to define other special symbols beginning with
1646 a double period: for example, \c{..start} is used to specify the
1647 entry point in the \c{obj} output format (see \k{dotdotstart}).
1650 \C{preproc} The NASM \i{Preprocessor}
1652 NASM contains a powerful \i{macro processor}, which supports
1653 conditional assembly, multi-level file inclusion, two forms of macro
1654 (single-line and multi-line), and a `context stack' mechanism for
1655 extra macro power. Preprocessor directives all begin with a \c{%}
1658 The preprocessor collapses all lines which end with a backslash (\\)
1659 character into a single line. Thus:
1661 \c %define THIS_VERY_LONG_MACRO_NAME_IS_DEFINED_TO \\
1664 will work like a single-line macro without the backslash-newline
1667 \H{slmacro} \i{Single-Line Macros}
1669 \S{define} The Normal Way: \I\c{%idefine}\i\c{%define}
1671 Single-line macros are defined using the \c{%define} preprocessor
1672 directive. The definitions work in a similar way to C; so you can do
1675 \c %define ctrl 0x1F &
1676 \c %define param(a,b) ((a)+(a)*(b))
1678 \c mov byte [param(2,ebx)], ctrl 'D'
1680 which will expand to
1682 \c mov byte [(2)+(2)*(ebx)], 0x1F & 'D'
1684 When the expansion of a single-line macro contains tokens which
1685 invoke another macro, the expansion is performed at invocation time,
1686 not at definition time. Thus the code
1688 \c %define a(x) 1+b(x)
1693 will evaluate in the expected way to \c{mov ax,1+2*8}, even though
1694 the macro \c{b} wasn't defined at the time of definition of \c{a}.
1696 Macros defined with \c{%define} are \i{case sensitive}: after
1697 \c{%define foo bar}, only \c{foo} will expand to \c{bar}: \c{Foo} or
1698 \c{FOO} will not. By using \c{%idefine} instead of \c{%define} (the
1699 `i' stands for `insensitive') you can define all the case variants
1700 of a macro at once, so that \c{%idefine foo bar} would cause
1701 \c{foo}, \c{Foo}, \c{FOO}, \c{fOO} and so on all to expand to
1704 There is a mechanism which detects when a macro call has occurred as
1705 a result of a previous expansion of the same macro, to guard against
1706 \i{circular references} and infinite loops. If this happens, the
1707 preprocessor will only expand the first occurrence of the macro.
1710 \c %define a(x) 1+a(x)
1714 the macro \c{a(3)} will expand once, becoming \c{1+a(3)}, and will
1715 then expand no further. This behaviour can be useful: see \k{32c}
1716 for an example of its use.
1718 You can \I{overloading, single-line macros}overload single-line
1719 macros: if you write
1721 \c %define foo(x) 1+x
1722 \c %define foo(x,y) 1+x*y
1724 the preprocessor will be able to handle both types of macro call,
1725 by counting the parameters you pass; so \c{foo(3)} will become
1726 \c{1+3} whereas \c{foo(ebx,2)} will become \c{1+ebx*2}. However, if
1731 then no other definition of \c{foo} will be accepted: a macro with
1732 no parameters prohibits the definition of the same name as a macro
1733 \e{with} parameters, and vice versa.
1735 This doesn't prevent single-line macros being \e{redefined}: you can
1736 perfectly well define a macro with
1740 and then re-define it later in the same source file with
1744 Then everywhere the macro \c{foo} is invoked, it will be expanded
1745 according to the most recent definition. This is particularly useful
1746 when defining single-line macros with \c{%assign} (see \k{assign}).
1748 You can \i{pre-define} single-line macros using the `-d' option on
1749 the NASM command line: see \k{opt-d}.
1752 \S{concat%+} Concatenating Single Line Macro Tokens: \i\c{%+}
1754 Individual tokens in single line macros can be concatenated, to produce
1755 longer tokens for later processing. This can be useful if there are
1756 several similar macros that perform similar functions.
1758 As an example, consider the following:
1760 \c %define BDASTART 400h ; Start of BIOS data area
1762 \c struc tBIOSDA ; its structure
1768 Now, if we need to access the elements of tBIOSDA in different places,
1771 \c mov ax,BDASTART + tBIOSDA.COM1addr
1772 \c mov bx,BDASTART + tBIOSDA.COM2addr
1774 This will become pretty ugly (and tedious) if used in many places, and
1775 can be reduced in size significantly by using the following macro:
1777 \c ; Macro to access BIOS variables by their names (from tBDA):
1779 \c %define BDA(x) BDASTART + tBIOSDA. %+ x
1781 Now the above code can be written as:
1783 \c mov ax,BDA(COM1addr)
1784 \c mov bx,BDA(COM2addr)
1786 Using this feature, we can simplify references to a lot of macros (and,
1787 in turn, reduce typing errors).
1790 \S{undef} Undefining macros: \i\c{%undef}
1792 Single-line macros can be removed with the \c{%undef} command. For
1793 example, the following sequence:
1800 will expand to the instruction \c{mov eax, foo}, since after
1801 \c{%undef} the macro \c{foo} is no longer defined.
1803 Macros that would otherwise be pre-defined can be undefined on the
1804 command-line using the `-u' option on the NASM command line: see
1808 \S{assign} \i{Preprocessor Variables}: \i\c{%assign}
1810 An alternative way to define single-line macros is by means of the
1811 \c{%assign} command (and its \i{case sensitive}case-insensitive
1812 counterpart \i\c{%iassign}, which differs from \c{%assign} in
1813 exactly the same way that \c{%idefine} differs from \c{%define}).
1815 \c{%assign} is used to define single-line macros which take no
1816 parameters and have a numeric value. This value can be specified in
1817 the form of an expression, and it will be evaluated once, when the
1818 \c{%assign} directive is processed.
1820 Like \c{%define}, macros defined using \c{%assign} can be re-defined
1821 later, so you can do things like
1825 to increment the numeric value of a macro.
1827 \c{%assign} is useful for controlling the termination of \c{%rep}
1828 preprocessor loops: see \k{rep} for an example of this. Another
1829 use for \c{%assign} is given in \k{16c} and \k{32c}.
1831 The expression passed to \c{%assign} is a \i{critical expression}
1832 (see \k{crit}), and must also evaluate to a pure number (rather than
1833 a relocatable reference such as a code or data address, or anything
1834 involving a register).
1837 \H{strlen} \i{String Handling in Macros}: \i\c{%strlen} and \i\c{%substr}
1839 It's often useful to be able to handle strings in macros. NASM
1840 supports two simple string handling macro operators from which
1841 more complex operations can be constructed.
1844 \S{strlen} \i{String Length}: \i\c{%strlen}
1846 The \c{%strlen} macro is like \c{%assign} macro in that it creates
1847 (or redefines) a numeric value to a macro. The difference is that
1848 with \c{%strlen}, the numeric value is the length of a string. An
1849 example of the use of this would be:
1851 \c %strlen charcnt 'my string'
1853 In this example, \c{charcnt} would receive the value 8, just as
1854 if an \c{%assign} had been used. In this example, \c{'my string'}
1855 was a literal string but it could also have been a single-line
1856 macro that expands to a string, as in the following example:
1858 \c %define sometext 'my string'
1859 \c %strlen charcnt sometext
1861 As in the first case, this would result in \c{charcnt} being
1862 assigned the value of 8.
1865 \S{substr} \i{Sub-strings}: \i\c{%substr}
1867 Individual letters in strings can be extracted using \c{%substr}.
1868 An example of its use is probably more useful than the description:
1870 \c %substr mychar 'xyz' 1 ; equivalent to %define mychar 'x'
1871 \c %substr mychar 'xyz' 2 ; equivalent to %define mychar 'y'
1872 \c %substr mychar 'xyz' 3 ; equivalent to %define mychar 'z'
1874 In this example, mychar gets the value of 'y'. As with \c{%strlen}
1875 (see \k{strlen}), the first parameter is the single-line macro to
1876 be created and the second is the string. The third parameter
1877 specifies which character is to be selected. Note that the first
1878 index is 1, not 0 and the last index is equal to the value that
1879 \c{%strlen} would assign given the same string. Index values out
1880 of range result in an empty string.
1883 \H{mlmacro} \i{Multi-Line Macros}: \I\c{%imacro}\i\c{%macro}
1885 Multi-line macros are much more like the type of macro seen in MASM
1886 and TASM: a multi-line macro definition in NASM looks something like
1889 \c %macro prologue 1
1897 This defines a C-like function prologue as a macro: so you would
1898 invoke the macro with a call such as
1900 \c myfunc: prologue 12
1902 which would expand to the three lines of code
1908 The number \c{1} after the macro name in the \c{%macro} line defines
1909 the number of parameters the macro \c{prologue} expects to receive.
1910 The use of \c{%1} inside the macro definition refers to the first
1911 parameter to the macro call. With a macro taking more than one
1912 parameter, subsequent parameters would be referred to as \c{%2},
1915 Multi-line macros, like single-line macros, are \i{case-sensitive},
1916 unless you define them using the alternative directive \c{%imacro}.
1918 If you need to pass a comma as \e{part} of a parameter to a
1919 multi-line macro, you can do that by enclosing the entire parameter
1920 in \I{braces, around macro parameters}braces. So you could code
1929 \c silly 'a', letter_a ; letter_a: db 'a'
1930 \c silly 'ab', string_ab ; string_ab: db 'ab'
1931 \c silly {13,10}, crlf ; crlf: db 13,10
1934 \S{mlmacover} Overloading Multi-Line Macros\I{overloading, multi-line macros}
1936 As with single-line macros, multi-line macros can be overloaded by
1937 defining the same macro name several times with different numbers of
1938 parameters. This time, no exception is made for macros with no
1939 parameters at all. So you could define
1941 \c %macro prologue 0
1948 to define an alternative form of the function prologue which
1949 allocates no local stack space.
1951 Sometimes, however, you might want to `overload' a machine
1952 instruction; for example, you might want to define
1961 so that you could code
1963 \c push ebx ; this line is not a macro call
1964 \c push eax,ecx ; but this one is
1966 Ordinarily, NASM will give a warning for the first of the above two
1967 lines, since \c{push} is now defined to be a macro, and is being
1968 invoked with a number of parameters for which no definition has been
1969 given. The correct code will still be generated, but the assembler
1970 will give a warning. This warning can be disabled by the use of the
1971 \c{-w-macro-params} command-line option (see \k{opt-w}).
1974 \S{maclocal} \i{Macro-Local Labels}
1976 NASM allows you to define labels within a multi-line macro
1977 definition in such a way as to make them local to the macro call: so
1978 calling the same macro multiple times will use a different label
1979 each time. You do this by prefixing \i\c{%%} to the label name. So
1980 you can invent an instruction which executes a \c{RET} if the \c{Z}
1981 flag is set by doing this:
1991 You can call this macro as many times as you want, and every time
1992 you call it NASM will make up a different `real' name to substitute
1993 for the label \c{%%skip}. The names NASM invents are of the form
1994 \c{..@2345.skip}, where the number 2345 changes with every macro
1995 call. The \i\c{..@} prefix prevents macro-local labels from
1996 interfering with the local label mechanism, as described in
1997 \k{locallab}. You should avoid defining your own labels in this form
1998 (the \c{..@} prefix, then a number, then another period) in case
1999 they interfere with macro-local labels.
2002 \S{mlmacgre} \i{Greedy Macro Parameters}
2004 Occasionally it is useful to define a macro which lumps its entire
2005 command line into one parameter definition, possibly after
2006 extracting one or two smaller parameters from the front. An example
2007 might be a macro to write a text string to a file in MS-DOS, where
2008 you might want to be able to write
2010 \c writefile [filehandle],"hello, world",13,10
2012 NASM allows you to define the last parameter of a macro to be
2013 \e{greedy}, meaning that if you invoke the macro with more
2014 parameters than it expects, all the spare parameters get lumped into
2015 the last defined one along with the separating commas. So if you
2018 \c %macro writefile 2+
2024 \c mov cx,%%endstr-%%str
2031 then the example call to \c{writefile} above will work as expected:
2032 the text before the first comma, \c{[filehandle]}, is used as the
2033 first macro parameter and expanded when \c{%1} is referred to, and
2034 all the subsequent text is lumped into \c{%2} and placed after the
2037 The greedy nature of the macro is indicated to NASM by the use of
2038 the \I{+ modifier}\c{+} sign after the parameter count on the
2041 If you define a greedy macro, you are effectively telling NASM how
2042 it should expand the macro given \e{any} number of parameters from
2043 the actual number specified up to infinity; in this case, for
2044 example, NASM now knows what to do when it sees a call to
2045 \c{writefile} with 2, 3, 4 or more parameters. NASM will take this
2046 into account when overloading macros, and will not allow you to
2047 define another form of \c{writefile} taking 4 parameters (for
2050 Of course, the above macro could have been implemented as a
2051 non-greedy macro, in which case the call to it would have had to
2054 \c writefile [filehandle], {"hello, world",13,10}
2056 NASM provides both mechanisms for putting \i{commas in macro
2057 parameters}, and you choose which one you prefer for each macro
2060 See \k{sectmac} for a better way to write the above macro.
2063 \S{mlmacdef} \i{Default Macro Parameters}
2065 NASM also allows you to define a multi-line macro with a \e{range}
2066 of allowable parameter counts. If you do this, you can specify
2067 defaults for \i{omitted parameters}. So, for example:
2069 \c %macro die 0-1 "Painful program death has occurred."
2077 This macro (which makes use of the \c{writefile} macro defined in
2078 \k{mlmacgre}) can be called with an explicit error message, which it
2079 will display on the error output stream before exiting, or it can be
2080 called with no parameters, in which case it will use the default
2081 error message supplied in the macro definition.
2083 In general, you supply a minimum and maximum number of parameters
2084 for a macro of this type; the minimum number of parameters are then
2085 required in the macro call, and then you provide defaults for the
2086 optional ones. So if a macro definition began with the line
2088 \c %macro foobar 1-3 eax,[ebx+2]
2090 then it could be called with between one and three parameters, and
2091 \c{%1} would always be taken from the macro call. \c{%2}, if not
2092 specified by the macro call, would default to \c{eax}, and \c{%3} if
2093 not specified would default to \c{[ebx+2]}.
2095 You may omit parameter defaults from the macro definition, in which
2096 case the parameter default is taken to be blank. This can be useful
2097 for macros which can take a variable number of parameters, since the
2098 \i\c{%0} token (see \k{percent0}) allows you to determine how many
2099 parameters were really passed to the macro call.
2101 This defaulting mechanism can be combined with the greedy-parameter
2102 mechanism; so the \c{die} macro above could be made more powerful,
2103 and more useful, by changing the first line of the definition to
2105 \c %macro die 0-1+ "Painful program death has occurred.",13,10
2107 The maximum parameter count can be infinite, denoted by \c{*}. In
2108 this case, of course, it is impossible to provide a \e{full} set of
2109 default parameters. Examples of this usage are shown in \k{rotate}.
2112 \S{percent0} \i\c{%0}: \I{counting macro parameters}Macro Parameter Counter
2114 For a macro which can take a variable number of parameters, the
2115 parameter reference \c{%0} will return a numeric constant giving the
2116 number of parameters passed to the macro. This can be used as an
2117 argument to \c{%rep} (see \k{rep}) in order to iterate through all
2118 the parameters of a macro. Examples are given in \k{rotate}.
2121 \S{rotate} \i\c{%rotate}: \i{Rotating Macro Parameters}
2123 Unix shell programmers will be familiar with the \I{shift
2124 command}\c{shift} shell command, which allows the arguments passed
2125 to a shell script (referenced as \c{$1}, \c{$2} and so on) to be
2126 moved left by one place, so that the argument previously referenced
2127 as \c{$2} becomes available as \c{$1}, and the argument previously
2128 referenced as \c{$1} is no longer available at all.
2130 NASM provides a similar mechanism, in the form of \c{%rotate}. As
2131 its name suggests, it differs from the Unix \c{shift} in that no
2132 parameters are lost: parameters rotated off the left end of the
2133 argument list reappear on the right, and vice versa.
2135 \c{%rotate} is invoked with a single numeric argument (which may be
2136 an expression). The macro parameters are rotated to the left by that
2137 many places. If the argument to \c{%rotate} is negative, the macro
2138 parameters are rotated to the right.
2140 \I{iterating over macro parameters}So a pair of macros to save and
2141 restore a set of registers might work as follows:
2143 \c %macro multipush 1-*
2152 This macro invokes the \c{PUSH} instruction on each of its arguments
2153 in turn, from left to right. It begins by pushing its first
2154 argument, \c{%1}, then invokes \c{%rotate} to move all the arguments
2155 one place to the left, so that the original second argument is now
2156 available as \c{%1}. Repeating this procedure as many times as there
2157 were arguments (achieved by supplying \c{%0} as the argument to
2158 \c{%rep}) causes each argument in turn to be pushed.
2160 Note also the use of \c{*} as the maximum parameter count,
2161 indicating that there is no upper limit on the number of parameters
2162 you may supply to the \i\c{multipush} macro.
2164 It would be convenient, when using this macro, to have a \c{POP}
2165 equivalent, which \e{didn't} require the arguments to be given in
2166 reverse order. Ideally, you would write the \c{multipush} macro
2167 call, then cut-and-paste the line to where the pop needed to be
2168 done, and change the name of the called macro to \c{multipop}, and
2169 the macro would take care of popping the registers in the opposite
2170 order from the one in which they were pushed.
2172 This can be done by the following definition:
2174 \c %macro multipop 1-*
2183 This macro begins by rotating its arguments one place to the
2184 \e{right}, so that the original \e{last} argument appears as \c{%1}.
2185 This is then popped, and the arguments are rotated right again, so
2186 the second-to-last argument becomes \c{%1}. Thus the arguments are
2187 iterated through in reverse order.
2190 \S{concat} \i{Concatenating Macro Parameters}
2192 NASM can concatenate macro parameters on to other text surrounding
2193 them. This allows you to declare a family of symbols, for example,
2194 in a macro definition. If, for example, you wanted to generate a
2195 table of key codes along with offsets into the table, you could code
2198 \c %macro keytab_entry 2
2200 \c keypos%1 equ $-keytab
2206 \c keytab_entry F1,128+1
2207 \c keytab_entry F2,128+2
2208 \c keytab_entry Return,13
2210 which would expand to
2213 \c keyposF1 equ $-keytab
2215 \c keyposF2 equ $-keytab
2217 \c keyposReturn equ $-keytab
2220 You can just as easily concatenate text on to the other end of a
2221 macro parameter, by writing \c{%1foo}.
2223 If you need to append a \e{digit} to a macro parameter, for example
2224 defining labels \c{foo1} and \c{foo2} when passed the parameter
2225 \c{foo}, you can't code \c{%11} because that would be taken as the
2226 eleventh macro parameter. Instead, you must code
2227 \I{braces, after % sign}\c{%\{1\}1}, which will separate the first
2228 \c{1} (giving the number of the macro parameter) from the second
2229 (literal text to be concatenated to the parameter).
2231 This concatenation can also be applied to other preprocessor in-line
2232 objects, such as macro-local labels (\k{maclocal}) and context-local
2233 labels (\k{ctxlocal}). In all cases, ambiguities in syntax can be
2234 resolved by enclosing everything after the \c{%} sign and before the
2235 literal text in braces: so \c{%\{%foo\}bar} concatenates the text
2236 \c{bar} to the end of the real name of the macro-local label
2237 \c{%%foo}. (This is unnecessary, since the form NASM uses for the
2238 real names of macro-local labels means that the two usages
2239 \c{%\{%foo\}bar} and \c{%%foobar} would both expand to the same
2240 thing anyway; nevertheless, the capability is there.)
2243 \S{mlmaccc} \i{Condition Codes as Macro Parameters}
2245 NASM can give special treatment to a macro parameter which contains
2246 a condition code. For a start, you can refer to the macro parameter
2247 \c{%1} by means of the alternative syntax \i\c{%+1}, which informs
2248 NASM that this macro parameter is supposed to contain a condition
2249 code, and will cause the preprocessor to report an error message if
2250 the macro is called with a parameter which is \e{not} a valid
2253 Far more usefully, though, you can refer to the macro parameter by
2254 means of \i\c{%-1}, which NASM will expand as the \e{inverse}
2255 condition code. So the \c{retz} macro defined in \k{maclocal} can be
2256 replaced by a general \i{conditional-return macro} like this:
2266 This macro can now be invoked using calls like \c{retc ne}, which
2267 will cause the conditional-jump instruction in the macro expansion
2268 to come out as \c{JE}, or \c{retc po} which will make the jump a
2271 The \c{%+1} macro-parameter reference is quite happy to interpret
2272 the arguments \c{CXZ} and \c{ECXZ} as valid condition codes;
2273 however, \c{%-1} will report an error if passed either of these,
2274 because no inverse condition code exists.
2277 \S{nolist} \i{Disabling Listing Expansion}\I\c{.nolist}
2279 When NASM is generating a listing file from your program, it will
2280 generally expand multi-line macros by means of writing the macro
2281 call and then listing each line of the expansion. This allows you to
2282 see which instructions in the macro expansion are generating what
2283 code; however, for some macros this clutters the listing up
2286 NASM therefore provides the \c{.nolist} qualifier, which you can
2287 include in a macro definition to inhibit the expansion of the macro
2288 in the listing file. The \c{.nolist} qualifier comes directly after
2289 the number of parameters, like this:
2291 \c %macro foo 1.nolist
2295 \c %macro bar 1-5+.nolist a,b,c,d,e,f,g,h
2297 \H{condasm} \i{Conditional Assembly}\I\c{%if}
2299 Similarly to the C preprocessor, NASM allows sections of a source
2300 file to be assembled only if certain conditions are met. The general
2301 syntax of this feature looks like this:
2304 \c ; some code which only appears if <condition> is met
2305 \c %elif<condition2>
2306 \c ; only appears if <condition> is not met but <condition2> is
2308 \c ; this appears if neither <condition> nor <condition2> was met
2311 The \i\c{%else} clause is optional, as is the \i\c{%elif} clause.
2312 You can have more than one \c{%elif} clause as well.
2315 \S{ifdef} \i\c{%ifdef}: Testing Single-Line Macro Existence\I{testing,
2316 single-line macro existence}
2318 Beginning a conditional-assembly block with the line \c{%ifdef
2319 MACRO} will assemble the subsequent code if, and only if, a
2320 single-line macro called \c{MACRO} is defined. If not, then the
2321 \c{%elif} and \c{%else} blocks (if any) will be processed instead.
2323 For example, when debugging a program, you might want to write code
2326 \c ; perform some function
2328 \c writefile 2,"Function performed successfully",13,10
2330 \c ; go and do something else
2332 Then you could use the command-line option \c{-dDEBUG} to create a
2333 version of the program which produced debugging messages, and remove
2334 the option to generate the final release version of the program.
2336 You can test for a macro \e{not} being defined by using
2337 \i\c{%ifndef} instead of \c{%ifdef}. You can also test for macro
2338 definitions in \c{%elif} blocks by using \i\c{%elifdef} and
2342 \S{ifmacro} \i\c{ifmacro}: Testing Multi-Line Macro
2343 Existence\I{testing, multi-line macro existence}
2345 The \c{%ifmacro} directive operates in the same way as the \c{%ifdef}
2346 directive, except that it checks for the existence of a multi-line macro.
2348 For example, you may be working with a large project and not have control
2349 over the macros in a library. You may want to create a macro with one
2350 name if it doesn't already exist, and another name if one with that name
2353 The \c{%ifmacro} is considered true if defining a macro with the given name
2354 and number of arguments would cause a definitions conflict. For example:
2356 \c %ifmacro MyMacro 1-3
2358 \c %error "MyMacro 1-3" causes a conflict with an existing macro.
2362 \c %macro MyMacro 1-3
2364 \c ; insert code to define the macro
2370 This will create the macro "MyMacro 1-3" if no macro already exists which
2371 would conflict with it, and emits a warning if there would be a definition
2374 You can test for the macro not existing by using the \i\c{%ifnmacro} instead
2375 of \c{%ifmacro}. Additional tests can be performed in \c{%elif} blocks by using
2376 \i\c{%elifmacro} and \i\c{%elifnmacro}.
2379 \S{ifctx} \i\c{%ifctx}: Testing the Context Stack\I{testing, context
2382 The conditional-assembly construct \c{%ifctx ctxname} will cause the
2383 subsequent code to be assembled if and only if the top context on
2384 the preprocessor's context stack has the name \c{ctxname}. As with
2385 \c{%ifdef}, the inverse and \c{%elif} forms \i\c{%ifnctx},
2386 \i\c{%elifctx} and \i\c{%elifnctx} are also supported.
2388 For more details of the context stack, see \k{ctxstack}. For a
2389 sample use of \c{%ifctx}, see \k{blockif}.
2392 \S{if} \i\c{%if}: Testing Arbitrary Numeric Expressions\I{testing,
2393 arbitrary numeric expressions}
2395 The conditional-assembly construct \c{%if expr} will cause the
2396 subsequent code to be assembled if and only if the value of the
2397 numeric expression \c{expr} is non-zero. An example of the use of
2398 this feature is in deciding when to break out of a \c{%rep}
2399 preprocessor loop: see \k{rep} for a detailed example.
2401 The expression given to \c{%if}, and its counterpart \i\c{%elif}, is
2402 a critical expression (see \k{crit}).
2404 \c{%if} extends the normal NASM expression syntax, by providing a
2405 set of \i{relational operators} which are not normally available in
2406 expressions. The operators \i\c{=}, \i\c{<}, \i\c{>}, \i\c{<=},
2407 \i\c{>=} and \i\c{<>} test equality, less-than, greater-than,
2408 less-or-equal, greater-or-equal and not-equal respectively. The
2409 C-like forms \i\c{==} and \i\c{!=} are supported as alternative
2410 forms of \c{=} and \c{<>}. In addition, low-priority logical
2411 operators \i\c{&&}, \i\c{^^} and \i\c{||} are provided, supplying
2412 \i{logical AND}, \i{logical XOR} and \i{logical OR}. These work like
2413 the C logical operators (although C has no logical XOR), in that
2414 they always return either 0 or 1, and treat any non-zero input as 1
2415 (so that \c{^^}, for example, returns 1 if exactly one of its inputs
2416 is zero, and 0 otherwise). The relational operators also return 1
2417 for true and 0 for false.
2420 \S{ifidn} \i\c{%ifidn} and \i\c{%ifidni}: Testing Exact Text
2421 Identity\I{testing, exact text identity}
2423 The construct \c{%ifidn text1,text2} will cause the subsequent code
2424 to be assembled if and only if \c{text1} and \c{text2}, after
2425 expanding single-line macros, are identical pieces of text.
2426 Differences in white space are not counted.
2428 \c{%ifidni} is similar to \c{%ifidn}, but is \i{case-insensitive}.
2430 For example, the following macro pushes a register or number on the
2431 stack, and allows you to treat \c{IP} as a real register:
2433 \c %macro pushparam 1
2444 Like most other \c{%if} constructs, \c{%ifidn} has a counterpart
2445 \i\c{%elifidn}, and negative forms \i\c{%ifnidn} and \i\c{%elifnidn}.
2446 Similarly, \c{%ifidni} has counterparts \i\c{%elifidni},
2447 \i\c{%ifnidni} and \i\c{%elifnidni}.
2450 \S{iftyp} \i\c{%ifid}, \i\c{%ifnum}, \i\c{%ifstr}: Testing Token
2451 Types\I{testing, token types}
2453 Some macros will want to perform different tasks depending on
2454 whether they are passed a number, a string, or an identifier. For
2455 example, a string output macro might want to be able to cope with
2456 being passed either a string constant or a pointer to an existing
2459 The conditional assembly construct \c{%ifid}, taking one parameter
2460 (which may be blank), assembles the subsequent code if and only if
2461 the first token in the parameter exists and is an identifier.
2462 \c{%ifnum} works similarly, but tests for the token being a numeric
2463 constant; \c{%ifstr} tests for it being a string.
2465 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
2466 extended to take advantage of \c{%ifstr} in the following fashion:
2468 \c %macro writefile 2-3+
2477 \c %%endstr: mov dx,%%str
2478 \c mov cx,%%endstr-%%str
2489 Then the \c{writefile} macro can cope with being called in either of
2490 the following two ways:
2492 \c writefile [file], strpointer, length
2493 \c writefile [file], "hello", 13, 10
2495 In the first, \c{strpointer} is used as the address of an
2496 already-declared string, and \c{length} is used as its length; in
2497 the second, a string is given to the macro, which therefore declares
2498 it itself and works out the address and length for itself.
2500 Note the use of \c{%if} inside the \c{%ifstr}: this is to detect
2501 whether the macro was passed two arguments (so the string would be a
2502 single string constant, and \c{db %2} would be adequate) or more (in
2503 which case, all but the first two would be lumped together into
2504 \c{%3}, and \c{db %2,%3} would be required).
2506 \I\c{%ifnid}\I\c{%elifid}\I\c{%elifnid}\I\c{%ifnnum}\I\c{%elifnum}
2507 \I\c{%elifnnum}\I\c{%ifnstr}\I\c{%elifstr}\I\c{%elifnstr}
2508 The usual \c{%elifXXX}, \c{%ifnXXX} and \c{%elifnXXX} versions exist
2509 for each of \c{%ifid}, \c{%ifnum} and \c{%ifstr}.
2512 \S{pperror} \i\c{%error}: Reporting \i{User-Defined Errors}
2514 The preprocessor directive \c{%error} will cause NASM to report an
2515 error if it occurs in assembled code. So if other users are going to
2516 try to assemble your source files, you can ensure that they define
2517 the right macros by means of code like this:
2519 \c %ifdef SOME_MACRO
2521 \c %elifdef SOME_OTHER_MACRO
2522 \c ; do some different setup
2524 \c %error Neither SOME_MACRO nor SOME_OTHER_MACRO was defined.
2527 Then any user who fails to understand the way your code is supposed
2528 to be assembled will be quickly warned of their mistake, rather than
2529 having to wait until the program crashes on being run and then not
2530 knowing what went wrong.
2533 \H{rep} \i{Preprocessor Loops}\I{repeating code}: \i\c{%rep}
2535 NASM's \c{TIMES} prefix, though useful, cannot be used to invoke a
2536 multi-line macro multiple times, because it is processed by NASM
2537 after macros have already been expanded. Therefore NASM provides
2538 another form of loop, this time at the preprocessor level: \c{%rep}.
2540 The directives \c{%rep} and \i\c{%endrep} (\c{%rep} takes a numeric
2541 argument, which can be an expression; \c{%endrep} takes no
2542 arguments) can be used to enclose a chunk of code, which is then
2543 replicated as many times as specified by the preprocessor:
2547 \c inc word [table+2*i]
2551 This will generate a sequence of 64 \c{INC} instructions,
2552 incrementing every word of memory from \c{[table]} to
2555 For more complex termination conditions, or to break out of a repeat
2556 loop part way along, you can use the \i\c{%exitrep} directive to
2557 terminate the loop, like this:
2572 \c fib_number equ ($-fibonacci)/2
2574 This produces a list of all the Fibonacci numbers that will fit in
2575 16 bits. Note that a maximum repeat count must still be given to
2576 \c{%rep}. This is to prevent the possibility of NASM getting into an
2577 infinite loop in the preprocessor, which (on multitasking or
2578 multi-user systems) would typically cause all the system memory to
2579 be gradually used up and other applications to start crashing.
2582 \H{include} \i{Including Other Files}
2584 Using, once again, a very similar syntax to the C preprocessor,
2585 NASM's preprocessor lets you include other source files into your
2586 code. This is done by the use of the \i\c{%include} directive:
2588 \c %include "macros.mac"
2590 will include the contents of the file \c{macros.mac} into the source
2591 file containing the \c{%include} directive.
2593 Include files are \I{searching for include files}searched for in the
2594 current directory (the directory you're in when you run NASM, as
2595 opposed to the location of the NASM executable or the location of
2596 the source file), plus any directories specified on the NASM command
2597 line using the \c{-i} option.
2599 The standard C idiom for preventing a file being included more than
2600 once is just as applicable in NASM: if the file \c{macros.mac} has
2603 \c %ifndef MACROS_MAC
2604 \c %define MACROS_MAC
2605 \c ; now define some macros
2608 then including the file more than once will not cause errors,
2609 because the second time the file is included nothing will happen
2610 because the macro \c{MACROS_MAC} will already be defined.
2612 You can force a file to be included even if there is no \c{%include}
2613 directive that explicitly includes it, by using the \i\c{-p} option
2614 on the NASM command line (see \k{opt-p}).
2617 \H{ctxstack} The \i{Context Stack}
2619 Having labels that are local to a macro definition is sometimes not
2620 quite powerful enough: sometimes you want to be able to share labels
2621 between several macro calls. An example might be a \c{REPEAT} ...
2622 \c{UNTIL} loop, in which the expansion of the \c{REPEAT} macro
2623 would need to be able to refer to a label which the \c{UNTIL} macro
2624 had defined. However, for such a macro you would also want to be
2625 able to nest these loops.
2627 NASM provides this level of power by means of a \e{context stack}.
2628 The preprocessor maintains a stack of \e{contexts}, each of which is
2629 characterised by a name. You add a new context to the stack using
2630 the \i\c{%push} directive, and remove one using \i\c{%pop}. You can
2631 define labels that are local to a particular context on the stack.
2634 \S{pushpop} \i\c{%push} and \i\c{%pop}: \I{creating
2635 contexts}\I{removing contexts}Creating and Removing Contexts
2637 The \c{%push} directive is used to create a new context and place it
2638 on the top of the context stack. \c{%push} requires one argument,
2639 which is the name of the context. For example:
2643 This pushes a new context called \c{foobar} on the stack. You can
2644 have several contexts on the stack with the same name: they can
2645 still be distinguished.
2647 The directive \c{%pop}, requiring no arguments, removes the top
2648 context from the context stack and destroys it, along with any
2649 labels associated with it.
2652 \S{ctxlocal} \i{Context-Local Labels}
2654 Just as the usage \c{%%foo} defines a label which is local to the
2655 particular macro call in which it is used, the usage \I{%$}\c{%$foo}
2656 is used to define a label which is local to the context on the top
2657 of the context stack. So the \c{REPEAT} and \c{UNTIL} example given
2658 above could be implemented by means of:
2674 and invoked by means of, for example,
2682 which would scan every fourth byte of a string in search of the byte
2685 If you need to define, or access, labels local to the context
2686 \e{below} the top one on the stack, you can use \I{%$$}\c{%$$foo}, or
2687 \c{%$$$foo} for the context below that, and so on.
2690 \S{ctxdefine} \i{Context-Local Single-Line Macros}
2692 NASM also allows you to define single-line macros which are local to
2693 a particular context, in just the same way:
2695 \c %define %$localmac 3
2697 will define the single-line macro \c{%$localmac} to be local to the
2698 top context on the stack. Of course, after a subsequent \c{%push},
2699 it can then still be accessed by the name \c{%$$localmac}.
2702 \S{ctxrepl} \i\c{%repl}: \I{renaming contexts}Renaming a Context
2704 If you need to change the name of the top context on the stack (in
2705 order, for example, to have it respond differently to \c{%ifctx}),
2706 you can execute a \c{%pop} followed by a \c{%push}; but this will
2707 have the side effect of destroying all context-local labels and
2708 macros associated with the context that was just popped.
2710 NASM provides the directive \c{%repl}, which \e{replaces} a context
2711 with a different name, without touching the associated macros and
2712 labels. So you could replace the destructive code
2717 with the non-destructive version \c{%repl newname}.
2720 \S{blockif} Example Use of the \i{Context Stack}: \i{Block IFs}
2722 This example makes use of almost all the context-stack features,
2723 including the conditional-assembly construct \i\c{%ifctx}, to
2724 implement a block IF statement as a set of macros.
2740 \c %error "expected `if' before `else'"
2754 \c %error "expected `if' or `else' before `endif'"
2759 This code is more robust than the \c{REPEAT} and \c{UNTIL} macros
2760 given in \k{ctxlocal}, because it uses conditional assembly to check
2761 that the macros are issued in the right order (for example, not
2762 calling \c{endif} before \c{if}) and issues a \c{%error} if they're
2765 In addition, the \c{endif} macro has to be able to cope with the two
2766 distinct cases of either directly following an \c{if}, or following
2767 an \c{else}. It achieves this, again, by using conditional assembly
2768 to do different things depending on whether the context on top of
2769 the stack is \c{if} or \c{else}.
2771 The \c{else} macro has to preserve the context on the stack, in
2772 order to have the \c{%$ifnot} referred to by the \c{if} macro be the
2773 same as the one defined by the \c{endif} macro, but has to change
2774 the context's name so that \c{endif} will know there was an
2775 intervening \c{else}. It does this by the use of \c{%repl}.
2777 A sample usage of these macros might look like:
2799 The block-\c{IF} macros handle nesting quite happily, by means of
2800 pushing another context, describing the inner \c{if}, on top of the
2801 one describing the outer \c{if}; thus \c{else} and \c{endif} always
2802 refer to the last unmatched \c{if} or \c{else}.
2805 \H{stdmac} \i{Standard Macros}
2807 NASM defines a set of standard macros, which are already defined
2808 when it starts to process any source file. If you really need a
2809 program to be assembled with no pre-defined macros, you can use the
2810 \i\c{%clear} directive to empty the preprocessor of everything.
2812 Most \i{user-level assembler directives} (see \k{directive}) are
2813 implemented as macros which invoke primitive directives; these are
2814 described in \k{directive}. The rest of the standard macro set is
2818 \S{stdmacver} \i\c{__NASM_MAJOR__}, \i\c{__NASM_MINOR__} and
2819 \i\c{__NASM_SUBMINOR__}: \i{NASM Version}
2821 The single-line macros \c{__NASM_MAJOR__}, \c{__NASM_MINOR__} and
2822 \c{__NASM_SUBMINOR__} expand to the major, minor and subminor parts of
2823 the \i{version number of NASM} being used. So, under NASM 0.98.31 for
2824 example, \c{__NASM_MAJOR__} would be defined to be 0, \c{__NASM_MINOR__}
2825 would be defined as 98 and \c{__NASM_SUBMINOR__} would be defined to 31.
2828 \S{stdmacverstr} \i\c{__NASM_VER__}: \i{NASM Version string}
2830 The single-line macro \c{__NASM_VER__} expands to a string which defines
2831 the version number of nasm being used. So, under NASM 0.98.31 for example,
2840 \S{fileline} \i\c{__FILE__} and \i\c{__LINE__}: File Name and Line Number
2842 Like the C preprocessor, NASM allows the user to find out the file
2843 name and line number containing the current instruction. The macro
2844 \c{__FILE__} expands to a string constant giving the name of the
2845 current input file (which may change through the course of assembly
2846 if \c{%include} directives are used), and \c{__LINE__} expands to a
2847 numeric constant giving the current line number in the input file.
2849 These macros could be used, for example, to communicate debugging
2850 information to a macro, since invoking \c{__LINE__} inside a macro
2851 definition (either single-line or multi-line) will return the line
2852 number of the macro \e{call}, rather than \e{definition}. So to
2853 determine where in a piece of code a crash is occurring, for
2854 example, one could write a routine \c{stillhere}, which is passed a
2855 line number in \c{EAX} and outputs something like `line 155: still
2856 here'. You could then write a macro
2858 \c %macro notdeadyet 0
2867 and then pepper your code with calls to \c{notdeadyet} until you
2868 find the crash point.
2871 \S{struc} \i\c{STRUC} and \i\c{ENDSTRUC}: \i{Declaring Structure} Data Types
2873 The core of NASM contains no intrinsic means of defining data
2874 structures; instead, the preprocessor is sufficiently powerful that
2875 data structures can be implemented as a set of macros. The macros
2876 \c{STRUC} and \c{ENDSTRUC} are used to define a structure data type.
2878 \c{STRUC} takes one parameter, which is the name of the data type.
2879 This name is defined as a symbol with the value zero, and also has
2880 the suffix \c{_size} appended to it and is then defined as an
2881 \c{EQU} giving the size of the structure. Once \c{STRUC} has been
2882 issued, you are defining the structure, and should define fields
2883 using the \c{RESB} family of pseudo-instructions, and then invoke
2884 \c{ENDSTRUC} to finish the definition.
2886 For example, to define a structure called \c{mytype} containing a
2887 longword, a word, a byte and a string of bytes, you might code
2898 The above code defines six symbols: \c{mt_long} as 0 (the offset
2899 from the beginning of a \c{mytype} structure to the longword field),
2900 \c{mt_word} as 4, \c{mt_byte} as 6, \c{mt_str} as 7, \c{mytype_size}
2901 as 39, and \c{mytype} itself as zero.
2903 The reason why the structure type name is defined at zero is a side
2904 effect of allowing structures to work with the local label
2905 mechanism: if your structure members tend to have the same names in
2906 more than one structure, you can define the above structure like this:
2917 This defines the offsets to the structure fields as \c{mytype.long},
2918 \c{mytype.word}, \c{mytype.byte} and \c{mytype.str}.
2920 NASM, since it has no \e{intrinsic} structure support, does not
2921 support any form of period notation to refer to the elements of a
2922 structure once you have one (except the above local-label notation),
2923 so code such as \c{mov ax,[mystruc.mt_word]} is not valid.
2924 \c{mt_word} is a constant just like any other constant, so the
2925 correct syntax is \c{mov ax,[mystruc+mt_word]} or \c{mov
2926 ax,[mystruc+mytype.word]}.
2929 \S{istruc} \i\c{ISTRUC}, \i\c{AT} and \i\c{IEND}: Declaring
2930 \i{Instances of Structures}
2932 Having defined a structure type, the next thing you typically want
2933 to do is to declare instances of that structure in your data
2934 segment. NASM provides an easy way to do this in the \c{ISTRUC}
2935 mechanism. To declare a structure of type \c{mytype} in a program,
2936 you code something like this:
2941 \c at mt_long, dd 123456
2942 \c at mt_word, dw 1024
2943 \c at mt_byte, db 'x'
2944 \c at mt_str, db 'hello, world', 13, 10, 0
2948 The function of the \c{AT} macro is to make use of the \c{TIMES}
2949 prefix to advance the assembly position to the correct point for the
2950 specified structure field, and then to declare the specified data.
2951 Therefore the structure fields must be declared in the same order as
2952 they were specified in the structure definition.
2954 If the data to go in a structure field requires more than one source
2955 line to specify, the remaining source lines can easily come after
2956 the \c{AT} line. For example:
2958 \c at mt_str, db 123,134,145,156,167,178,189
2961 Depending on personal taste, you can also omit the code part of the
2962 \c{AT} line completely, and start the structure field on the next
2966 \c db 'hello, world'
2970 \S{align} \i\c{ALIGN} and \i\c{ALIGNB}: Data Alignment
2972 The \c{ALIGN} and \c{ALIGNB} macros provides a convenient way to
2973 align code or data on a word, longword, paragraph or other boundary.
2974 (Some assemblers call this directive \i\c{EVEN}.) The syntax of the
2975 \c{ALIGN} and \c{ALIGNB} macros is
2977 \c align 4 ; align on 4-byte boundary
2978 \c align 16 ; align on 16-byte boundary
2979 \c align 8,db 0 ; pad with 0s rather than NOPs
2980 \c align 4,resb 1 ; align to 4 in the BSS
2981 \c alignb 4 ; equivalent to previous line
2983 Both macros require their first argument to be a power of two; they
2984 both compute the number of additional bytes required to bring the
2985 length of the current section up to a multiple of that power of two,
2986 and then apply the \c{TIMES} prefix to their second argument to
2987 perform the alignment.
2989 If the second argument is not specified, the default for \c{ALIGN}
2990 is \c{NOP}, and the default for \c{ALIGNB} is \c{RESB 1}. So if the
2991 second argument is specified, the two macros are equivalent.
2992 Normally, you can just use \c{ALIGN} in code and data sections and
2993 \c{ALIGNB} in BSS sections, and never need the second argument
2994 except for special purposes.
2996 \c{ALIGN} and \c{ALIGNB}, being simple macros, perform no error
2997 checking: they cannot warn you if their first argument fails to be a
2998 power of two, or if their second argument generates more than one
2999 byte of code. In each of these cases they will silently do the wrong
3002 \c{ALIGNB} (or \c{ALIGN} with a second argument of \c{RESB 1}) can
3003 be used within structure definitions:
3020 This will ensure that the structure members are sensibly aligned
3021 relative to the base of the structure.
3023 A final caveat: \c{ALIGN} and \c{ALIGNB} work relative to the
3024 beginning of the \e{section}, not the beginning of the address space
3025 in the final executable. Aligning to a 16-byte boundary when the
3026 section you're in is only guaranteed to be aligned to a 4-byte
3027 boundary, for example, is a waste of effort. Again, NASM does not
3028 check that the section's alignment characteristics are sensible for
3029 the use of \c{ALIGN} or \c{ALIGNB}.
3032 \H{tasmcompat} \i{TASM Compatible Preprocessor Directives}
3034 The following preprocessor directives may only be used when TASM
3035 compatibility is turned on using the \c{-t} command line switch
3036 (This switch is described in \k{opt-t}.)
3038 \b\c{%arg} (see \k{arg})
3040 \b\c{%stacksize} (see \k{stacksize})
3042 \b\c{%local} (see \k{local})
3045 \S{arg} \i\c{%arg} Directive
3047 The \c{%arg} directive is used to simplify the handling of
3048 parameters passed on the stack. Stack based parameter passing
3049 is used by many high level languages, including C, C++ and Pascal.
3051 While NASM comes with macros which attempt to duplicate this
3052 functionality (see \k{16cmacro}), the syntax is not particularly
3053 convenient to use and is not TASM compatible. Here is an example
3054 which shows the use of \c{%arg} without any external macros:
3058 \c %push mycontext ; save the current context
3059 \c %stacksize large ; tell NASM to use bp
3060 \c %arg i:word, j_ptr:word
3067 \c %pop ; restore original context
3069 This is similar to the procedure defined in \k{16cmacro} and adds
3070 the value in i to the value pointed to by j_ptr and returns the
3071 sum in the ax register. See \k{pushpop} for an explanation of
3072 \c{push} and \c{pop} and the use of context stacks.
3075 \S{stacksize} \i\c{%stacksize} Directive
3077 The \c{%stacksize} directive is used in conjunction with the
3078 \c{%arg} (see \k{arg}) and the \c{%local} (see \k{local}) directives.
3079 It tells NASM the default size to use for subsequent \c{%arg} and
3080 \c{%local} directives. The \c{%stacksize} directive takes one
3081 required argument which is one of \c{flat}, \c{large} or \c{small}.
3085 This form causes NASM to use stack-based parameter addressing
3086 relative to \c{ebp} and it assumes that a near form of call was used
3087 to get to this label (i.e. that \c{eip} is on the stack).
3091 This form uses \c{bp} to do stack-based parameter addressing and
3092 assumes that a far form of call was used to get to this address
3093 (i.e. that \c{ip} and \c{cs} are on the stack).
3097 This form also uses \c{bp} to address stack parameters, but it is
3098 different from \c{large} because it also assumes that the old value
3099 of bp is pushed onto the stack (i.e. it expects an \c{ENTER}
3100 instruction). In other words, it expects that \c{bp}, \c{ip} and
3101 \c{cs} are on the top of the stack, underneath any local space which
3102 may have been allocated by \c{ENTER}. This form is probably most
3103 useful when used in combination with the \c{%local} directive
3107 \S{local} \i\c{%local} Directive
3109 The \c{%local} directive is used to simplify the use of local
3110 temporary stack variables allocated in a stack frame. Automatic
3111 local variables in C are an example of this kind of variable. The
3112 \c{%local} directive is most useful when used with the \c{%stacksize}
3113 (see \k{stacksize} and is also compatible with the \c{%arg} directive
3114 (see \k{arg}). It allows simplified reference to variables on the
3115 stack which have been allocated typically by using the \c{ENTER}
3116 instruction (see \k{insENTER} for a description of that instruction).
3117 An example of its use is the following:
3121 \c %push mycontext ; save the current context
3122 \c %stacksize small ; tell NASM to use bp
3123 \c %assign %$localsize 0 ; see text for explanation
3124 \c %local old_ax:word, old_dx:word
3126 \c enter %$localsize,0 ; see text for explanation
3127 \c mov [old_ax],ax ; swap ax & bx
3128 \c mov [old_dx],dx ; and swap dx & cx
3133 \c leave ; restore old bp
3136 \c %pop ; restore original context
3138 The \c{%$localsize} variable is used internally by the
3139 \c{%local} directive and \e{must} be defined within the
3140 current context before the \c{%local} directive may be used.
3141 Failure to do so will result in one expression syntax error for
3142 each \c{%local} variable declared. It then may be used in
3143 the construction of an appropriately sized ENTER instruction
3144 as shown in the example.
3146 \H{otherpreproc} \i{Other Preprocessor Directives}
3148 The following preprocessor directive is supported to allow NASM to
3149 correctly handle output of the cpp C language preprocessor.
3151 \b\c{%line} (see \k{line})
3153 \S{line} \i\c{%line} Directive
3155 The \c{%line} directive is used to notify NASM that the input line
3156 corresponds to a specific line number in another file. Typically
3157 this other file would be an original source file, with the current
3158 NASM input being the output of a pre-processor. The \c{%line}
3159 directive allows NASM to output messages which indicate the line
3160 number of the original source file, instead of the file that is being
3163 This preprocessor directive is not generally of use to programmers,
3164 by may be of interest to preprocessor authors. The usage of the
3165 \c{%line} preprocessor directive is as follows:
3167 \c %line nnn[+mmm] [filename]
3169 In this directive, \c{nnn} indentifies the line of the original source
3170 file which this line corresponds to. \c{mmm} is an optional parameter
3171 which specifies a line increment value; each line of the input file
3172 read in is considered to correspond to \c{mmm} lines of the original
3173 source file. Finally, \c{filename} is an optional parameter which
3174 specifies the file name of the original source file.
3176 After reading a \c{%line} preprocessor directive, NASM will report
3177 all file name and line numbers relative to the values specified
3180 \C{directive} \i{Assembler Directives}
3182 NASM, though it attempts to avoid the bureaucracy of assemblers like
3183 MASM and TASM, is nevertheless forced to support a \e{few}
3184 directives. These are described in this chapter.
3186 NASM's directives come in two types: \I{user-level
3187 directives}\e{user-level} directives and \I{primitive
3188 directives}\e{primitive} directives. Typically, each directive has a
3189 user-level form and a primitive form. In almost all cases, we
3190 recommend that users use the user-level forms of the directives,
3191 which are implemented as macros which call the primitive forms.
3193 Primitive directives are enclosed in square brackets; user-level
3196 In addition to the universal directives described in this chapter,
3197 each object file format can optionally supply extra directives in
3198 order to control particular features of that file format. These
3199 \I{format-specific directives}\e{format-specific} directives are
3200 documented along with the formats that implement them, in \k{outfmt}.
3203 \H{bits} \i\c{BITS}: Specifying Target \i{Processor Mode}
3205 The \c{BITS} directive specifies whether NASM should generate code
3206 \I{16-bit mode, versus 32-bit mode}designed to run on a processor
3207 operating in 16-bit mode, or code designed to run on a processor
3208 operating in 32-bit mode. The syntax is \c{BITS 16} or \c{BITS 32}.
3210 In most cases, you should not need to use \c{BITS} explicitly. The
3211 \c{aout}, \c{coff}, \c{elf} and \c{win32} object formats, which are
3212 designed for use in 32-bit operating systems, all cause NASM to
3213 select 32-bit mode by default. The \c{obj} object format allows you
3214 to specify each segment you define as either \c{USE16} or \c{USE32},
3215 and NASM will set its operating mode accordingly, so the use of the
3216 \c{BITS} directive is once again unnecessary.
3218 The most likely reason for using the \c{BITS} directive is to write
3219 32-bit code in a flat binary file; this is because the \c{bin}
3220 output format defaults to 16-bit mode in anticipation of it being
3221 used most frequently to write DOS \c{.COM} programs, DOS \c{.SYS}
3222 device drivers and boot loader software.
3224 You do \e{not} need to specify \c{BITS 32} merely in order to use
3225 32-bit instructions in a 16-bit DOS program; if you do, the
3226 assembler will generate incorrect code because it will be writing
3227 code targeted at a 32-bit platform, to be run on a 16-bit one.
3229 When NASM is in \c{BITS 16} state, instructions which use 32-bit
3230 data are prefixed with an 0x66 byte, and those referring to 32-bit
3231 addresses have an 0x67 prefix. In \c{BITS 32} state, the reverse is
3232 true: 32-bit instructions require no prefixes, whereas instructions
3233 using 16-bit data need an 0x66 and those working on 16-bit addresses
3236 The \c{BITS} directive has an exactly equivalent primitive form,
3237 \c{[BITS 16]} and \c{[BITS 32]}. The user-level form is a macro
3238 which has no function other than to call the primitive form.
3241 \S{USE16 & USE32} \i\c{USE16} & \i\c{USE32}: Aliases for BITS
3243 The `\c{USE16}' and `\c{USE32}' directives can be used in place of
3244 `\c{BITS 16}' and `\c{BITS 32}', for compatibility with other assemblers.
3247 \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining
3250 \I{changing sections}\I{switching between sections}The \c{SECTION}
3251 directive (\c{SEGMENT} is an exactly equivalent synonym) changes
3252 which section of the output file the code you write will be
3253 assembled into. In some object file formats, the number and names of
3254 sections are fixed; in others, the user may make up as many as they
3255 wish. Hence \c{SECTION} may sometimes give an error message, or may
3256 define a new section, if you try to switch to a section that does
3259 The Unix object formats, and the \c{bin} object format, all support
3260 the \i{standardised section names} \c{.text}, \c{.data} and \c{.bss}
3261 for the code, data and uninitialised-data sections. The \c{obj}
3262 format, by contrast, does not recognise these section names as being
3263 special, and indeed will strip off the leading period of any section
3267 \S{sectmac} The \i\c{__SECT__} Macro
3269 The \c{SECTION} directive is unusual in that its user-level form
3270 functions differently from its primitive form. The primitive form,
3271 \c{[SECTION xyz]}, simply switches the current target section to the
3272 one given. The user-level form, \c{SECTION xyz}, however, first
3273 defines the single-line macro \c{__SECT__} to be the primitive
3274 \c{[SECTION]} directive which it is about to issue, and then issues
3275 it. So the user-level directive
3279 expands to the two lines
3281 \c %define __SECT__ [SECTION .text]
3284 Users may find it useful to make use of this in their own macros.
3285 For example, the \c{writefile} macro defined in \k{mlmacgre} can be
3286 usefully rewritten in the following more sophisticated form:
3288 \c %macro writefile 2+
3298 \c mov cx,%%endstr-%%str
3305 This form of the macro, once passed a string to output, first
3306 switches temporarily to the data section of the file, using the
3307 primitive form of the \c{SECTION} directive so as not to modify
3308 \c{__SECT__}. It then declares its string in the data section, and
3309 then invokes \c{__SECT__} to switch back to \e{whichever} section
3310 the user was previously working in. It thus avoids the need, in the
3311 previous version of the macro, to include a \c{JMP} instruction to
3312 jump over the data, and also does not fail if, in a complicated
3313 \c{OBJ} format module, the user could potentially be assembling the
3314 code in any of several separate code sections.
3317 \H{absolute} \i\c{ABSOLUTE}: Defining Absolute Labels
3319 The \c{ABSOLUTE} directive can be thought of as an alternative form
3320 of \c{SECTION}: it causes the subsequent code to be directed at no
3321 physical section, but at the hypothetical section starting at the
3322 given absolute address. The only instructions you can use in this
3323 mode are the \c{RESB} family.
3325 \c{ABSOLUTE} is used as follows:
3333 This example describes a section of the PC BIOS data area, at
3334 segment address 0x40: the above code defines \c{kbuf_chr} to be
3335 0x1A, \c{kbuf_free} to be 0x1C, and \c{kbuf} to be 0x1E.
3337 The user-level form of \c{ABSOLUTE}, like that of \c{SECTION},
3338 redefines the \i\c{__SECT__} macro when it is invoked.
3340 \i\c{STRUC} and \i\c{ENDSTRUC} are defined as macros which use
3341 \c{ABSOLUTE} (and also \c{__SECT__}).
3343 \c{ABSOLUTE} doesn't have to take an absolute constant as an
3344 argument: it can take an expression (actually, a \i{critical
3345 expression}: see \k{crit}) and it can be a value in a segment. For
3346 example, a TSR can re-use its setup code as run-time BSS like this:
3348 \c org 100h ; it's a .COM program
3350 \c jmp setup ; setup code comes last
3352 \c ; the resident part of the TSR goes here
3354 \c ; now write the code that installs the TSR here
3358 \c runtimevar1 resw 1
3359 \c runtimevar2 resd 20
3363 This defines some variables `on top of' the setup code, so that
3364 after the setup has finished running, the space it took up can be
3365 re-used as data storage for the running TSR. The symbol `tsr_end'
3366 can be used to calculate the total size of the part of the TSR that
3367 needs to be made resident.
3370 \H{extern} \i\c{EXTERN}: \i{Importing Symbols} from Other Modules
3372 \c{EXTERN} is similar to the MASM directive \c{EXTRN} and the C
3373 keyword \c{extern}: it is used to declare a symbol which is not
3374 defined anywhere in the module being assembled, but is assumed to be
3375 defined in some other module and needs to be referred to by this
3376 one. Not every object-file format can support external variables:
3377 the \c{bin} format cannot.
3379 The \c{EXTERN} directive takes as many arguments as you like. Each
3380 argument is the name of a symbol:
3383 \c extern _sscanf,_fscanf
3385 Some object-file formats provide extra features to the \c{EXTERN}
3386 directive. In all cases, the extra features are used by suffixing a
3387 colon to the symbol name followed by object-format specific text.
3388 For example, the \c{obj} format allows you to declare that the
3389 default segment base of an external should be the group \c{dgroup}
3390 by means of the directive
3392 \c extern _variable:wrt dgroup
3394 The primitive form of \c{EXTERN} differs from the user-level form
3395 only in that it can take only one argument at a time: the support
3396 for multiple arguments is implemented at the preprocessor level.
3398 You can declare the same variable as \c{EXTERN} more than once: NASM
3399 will quietly ignore the second and later redeclarations. You can't
3400 declare a variable as \c{EXTERN} as well as something else, though.
3403 \H{global} \i\c{GLOBAL}: \i{Exporting Symbols} to Other Modules
3405 \c{GLOBAL} is the other end of \c{EXTERN}: if one module declares a
3406 symbol as \c{EXTERN} and refers to it, then in order to prevent
3407 linker errors, some other module must actually \e{define} the
3408 symbol and declare it as \c{GLOBAL}. Some assemblers use the name
3409 \i\c{PUBLIC} for this purpose.
3411 The \c{GLOBAL} directive applying to a symbol must appear \e{before}
3412 the definition of the symbol.
3414 \c{GLOBAL} uses the same syntax as \c{EXTERN}, except that it must
3415 refer to symbols which \e{are} defined in the same module as the
3416 \c{GLOBAL} directive. For example:
3422 \c{GLOBAL}, like \c{EXTERN}, allows object formats to define private
3423 extensions by means of a colon. The \c{elf} object format, for
3424 example, lets you specify whether global data items are functions or
3427 \c global hashlookup:function, hashtable:data
3429 Like \c{EXTERN}, the primitive form of \c{GLOBAL} differs from the
3430 user-level form only in that it can take only one argument at a
3434 \H{common} \i\c{COMMON}: Defining Common Data Areas
3436 The \c{COMMON} directive is used to declare \i\e{common variables}.
3437 A common variable is much like a global variable declared in the
3438 uninitialised data section, so that
3442 is similar in function to
3449 The difference is that if more than one module defines the same
3450 common variable, then at link time those variables will be
3451 \e{merged}, and references to \c{intvar} in all modules will point
3452 at the same piece of memory.
3454 Like \c{GLOBAL} and \c{EXTERN}, \c{COMMON} supports object-format
3455 specific extensions. For example, the \c{obj} format allows common
3456 variables to be NEAR or FAR, and the \c{elf} format allows you to
3457 specify the alignment requirements of a common variable:
3459 \c common commvar 4:near ; works in OBJ
3460 \c common intarray 100:4 ; works in ELF: 4 byte aligned
3462 Once again, like \c{EXTERN} and \c{GLOBAL}, the primitive form of
3463 \c{COMMON} differs from the user-level form only in that it can take
3464 only one argument at a time.
3467 \H{CPU} \i\c{CPU XXX}: Defining CPU Dependencies
3469 The \i\c{CPU} directive restricts assembly to those instructions which
3470 are available on the specified CPU.
3474 \b\c{CPU 8086} Assemble only 8086 instruction set
3476 \b\c{CPU 186} Assemble instructions up to the 80186 instruction set
3478 \b\c{CPU 286} Assemble instructions up to the 286 instruction set
3480 \b\c{CPU 386} Assemble instructions up to the 386 instruction set
3482 \b\c{CPU 486} 486 instruction set
3484 \b\c{CPU 586} Pentium instruction set
3486 \b\c{CPU PENTIUM} Same as 586
3488 \b\c{CPU 686} P6 instruction set
3490 \b\c{CPU PPRO} Same as 686
3492 \b\c{CPU P2} Same as 686
3494 \b\c{CPU P3} Pentium III and Katmai instruction sets
3496 \b\c{CPU KATMAI} Same as P3
3498 \b\c{CPU P4} Pentium 4 (Willamette) instruction set
3500 \b\c{CPU WILLAMETTE} Same as P4
3502 All options are case insensitive. All instructions will
3503 be selected only if they apply to the selected cpu or lower.
3506 \C{outfmt} \i{Output Formats}
3508 NASM is a portable assembler, designed to be able to compile on any
3509 ANSI C-supporting platform and produce output to run on a variety of
3510 Intel x86 operating systems. For this reason, it has a large number
3511 of available output formats, selected using the \i\c{-f} option on
3512 the NASM \i{command line}. Each of these formats, along with its
3513 extensions to the base NASM syntax, is detailed in this chapter.
3515 As stated in \k{opt-o}, NASM chooses a \i{default name} for your
3516 output file based on the input file name and the chosen output
3517 format. This will be generated by removing the \i{extension}
3518 (\c{.asm}, \c{.s}, or whatever you like to use) from the input file
3519 name, and substituting an extension defined by the output format.
3520 The extensions are given with each format below.
3523 \H{binfmt} \i\c{bin}: \i{Flat-Form Binary}\I{pure binary} Output
3525 The \c{bin} format does not produce object files: it generates
3526 nothing in the output file except the code you wrote. Such `pure
3527 binary' files are used by \i{MS-DOS}: \i\c{.COM} executables and
3528 \i\c{.SYS} device drivers are pure binary files. Pure binary output
3529 is also useful for \i{operating system} and \i{boot loader}
3532 The \c{bin} format supports \i{multiple section names}. For details of
3533 how nasm handles sections in the \c{bin} format, see \k{multisec}.
3535 Using the \c{bin} format puts NASM by default into 16-bit mode (see
3536 \k{bits}). In order to use \c{bin} to write 32-bit code such as an
3537 OS kernel, you need to explicitly issue the \I\c{BITS}\c{BITS 32}
3540 \c{bin} has no default output file name extension: instead, it
3541 leaves your file name as it is once the original extension has been
3542 removed. Thus, the default is for NASM to assemble \c{binprog.asm}
3543 into a binary file called \c{binprog}.
3546 \S{org} \i\c{ORG}: Binary File \i{Program Origin}
3548 The \c{bin} format provides an additional directive to the list
3549 given in \k{directive}: \c{ORG}. The function of the \c{ORG}
3550 directive is to specify the origin address which NASM will assume
3551 the program begins at when it is loaded into memory.
3553 For example, the following code will generate the longword
3560 Unlike the \c{ORG} directive provided by MASM-compatible assemblers,
3561 which allows you to jump around in the object file and overwrite
3562 code you have already generated, NASM's \c{ORG} does exactly what
3563 the directive says: \e{origin}. Its sole function is to specify one
3564 offset which is added to all internal address references within the
3565 section; it does not permit any of the trickery that MASM's version
3566 does. See \k{proborg} for further comments.
3569 \S{binseg} \c{bin} Extensions to the \c{SECTION}
3570 Directive\I{SECTION, bin extensions to}
3572 The \c{bin} output format extends the \c{SECTION} (or \c{SEGMENT})
3573 directive to allow you to specify the alignment requirements of
3574 segments. This is done by appending the \i\c{ALIGN} qualifier to the
3575 end of the section-definition line. For example,
3577 \c section .data align=16
3579 switches to the section \c{.data} and also specifies that it must be
3580 aligned on a 16-byte boundary.
3582 The parameter to \c{ALIGN} specifies how many low bits of the
3583 section start address must be forced to zero. The alignment value
3584 given may be any power of two.\I{section alignment, in
3585 bin}\I{segment alignment, in bin}\I{alignment, in bin sections}
3588 \S{multisec} \c{Multisection}\I{bin, multisection} support for the BIN format.
3590 The \c{bin} format allows the use of multiple sections, which are
3591 ordered according to a few basic rules.
3593 \b Any code which comes before an explicit \c{SECTION} directive
3594 is directed by default into the \c{.text} section.
3596 \b If a \c{.text} section is not given an \c{ORG} statement, it is
3597 allocated \c{ORG 0} by default.
3599 \b Sections which have an \c{ORG} statement, explicit or implicit,
3600 are placed in the order of the \c{ORG} statement. The code is padded
3601 with 0s to give the correct offsets within the output file.
3603 \b If a section has multiple \c{ORG} statements, the last \c{ORG} statement
3604 is applied to the entire section, without affecting the order in
3605 which the separate parts of the section are put together at assembly
3608 \b Sections without an \c{ORG} statement will be placed after those which
3609 do have one, and they will be placed in the order that they are first
3612 \b The \c{.data} section does not follow any special rules, unlike the
3613 \c{.text} and \c{.bss} sections.
3615 \b The \c{.bss} section will be placed after all other sections.
3617 \b All sections are aligned on dword boundaries, unless a higher level
3618 of alignment has been specified.
3620 \b Sections cannot overlap.
3623 \H{objfmt} \i\c{obj}: \i{Microsoft OMF}\I{OMF} Object Files
3625 The \c{obj} file format (NASM calls it \c{obj} rather than \c{omf}
3626 for historical reasons) is the one produced by \i{MASM} and
3627 \i{TASM}, which is typically fed to 16-bit DOS linkers to produce
3628 \i\c{.EXE} files. It is also the format used by \i{OS/2}.
3630 \c{obj} provides a default output file-name extension of \c{.obj}.
3632 \c{obj} is not exclusively a 16-bit format, though: NASM has full
3633 support for the 32-bit extensions to the format. In particular,
3634 32-bit \c{obj} format files are used by \i{Borland's Win32
3635 compilers}, instead of using Microsoft's newer \i\c{win32} object
3638 The \c{obj} format does not define any special segment names: you
3639 can call your segments anything you like. Typical names for segments
3640 in \c{obj} format files are \c{CODE}, \c{DATA} and \c{BSS}.
3642 If your source file contains code before specifying an explicit
3643 \c{SEGMENT} directive, then NASM will invent its own segment called
3644 \i\c{__NASMDEFSEG} for you.
3646 When you define a segment in an \c{obj} file, NASM defines the
3647 segment name as a symbol as well, so that you can access the segment
3648 address of the segment. So, for example:
3657 \c mov ax,data ; get segment address of data
3658 \c mov ds,ax ; and move it into DS
3659 \c inc word [dvar] ; now this reference will work
3662 The \c{obj} format also enables the use of the \i\c{SEG} and
3663 \i\c{WRT} operators, so that you can write code which does things
3668 \c mov ax,seg foo ; get preferred segment of foo
3670 \c mov ax,data ; a different segment
3672 \c mov ax,[ds:foo] ; this accesses `foo'
3673 \c mov [es:foo wrt data],bx ; so does this
3676 \S{objseg} \c{obj} Extensions to the \c{SEGMENT}
3677 Directive\I{SEGMENT, obj extensions to}
3679 The \c{obj} output format extends the \c{SEGMENT} (or \c{SECTION})
3680 directive to allow you to specify various properties of the segment
3681 you are defining. This is done by appending extra qualifiers to the
3682 end of the segment-definition line. For example,
3684 \c segment code private align=16
3686 defines the segment \c{code}, but also declares it to be a private
3687 segment, and requires that the portion of it described in this code
3688 module must be aligned on a 16-byte boundary.
3690 The available qualifiers are:
3692 \b \i\c{PRIVATE}, \i\c{PUBLIC}, \i\c{COMMON} and \i\c{STACK} specify
3693 the combination characteristics of the segment. \c{PRIVATE} segments
3694 do not get combined with any others by the linker; \c{PUBLIC} and
3695 \c{STACK} segments get concatenated together at link time; and
3696 \c{COMMON} segments all get overlaid on top of each other rather
3697 than stuck end-to-end.
3699 \b \i\c{ALIGN} is used, as shown above, to specify how many low bits
3700 of the segment start address must be forced to zero. The alignment
3701 value given may be any power of two from 1 to 4096; in reality, the
3702 only values supported are 1, 2, 4, 16, 256 and 4096, so if 8 is
3703 specified it will be rounded up to 16, and 32, 64 and 128 will all
3704 be rounded up to 256, and so on. Note that alignment to 4096-byte
3705 boundaries is a \i{PharLap} extension to the format and may not be
3706 supported by all linkers.\I{section alignment, in OBJ}\I{segment
3707 alignment, in OBJ}\I{alignment, in OBJ sections}
3709 \b \i\c{CLASS} can be used to specify the segment class; this feature
3710 indicates to the linker that segments of the same class should be
3711 placed near each other in the output file. The class name can be any
3712 word, e.g. \c{CLASS=CODE}.
3714 \b \i\c{OVERLAY}, like \c{CLASS}, is specified with an arbitrary word
3715 as an argument, and provides overlay information to an
3716 overlay-capable linker.
3718 \b Segments can be declared as \i\c{USE16} or \i\c{USE32}, which has
3719 the effect of recording the choice in the object file and also
3720 ensuring that NASM's default assembly mode when assembling in that
3721 segment is 16-bit or 32-bit respectively.
3723 \b When writing \i{OS/2} object files, you should declare 32-bit
3724 segments as \i\c{FLAT}, which causes the default segment base for
3725 anything in the segment to be the special group \c{FLAT}, and also
3726 defines the group if it is not already defined.
3728 \b The \c{obj} file format also allows segments to be declared as
3729 having a pre-defined absolute segment address, although no linkers
3730 are currently known to make sensible use of this feature;
3731 nevertheless, NASM allows you to declare a segment such as
3732 \c{SEGMENT SCREEN ABSOLUTE=0xB800} if you need to. The \i\c{ABSOLUTE}
3733 and \c{ALIGN} keywords are mutually exclusive.
3735 NASM's default segment attributes are \c{PUBLIC}, \c{ALIGN=1}, no
3736 class, no overlay, and \c{USE16}.
3739 \S{group} \i\c{GROUP}: Defining Groups of Segments\I{segments, groups of}
3741 The \c{obj} format also allows segments to be grouped, so that a
3742 single segment register can be used to refer to all the segments in
3743 a group. NASM therefore supplies the \c{GROUP} directive, whereby
3752 \c ; some uninitialised data
3754 \c group dgroup data bss
3756 which will define a group called \c{dgroup} to contain the segments
3757 \c{data} and \c{bss}. Like \c{SEGMENT}, \c{GROUP} causes the group
3758 name to be defined as a symbol, so that you can refer to a variable
3759 \c{var} in the \c{data} segment as \c{var wrt data} or as \c{var wrt
3760 dgroup}, depending on which segment value is currently in your
3763 If you just refer to \c{var}, however, and \c{var} is declared in a
3764 segment which is part of a group, then NASM will default to giving
3765 you the offset of \c{var} from the beginning of the \e{group}, not
3766 the \e{segment}. Therefore \c{SEG var}, also, will return the group
3767 base rather than the segment base.
3769 NASM will allow a segment to be part of more than one group, but
3770 will generate a warning if you do this. Variables declared in a
3771 segment which is part of more than one group will default to being
3772 relative to the first group that was defined to contain the segment.
3774 A group does not have to contain any segments; you can still make
3775 \c{WRT} references to a group which does not contain the variable
3776 you are referring to. OS/2, for example, defines the special group
3777 \c{FLAT} with no segments in it.
3780 \S{uppercase} \i\c{UPPERCASE}: Disabling Case Sensitivity in Output
3782 Although NASM itself is \i{case sensitive}, some OMF linkers are
3783 not; therefore it can be useful for NASM to output single-case
3784 object files. The \c{UPPERCASE} format-specific directive causes all
3785 segment, group and symbol names that are written to the object file
3786 to be forced to upper case just before being written. Within a
3787 source file, NASM is still case-sensitive; but the object file can
3788 be written entirely in upper case if desired.
3790 \c{UPPERCASE} is used alone on a line; it requires no parameters.
3793 \S{import} \i\c{IMPORT}: Importing DLL Symbols\I{DLL symbols,
3794 importing}\I{symbols, importing from DLLs}
3796 The \c{IMPORT} format-specific directive defines a symbol to be
3797 imported from a DLL, for use if you are writing a DLL's \i{import
3798 library} in NASM. You still need to declare the symbol as \c{EXTERN}
3799 as well as using the \c{IMPORT} directive.
3801 The \c{IMPORT} directive takes two required parameters, separated by
3802 white space, which are (respectively) the name of the symbol you
3803 wish to import and the name of the library you wish to import it
3806 \c import WSAStartup wsock32.dll
3808 A third optional parameter gives the name by which the symbol is
3809 known in the library you are importing it from, in case this is not
3810 the same as the name you wish the symbol to be known by to your code
3811 once you have imported it. For example:
3813 \c import asyncsel wsock32.dll WSAAsyncSelect
3816 \S{export} \i\c{EXPORT}: Exporting DLL Symbols\I{DLL symbols,
3817 exporting}\I{symbols, exporting from DLLs}
3819 The \c{EXPORT} format-specific directive defines a global symbol to
3820 be exported as a DLL symbol, for use if you are writing a DLL in
3821 NASM. You still need to declare the symbol as \c{GLOBAL} as well as
3822 using the \c{EXPORT} directive.
3824 \c{EXPORT} takes one required parameter, which is the name of the
3825 symbol you wish to export, as it was defined in your source file. An
3826 optional second parameter (separated by white space from the first)
3827 gives the \e{external} name of the symbol: the name by which you
3828 wish the symbol to be known to programs using the DLL. If this name
3829 is the same as the internal name, you may leave the second parameter
3832 Further parameters can be given to define attributes of the exported
3833 symbol. These parameters, like the second, are separated by white
3834 space. If further parameters are given, the external name must also
3835 be specified, even if it is the same as the internal name. The
3836 available attributes are:
3838 \b \c{resident} indicates that the exported name is to be kept
3839 resident by the system loader. This is an optimisation for
3840 frequently used symbols imported by name.
3842 \b \c{nodata} indicates that the exported symbol is a function which
3843 does not make use of any initialised data.
3845 \b \c{parm=NNN}, where \c{NNN} is an integer, sets the number of
3846 parameter words for the case in which the symbol is a call gate
3847 between 32-bit and 16-bit segments.
3849 \b An attribute which is just a number indicates that the symbol
3850 should be exported with an identifying number (ordinal), and gives
3856 \c export myfunc TheRealMoreFormalLookingFunctionName
3857 \c export myfunc myfunc 1234 ; export by ordinal
3858 \c export myfunc myfunc resident parm=23 nodata
3861 \S{dotdotstart} \i\c{..start}: Defining the \i{Program Entry
3864 \c{OMF} linkers require exactly one of the object files being linked to
3865 define the program entry point, where execution will begin when the
3866 program is run. If the object file that defines the entry point is
3867 assembled using NASM, you specify the entry point by declaring the
3868 special symbol \c{..start} at the point where you wish execution to
3872 \S{objextern} \c{obj} Extensions to the \c{EXTERN}
3873 Directive\I{EXTERN, obj extensions to}
3875 If you declare an external symbol with the directive
3879 then references such as \c{mov ax,foo} will give you the offset of
3880 \c{foo} from its preferred segment base (as specified in whichever
3881 module \c{foo} is actually defined in). So to access the contents of
3882 \c{foo} you will usually need to do something like
3884 \c mov ax,seg foo ; get preferred segment base
3885 \c mov es,ax ; move it into ES
3886 \c mov ax,[es:foo] ; and use offset `foo' from it
3888 This is a little unwieldy, particularly if you know that an external
3889 is going to be accessible from a given segment or group, say
3890 \c{dgroup}. So if \c{DS} already contained \c{dgroup}, you could
3893 \c mov ax,[foo wrt dgroup]
3895 However, having to type this every time you want to access \c{foo}
3896 can be a pain; so NASM allows you to declare \c{foo} in the
3899 \c extern foo:wrt dgroup
3901 This form causes NASM to pretend that the preferred segment base of
3902 \c{foo} is in fact \c{dgroup}; so the expression \c{seg foo} will
3903 now return \c{dgroup}, and the expression \c{foo} is equivalent to
3906 This \I{default-WRT mechanism}default-\c{WRT} mechanism can be used
3907 to make externals appear to be relative to any group or segment in
3908 your program. It can also be applied to common variables: see
3912 \S{objcommon} \c{obj} Extensions to the \c{COMMON}
3913 Directive\I{COMMON, obj extensions to}
3915 The \c{obj} format allows common variables to be either near\I{near
3916 common variables} or far\I{far common variables}; NASM allows you to
3917 specify which your variables should be by the use of the syntax
3919 \c common nearvar 2:near ; `nearvar' is a near common
3920 \c common farvar 10:far ; and `farvar' is far
3922 Far common variables may be greater in size than 64Kb, and so the
3923 OMF specification says that they are declared as a number of
3924 \e{elements} of a given size. So a 10-byte far common variable could
3925 be declared as ten one-byte elements, five two-byte elements, two
3926 five-byte elements or one ten-byte element.
3928 Some \c{OMF} linkers require the \I{element size, in common
3929 variables}\I{common variables, element size}element size, as well as
3930 the variable size, to match when resolving common variables declared
3931 in more than one module. Therefore NASM must allow you to specify
3932 the element size on your far common variables. This is done by the
3935 \c common c_5by2 10:far 5 ; two five-byte elements
3936 \c common c_2by5 10:far 2 ; five two-byte elements
3938 If no element size is specified, the default is 1. Also, the \c{FAR}
3939 keyword is not required when an element size is specified, since
3940 only far commons may have element sizes at all. So the above
3941 declarations could equivalently be
3943 \c common c_5by2 10:5 ; two five-byte elements
3944 \c common c_2by5 10:2 ; five two-byte elements
3946 In addition to these extensions, the \c{COMMON} directive in \c{obj}
3947 also supports default-\c{WRT} specification like \c{EXTERN} does
3948 (explained in \k{objextern}). So you can also declare things like
3950 \c common foo 10:wrt dgroup
3951 \c common bar 16:far 2:wrt data
3952 \c common baz 24:wrt data:6
3955 \H{win32fmt} \i\c{win32}: Microsoft Win32 Object Files
3957 The \c{win32} output format generates Microsoft Win32 object files,
3958 suitable for passing to Microsoft linkers such as \i{Visual C++}.
3959 Note that Borland Win32 compilers do not use this format, but use
3960 \c{obj} instead (see \k{objfmt}).
3962 \c{win32} provides a default output file-name extension of \c{.obj}.
3964 Note that although Microsoft say that Win32 object files follow the
3965 \c{COFF} (Common Object File Format) standard, the object files produced
3966 by Microsoft Win32 compilers are not compatible with COFF linkers
3967 such as DJGPP's, and vice versa. This is due to a difference of
3968 opinion over the precise semantics of PC-relative relocations. To
3969 produce COFF files suitable for DJGPP, use NASM's \c{coff} output
3970 format; conversely, the \c{coff} format does not produce object
3971 files that Win32 linkers can generate correct output from.
3974 \S{win32sect} \c{win32} Extensions to the \c{SECTION}
3975 Directive\I{SECTION, win32 extensions to}
3977 Like the \c{obj} format, \c{win32} allows you to specify additional
3978 information on the \c{SECTION} directive line, to control the type
3979 and properties of sections you declare. Section types and properties
3980 are generated automatically by NASM for the \i{standard section names}
3981 \c{.text}, \c{.data} and \c{.bss}, but may still be overridden by
3984 The available qualifiers are:
3986 \b \c{code}, or equivalently \c{text}, defines the section to be a
3987 code section. This marks the section as readable and executable, but
3988 not writable, and also indicates to the linker that the type of the
3991 \b \c{data} and \c{bss} define the section to be a data section,
3992 analogously to \c{code}. Data sections are marked as readable and
3993 writable, but not executable. \c{data} declares an initialised data
3994 section, whereas \c{bss} declares an uninitialised data section.
3996 \b \c{rdata} declares an initialised data section that is readable
3997 but not writable. Microsoft compilers use this section to place
4000 \b \c{info} defines the section to be an \i{informational section},
4001 which is not included in the executable file by the linker, but may
4002 (for example) pass information \e{to} the linker. For example,
4003 declaring an \c{info}-type section called \i\c{.drectve} causes the
4004 linker to interpret the contents of the section as command-line
4007 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
4008 \I{section alignment, in win32}\I{alignment, in win32
4009 sections}alignment requirements of the section. The maximum you may
4010 specify is 64: the Win32 object file format contains no means to
4011 request a greater section alignment than this. If alignment is not
4012 explicitly specified, the defaults are 16-byte alignment for code
4013 sections, 8-byte alignment for rdata sections and 4-byte alignment
4014 for data (and BSS) sections.
4015 Informational sections get a default alignment of 1 byte (no
4016 alignment), though the value does not matter.
4018 The defaults assumed by NASM if you do not specify the above
4021 \c section .text code align=16
4022 \c section .data data align=4
4023 \c section .rdata rdata align=8
4024 \c section .bss bss align=4
4026 Any other section name is treated by default like \c{.text}.
4029 \H{cofffmt} \i\c{coff}: \i{Common Object File Format}
4031 The \c{coff} output type produces \c{COFF} object files suitable for
4032 linking with the \i{DJGPP} linker.
4034 \c{coff} provides a default output file-name extension of \c{.o}.
4036 The \c{coff} format supports the same extensions to the \c{SECTION}
4037 directive as \c{win32} does, except that the \c{align} qualifier and
4038 the \c{info} section type are not supported.
4041 \H{elffmt} \i\c{elf}: \I{ELF}\I{linux, elf}\i{Executable and Linkable
4042 Format} Object Files
4044 The \c{elf} output format generates \c{ELF32} (Executable and Linkable
4045 Format) object files, as used by Linux as well as \i{Unix System V},
4046 including \i{Solaris x86}, \i{UnixWare} and \i{SCO Unix}. \c{elf}
4047 provides a default output file-name extension of \c{.o}.
4050 \S{elfsect} \c{elf} Extensions to the \c{SECTION}
4051 Directive\I{SECTION, elf extensions to}
4053 Like the \c{obj} format, \c{elf} allows you to specify additional
4054 information on the \c{SECTION} directive line, to control the type
4055 and properties of sections you declare. Section types and properties
4056 are generated automatically by NASM for the \i{standard section
4057 names} \i\c{.text}, \i\c{.data} and \i\c{.bss}, but may still be
4058 overridden by these qualifiers.
4060 The available qualifiers are:
4062 \b \i\c{alloc} defines the section to be one which is loaded into
4063 memory when the program is run. \i\c{noalloc} defines it to be one
4064 which is not, such as an informational or comment section.
4066 \b \i\c{exec} defines the section to be one which should have execute
4067 permission when the program is run. \i\c{noexec} defines it as one
4070 \b \i\c{write} defines the section to be one which should be writable
4071 when the program is run. \i\c{nowrite} defines it as one which should
4074 \b \i\c{progbits} defines the section to be one with explicit contents
4075 stored in the object file: an ordinary code or data section, for
4076 example, \i\c{nobits} defines the section to be one with no explicit
4077 contents given, such as a BSS section.
4079 \b \c{align=}, used with a trailing number as in \c{obj}, gives the
4080 \I{section alignment, in elf}\I{alignment, in elf sections}alignment
4081 requirements of the section.
4083 The defaults assumed by NASM if you do not specify the above
4086 \c section .text progbits alloc exec nowrite align=16
4087 \c section .rodata progbits alloc noexec nowrite align=4
4088 \c section .data progbits alloc noexec write align=4
4089 \c section .bss nobits alloc noexec write align=4
4090 \c section other progbits alloc noexec nowrite align=1
4092 (Any section name other than \c{.text}, \c{.rodata}, \c{.data} and
4093 \c{.bss} is treated by default like \c{other} in the above code.)
4096 \S{elfwrt} \i{Position-Independent Code}\I{PIC}: \c{elf} Special
4097 Symbols and \i\c{WRT}
4099 The \c{ELF} specification contains enough features to allow
4100 position-independent code (PIC) to be written, which makes \i{ELF
4101 shared libraries} very flexible. However, it also means NASM has to
4102 be able to generate a variety of strange relocation types in ELF
4103 object files, if it is to be an assembler which can write PIC.
4105 Since \c{ELF} does not support segment-base references, the \c{WRT}
4106 operator is not used for its normal purpose; therefore NASM's
4107 \c{elf} output format makes use of \c{WRT} for a different purpose,
4108 namely the PIC-specific \I{relocations, PIC-specific}relocation
4111 \c{elf} defines five special symbols which you can use as the
4112 right-hand side of the \c{WRT} operator to obtain PIC relocation
4113 types. They are \i\c{..gotpc}, \i\c{..gotoff}, \i\c{..got},
4114 \i\c{..plt} and \i\c{..sym}. Their functions are summarised here:
4116 \b Referring to the symbol marking the global offset table base
4117 using \c{wrt ..gotpc} will end up giving the distance from the
4118 beginning of the current section to the global offset table.
4119 (\i\c{_GLOBAL_OFFSET_TABLE_} is the standard symbol name used to
4120 refer to the \i{GOT}.) So you would then need to add \i\c{$$} to the
4121 result to get the real address of the GOT.
4123 \b Referring to a location in one of your own sections using \c{wrt
4124 ..gotoff} will give the distance from the beginning of the GOT to
4125 the specified location, so that adding on the address of the GOT
4126 would give the real address of the location you wanted.
4128 \b Referring to an external or global symbol using \c{wrt ..got}
4129 causes the linker to build an entry \e{in} the GOT containing the
4130 address of the symbol, and the reference gives the distance from the
4131 beginning of the GOT to the entry; so you can add on the address of
4132 the GOT, load from the resulting address, and end up with the
4133 address of the symbol.
4135 \b Referring to a procedure name using \c{wrt ..plt} causes the
4136 linker to build a \i{procedure linkage table} entry for the symbol,
4137 and the reference gives the address of the \i{PLT} entry. You can
4138 only use this in contexts which would generate a PC-relative
4139 relocation normally (i.e. as the destination for \c{CALL} or
4140 \c{JMP}), since ELF contains no relocation type to refer to PLT
4143 \b Referring to a symbol name using \c{wrt ..sym} causes NASM to
4144 write an ordinary relocation, but instead of making the relocation
4145 relative to the start of the section and then adding on the offset
4146 to the symbol, it will write a relocation record aimed directly at
4147 the symbol in question. The distinction is a necessary one due to a
4148 peculiarity of the dynamic linker.
4150 A fuller explanation of how to use these relocation types to write
4151 shared libraries entirely in NASM is given in \k{picdll}.
4154 \S{elfglob} \c{elf} Extensions to the \c{GLOBAL} Directive\I{GLOBAL,
4155 elf extensions to}\I{GLOBAL, aoutb extensions to}
4157 \c{ELF} object files can contain more information about a global symbol
4158 than just its address: they can contain the \I{symbol sizes,
4159 specifying}\I{size, of symbols}size of the symbol and its \I{symbol
4160 types, specifying}\I{type, of symbols}type as well. These are not
4161 merely debugger conveniences, but are actually necessary when the
4162 program being written is a \i{shared library}. NASM therefore
4163 supports some extensions to the \c{GLOBAL} directive, allowing you
4164 to specify these features.
4166 You can specify whether a global variable is a function or a data
4167 object by suffixing the name with a colon and the word
4168 \i\c{function} or \i\c{data}. (\i\c{object} is a synonym for
4169 \c{data}.) For example:
4171 \c global hashlookup:function, hashtable:data
4173 exports the global symbol \c{hashlookup} as a function and
4174 \c{hashtable} as a data object.
4176 You can also specify the size of the data associated with the
4177 symbol, as a numeric expression (which may involve labels, and even
4178 forward references) after the type specifier. Like this:
4180 \c global hashtable:data (hashtable.end - hashtable)
4183 \c db this,that,theother ; some data here
4186 This makes NASM automatically calculate the length of the table and
4187 place that information into the \c{ELF} symbol table.
4189 Declaring the type and size of global symbols is necessary when
4190 writing shared library code. For more information, see
4194 \S{elfcomm} \c{elf} Extensions to the \c{COMMON} Directive
4195 \I{COMMON, elf extensions to}
4197 \c{ELF} also allows you to specify alignment requirements \I{common
4198 variables, alignment in elf}\I{alignment, of elf common variables}on
4199 common variables. This is done by putting a number (which must be a
4200 power of two) after the name and size of the common variable,
4201 separated (as usual) by a colon. For example, an array of
4202 doublewords would benefit from 4-byte alignment:
4204 \c common dwordarray 128:4
4206 This declares the total size of the array to be 128 bytes, and
4207 requires that it be aligned on a 4-byte boundary.
4210 \S{elf16} 16-bit code and ELF
4211 \I{ELF, 16-bit code and}
4213 The \c{ELF32} specification doesn't provide relocations for 8- and
4214 16-bit values, but the GNU \c{ld} linker adds these as an extension.
4215 NASM can generate GNU-compatible relocations, to allow 16-bit code to
4216 be linked as ELF using GNU \c{ld}. If NASM is used with the
4217 \c{-w+gnu-elf-extensions} option, a warning is issued when one of
4218 these relocations is generated.
4220 \H{aoutfmt} \i\c{aout}: Linux \I{a.out, Linux version}\I{linux, a.out}\c{a.out} Object Files
4222 The \c{aout} format generates \c{a.out} object files, in the form used
4223 by early Linux systems (current Linux systems use ELF, see
4224 \k{elffmt}.) These differ from other \c{a.out} object files in that
4225 the magic number in the first four bytes of the file is
4226 different; also, some implementations of \c{a.out}, for example
4227 NetBSD's, support position-independent code, which Linux's
4228 implementation does not.
4230 \c{a.out} provides a default output file-name extension of \c{.o}.
4232 \c{a.out} is a very simple object format. It supports no special
4233 directives, no special symbols, no use of \c{SEG} or \c{WRT}, and no
4234 extensions to any standard directives. It supports only the three
4235 \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4238 \H{aoutfmt} \i\c{aoutb}: \i{NetBSD}/\i{FreeBSD}/\i{OpenBSD}
4239 \I{a.out, BSD version}\c{a.out} Object Files
4241 The \c{aoutb} format generates \c{a.out} object files, in the form
4242 used by the various free \c{BSD Unix} clones, \c{NetBSD}, \c{FreeBSD}
4243 and \c{OpenBSD}. For simple object files, this object format is exactly
4244 the same as \c{aout} except for the magic number in the first four bytes
4245 of the file. However, the \c{aoutb} format supports
4246 \I{PIC}\i{position-independent code} in the same way as the \c{elf}
4247 format, so you can use it to write \c{BSD} \i{shared libraries}.
4249 \c{aoutb} provides a default output file-name extension of \c{.o}.
4251 \c{aoutb} supports no special directives, no special symbols, and
4252 only the three \i{standard section names} \i\c{.text}, \i\c{.data}
4253 and \i\c{.bss}. However, it also supports the same use of \i\c{WRT} as
4254 \c{elf} does, to provide position-independent code relocation types.
4255 See \k{elfwrt} for full documentation of this feature.
4257 \c{aoutb} also supports the same extensions to the \c{GLOBAL}
4258 directive as \c{elf} does: see \k{elfglob} for documentation of
4262 \H{as86fmt} \c{as86}: \i{Minix}/Linux\I{linux, as86} \i\c{as86} Object Files
4264 The Minix/Linux 16-bit assembler \c{as86} has its own non-standard
4265 object file format. Although its companion linker \i\c{ld86} produces
4266 something close to ordinary \c{a.out} binaries as output, the object
4267 file format used to communicate between \c{as86} and \c{ld86} is not
4270 NASM supports this format, just in case it is useful, as \c{as86}.
4271 \c{as86} provides a default output file-name extension of \c{.o}.
4273 \c{as86} is a very simple object format (from the NASM user's point
4274 of view). It supports no special directives, no special symbols, no
4275 use of \c{SEG} or \c{WRT}, and no extensions to any standard
4276 directives. It supports only the three \i{standard section names}
4277 \i\c{.text}, \i\c{.data} and \i\c{.bss}.
4280 \H{rdffmt} \I{RDOFF}\i\c{rdf}: \i{Relocatable Dynamic Object File
4283 The \c{rdf} output format produces \c{RDOFF} object files. \c{RDOFF}
4284 (Relocatable Dynamic Object File Format) is a home-grown object-file
4285 format, designed alongside NASM itself and reflecting in its file
4286 format the internal structure of the assembler.
4288 \c{RDOFF} is not used by any well-known operating systems. Those
4289 writing their own systems, however, may well wish to use \c{RDOFF}
4290 as their object format, on the grounds that it is designed primarily
4291 for simplicity and contains very little file-header bureaucracy.
4293 The Unix NASM archive, and the DOS archive which includes sources,
4294 both contain an \I{rdoff subdirectory}\c{rdoff} subdirectory holding
4295 a set of RDOFF utilities: an RDF linker, an \c{RDF} static-library
4296 manager, an RDF file dump utility, and a program which will load and
4297 execute an RDF executable under Linux.
4299 \c{rdf} supports only the \i{standard section names} \i\c{.text},
4300 \i\c{.data} and \i\c{.bss}.
4303 \S{rdflib} Requiring a Library: The \i\c{LIBRARY} Directive
4305 \c{RDOFF} contains a mechanism for an object file to demand a given
4306 library to be linked to the module, either at load time or run time.
4307 This is done by the \c{LIBRARY} directive, which takes one argument
4308 which is the name of the module:
4310 \c library mylib.rdl
4313 \S{rdfmod} Specifying a Module Name: The \i\c{MODULE} Directive
4315 Special \c{RDOFF} header record is used to store the name of the module.
4316 It can be used, for example, by run-time loader to perform dynamic
4317 linking. \c{MODULE} directive takes one argument which is the name
4322 Note that when you statically link modules and tell linker to strip
4323 the symbols from output file, all module names will be stripped too.
4324 To avoid it, you should start module names with \I{$, prefix}\c{$}, like:
4326 \c module $kernel.core
4329 \S{rdfglob} \c{rdf} Extensions to the \c{GLOBAL} directive\I{GLOBAL,
4332 \c{RDOFF} global symbols can contain additional information needed by
4333 the static linker. You can mark a global symbol as exported, thus
4334 telling the linker do not strip it from target executable or library
4335 file. Like in \c{ELF}, you can also specify whether an exported symbol
4336 is a procedure (function) or data object.
4338 Suffixing the name with a colon and the word \i\c{export} you make the
4341 \c global sys_open:export
4343 To specify that exported symbol is a procedure (function), you add the
4344 word \i\c{proc} or \i\c{function} after declaration:
4346 \c global sys_open:export proc
4348 Similarly, to specify exported data object, add the word \i\c{data}
4349 or \i\c{object} to the directive:
4351 \c global kernel_ticks:export data
4354 \H{dbgfmt} \i\c{dbg}: Debugging Format
4356 The \c{dbg} output format is not built into NASM in the default
4357 configuration. If you are building your own NASM executable from the
4358 sources, you can define \i\c{OF_DBG} in \c{outform.h} or on the
4359 compiler command line, and obtain the \c{dbg} output format.
4361 The \c{dbg} format does not output an object file as such; instead,
4362 it outputs a text file which contains a complete list of all the
4363 transactions between the main body of NASM and the output-format
4364 back end module. It is primarily intended to aid people who want to
4365 write their own output drivers, so that they can get a clearer idea
4366 of the various requests the main program makes of the output driver,
4367 and in what order they happen.
4369 For simple files, one can easily use the \c{dbg} format like this:
4371 \c nasm -f dbg filename.asm
4373 which will generate a diagnostic file called \c{filename.dbg}.
4374 However, this will not work well on files which were designed for a
4375 different object format, because each object format defines its own
4376 macros (usually user-level forms of directives), and those macros
4377 will not be defined in the \c{dbg} format. Therefore it can be
4378 useful to run NASM twice, in order to do the preprocessing with the
4379 native object format selected:
4381 \c nasm -e -f rdf -o rdfprog.i rdfprog.asm
4382 \c nasm -a -f dbg rdfprog.i
4384 This preprocesses \c{rdfprog.asm} into \c{rdfprog.i}, keeping the
4385 \c{rdf} object format selected in order to make sure RDF special
4386 directives are converted into primitive form correctly. Then the
4387 preprocessed source is fed through the \c{dbg} format to generate
4388 the final diagnostic output.
4390 This workaround will still typically not work for programs intended
4391 for \c{obj} format, because the \c{obj} \c{SEGMENT} and \c{GROUP}
4392 directives have side effects of defining the segment and group names
4393 as symbols; \c{dbg} will not do this, so the program will not
4394 assemble. You will have to work around that by defining the symbols
4395 yourself (using \c{EXTERN}, for example) if you really need to get a
4396 \c{dbg} trace of an \c{obj}-specific source file.
4398 \c{dbg} accepts any section name and any directives at all, and logs
4399 them all to its output file.
4402 \C{16bit} Writing 16-bit Code (DOS, Windows 3/3.1)
4404 This chapter attempts to cover some of the common issues encountered
4405 when writing 16-bit code to run under \c{MS-DOS} or \c{Windows 3.x}. It
4406 covers how to link programs to produce \c{.EXE} or \c{.COM} files,
4407 how to write \c{.SYS} device drivers, and how to interface assembly
4408 language code with 16-bit C compilers and with Borland Pascal.
4411 \H{exefiles} Producing \i\c{.EXE} Files
4413 Any large program written under DOS needs to be built as a \c{.EXE}
4414 file: only \c{.EXE} files have the necessary internal structure
4415 required to span more than one 64K segment. \i{Windows} programs,
4416 also, have to be built as \c{.EXE} files, since Windows does not
4417 support the \c{.COM} format.
4419 In general, you generate \c{.EXE} files by using the \c{obj} output
4420 format to produce one or more \i\c{.OBJ} files, and then linking
4421 them together using a linker. However, NASM also supports the direct
4422 generation of simple DOS \c{.EXE} files using the \c{bin} output
4423 format (by using \c{DB} and \c{DW} to construct the \c{.EXE} file
4424 header), and a macro package is supplied to do this. Thanks to
4425 Yann Guidon for contributing the code for this.
4427 NASM may also support \c{.EXE} natively as another output format in
4431 \S{objexe} Using the \c{obj} Format To Generate \c{.EXE} Files
4433 This section describes the usual method of generating \c{.EXE} files
4434 by linking \c{.OBJ} files together.
4436 Most 16-bit programming language packages come with a suitable
4437 linker; if you have none of these, there is a free linker called
4438 \i{VAL}\I{linker, free}, available in \c{LZH} archive format from
4439 \W{ftp://x2ftp.oulu.fi/pub/msdos/programming/lang/}\i\c{x2ftp.oulu.fi}.
4440 An LZH archiver can be found at
4441 \W{ftp://ftp.simtel.net/pub/simtelnet/msdos/arcers}\i\c{ftp.simtel.net}.
4442 There is another `free' linker (though this one doesn't come with
4443 sources) called \i{FREELINK}, available from
4444 \W{http://www.pcorner.com/tpc/old/3-101.html}\i\c{www.pcorner.com}.
4445 A third, \i\c{djlink}, written by DJ Delorie, is available at
4446 \W{http://www.delorie.com/djgpp/16bit/djlink/}\i\c{www.delorie.com}.
4447 A fourth linker, \i\c{ALINK}, written by Anthony A.J. Williams, is
4448 available at \W{http://alink.sourceforge.net}\i\c{alink.sourceforge.net}.
4450 When linking several \c{.OBJ} files into a \c{.EXE} file, you should
4451 ensure that exactly one of them has a start point defined (using the
4452 \I{program entry point}\i\c{..start} special symbol defined by the
4453 \c{obj} format: see \k{dotdotstart}). If no module defines a start
4454 point, the linker will not know what value to give the entry-point
4455 field in the output file header; if more than one defines a start
4456 point, the linker will not know \e{which} value to use.
4458 An example of a NASM source file which can be assembled to a
4459 \c{.OBJ} file and linked on its own to a \c{.EXE} is given here. It
4460 demonstrates the basic principles of defining a stack, initialising
4461 the segment registers, and declaring a start point. This file is
4462 also provided in the \I{test subdirectory}\c{test} subdirectory of
4463 the NASM archives, under the name \c{objexe.asm}.
4474 This initial piece of code sets up \c{DS} to point to the data
4475 segment, and initialises \c{SS} and \c{SP} to point to the top of
4476 the provided stack. Notice that interrupts are implicitly disabled
4477 for one instruction after a move into \c{SS}, precisely for this
4478 situation, so that there's no chance of an interrupt occurring
4479 between the loads of \c{SS} and \c{SP} and not having a stack to
4482 Note also that the special symbol \c{..start} is defined at the
4483 beginning of this code, which means that will be the entry point
4484 into the resulting executable file.
4490 The above is the main program: load \c{DS:DX} with a pointer to the
4491 greeting message (\c{hello} is implicitly relative to the segment
4492 \c{data}, which was loaded into \c{DS} in the setup code, so the
4493 full pointer is valid), and call the DOS print-string function.
4498 This terminates the program using another DOS system call.
4502 \c hello: db 'hello, world', 13, 10, '$'
4504 The data segment contains the string we want to display.
4506 \c segment stack stack
4510 The above code declares a stack segment containing 64 bytes of
4511 uninitialised stack space, and points \c{stacktop} at the top of it.
4512 The directive \c{segment stack stack} defines a segment \e{called}
4513 \c{stack}, and also of \e{type} \c{STACK}. The latter is not
4514 necessary to the correct running of the program, but linkers are
4515 likely to issue warnings or errors if your program has no segment of
4518 The above file, when assembled into a \c{.OBJ} file, will link on
4519 its own to a valid \c{.EXE} file, which when run will print `hello,
4520 world' and then exit.
4523 \S{binexe} Using the \c{bin} Format To Generate \c{.EXE} Files
4525 The \c{.EXE} file format is simple enough that it's possible to
4526 build a \c{.EXE} file by writing a pure-binary program and sticking
4527 a 32-byte header on the front. This header is simple enough that it
4528 can be generated using \c{DB} and \c{DW} commands by NASM itself, so
4529 that you can use the \c{bin} output format to directly generate
4532 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4533 subdirectory, is a file \i\c{exebin.mac} of macros. It defines three
4534 macros: \i\c{EXE_begin}, \i\c{EXE_stack} and \i\c{EXE_end}.
4536 To produce a \c{.EXE} file using this method, you should start by
4537 using \c{%include} to load the \c{exebin.mac} macro package into
4538 your source file. You should then issue the \c{EXE_begin} macro call
4539 (which takes no arguments) to generate the file header data. Then
4540 write code as normal for the \c{bin} format - you can use all three
4541 standard sections \c{.text}, \c{.data} and \c{.bss}. At the end of
4542 the file you should call the \c{EXE_end} macro (again, no arguments),
4543 which defines some symbols to mark section sizes, and these symbols
4544 are referred to in the header code generated by \c{EXE_begin}.
4546 In this model, the code you end up writing starts at \c{0x100}, just
4547 like a \c{.COM} file - in fact, if you strip off the 32-byte header
4548 from the resulting \c{.EXE} file, you will have a valid \c{.COM}
4549 program. All the segment bases are the same, so you are limited to a
4550 64K program, again just like a \c{.COM} file. Note that an \c{ORG}
4551 directive is issued by the \c{EXE_begin} macro, so you should not
4552 explicitly issue one of your own.
4554 You can't directly refer to your segment base value, unfortunately,
4555 since this would require a relocation in the header, and things
4556 would get a lot more complicated. So you should get your segment
4557 base by copying it out of \c{CS} instead.
4559 On entry to your \c{.EXE} file, \c{SS:SP} are already set up to
4560 point to the top of a 2Kb stack. You can adjust the default stack
4561 size of 2Kb by calling the \c{EXE_stack} macro. For example, to
4562 change the stack size of your program to 64 bytes, you would call
4565 A sample program which generates a \c{.EXE} file in this way is
4566 given in the \c{test} subdirectory of the NASM archive, as
4570 \H{comfiles} Producing \i\c{.COM} Files
4572 While large DOS programs must be written as \c{.EXE} files, small
4573 ones are often better written as \c{.COM} files. \c{.COM} files are
4574 pure binary, and therefore most easily produced using the \c{bin}
4578 \S{combinfmt} Using the \c{bin} Format To Generate \c{.COM} Files
4580 \c{.COM} files expect to be loaded at offset \c{100h} into their
4581 segment (though the segment may change). Execution then begins at
4582 \I\c{ORG}\c{100h}, i.e. right at the start of the program. So to
4583 write a \c{.COM} program, you would create a source file looking
4591 \c ; put your code here
4595 \c ; put data items here
4599 \c ; put uninitialised data here
4601 The \c{bin} format puts the \c{.text} section first in the file, so
4602 you can declare data or BSS items before beginning to write code if
4603 you want to and the code will still end up at the front of the file
4606 The BSS (uninitialised data) section does not take up space in the
4607 \c{.COM} file itself: instead, addresses of BSS items are resolved
4608 to point at space beyond the end of the file, on the grounds that
4609 this will be free memory when the program is run. Therefore you
4610 should not rely on your BSS being initialised to all zeros when you
4613 To assemble the above program, you should use a command line like
4615 \c nasm myprog.asm -fbin -o myprog.com
4617 The \c{bin} format would produce a file called \c{myprog} if no
4618 explicit output file name were specified, so you have to override it
4619 and give the desired file name.
4622 \S{comobjfmt} Using the \c{obj} Format To Generate \c{.COM} Files
4624 If you are writing a \c{.COM} program as more than one module, you
4625 may wish to assemble several \c{.OBJ} files and link them together
4626 into a \c{.COM} program. You can do this, provided you have a linker
4627 capable of outputting \c{.COM} files directly (\i{TLINK} does this),
4628 or alternatively a converter program such as \i\c{EXE2BIN} to
4629 transform the \c{.EXE} file output from the linker into a \c{.COM}
4632 If you do this, you need to take care of several things:
4634 \b The first object file containing code should start its code
4635 segment with a line like \c{RESB 100h}. This is to ensure that the
4636 code begins at offset \c{100h} relative to the beginning of the code
4637 segment, so that the linker or converter program does not have to
4638 adjust address references within the file when generating the
4639 \c{.COM} file. Other assemblers use an \i\c{ORG} directive for this
4640 purpose, but \c{ORG} in NASM is a format-specific directive to the
4641 \c{bin} output format, and does not mean the same thing as it does
4642 in MASM-compatible assemblers.
4644 \b You don't need to define a stack segment.
4646 \b All your segments should be in the same group, so that every time
4647 your code or data references a symbol offset, all offsets are
4648 relative to the same segment base. This is because, when a \c{.COM}
4649 file is loaded, all the segment registers contain the same value.
4652 \H{sysfiles} Producing \i\c{.SYS} Files
4654 \i{MS-DOS device drivers} - \c{.SYS} files - are pure binary files,
4655 similar to \c{.COM} files, except that they start at origin zero
4656 rather than \c{100h}. Therefore, if you are writing a device driver
4657 using the \c{bin} format, you do not need the \c{ORG} directive,
4658 since the default origin for \c{bin} is zero. Similarly, if you are
4659 using \c{obj}, you do not need the \c{RESB 100h} at the start of
4662 \c{.SYS} files start with a header structure, containing pointers to
4663 the various routines inside the driver which do the work. This
4664 structure should be defined at the start of the code segment, even
4665 though it is not actually code.
4667 For more information on the format of \c{.SYS} files, and the data
4668 which has to go in the header structure, a list of books is given in
4669 the Frequently Asked Questions list for the newsgroup
4670 \W{news:comp.os.msdos.programmer}\i\c{comp.os.msdos.programmer}.
4673 \H{16c} Interfacing to 16-bit C Programs
4675 This section covers the basics of writing assembly routines that
4676 call, or are called from, C programs. To do this, you would
4677 typically write an assembly module as a \c{.OBJ} file, and link it
4678 with your C modules to produce a \i{mixed-language program}.
4681 \S{16cunder} External Symbol Names
4683 \I{C symbol names}\I{underscore, in C symbols}C compilers have the
4684 convention that the names of all global symbols (functions or data)
4685 they define are formed by prefixing an underscore to the name as it
4686 appears in the C program. So, for example, the function a C
4687 programmer thinks of as \c{printf} appears to an assembly language
4688 programmer as \c{_printf}. This means that in your assembly
4689 programs, you can define symbols without a leading underscore, and
4690 not have to worry about name clashes with C symbols.
4692 If you find the underscores inconvenient, you can define macros to
4693 replace the \c{GLOBAL} and \c{EXTERN} directives as follows:
4709 (These forms of the macros only take one argument at a time; a
4710 \c{%rep} construct could solve this.)
4712 If you then declare an external like this:
4716 then the macro will expand it as
4719 \c %define printf _printf
4721 Thereafter, you can reference \c{printf} as if it was a symbol, and
4722 the preprocessor will put the leading underscore on where necessary.
4724 The \c{cglobal} macro works similarly. You must use \c{cglobal}
4725 before defining the symbol in question, but you would have had to do
4726 that anyway if you used \c{GLOBAL}.
4729 \S{16cmodels} \i{Memory Models}
4731 NASM contains no mechanism to support the various C memory models
4732 directly; you have to keep track yourself of which one you are
4733 writing for. This means you have to keep track of the following
4736 \b In models using a single code segment (tiny, small and compact),
4737 functions are near. This means that function pointers, when stored
4738 in data segments or pushed on the stack as function arguments, are
4739 16 bits long and contain only an offset field (the \c{CS} register
4740 never changes its value, and always gives the segment part of the
4741 full function address), and that functions are called using ordinary
4742 near \c{CALL} instructions and return using \c{RETN} (which, in
4743 NASM, is synonymous with \c{RET} anyway). This means both that you
4744 should write your own routines to return with \c{RETN}, and that you
4745 should call external C routines with near \c{CALL} instructions.
4747 \b In models using more than one code segment (medium, large and
4748 huge), functions are far. This means that function pointers are 32
4749 bits long (consisting of a 16-bit offset followed by a 16-bit
4750 segment), and that functions are called using \c{CALL FAR} (or
4751 \c{CALL seg:offset}) and return using \c{RETF}. Again, you should
4752 therefore write your own routines to return with \c{RETF} and use
4753 \c{CALL FAR} to call external routines.
4755 \b In models using a single data segment (tiny, small and medium),
4756 data pointers are 16 bits long, containing only an offset field (the
4757 \c{DS} register doesn't change its value, and always gives the
4758 segment part of the full data item address).
4760 \b In models using more than one data segment (compact, large and
4761 huge), data pointers are 32 bits long, consisting of a 16-bit offset
4762 followed by a 16-bit segment. You should still be careful not to
4763 modify \c{DS} in your routines without restoring it afterwards, but
4764 \c{ES} is free for you to use to access the contents of 32-bit data
4765 pointers you are passed.
4767 \b The huge memory model allows single data items to exceed 64K in
4768 size. In all other memory models, you can access the whole of a data
4769 item just by doing arithmetic on the offset field of the pointer you
4770 are given, whether a segment field is present or not; in huge model,
4771 you have to be more careful of your pointer arithmetic.
4773 \b In most memory models, there is a \e{default} data segment, whose
4774 segment address is kept in \c{DS} throughout the program. This data
4775 segment is typically the same segment as the stack, kept in \c{SS},
4776 so that functions' local variables (which are stored on the stack)
4777 and global data items can both be accessed easily without changing
4778 \c{DS}. Particularly large data items are typically stored in other
4779 segments. However, some memory models (though not the standard
4780 ones, usually) allow the assumption that \c{SS} and \c{DS} hold the
4781 same value to be removed. Be careful about functions' local
4782 variables in this latter case.
4784 In models with a single code segment, the segment is called
4785 \i\c{_TEXT}, so your code segment must also go by this name in order
4786 to be linked into the same place as the main code segment. In models
4787 with a single data segment, or with a default data segment, it is
4791 \S{16cfunc} Function Definitions and Function Calls
4793 \I{functions, C calling convention}The \i{C calling convention} in
4794 16-bit programs is as follows. In the following description, the
4795 words \e{caller} and \e{callee} are used to denote the function
4796 doing the calling and the function which gets called.
4798 \b The caller pushes the function's parameters on the stack, one
4799 after another, in reverse order (right to left, so that the first
4800 argument specified to the function is pushed last).
4802 \b The caller then executes a \c{CALL} instruction to pass control
4803 to the callee. This \c{CALL} is either near or far depending on the
4806 \b The callee receives control, and typically (although this is not
4807 actually necessary, in functions which do not need to access their
4808 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
4809 be able to use \c{BP} as a base pointer to find its parameters on
4810 the stack. However, the caller was probably doing this too, so part
4811 of the calling convention states that \c{BP} must be preserved by
4812 any C function. Hence the callee, if it is going to set up \c{BP} as
4813 a \i\e{frame pointer}, must push the previous value first.
4815 \b The callee may then access its parameters relative to \c{BP}.
4816 The word at \c{[BP]} holds the previous value of \c{BP} as it was
4817 pushed; the next word, at \c{[BP+2]}, holds the offset part of the
4818 return address, pushed implicitly by \c{CALL}. In a small-model
4819 (near) function, the parameters start after that, at \c{[BP+4]}; in
4820 a large-model (far) function, the segment part of the return address
4821 lives at \c{[BP+4]}, and the parameters begin at \c{[BP+6]}. The
4822 leftmost parameter of the function, since it was pushed last, is
4823 accessible at this offset from \c{BP}; the others follow, at
4824 successively greater offsets. Thus, in a function such as \c{printf}
4825 which takes a variable number of parameters, the pushing of the
4826 parameters in reverse order means that the function knows where to
4827 find its first parameter, which tells it the number and type of the
4830 \b The callee may also wish to decrease \c{SP} further, so as to
4831 allocate space on the stack for local variables, which will then be
4832 accessible at negative offsets from \c{BP}.
4834 \b The callee, if it wishes to return a value to the caller, should
4835 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
4836 of the value. Floating-point results are sometimes (depending on the
4837 compiler) returned in \c{ST0}.
4839 \b Once the callee has finished processing, it restores \c{SP} from
4840 \c{BP} if it had allocated local stack space, then pops the previous
4841 value of \c{BP}, and returns via \c{RETN} or \c{RETF} depending on
4844 \b When the caller regains control from the callee, the function
4845 parameters are still on the stack, so it typically adds an immediate
4846 constant to \c{SP} to remove them (instead of executing a number of
4847 slow \c{POP} instructions). Thus, if a function is accidentally
4848 called with the wrong number of parameters due to a prototype
4849 mismatch, the stack will still be returned to a sensible state since
4850 the caller, which \e{knows} how many parameters it pushed, does the
4853 It is instructive to compare this calling convention with that for
4854 Pascal programs (described in \k{16bpfunc}). Pascal has a simpler
4855 convention, since no functions have variable numbers of parameters.
4856 Therefore the callee knows how many parameters it should have been
4857 passed, and is able to deallocate them from the stack itself by
4858 passing an immediate argument to the \c{RET} or \c{RETF}
4859 instruction, so the caller does not have to do it. Also, the
4860 parameters are pushed in left-to-right order, not right-to-left,
4861 which means that a compiler can give better guarantees about
4862 sequence points without performance suffering.
4864 Thus, you would define a function in C style in the following way.
4865 The following example is for small model:
4872 \c sub sp,0x40 ; 64 bytes of local stack space
4873 \c mov bx,[bp+4] ; first parameter to function
4877 \c mov sp,bp ; undo "sub sp,0x40" above
4881 For a large-model function, you would replace \c{RET} by \c{RETF},
4882 and look for the first parameter at \c{[BP+6]} instead of
4883 \c{[BP+4]}. Of course, if one of the parameters is a pointer, then
4884 the offsets of \e{subsequent} parameters will change depending on
4885 the memory model as well: far pointers take up four bytes on the
4886 stack when passed as a parameter, whereas near pointers take up two.
4888 At the other end of the process, to call a C function from your
4889 assembly code, you would do something like this:
4893 \c ; and then, further down...
4895 \c push word [myint] ; one of my integer variables
4896 \c push word mystring ; pointer into my data segment
4898 \c add sp,byte 4 ; `byte' saves space
4900 \c ; then those data items...
4905 \c mystring db 'This number -> %d <- should be 1234',10,0
4907 This piece of code is the small-model assembly equivalent of the C
4910 \c int myint = 1234;
4911 \c printf("This number -> %d <- should be 1234\n", myint);
4913 In large model, the function-call code might look more like this. In
4914 this example, it is assumed that \c{DS} already holds the segment
4915 base of the segment \c{_DATA}. If not, you would have to initialise
4918 \c push word [myint]
4919 \c push word seg mystring ; Now push the segment, and...
4920 \c push word mystring ; ... offset of "mystring"
4924 The integer value still takes up one word on the stack, since large
4925 model does not affect the size of the \c{int} data type. The first
4926 argument (pushed last) to \c{printf}, however, is a data pointer,
4927 and therefore has to contain a segment and offset part. The segment
4928 should be stored second in memory, and therefore must be pushed
4929 first. (Of course, \c{PUSH DS} would have been a shorter instruction
4930 than \c{PUSH WORD SEG mystring}, if \c{DS} was set up as the above
4931 example assumed.) Then the actual call becomes a far call, since
4932 functions expect far calls in large model; and \c{SP} has to be
4933 increased by 6 rather than 4 afterwards to make up for the extra
4937 \S{16cdata} Accessing Data Items
4939 To get at the contents of C variables, or to declare variables which
4940 C can access, you need only declare the names as \c{GLOBAL} or
4941 \c{EXTERN}. (Again, the names require leading underscores, as stated
4942 in \k{16cunder}.) Thus, a C variable declared as \c{int i} can be
4943 accessed from assembler as
4949 And to declare your own integer variable which C programs can access
4950 as \c{extern int j}, you do this (making sure you are assembling in
4951 the \c{_DATA} segment, if necessary):
4957 To access a C array, you need to know the size of the components of
4958 the array. For example, \c{int} variables are two bytes long, so if
4959 a C program declares an array as \c{int a[10]}, you can access
4960 \c{a[3]} by coding \c{mov ax,[_a+6]}. (The byte offset 6 is obtained
4961 by multiplying the desired array index, 3, by the size of the array
4962 element, 2.) The sizes of the C base types in 16-bit compilers are:
4963 1 for \c{char}, 2 for \c{short} and \c{int}, 4 for \c{long} and
4964 \c{float}, and 8 for \c{double}.
4966 To access a C \i{data structure}, you need to know the offset from
4967 the base of the structure to the field you are interested in. You
4968 can either do this by converting the C structure definition into a
4969 NASM structure definition (using \i\c{STRUC}), or by calculating the
4970 one offset and using just that.
4972 To do either of these, you should read your C compiler's manual to
4973 find out how it organises data structures. NASM gives no special
4974 alignment to structure members in its own \c{STRUC} macro, so you
4975 have to specify alignment yourself if the C compiler generates it.
4976 Typically, you might find that a structure like
4983 might be four bytes long rather than three, since the \c{int} field
4984 would be aligned to a two-byte boundary. However, this sort of
4985 feature tends to be a configurable option in the C compiler, either
4986 using command-line options or \c{#pragma} lines, so you have to find
4987 out how your own compiler does it.
4990 \S{16cmacro} \i\c{c16.mac}: Helper Macros for the 16-bit C Interface
4992 Included in the NASM archives, in the \I{misc subdirectory}\c{misc}
4993 directory, is a file \c{c16.mac} of macros. It defines three macros:
4994 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
4995 used for C-style procedure definitions, and they automate a lot of
4996 the work involved in keeping track of the calling convention.
4998 (An alternative, TASM compatible form of \c{arg} is also now built
4999 into NASM's preprocessor. See \k{tasmcompat} for details.)
5001 An example of an assembly function using the macro set is given
5008 \c mov ax,[bp + %$i]
5009 \c mov bx,[bp + %$j]
5014 This defines \c{_nearproc} to be a procedure taking two arguments,
5015 the first (\c{i}) an integer and the second (\c{j}) a pointer to an
5016 integer. It returns \c{i + *j}.
5018 Note that the \c{arg} macro has an \c{EQU} as the first line of its
5019 expansion, and since the label before the macro call gets prepended
5020 to the first line of the expanded macro, the \c{EQU} works, defining
5021 \c{%$i} to be an offset from \c{BP}. A context-local variable is
5022 used, local to the context pushed by the \c{proc} macro and popped
5023 by the \c{endproc} macro, so that the same argument name can be used
5024 in later procedures. Of course, you don't \e{have} to do that.
5026 The macro set produces code for near functions (tiny, small and
5027 compact-model code) by default. You can have it generate far
5028 functions (medium, large and huge-model code) by means of coding
5029 \I\c{FARCODE}\c{%define FARCODE}. This changes the kind of return
5030 instruction generated by \c{endproc}, and also changes the starting
5031 point for the argument offsets. The macro set contains no intrinsic
5032 dependency on whether data pointers are far or not.
5034 \c{arg} can take an optional parameter, giving the size of the
5035 argument. If no size is given, 2 is assumed, since it is likely that
5036 many function parameters will be of type \c{int}.
5038 The large-model equivalent of the above function would look like this:
5046 \c mov ax,[bp + %$i]
5047 \c mov bx,[bp + %$j]
5048 \c mov es,[bp + %$j + 2]
5053 This makes use of the argument to the \c{arg} macro to define a
5054 parameter of size 4, because \c{j} is now a far pointer. When we
5055 load from \c{j}, we must load a segment and an offset.
5058 \H{16bp} Interfacing to \i{Borland Pascal} Programs
5060 Interfacing to Borland Pascal programs is similar in concept to
5061 interfacing to 16-bit C programs. The differences are:
5063 \b The leading underscore required for interfacing to C programs is
5064 not required for Pascal.
5066 \b The memory model is always large: functions are far, data
5067 pointers are far, and no data item can be more than 64K long.
5068 (Actually, some functions are near, but only those functions that
5069 are local to a Pascal unit and never called from outside it. All
5070 assembly functions that Pascal calls, and all Pascal functions that
5071 assembly routines are able to call, are far.) However, all static
5072 data declared in a Pascal program goes into the default data
5073 segment, which is the one whose segment address will be in \c{DS}
5074 when control is passed to your assembly code. The only things that
5075 do not live in the default data segment are local variables (they
5076 live in the stack segment) and dynamically allocated variables. All
5077 data \e{pointers}, however, are far.
5079 \b The function calling convention is different - described below.
5081 \b Some data types, such as strings, are stored differently.
5083 \b There are restrictions on the segment names you are allowed to
5084 use - Borland Pascal will ignore code or data declared in a segment
5085 it doesn't like the name of. The restrictions are described below.
5088 \S{16bpfunc} The Pascal Calling Convention
5090 \I{functions, Pascal calling convention}\I{Pascal calling
5091 convention}The 16-bit Pascal calling convention is as follows. In
5092 the following description, the words \e{caller} and \e{callee} are
5093 used to denote the function doing the calling and the function which
5096 \b The caller pushes the function's parameters on the stack, one
5097 after another, in normal order (left to right, so that the first
5098 argument specified to the function is pushed first).
5100 \b The caller then executes a far \c{CALL} instruction to pass
5101 control to the callee.
5103 \b The callee receives control, and typically (although this is not
5104 actually necessary, in functions which do not need to access their
5105 parameters) starts by saving the value of \c{SP} in \c{BP} so as to
5106 be able to use \c{BP} as a base pointer to find its parameters on
5107 the stack. However, the caller was probably doing this too, so part
5108 of the calling convention states that \c{BP} must be preserved by
5109 any function. Hence the callee, if it is going to set up \c{BP} as a
5110 \i{frame pointer}, must push the previous value first.
5112 \b The callee may then access its parameters relative to \c{BP}.
5113 The word at \c{[BP]} holds the previous value of \c{BP} as it was
5114 pushed. The next word, at \c{[BP+2]}, holds the offset part of the
5115 return address, and the next one at \c{[BP+4]} the segment part. The
5116 parameters begin at \c{[BP+6]}. The rightmost parameter of the
5117 function, since it was pushed last, is accessible at this offset
5118 from \c{BP}; the others follow, at successively greater offsets.
5120 \b The callee may also wish to decrease \c{SP} further, so as to
5121 allocate space on the stack for local variables, which will then be
5122 accessible at negative offsets from \c{BP}.
5124 \b The callee, if it wishes to return a value to the caller, should
5125 leave the value in \c{AL}, \c{AX} or \c{DX:AX} depending on the size
5126 of the value. Floating-point results are returned in \c{ST0}.
5127 Results of type \c{Real} (Borland's own custom floating-point data
5128 type, not handled directly by the FPU) are returned in \c{DX:BX:AX}.
5129 To return a result of type \c{String}, the caller pushes a pointer
5130 to a temporary string before pushing the parameters, and the callee
5131 places the returned string value at that location. The pointer is
5132 not a parameter, and should not be removed from the stack by the
5133 \c{RETF} instruction.
5135 \b Once the callee has finished processing, it restores \c{SP} from
5136 \c{BP} if it had allocated local stack space, then pops the previous
5137 value of \c{BP}, and returns via \c{RETF}. It uses the form of
5138 \c{RETF} with an immediate parameter, giving the number of bytes
5139 taken up by the parameters on the stack. This causes the parameters
5140 to be removed from the stack as a side effect of the return
5143 \b When the caller regains control from the callee, the function
5144 parameters have already been removed from the stack, so it needs to
5147 Thus, you would define a function in Pascal style, taking two
5148 \c{Integer}-type parameters, in the following way:
5154 \c sub sp,0x40 ; 64 bytes of local stack space
5155 \c mov bx,[bp+8] ; first parameter to function
5156 \c mov bx,[bp+6] ; second parameter to function
5160 \c mov sp,bp ; undo "sub sp,0x40" above
5162 \c retf 4 ; total size of params is 4
5164 At the other end of the process, to call a Pascal function from your
5165 assembly code, you would do something like this:
5169 \c ; and then, further down...
5171 \c push word seg mystring ; Now push the segment, and...
5172 \c push word mystring ; ... offset of "mystring"
5173 \c push word [myint] ; one of my variables
5174 \c call far SomeFunc
5176 This is equivalent to the Pascal code
5178 \c procedure SomeFunc(String: PChar; Int: Integer);
5179 \c SomeFunc(@mystring, myint);
5182 \S{16bpseg} Borland Pascal \I{segment names, Borland Pascal}Segment
5185 Since Borland Pascal's internal unit file format is completely
5186 different from \c{OBJ}, it only makes a very sketchy job of actually
5187 reading and understanding the various information contained in a
5188 real \c{OBJ} file when it links that in. Therefore an object file
5189 intended to be linked to a Pascal program must obey a number of
5192 \b Procedures and functions must be in a segment whose name is
5193 either \c{CODE}, \c{CSEG}, or something ending in \c{_TEXT}.
5195 \b Initialised data must be in a segment whose name is either
5196 \c{CONST} or something ending in \c{_DATA}.
5198 \b Uninitialised data must be in a segment whose name is either
5199 \c{DATA}, \c{DSEG}, or something ending in \c{_BSS}.
5201 \b Any other segments in the object file are completely ignored.
5202 \c{GROUP} directives and segment attributes are also ignored.
5205 \S{16bpmacro} Using \i\c{c16.mac} With Pascal Programs
5207 The \c{c16.mac} macro package, described in \k{16cmacro}, can also
5208 be used to simplify writing functions to be called from Pascal
5209 programs, if you code \I\c{PASCAL}\c{%define PASCAL}. This
5210 definition ensures that functions are far (it implies
5211 \i\c{FARCODE}), and also causes procedure return instructions to be
5212 generated with an operand.
5214 Defining \c{PASCAL} does not change the code which calculates the
5215 argument offsets; you must declare your function's arguments in
5216 reverse order. For example:
5224 \c mov ax,[bp + %$i]
5225 \c mov bx,[bp + %$j]
5226 \c mov es,[bp + %$j + 2]
5231 This defines the same routine, conceptually, as the example in
5232 \k{16cmacro}: it defines a function taking two arguments, an integer
5233 and a pointer to an integer, which returns the sum of the integer
5234 and the contents of the pointer. The only difference between this
5235 code and the large-model C version is that \c{PASCAL} is defined
5236 instead of \c{FARCODE}, and that the arguments are declared in
5240 \C{32bit} Writing 32-bit Code (Unix, Win32, DJGPP)
5242 This chapter attempts to cover some of the common issues involved
5243 when writing 32-bit code, to run under \i{Win32} or Unix, or to be
5244 linked with C code generated by a Unix-style C compiler such as
5245 \i{DJGPP}. It covers how to write assembly code to interface with
5246 32-bit C routines, and how to write position-independent code for
5249 Almost all 32-bit code, and in particular all code running under
5250 \c{Win32}, \c{DJGPP} or any of the PC Unix variants, runs in \I{flat
5251 memory model}\e{flat} memory model. This means that the segment registers
5252 and paging have already been set up to give you the same 32-bit 4Gb
5253 address space no matter what segment you work relative to, and that
5254 you should ignore all segment registers completely. When writing
5255 flat-model application code, you never need to use a segment
5256 override or modify any segment register, and the code-section
5257 addresses you pass to \c{CALL} and \c{JMP} live in the same address
5258 space as the data-section addresses you access your variables by and
5259 the stack-section addresses you access local variables and procedure
5260 parameters by. Every address is 32 bits long and contains only an
5264 \H{32c} Interfacing to 32-bit C Programs
5266 A lot of the discussion in \k{16c}, about interfacing to 16-bit C
5267 programs, still applies when working in 32 bits. The absence of
5268 memory models or segmentation worries simplifies things a lot.
5271 \S{32cunder} External Symbol Names
5273 Most 32-bit C compilers share the convention used by 16-bit
5274 compilers, that the names of all global symbols (functions or data)
5275 they define are formed by prefixing an underscore to the name as it
5276 appears in the C program. However, not all of them do: the \c{ELF}
5277 specification states that C symbols do \e{not} have a leading
5278 underscore on their assembly-language names.
5280 The older Linux \c{a.out} C compiler, all \c{Win32} compilers,
5281 \c{DJGPP}, and \c{NetBSD} and \c{FreeBSD}, all use the leading
5282 underscore; for these compilers, the macros \c{cextern} and
5283 \c{cglobal}, as given in \k{16cunder}, will still work. For \c{ELF},
5284 though, the leading underscore should not be used.
5287 \S{32cfunc} Function Definitions and Function Calls
5289 \I{functions, C calling convention}The \i{C calling convention}The C
5290 calling convention in 32-bit programs is as follows. In the
5291 following description, the words \e{caller} and \e{callee} are used
5292 to denote the function doing the calling and the function which gets
5295 \b The caller pushes the function's parameters on the stack, one
5296 after another, in reverse order (right to left, so that the first
5297 argument specified to the function is pushed last).
5299 \b The caller then executes a near \c{CALL} instruction to pass
5300 control to the callee.
5302 \b The callee receives control, and typically (although this is not
5303 actually necessary, in functions which do not need to access their
5304 parameters) starts by saving the value of \c{ESP} in \c{EBP} so as
5305 to be able to use \c{EBP} as a base pointer to find its parameters
5306 on the stack. However, the caller was probably doing this too, so
5307 part of the calling convention states that \c{EBP} must be preserved
5308 by any C function. Hence the callee, if it is going to set up
5309 \c{EBP} as a \i{frame pointer}, must push the previous value first.
5311 \b The callee may then access its parameters relative to \c{EBP}.
5312 The doubleword at \c{[EBP]} holds the previous value of \c{EBP} as
5313 it was pushed; the next doubleword, at \c{[EBP+4]}, holds the return
5314 address, pushed implicitly by \c{CALL}. The parameters start after
5315 that, at \c{[EBP+8]}. The leftmost parameter of the function, since
5316 it was pushed last, is accessible at this offset from \c{EBP}; the
5317 others follow, at successively greater offsets. Thus, in a function
5318 such as \c{printf} which takes a variable number of parameters, the
5319 pushing of the parameters in reverse order means that the function
5320 knows where to find its first parameter, which tells it the number
5321 and type of the remaining ones.
5323 \b The callee may also wish to decrease \c{ESP} further, so as to
5324 allocate space on the stack for local variables, which will then be
5325 accessible at negative offsets from \c{EBP}.
5327 \b The callee, if it wishes to return a value to the caller, should
5328 leave the value in \c{AL}, \c{AX} or \c{EAX} depending on the size
5329 of the value. Floating-point results are typically returned in
5332 \b Once the callee has finished processing, it restores \c{ESP} from
5333 \c{EBP} if it had allocated local stack space, then pops the previous
5334 value of \c{EBP}, and returns via \c{RET} (equivalently, \c{RETN}).
5336 \b When the caller regains control from the callee, the function
5337 parameters are still on the stack, so it typically adds an immediate
5338 constant to \c{ESP} to remove them (instead of executing a number of
5339 slow \c{POP} instructions). Thus, if a function is accidentally
5340 called with the wrong number of parameters due to a prototype
5341 mismatch, the stack will still be returned to a sensible state since
5342 the caller, which \e{knows} how many parameters it pushed, does the
5345 There is an alternative calling convention used by Win32 programs
5346 for Windows API calls, and also for functions called \e{by} the
5347 Windows API such as window procedures: they follow what Microsoft
5348 calls the \c{__stdcall} convention. This is slightly closer to the
5349 Pascal convention, in that the callee clears the stack by passing a
5350 parameter to the \c{RET} instruction. However, the parameters are
5351 still pushed in right-to-left order.
5353 Thus, you would define a function in C style in the following way:
5360 \c sub esp,0x40 ; 64 bytes of local stack space
5361 \c mov ebx,[ebp+8] ; first parameter to function
5365 \c leave ; mov esp,ebp / pop ebp
5368 At the other end of the process, to call a C function from your
5369 assembly code, you would do something like this:
5373 \c ; and then, further down...
5375 \c push dword [myint] ; one of my integer variables
5376 \c push dword mystring ; pointer into my data segment
5378 \c add esp,byte 8 ; `byte' saves space
5380 \c ; then those data items...
5385 \c mystring db 'This number -> %d <- should be 1234',10,0
5387 This piece of code is the assembly equivalent of the C code
5389 \c int myint = 1234;
5390 \c printf("This number -> %d <- should be 1234\n", myint);
5393 \S{32cdata} Accessing Data Items
5395 To get at the contents of C variables, or to declare variables which
5396 C can access, you need only declare the names as \c{GLOBAL} or
5397 \c{EXTERN}. (Again, the names require leading underscores, as stated
5398 in \k{32cunder}.) Thus, a C variable declared as \c{int i} can be
5399 accessed from assembler as
5404 And to declare your own integer variable which C programs can access
5405 as \c{extern int j}, you do this (making sure you are assembling in
5406 the \c{_DATA} segment, if necessary):
5411 To access a C array, you need to know the size of the components of
5412 the array. For example, \c{int} variables are four bytes long, so if
5413 a C program declares an array as \c{int a[10]}, you can access
5414 \c{a[3]} by coding \c{mov ax,[_a+12]}. (The byte offset 12 is obtained
5415 by multiplying the desired array index, 3, by the size of the array
5416 element, 4.) The sizes of the C base types in 32-bit compilers are:
5417 1 for \c{char}, 2 for \c{short}, 4 for \c{int}, \c{long} and
5418 \c{float}, and 8 for \c{double}. Pointers, being 32-bit addresses,
5419 are also 4 bytes long.
5421 To access a C \i{data structure}, you need to know the offset from
5422 the base of the structure to the field you are interested in. You
5423 can either do this by converting the C structure definition into a
5424 NASM structure definition (using \c{STRUC}), or by calculating the
5425 one offset and using just that.
5427 To do either of these, you should read your C compiler's manual to
5428 find out how it organises data structures. NASM gives no special
5429 alignment to structure members in its own \i\c{STRUC} macro, so you
5430 have to specify alignment yourself if the C compiler generates it.
5431 Typically, you might find that a structure like
5438 might be eight bytes long rather than five, since the \c{int} field
5439 would be aligned to a four-byte boundary. However, this sort of
5440 feature is sometimes a configurable option in the C compiler, either
5441 using command-line options or \c{#pragma} lines, so you have to find
5442 out how your own compiler does it.
5445 \S{32cmacro} \i\c{c32.mac}: Helper Macros for the 32-bit C Interface
5447 Included in the NASM archives, in the \I{misc directory}\c{misc}
5448 directory, is a file \c{c32.mac} of macros. It defines three macros:
5449 \i\c{proc}, \i\c{arg} and \i\c{endproc}. These are intended to be
5450 used for C-style procedure definitions, and they automate a lot of
5451 the work involved in keeping track of the calling convention.
5453 An example of an assembly function using the macro set is given
5460 \c mov eax,[ebp + %$i]
5461 \c mov ebx,[ebp + %$j]
5466 This defines \c{_proc32} to be a procedure taking two arguments, the
5467 first (\c{i}) an integer and the second (\c{j}) a pointer to an
5468 integer. It returns \c{i + *j}.
5470 Note that the \c{arg} macro has an \c{EQU} as the first line of its
5471 expansion, and since the label before the macro call gets prepended
5472 to the first line of the expanded macro, the \c{EQU} works, defining
5473 \c{%$i} to be an offset from \c{BP}. A context-local variable is
5474 used, local to the context pushed by the \c{proc} macro and popped
5475 by the \c{endproc} macro, so that the same argument name can be used
5476 in later procedures. Of course, you don't \e{have} to do that.
5478 \c{arg} can take an optional parameter, giving the size of the
5479 argument. If no size is given, 4 is assumed, since it is likely that
5480 many function parameters will be of type \c{int} or pointers.
5483 \H{picdll} Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF \i{Shared
5486 \c{ELF} replaced the older \c{a.out} object file format under Linux
5487 because it contains support for \i{position-independent code}
5488 (\i{PIC}), which makes writing shared libraries much easier. NASM
5489 supports the \c{ELF} position-independent code features, so you can
5490 write Linux \c{ELF} shared libraries in NASM.
5492 \i{NetBSD}, and its close cousins \i{FreeBSD} and \i{OpenBSD}, take
5493 a different approach by hacking PIC support into the \c{a.out}
5494 format. NASM supports this as the \i\c{aoutb} output format, so you
5495 can write \i{BSD} shared libraries in NASM too.
5497 The operating system loads a PIC shared library by memory-mapping
5498 the library file at an arbitrarily chosen point in the address space
5499 of the running process. The contents of the library's code section
5500 must therefore not depend on where it is loaded in memory.
5502 Therefore, you cannot get at your variables by writing code like
5505 \c mov eax,[myvar] ; WRONG
5507 Instead, the linker provides an area of memory called the
5508 \i\e{global offset table}, or \i{GOT}; the GOT is situated at a
5509 constant distance from your library's code, so if you can find out
5510 where your library is loaded (which is typically done using a
5511 \c{CALL} and \c{POP} combination), you can obtain the address of the
5512 GOT, and you can then load the addresses of your variables out of
5513 linker-generated entries in the GOT.
5515 The \e{data} section of a PIC shared library does not have these
5516 restrictions: since the data section is writable, it has to be
5517 copied into memory anyway rather than just paged in from the library
5518 file, so as long as it's being copied it can be relocated too. So
5519 you can put ordinary types of relocation in the data section without
5520 too much worry (but see \k{picglobal} for a caveat).
5523 \S{picgot} Obtaining the Address of the GOT
5525 Each code module in your shared library should define the GOT as an
5528 \c extern _GLOBAL_OFFSET_TABLE_ ; in ELF
5529 \c extern __GLOBAL_OFFSET_TABLE_ ; in BSD a.out
5531 At the beginning of any function in your shared library which plans
5532 to access your data or BSS sections, you must first calculate the
5533 address of the GOT. This is typically done by writing the function
5542 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-.get_GOT wrt ..gotpc
5544 \c ; the function body comes here
5551 (For BSD, again, the symbol \c{_GLOBAL_OFFSET_TABLE} requires a
5552 second leading underscore.)
5554 The first two lines of this function are simply the standard C
5555 prologue to set up a stack frame, and the last three lines are
5556 standard C function epilogue. The third line, and the fourth to last
5557 line, save and restore the \c{EBX} register, because PIC shared
5558 libraries use this register to store the address of the GOT.
5560 The interesting bit is the \c{CALL} instruction and the following
5561 two lines. The \c{CALL} and \c{POP} combination obtains the address
5562 of the label \c{.get_GOT}, without having to know in advance where
5563 the program was loaded (since the \c{CALL} instruction is encoded
5564 relative to the current position). The \c{ADD} instruction makes use
5565 of one of the special PIC relocation types: \i{GOTPC relocation}.
5566 With the \i\c{WRT ..gotpc} qualifier specified, the symbol
5567 referenced (here \c{_GLOBAL_OFFSET_TABLE_}, the special symbol
5568 assigned to the GOT) is given as an offset from the beginning of the
5569 section. (Actually, \c{ELF} encodes it as the offset from the operand
5570 field of the \c{ADD} instruction, but NASM simplifies this
5571 deliberately, so you do things the same way for both \c{ELF} and
5572 \c{BSD}.) So the instruction then \e{adds} the beginning of the section,
5573 to get the real address of the GOT, and subtracts the value of
5574 \c{.get_GOT} which it knows is in \c{EBX}. Therefore, by the time
5575 that instruction has finished, \c{EBX} contains the address of the GOT.
5577 If you didn't follow that, don't worry: it's never necessary to
5578 obtain the address of the GOT by any other means, so you can put
5579 those three instructions into a macro and safely ignore them:
5586 \c add ebx,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc
5590 \S{piclocal} Finding Your Local Data Items
5592 Having got the GOT, you can then use it to obtain the addresses of
5593 your data items. Most variables will reside in the sections you have
5594 declared; they can be accessed using the \I{GOTOFF
5595 relocation}\c{..gotoff} special \I\c{WRT ..gotoff}\c{WRT} type. The
5596 way this works is like this:
5598 \c lea eax,[ebx+myvar wrt ..gotoff]
5600 The expression \c{myvar wrt ..gotoff} is calculated, when the shared
5601 library is linked, to be the offset to the local variable \c{myvar}
5602 from the beginning of the GOT. Therefore, adding it to \c{EBX} as
5603 above will place the real address of \c{myvar} in \c{EAX}.
5605 If you declare variables as \c{GLOBAL} without specifying a size for
5606 them, they are shared between code modules in the library, but do
5607 not get exported from the library to the program that loaded it.
5608 They will still be in your ordinary data and BSS sections, so you
5609 can access them in the same way as local variables, using the above
5610 \c{..gotoff} mechanism.
5612 Note that due to a peculiarity of the way BSD \c{a.out} format
5613 handles this relocation type, there must be at least one non-local
5614 symbol in the same section as the address you're trying to access.
5617 \S{picextern} Finding External and Common Data Items
5619 If your library needs to get at an external variable (external to
5620 the \e{library}, not just to one of the modules within it), you must
5621 use the \I{GOT relocations}\I\c{WRT ..got}\c{..got} type to get at
5622 it. The \c{..got} type, instead of giving you the offset from the
5623 GOT base to the variable, gives you the offset from the GOT base to
5624 a GOT \e{entry} containing the address of the variable. The linker
5625 will set up this GOT entry when it builds the library, and the
5626 dynamic linker will place the correct address in it at load time. So
5627 to obtain the address of an external variable \c{extvar} in \c{EAX},
5630 \c mov eax,[ebx+extvar wrt ..got]
5632 This loads the address of \c{extvar} out of an entry in the GOT. The
5633 linker, when it builds the shared library, collects together every
5634 relocation of type \c{..got}, and builds the GOT so as to ensure it
5635 has every necessary entry present.
5637 Common variables must also be accessed in this way.
5640 \S{picglobal} Exporting Symbols to the Library User
5642 If you want to export symbols to the user of the library, you have
5643 to declare whether they are functions or data, and if they are data,
5644 you have to give the size of the data item. This is because the
5645 dynamic linker has to build \I{PLT}\i{procedure linkage table}
5646 entries for any exported functions, and also moves exported data
5647 items away from the library's data section in which they were
5650 So to export a function to users of the library, you must use
5652 \c global func:function ; declare it as a function
5658 And to export a data item such as an array, you would have to code
5660 \c global array:data array.end-array ; give the size too
5665 Be careful: If you export a variable to the library user, by
5666 declaring it as \c{GLOBAL} and supplying a size, the variable will
5667 end up living in the data section of the main program, rather than
5668 in your library's data section, where you declared it. So you will
5669 have to access your own global variable with the \c{..got} mechanism
5670 rather than \c{..gotoff}, as if it were external (which,
5671 effectively, it has become).
5673 Equally, if you need to store the address of an exported global in
5674 one of your data sections, you can't do it by means of the standard
5677 \c dataptr: dd global_data_item ; WRONG
5679 NASM will interpret this code as an ordinary relocation, in which
5680 \c{global_data_item} is merely an offset from the beginning of the
5681 \c{.data} section (or whatever); so this reference will end up
5682 pointing at your data section instead of at the exported global
5683 which resides elsewhere.
5685 Instead of the above code, then, you must write
5687 \c dataptr: dd global_data_item wrt ..sym
5689 which makes use of the special \c{WRT} type \I\c{WRT ..sym}\c{..sym}
5690 to instruct NASM to search the symbol table for a particular symbol
5691 at that address, rather than just relocating by section base.
5693 Either method will work for functions: referring to one of your
5694 functions by means of
5696 \c funcptr: dd my_function
5698 will give the user the address of the code you wrote, whereas
5700 \c funcptr: dd my_function wrt .sym
5702 will give the address of the procedure linkage table for the
5703 function, which is where the calling program will \e{believe} the
5704 function lives. Either address is a valid way to call the function.
5707 \S{picproc} Calling Procedures Outside the Library
5709 Calling procedures outside your shared library has to be done by
5710 means of a \i\e{procedure linkage table}, or \i{PLT}. The PLT is
5711 placed at a known offset from where the library is loaded, so the
5712 library code can make calls to the PLT in a position-independent
5713 way. Within the PLT there is code to jump to offsets contained in
5714 the GOT, so function calls to other shared libraries or to routines
5715 in the main program can be transparently passed off to their real
5718 To call an external routine, you must use another special PIC
5719 relocation type, \I{PLT relocations}\i\c{WRT ..plt}. This is much
5720 easier than the GOT-based ones: you simply replace calls such as
5721 \c{CALL printf} with the PLT-relative version \c{CALL printf WRT
5725 \S{link} Generating the Library File
5727 Having written some code modules and assembled them to \c{.o} files,
5728 you then generate your shared library with a command such as
5730 \c ld -shared -o library.so module1.o module2.o # for ELF
5731 \c ld -Bshareable -o library.so module1.o module2.o # for BSD
5733 For ELF, if your shared library is going to reside in system
5734 directories such as \c{/usr/lib} or \c{/lib}, it is usually worth
5735 using the \i\c{-soname} flag to the linker, to store the final
5736 library file name, with a version number, into the library:
5738 \c ld -shared -soname library.so.1 -o library.so.1.2 *.o
5740 You would then copy \c{library.so.1.2} into the library directory,
5741 and create \c{library.so.1} as a symbolic link to it.
5744 \C{mixsize} Mixing 16 and 32 Bit Code
5746 This chapter tries to cover some of the issues, largely related to
5747 unusual forms of addressing and jump instructions, encountered when
5748 writing operating system code such as protected-mode initialisation
5749 routines, which require code that operates in mixed segment sizes,
5750 such as code in a 16-bit segment trying to modify data in a 32-bit
5751 one, or jumps between different-size segments.
5754 \H{mixjump} Mixed-Size Jumps\I{jumps, mixed-size}
5756 \I{operating system, writing}\I{writing operating systems}The most
5757 common form of \i{mixed-size instruction} is the one used when
5758 writing a 32-bit OS: having done your setup in 16-bit mode, such as
5759 loading the kernel, you then have to boot it by switching into
5760 protected mode and jumping to the 32-bit kernel start address. In a
5761 fully 32-bit OS, this tends to be the \e{only} mixed-size
5762 instruction you need, since everything before it can be done in pure
5763 16-bit code, and everything after it can be pure 32-bit.
5765 This jump must specify a 48-bit far address, since the target
5766 segment is a 32-bit one. However, it must be assembled in a 16-bit
5767 segment, so just coding, for example,
5769 \c jmp 0x1234:0x56789ABC ; wrong!
5771 will not work, since the offset part of the address will be
5772 truncated to \c{0x9ABC} and the jump will be an ordinary 16-bit far
5775 The Linux kernel setup code gets round the inability of \c{as86} to
5776 generate the required instruction by coding it manually, using
5777 \c{DB} instructions. NASM can go one better than that, by actually
5778 generating the right instruction itself. Here's how to do it right:
5780 \c jmp dword 0x1234:0x56789ABC ; right
5782 \I\c{JMP DWORD}The \c{DWORD} prefix (strictly speaking, it should
5783 come \e{after} the colon, since it is declaring the \e{offset} field
5784 to be a doubleword; but NASM will accept either form, since both are
5785 unambiguous) forces the offset part to be treated as far, in the
5786 assumption that you are deliberately writing a jump from a 16-bit
5787 segment to a 32-bit one.
5789 You can do the reverse operation, jumping from a 32-bit segment to a
5790 16-bit one, by means of the \c{WORD} prefix:
5792 \c jmp word 0x8765:0x4321 ; 32 to 16 bit
5794 If the \c{WORD} prefix is specified in 16-bit mode, or the \c{DWORD}
5795 prefix in 32-bit mode, they will be ignored, since each is
5796 explicitly forcing NASM into a mode it was in anyway.
5799 \H{mixaddr} Addressing Between Different-Size Segments\I{addressing,
5800 mixed-size}\I{mixed-size addressing}
5802 If your OS is mixed 16 and 32-bit, or if you are writing a DOS
5803 extender, you are likely to have to deal with some 16-bit segments
5804 and some 32-bit ones. At some point, you will probably end up
5805 writing code in a 16-bit segment which has to access data in a
5806 32-bit segment, or vice versa.
5808 If the data you are trying to access in a 32-bit segment lies within
5809 the first 64K of the segment, you may be able to get away with using
5810 an ordinary 16-bit addressing operation for the purpose; but sooner
5811 or later, you will want to do 32-bit addressing from 16-bit mode.
5813 The easiest way to do this is to make sure you use a register for
5814 the address, since any effective address containing a 32-bit
5815 register is forced to be a 32-bit address. So you can do
5817 \c mov eax,offset_into_32_bit_segment_specified_by_fs
5818 \c mov dword [fs:eax],0x11223344
5820 This is fine, but slightly cumbersome (since it wastes an
5821 instruction and a register) if you already know the precise offset
5822 you are aiming at. The x86 architecture does allow 32-bit effective
5823 addresses to specify nothing but a 4-byte offset, so why shouldn't
5824 NASM be able to generate the best instruction for the purpose?
5826 It can. As in \k{mixjump}, you need only prefix the address with the
5827 \c{DWORD} keyword, and it will be forced to be a 32-bit address:
5829 \c mov dword [fs:dword my_offset],0x11223344
5831 Also as in \k{mixjump}, NASM is not fussy about whether the
5832 \c{DWORD} prefix comes before or after the segment override, so
5833 arguably a nicer-looking way to code the above instruction is
5835 \c mov dword [dword fs:my_offset],0x11223344
5837 Don't confuse the \c{DWORD} prefix \e{outside} the square brackets,
5838 which controls the size of the data stored at the address, with the
5839 one \c{inside} the square brackets which controls the length of the
5840 address itself. The two can quite easily be different:
5842 \c mov word [dword 0x12345678],0x9ABC
5844 This moves 16 bits of data to an address specified by a 32-bit
5847 You can also specify \c{WORD} or \c{DWORD} prefixes along with the
5848 \c{FAR} prefix to indirect far jumps or calls. For example:
5850 \c call dword far [fs:word 0x4321]
5852 This instruction contains an address specified by a 16-bit offset;
5853 it loads a 48-bit far pointer from that (16-bit segment and 32-bit
5854 offset), and calls that address.
5857 \H{mixother} Other Mixed-Size Instructions
5859 The other way you might want to access data might be using the
5860 string instructions (\c{LODSx}, \c{STOSx} and so on) or the
5861 \c{XLATB} instruction. These instructions, since they take no
5862 parameters, might seem to have no easy way to make them perform
5863 32-bit addressing when assembled in a 16-bit segment.
5865 This is the purpose of NASM's \i\c{a16} and \i\c{a32} prefixes. If
5866 you are coding \c{LODSB} in a 16-bit segment but it is supposed to
5867 be accessing a string in a 32-bit segment, you should load the
5868 desired address into \c{ESI} and then code
5872 The prefix forces the addressing size to 32 bits, meaning that
5873 \c{LODSB} loads from \c{[DS:ESI]} instead of \c{[DS:SI]}. To access
5874 a string in a 16-bit segment when coding in a 32-bit one, the
5875 corresponding \c{a16} prefix can be used.
5877 The \c{a16} and \c{a32} prefixes can be applied to any instruction
5878 in NASM's instruction table, but most of them can generate all the
5879 useful forms without them. The prefixes are necessary only for
5880 instructions with implicit addressing: \c{CMPSx} (\k{insCMPSB}),
5881 \c{SCASx} (\k{insSCASB}), \c{LODSx} (\k{insLODSB}), \c{STOSx}
5882 (\k{insSTOSB}), \c{MOVSx} (\k{insMOVSB}), \c{INSx} (\k{insINSB}),
5883 \c{OUTSx} (\k{insOUTSB}), and \c{XLATB} (\k{insXLATB}). Also, the
5884 various push and pop instructions (\c{PUSHA} and \c{POPF} as well as
5885 the more usual \c{PUSH} and \c{POP}) can accept \c{a16} or \c{a32}
5886 prefixes to force a particular one of \c{SP} or \c{ESP} to be used
5887 as a stack pointer, in case the stack segment in use is a different
5888 size from the code segment.
5890 \c{PUSH} and \c{POP}, when applied to segment registers in 32-bit
5891 mode, also have the slightly odd behaviour that they push and pop 4
5892 bytes at a time, of which the top two are ignored and the bottom two
5893 give the value of the segment register being manipulated. To force
5894 the 16-bit behaviour of segment-register push and pop instructions,
5895 you can use the operand-size prefix \i\c{o16}:
5900 This code saves a doubleword of stack space by fitting two segment
5901 registers into the space which would normally be consumed by pushing
5904 (You can also use the \i\c{o32} prefix to force the 32-bit behaviour
5905 when in 16-bit mode, but this seems less useful.)
5908 \C{trouble} Troubleshooting
5910 This chapter describes some of the common problems that users have
5911 been known to encounter with NASM, and answers them. It also gives
5912 instructions for reporting bugs in NASM if you find a difficulty
5913 that isn't listed here.
5916 \H{problems} Common Problems
5918 \S{inefficient} NASM Generates \i{Inefficient Code}
5920 I get a lot of `bug' reports about NASM generating inefficient, or
5921 even `wrong', code on instructions such as \c{ADD ESP,8}. This is a
5922 deliberate design feature, connected to predictability of output:
5923 NASM, on seeing \c{ADD ESP,8}, will generate the form of the
5924 instruction which leaves room for a 32-bit offset. You need to code
5925 \I\c{BYTE}\c{ADD ESP,BYTE 8} if you want the space-efficient
5926 form of the instruction. This isn't a bug: at worst it's a
5927 misfeature, and that's a matter of opinion only.
5930 \S{jmprange} My Jumps are Out of Range\I{out of range, jumps}
5932 Similarly, people complain that when they issue \i{conditional
5933 jumps} (which are \c{SHORT} by default) that try to jump too far,
5934 NASM reports `short jump out of range' instead of making the jumps
5937 This, again, is partly a predictability issue, but in fact has a
5938 more practical reason as well. NASM has no means of being told what
5939 type of processor the code it is generating will be run on; so it
5940 cannot decide for itself that it should generate \i\c{Jcc NEAR} type
5941 instructions, because it doesn't know that it's working for a 386 or
5942 above. Alternatively, it could replace the out-of-range short
5943 \c{JNE} instruction with a very short \c{JE} instruction that jumps
5944 over a \c{JMP NEAR}; this is a sensible solution for processors
5945 below a 386, but hardly efficient on processors which have good
5946 branch prediction \e{and} could have used \c{JNE NEAR} instead. So,
5947 once again, it's up to the user, not the assembler, to decide what
5948 instructions should be generated.
5951 \S{proborg} \i\c{ORG} Doesn't Work
5953 People writing \i{boot sector} programs in the \c{bin} format often
5954 complain that \c{ORG} doesn't work the way they'd like: in order to
5955 place the \c{0xAA55} signature word at the end of a 512-byte boot
5956 sector, people who are used to MASM tend to code
5960 \c ; some boot sector code
5965 This is not the intended use of the \c{ORG} directive in NASM, and
5966 will not work. The correct way to solve this problem in NASM is to
5967 use the \i\c{TIMES} directive, like this:
5971 \c ; some boot sector code
5973 \c TIMES 510-($-$$) DB 0
5976 The \c{TIMES} directive will insert exactly enough zero bytes into
5977 the output to move the assembly point up to 510. This method also
5978 has the advantage that if you accidentally fill your boot sector too
5979 full, NASM will catch the problem at assembly time and report it, so
5980 you won't end up with a boot sector that you have to disassemble to
5981 find out what's wrong with it.
5984 \S{probtimes} \i\c{TIMES} Doesn't Work
5986 The other common problem with the above code is people who write the
5991 by reasoning that \c{$} should be a pure number, just like 510, so
5992 the difference between them is also a pure number and can happily be
5995 NASM is a \e{modular} assembler: the various component parts are
5996 designed to be easily separable for re-use, so they don't exchange
5997 information unnecessarily. In consequence, the \c{bin} output
5998 format, even though it has been told by the \c{ORG} directive that
5999 the \c{.text} section should start at 0, does not pass that
6000 information back to the expression evaluator. So from the
6001 evaluator's point of view, \c{$} isn't a pure number: it's an offset
6002 from a section base. Therefore the difference between \c{$} and 510
6003 is also not a pure number, but involves a section base. Values
6004 involving section bases cannot be passed as arguments to \c{TIMES}.
6006 The solution, as in the previous section, is to code the \c{TIMES}
6009 \c TIMES 510-($-$$) DB 0
6011 in which \c{$} and \c{$$} are offsets from the same section base,
6012 and so their difference is a pure number. This will solve the
6013 problem and generate sensible code.
6016 \H{bugs} \i{Bugs}\I{reporting bugs}
6018 We have never yet released a version of NASM with any \e{known}
6019 bugs. That doesn't usually stop there being plenty we didn't know
6020 about, though. Any that you find should be reported firstly via the
6022 \W{https://sourceforge.net/projects/nasm/}\c{https://sourceforge.net/projects/nasm/}
6023 (click on "Bugs"), or if that fails then through one of the
6024 contacts in \k{contact}.
6026 Please read \k{qstart} first, and don't report the bug if it's
6027 listed in there as a deliberate feature. (If you think the feature
6028 is badly thought out, feel free to send us reasons why you think it
6029 should be changed, but don't just send us mail saying `This is a
6030 bug' if the documentation says we did it on purpose.) Then read
6031 \k{problems}, and don't bother reporting the bug if it's listed
6034 If you do report a bug, \e{please} give us all of the following
6037 \b What operating system you're running NASM under. DOS, Linux,
6038 NetBSD, Win16, Win32, VMS (I'd be impressed), whatever.
6040 \b If you're running NASM under DOS or Win32, tell us whether you've
6041 compiled your own executable from the DOS source archive, or whether
6042 you were using the standard distribution binaries out of the
6043 archive. If you were using a locally built executable, try to
6044 reproduce the problem using one of the standard binaries, as this
6045 will make it easier for us to reproduce your problem prior to fixing
6048 \b Which version of NASM you're using, and exactly how you invoked
6049 it. Give us the precise command line, and the contents of the
6050 \c{NASMENV} environment variable if any.
6052 \b Which versions of any supplementary programs you're using, and
6053 how you invoked them. If the problem only becomes visible at link
6054 time, tell us what linker you're using, what version of it you've
6055 got, and the exact linker command line. If the problem involves
6056 linking against object files generated by a compiler, tell us what
6057 compiler, what version, and what command line or options you used.
6058 (If you're compiling in an IDE, please try to reproduce the problem
6059 with the command-line version of the compiler.)
6061 \b If at all possible, send us a NASM source file which exhibits the
6062 problem. If this causes copyright problems (e.g. you can only
6063 reproduce the bug in restricted-distribution code) then bear in mind
6064 the following two points: firstly, we guarantee that any source code
6065 sent to us for the purposes of debugging NASM will be used \e{only}
6066 for the purposes of debugging NASM, and that we will delete all our
6067 copies of it as soon as we have found and fixed the bug or bugs in
6068 question; and secondly, we would prefer \e{not} to be mailed large
6069 chunks of code anyway. The smaller the file, the better. A
6070 three-line sample file that does nothing useful \e{except}
6071 demonstrate the problem is much easier to work with than a
6072 fully fledged ten-thousand-line program. (Of course, some errors
6073 \e{do} only crop up in large files, so this may not be possible.)
6075 \b A description of what the problem actually \e{is}. `It doesn't
6076 work' is \e{not} a helpful description! Please describe exactly what
6077 is happening that shouldn't be, or what isn't happening that should.
6078 Examples might be: `NASM generates an error message saying Line 3
6079 for an error that's actually on Line 5'; `NASM generates an error
6080 message that I believe it shouldn't be generating at all'; `NASM
6081 fails to generate an error message that I believe it \e{should} be
6082 generating'; `the object file produced from this source code crashes
6083 my linker'; `the ninth byte of the output file is 66 and I think it
6084 should be 77 instead'.
6086 \b If you believe the output file from NASM to be faulty, send it to
6087 us. That allows us to determine whether our own copy of NASM
6088 generates the same file, or whether the problem is related to
6089 portability issues between our development platforms and yours. We
6090 can handle binary files mailed to us as MIME attachments, uuencoded,
6091 and even BinHex. Alternatively, we may be able to provide an FTP
6092 site you can upload the suspect files to; but mailing them is easier
6095 \b Any other information or data files that might be helpful. If,
6096 for example, the problem involves NASM failing to generate an object
6097 file while TASM can generate an equivalent file without trouble,
6098 then send us \e{both} object files, so we can see what TASM is doing
6099 differently from us.
6102 \A{ndisasm} \i{Ndisasm}
6104 The Netwide Disassembler, NDISASM
6106 \H{ndisintro} Introduction
6109 The Netwide Disassembler is a small companion program to the Netwide
6110 Assembler, NASM. It seemed a shame to have an x86 assembler,
6111 complete with a full instruction table, and not make as much use of
6112 it as possible, so here's a disassembler which shares the
6113 instruction table (and some other bits of code) with NASM.
6115 The Netwide Disassembler does nothing except to produce
6116 disassemblies of \e{binary} source files. NDISASM does not have any
6117 understanding of object file formats, like \c{objdump}, and it will
6118 not understand \c{DOS .EXE} files like \c{debug} will. It just
6122 \H{ndisstart} Getting Started: Installation
6124 See \k{install} for installation instructions. NDISASM, like NASM,
6125 has a \c{man page} which you may want to put somewhere useful, if you
6126 are on a Unix system.
6129 \H{ndisrun} Running NDISASM
6131 To disassemble a file, you will typically use a command of the form
6133 \c ndisasm [-b16 | -b32] filename
6135 NDISASM can disassemble 16-bit code or 32-bit code equally easily,
6136 provided of course that you remember to specify which it is to work
6137 with. If no \i\c{-b} switch is present, NDISASM works in 16-bit mode by
6138 default. The \i\c{-u} switch (for USE32) also invokes 32-bit mode.
6140 Two more command line options are \i\c{-r} which reports the version
6141 number of NDISASM you are running, and \i\c{-h} which gives a short
6142 summary of command line options.
6145 \S{ndiscom} COM Files: Specifying an Origin
6147 To disassemble a \c{DOS .COM} file correctly, a disassembler must assume
6148 that the first instruction in the file is loaded at address \c{0x100},
6149 rather than at zero. NDISASM, which assumes by default that any file
6150 you give it is loaded at zero, will therefore need to be informed of
6153 The \i\c{-o} option allows you to declare a different origin for the
6154 file you are disassembling. Its argument may be expressed in any of
6155 the NASM numeric formats: decimal by default, if it begins with `\c{$}'
6156 or `\c{0x}' or ends in `\c{H}' it's \c{hex}, if it ends in `\c{Q}' it's
6157 \c{octal}, and if it ends in `\c{B}' it's \c{binary}.
6159 Hence, to disassemble a \c{.COM} file:
6161 \c ndisasm -o100h filename.com
6166 \S{ndissync} Code Following Data: Synchronisation
6168 Suppose you are disassembling a file which contains some data which
6169 isn't machine code, and \e{then} contains some machine code. NDISASM
6170 will faithfully plough through the data section, producing machine
6171 instructions wherever it can (although most of them will look
6172 bizarre, and some may have unusual prefixes, e.g. `\c{FS OR AX,0x240A}'),
6173 and generating `DB' instructions ever so often if it's totally stumped.
6174 Then it will reach the code section.
6176 Supposing NDISASM has just finished generating a strange machine
6177 instruction from part of the data section, and its file position is
6178 now one byte \e{before} the beginning of the code section. It's
6179 entirely possible that another spurious instruction will get
6180 generated, starting with the final byte of the data section, and
6181 then the correct first instruction in the code section will not be
6182 seen because the starting point skipped over it. This isn't really
6185 To avoid this, you can specify a `\i\c{synchronisation}' point, or indeed
6186 as many synchronisation points as you like (although NDISASM can
6187 only handle 8192 sync points internally). The definition of a sync
6188 point is this: NDISASM guarantees to hit sync points exactly during
6189 disassembly. If it is thinking about generating an instruction which
6190 would cause it to jump over a sync point, it will discard that
6191 instruction and output a `\c{db}' instead. So it \e{will} start
6192 disassembly exactly from the sync point, and so you \e{will} see all
6193 the instructions in your code section.
6195 Sync points are specified using the \i\c{-s} option: they are measured
6196 in terms of the program origin, not the file position. So if you
6197 want to synchronise after 32 bytes of a \c{.COM} file, you would have to
6200 \c ndisasm -o100h -s120h file.com
6204 \c ndisasm -o100h -s20h file.com
6206 As stated above, you can specify multiple sync markers if you need
6207 to, just by repeating the \c{-s} option.
6210 \S{ndisisync} Mixed Code and Data: Automatic (Intelligent) Synchronisation
6213 Suppose you are disassembling the boot sector of a \c{DOS} floppy (maybe
6214 it has a virus, and you need to understand the virus so that you
6215 know what kinds of damage it might have done you). Typically, this
6216 will contain a \c{JMP} instruction, then some data, then the rest of the
6217 code. So there is a very good chance of NDISASM being \e{misaligned}
6218 when the data ends and the code begins. Hence a sync point is
6221 On the other hand, why should you have to specify the sync point
6222 manually? What you'd do in order to find where the sync point would
6223 be, surely, would be to read the \c{JMP} instruction, and then to use
6224 its target address as a sync point. So can NDISASM do that for you?
6226 The answer, of course, is yes: using either of the synonymous
6227 switches \i\c{-a} (for automatic sync) or \i\c{-i} (for intelligent
6228 sync) will enable \c{auto-sync} mode. Auto-sync mode automatically
6229 generates a sync point for any forward-referring PC-relative jump or
6230 call instruction that NDISASM encounters. (Since NDISASM is one-pass,
6231 if it encounters a PC-relative jump whose target has already been
6232 processed, there isn't much it can do about it...)
6234 Only PC-relative jumps are processed, since an absolute jump is
6235 either through a register (in which case NDISASM doesn't know what
6236 the register contains) or involves a segment address (in which case
6237 the target code isn't in the same segment that NDISASM is working
6238 in, and so the sync point can't be placed anywhere useful).
6240 For some kinds of file, this mechanism will automatically put sync
6241 points in all the right places, and save you from having to place
6242 any sync points manually. However, it should be stressed that
6243 auto-sync mode is \e{not} guaranteed to catch all the sync points, and
6244 you may still have to place some manually.
6246 Auto-sync mode doesn't prevent you from declaring manual sync
6247 points: it just adds automatically generated ones to the ones you
6248 provide. It's perfectly feasible to specify \c{-i} \e{and} some \c{-s}
6251 Another caveat with auto-sync mode is that if, by some unpleasant
6252 fluke, something in your data section should disassemble to a
6253 PC-relative call or jump instruction, NDISASM may obediently place a
6254 sync point in a totally random place, for example in the middle of
6255 one of the instructions in your code section. So you may end up with
6256 a wrong disassembly even if you use auto-sync. Again, there isn't
6257 much I can do about this. If you have problems, you'll have to use
6258 manual sync points, or use the \c{-k} option (documented below) to
6259 suppress disassembly of the data area.
6262 \S{ndisother} Other Options
6264 The \i\c{-e} option skips a header on the file, by ignoring the first N
6265 bytes. This means that the header is \e{not} counted towards the
6266 disassembly offset: if you give \c{-e10 -o10}, disassembly will start
6267 at byte 10 in the file, and this will be given offset 10, not 20.
6269 The \i\c{-k} option is provided with two comma-separated numeric
6270 arguments, the first of which is an assembly offset and the second
6271 is a number of bytes to skip. This \e{will} count the skipped bytes
6272 towards the assembly offset: its use is to suppress disassembly of a
6273 data section which wouldn't contain anything you wanted to see
6277 \H{ndisbugs} Bugs and Improvements
6279 There are no known bugs. However, any you find, with patches if
6280 possible, should be sent to \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk}
6281 or \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}, or to the
6283 \W{https://sourceforge.net/projects/nasm/}\c{https://sourceforge.net/projects/nasm/}
6284 and we'll try to fix them. Feel free to send contributions and
6285 new features as well.
6287 Future plans include awareness of which processors certain
6288 instructions will run on, and marking of instructions that are too
6289 advanced for some processor (or are \c{FPU} instructions, or are
6290 undocumented opcodes, or are privileged protected-mode instructions,
6295 I hope NDISASM is of some use to somebody. Including me. :-)
6297 I don't recommend taking NDISASM apart to see how an efficient
6298 disassembler works, because as far as I know, it isn't an efficient
6299 one anyway. You have been warned.
6302 \A{iref} x86 Instruction Reference
6304 This appendix provides a complete list of the machine instructions
6305 which NASM will assemble, and a short description of the function of
6308 It is not intended to be exhaustive documentation on the fine
6309 details of the instructions' function, such as which exceptions they
6310 can trigger: for such documentation, you should go to Intel's Web
6311 site, \W{http://developer.intel.com/design/Pentium4/manuals/}\c{http://developer.intel.com/design/Pentium4/manuals/}.
6313 Instead, this appendix is intended primarily to provide
6314 documentation on the way the instructions may be used within NASM.
6315 For example, looking up \c{LOOP} will tell you that NASM allows
6316 \c{CX} or \c{ECX} to be specified as an optional second argument to
6317 the \c{LOOP} instruction, to enforce which of the two possible
6318 counter registers should be used if the default is not the one
6321 The instructions are not quite listed in alphabetical order, since
6322 groups of instructions with similar functions are lumped together in
6323 the same entry. Most of them don't move very far from their
6324 alphabetic position because of this.
6327 \H{iref-opr} Key to Operand Specifications
6329 The instruction descriptions in this appendix specify their operands
6330 using the following notation:
6332 \b Registers: \c{reg8} denotes an 8-bit \i{general purpose
6333 register}, \c{reg16} denotes a 16-bit general purpose register, and
6334 \c{reg32} a 32-bit one. \c{fpureg} denotes one of the eight FPU
6335 stack registers, \c{mmxreg} denotes one of the eight 64-bit MMX
6336 registers, and \c{segreg} denotes a segment register. In addition,
6337 some registers (such as \c{AL}, \c{DX} or
6338 \c{ECX}) may be specified explicitly.
6340 \b Immediate operands: \c{imm} denotes a generic \i{immediate operand}.
6341 \c{imm8}, \c{imm16} and \c{imm32} are used when the operand is
6342 intended to be a specific size. For some of these instructions, NASM
6343 needs an explicit specifier: for example, \c{ADD ESP,16} could be
6344 interpreted as either \c{ADD r/m32,imm32} or \c{ADD r/m32,imm8}.
6345 NASM chooses the former by default, and so you must specify \c{ADD
6346 ESP,BYTE 16} for the latter.
6348 \b Memory references: \c{mem} denotes a generic \i{memory reference};
6349 \c{mem8}, \c{mem16}, \c{mem32}, \c{mem64} and \c{mem80} are used
6350 when the operand needs to be a specific size. Again, a specifier is
6351 needed in some cases: \c{DEC [address]} is ambiguous and will be
6352 rejected by NASM. You must specify \c{DEC BYTE [address]}, \c{DEC
6353 WORD [address]} or \c{DEC DWORD [address]} instead.
6355 \b \i{Restricted memory references}: one form of the \c{MOV}
6356 instruction allows a memory address to be specified \e{without}
6357 allowing the normal range of register combinations and effective
6358 address processing. This is denoted by \c{memoffs8}, \c{memoffs16}
6361 \b Register or memory choices: many instructions can accept either a
6362 register \e{or} a memory reference as an operand. \c{r/m8} is a
6363 shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}.
6364 \c{r/m64} is MMX-related, and is a shorthand for \c{mmxreg/mem64}.
6367 \H{iref-opc} Key to Opcode Descriptions
6369 This appendix also provides the opcodes which NASM will generate for
6370 each form of each instruction. The opcodes are listed in the
6373 \b A hex number, such as \c{3F}, indicates a fixed byte containing
6376 \b A hex number followed by \c{+r}, such as \c{C8+r}, indicates that
6377 one of the operands to the instruction is a register, and the
6378 `register value' of that register should be added to the hex number
6379 to produce the generated byte. For example, EDX has register value
6380 2, so the code \c{C8+r}, when the register operand is EDX, generates
6381 the hex byte \c{CA}. Register values for specific registers are
6382 given in \k{iref-rv}.
6384 \b A hex number followed by \c{+cc}, such as \c{40+cc}, indicates
6385 that the instruction name has a condition code suffix, and the
6386 numeric representation of the condition code should be added to the
6387 hex number to produce the generated byte. For example, the code
6388 \c{40+cc}, when the instruction contains the \c{NE} condition,
6389 generates the hex byte \c{45}. Condition codes and their numeric
6390 representations are given in \k{iref-cc}.
6392 \b A slash followed by a digit, such as \c{/2}, indicates that one
6393 of the operands to the instruction is a memory address or register
6394 (denoted \c{mem} or \c{r/m}, with an optional size). This is to be
6395 encoded as an effective address, with a \i{ModR/M byte}, an optional
6396 \i{SIB byte}, and an optional displacement, and the spare (register)
6397 field of the ModR/M byte should be the digit given (which will be
6398 from 0 to 7, so it fits in three bits). The encoding of effective
6399 addresses is given in \k{iref-ea}.
6401 \b The code \c{/r} combines the above two: it indicates that one of
6402 the operands is a memory address or \c{r/m}, and another is a
6403 register, and that an effective address should be generated with the
6404 spare (register) field in the ModR/M byte being equal to the
6405 `register value' of the register operand. The encoding of effective
6406 addresses is given in \k{iref-ea}; register values are given in
6409 \b The codes \c{ib}, \c{iw} and \c{id} indicate that one of the
6410 operands to the instruction is an immediate value, and that this is
6411 to be encoded as a byte, little-endian word or little-endian
6412 doubleword respectively.
6414 \b The codes \c{rb}, \c{rw} and \c{rd} indicate that one of the
6415 operands to the instruction is an immediate value, and that the
6416 \e{difference} between this value and the address of the end of the
6417 instruction is to be encoded as a byte, word or doubleword
6418 respectively. Where the form \c{rw/rd} appears, it indicates that
6419 either \c{rw} or \c{rd} should be used according to whether assembly
6420 is being performed in \c{BITS 16} or \c{BITS 32} state respectively.
6422 \b The codes \c{ow} and \c{od} indicate that one of the operands to
6423 the instruction is a reference to the contents of a memory address
6424 specified as an immediate value: this encoding is used in some forms
6425 of the \c{MOV} instruction in place of the standard
6426 effective-address mechanism. The displacement is encoded as a word
6427 or doubleword. Again, \c{ow/od} denotes that \c{ow} or \c{od} should
6428 be chosen according to the \c{BITS} setting.
6430 \b The codes \c{o16} and \c{o32} indicate that the given form of the
6431 instruction should be assembled with operand size 16 or 32 bits. In
6432 other words, \c{o16} indicates a \c{66} prefix in \c{BITS 32} state,
6433 but generates no code in \c{BITS 16} state; and \c{o32} indicates a
6434 \c{66} prefix in \c{BITS 16} state but generates nothing in \c{BITS
6437 \b The codes \c{a16} and \c{a32}, similarly to \c{o16} and \c{o32},
6438 indicate the address size of the given form of the instruction.
6439 Where this does not match the \c{BITS} setting, a \c{67} prefix is
6443 \S{iref-rv} Register Values
6445 Where an instruction requires a register value, it is already
6446 implicit in the encoding of the rest of the instruction what type of
6447 register is intended: an 8-bit general-purpose register, a segment
6448 register, a debug register, an MMX register, or whatever. Therefore
6449 there is no problem with registers of different types sharing an
6452 The encodings for the various classes of register are:
6454 \b 8-bit general registers: \c{AL} is 0, \c{CL} is 1, \c{DL} is 2,
6455 \c{BL} is 3, \c{AH} is 4, \c{CH} is 5, \c{DH} is 6, and \c{BH} is
6458 \b 16-bit general registers: \c{AX} is 0, \c{CX} is 1, \c{DX} is 2,
6459 \c{BX} is 3, \c{SP} is 4, \c{BP} is 5, \c{SI} is 6, and \c{DI} is 7.
6461 \b 32-bit general registers: \c{EAX} is 0, \c{ECX} is 1, \c{EDX} is
6462 2, \c{EBX} is 3, \c{ESP} is 4, \c{EBP} is 5, \c{ESI} is 6, and
6465 \b \i{Segment registers}: \c{ES} is 0, \c{CS} is 1, \c{SS} is 2, \c{DS}
6466 is 3, \c{FS} is 4, and \c{GS} is 5.
6468 \b \I{floating-point, registers}Floating-point registers: \c{ST0}
6469 is 0, \c{ST1} is 1, \c{ST2} is 2, \c{ST3} is 3, \c{ST4} is 4,
6470 \c{ST5} is 5, \c{ST6} is 6, and \c{ST7} is 7.
6472 \b 64-bit \i{MMX registers}: \c{MM0} is 0, \c{MM1} is 1, \c{MM2} is 2,
6473 \c{MM3} is 3, \c{MM4} is 4, \c{MM5} is 5, \c{MM6} is 6, and \c{MM7}
6476 \b \i{Control registers}: \c{CR0} is 0, \c{CR2} is 2, \c{CR3} is 3,
6479 \b \i{Debug registers}: \c{DR0} is 0, \c{DR1} is 1, \c{DR2} is 2,
6480 \c{DR3} is 3, \c{DR6} is 6, and \c{DR7} is 7.
6482 \b \i{Test registers}: \c{TR3} is 3, \c{TR4} is 4, \c{TR5} is 5,
6483 \c{TR6} is 6, and \c{TR7} is 7.
6485 (Note that wherever a register name contains a number, that number
6486 is also the register value for that register.)
6489 \S{iref-cc} \i{Condition Codes}
6491 The available condition codes are given here, along with their
6492 numeric representations as part of opcodes. Many of these condition
6493 codes have synonyms, so several will be listed at a time.
6495 In the following descriptions, the word `either', when applied to two
6496 possible trigger conditions, is used to mean `either or both'. If
6497 `either but not both' is meant, the phrase `exactly one of' is used.
6499 \b \c{O} is 0 (trigger if the overflow flag is set); \c{NO} is 1.
6501 \b \c{B}, \c{C} and \c{NAE} are 2 (trigger if the carry flag is
6502 set); \c{AE}, \c{NB} and \c{NC} are 3.
6504 \b \c{E} and \c{Z} are 4 (trigger if the zero flag is set); \c{NE}
6507 \b \c{BE} and \c{NA} are 6 (trigger if either of the carry or zero
6508 flags is set); \c{A} and \c{NBE} are 7.
6510 \b \c{S} is 8 (trigger if the sign flag is set); \c{NS} is 9.
6512 \b \c{P} and \c{PE} are 10 (trigger if the parity flag is set);
6513 \c{NP} and \c{PO} are 11.
6515 \b \c{L} and \c{NGE} are 12 (trigger if exactly one of the sign and
6516 overflow flags is set); \c{GE} and \c{NL} are 13.
6518 \b \c{LE} and \c{NG} are 14 (trigger if either the zero flag is set,
6519 or exactly one of the sign and overflow flags is set); \c{G} and
6522 Note that in all cases, the sense of a condition code may be
6523 reversed by changing the low bit of the numeric representation.
6525 For details of when an instruction sets each of the status flags,
6526 see the individual instruction, plus the Status Flags reference
6530 \S{iref-SSE-cc} \i{SSE Condition Predicates}
6532 The condition predicates for SSE comparison instructions are the
6533 codes used as part of the opcode, to determine what form of
6534 comparison is being carried out. In each case, the imm8 value is
6535 the final byte of the opcode encoding, and the predicate is the
6536 code used as part of the mnemonic for the instruction (equivalent
6537 to the "cc" in an integer instruction that used a condition code).
6538 The instructions that use this will give details of what the various
6539 mnemonics are, this table is used to help you work out details of what
6542 \c Predi- imm8 Description Relation where: Emula- Result QNaN
6543 \c cate Encod- A Is 1st Operand tion if NaN Signal
6544 \c ing B Is 2nd Operand Operand Invalid
6546 \c EQ 000B equal A = B False No
6548 \c LT 001B less-than A < B False Yes
6550 \c LE 010B less-than- A <= B False Yes
6553 \c --- ---- greater A > B Swap False Yes
6557 \c --- ---- greater- A >= B Swap False Yes
6558 \c than-or-equal Operands,
6561 \c UNORD 011B unordered A, B = Unordered True No
6563 \c NEQ 100B not-equal A != B True No
6565 \c NLT 101B not-less- NOT(A < B) True Yes
6568 \c NLE 110B not-less- NOT(A <= B) True Yes
6572 \c --- ---- not-greater NOT(A > B) Swap True Yes
6576 \c --- ---- not-greater NOT(A >= B) Swap True Yes
6580 \c ORD 111B ordered A , B = Ordered False No
6582 The unordered relationship is true when at least one of the two
6583 values being compared is a NaN or in an unsupported format.
6585 Note that the comparisons which are listed as not having a predicate
6586 or encoding can only be achieved through software emulation, as
6587 described in the "emulation" column. Note in particular that an
6588 instruction such as \c{greater-than} is not the same as \c{NLE}, as,
6589 unlike with the \c{CMP} instruction, it has to take into account the
6590 possibility of one operand containing a NaN or an unsupported numeric
6594 \S{iref-Flags} \i{Status Flags}
6596 The status flags provide some information about the result of the
6597 arithmetic instructions. This information can be used by conditional
6598 instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of
6599 the other instructions (such as \c{ADC} and \c{INTO}).
6601 There are 6 status flags:
6605 Set if an arithmetic operation generates a
6606 carry or a borrow out of the most-significant bit of the result;
6607 cleared otherwise. This flag indicates an overflow condition for
6608 unsigned-integer arithmetic. It is also used in multiple-precision
6611 \c PF - Parity flag.
6613 Set if the least-significant byte of the result contains an even
6614 number of 1 bits; cleared otherwise.
6616 \c AF - Adjust flag.
6618 Set if an arithmetic operation generates a carry or a borrow
6619 out of bit 3 of the result; cleared otherwise. This flag is used
6620 in binary-coded decimal (BCD) arithmetic.
6624 Set if the result is zero; cleared otherwise.
6628 Set equal to the most-significant bit of the result, which is the
6629 sign bit of a signed integer. (0 indicates a positive value and 1
6630 indicates a negative value.)
6632 \c OF - Overflow flag.
6634 Set if the integer result is too large a positive number or too
6635 small a negative number (excluding the sign-bit) to fit in the
6636 destination operand; cleared otherwise. This flag indicates an
6637 overflow condition for signed-integer (two's complement) arithmetic.
6640 \S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB}
6642 An \i{effective address} is encoded in up to three parts: a ModR/M
6643 byte, an optional SIB byte, and an optional byte, word or doubleword
6646 The ModR/M byte consists of three fields: the \c{mod} field, ranging
6647 from 0 to 3, in the upper two bits of the byte, the \c{r/m} field,
6648 ranging from 0 to 7, in the lower three bits, and the spare
6649 (register) field in the middle (bit 3 to bit 5). The spare field is
6650 not relevant to the effective address being encoded, and either
6651 contains an extension to the instruction opcode or the register
6652 value of another operand.
6654 The ModR/M system can be used to encode a direct register reference
6655 rather than a memory access. This is always done by setting the
6656 \c{mod} field to 3 and the \c{r/m} field to the register value of
6657 the register in question (it must be a general-purpose register, and
6658 the size of the register must already be implicit in the encoding of
6659 the rest of the instruction). In this case, the SIB byte and
6660 displacement field are both absent.
6662 In 16-bit addressing mode (either \c{BITS 16} with no \c{67} prefix,
6663 or \c{BITS 32} with a \c{67} prefix), the SIB byte is never used.
6664 The general rules for \c{mod} and \c{r/m} (there is an exception,
6667 \b The \c{mod} field gives the length of the displacement field: 0
6668 means no displacement, 1 means one byte, and 2 means two bytes.
6670 \b The \c{r/m} field encodes the combination of registers to be
6671 added to the displacement to give the accessed address: 0 means
6672 \c{BX+SI}, 1 means \c{BX+DI}, 2 means \c{BP+SI}, 3 means \c{BP+DI},
6673 4 means \c{SI} only, 5 means \c{DI} only, 6 means \c{BP} only, and 7
6676 However, there is a special case:
6678 \b If \c{mod} is 0 and \c{r/m} is 6, the effective address encoded
6679 is not \c{[BP]} as the above rules would suggest, but instead
6680 \c{[disp16]}: the displacement field is present and is two bytes
6681 long, and no registers are added to the displacement.
6683 Therefore the effective address \c{[BP]} cannot be encoded as
6684 efficiently as \c{[BX]}; so if you code \c{[BP]} in a program, NASM
6685 adds a notional 8-bit zero displacement, and sets \c{mod} to 1,
6686 \c{r/m} to 6, and the one-byte displacement field to 0.
6688 In 32-bit addressing mode (either \c{BITS 16} with a \c{67} prefix,
6689 or \c{BITS 32} with no \c{67} prefix) the general rules (again,
6690 there are exceptions) for \c{mod} and \c{r/m} are:
6692 \b The \c{mod} field gives the length of the displacement field: 0
6693 means no displacement, 1 means one byte, and 2 means four bytes.
6695 \b If only one register is to be added to the displacement, and it
6696 is not \c{ESP}, the \c{r/m} field gives its register value, and the
6697 SIB byte is absent. If the \c{r/m} field is 4 (which would encode
6698 \c{ESP}), the SIB byte is present and gives the combination and
6699 scaling of registers to be added to the displacement.
6701 If the SIB byte is present, it describes the combination of
6702 registers (an optional base register, and an optional index register
6703 scaled by multiplication by 1, 2, 4 or 8) to be added to the
6704 displacement. The SIB byte is divided into the \c{scale} field, in
6705 the top two bits, the \c{index} field in the next three, and the
6706 \c{base} field in the bottom three. The general rules are:
6708 \b The \c{base} field encodes the register value of the base
6711 \b The \c{index} field encodes the register value of the index
6712 register, unless it is 4, in which case no index register is used
6713 (so \c{ESP} cannot be used as an index register).
6715 \b The \c{scale} field encodes the multiplier by which the index
6716 register is scaled before adding it to the base and displacement: 0
6717 encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.
6719 The exceptions to the 32-bit encoding rules are:
6721 \b If \c{mod} is 0 and \c{r/m} is 5, the effective address encoded
6722 is not \c{[EBP]} as the above rules would suggest, but instead
6723 \c{[disp32]}: the displacement field is present and is four bytes
6724 long, and no registers are added to the displacement.
6726 \b If \c{mod} is 0, \c{r/m} is 4 (meaning the SIB byte is present)
6727 and \c{base} is 4, the effective address encoded is not
6728 \c{[EBP+index]} as the above rules would suggest, but instead
6729 \c{[disp32+index]}: the displacement field is present and is four
6730 bytes long, and there is no base register (but the index register is
6731 still processed in the normal way).
6734 \H{iref-flg} Key to Instruction Flags
6736 Given along with each instruction in this appendix is a set of
6737 flags, denoting the type of the instruction. The types are as follows:
6739 \b \c{8086}, \c{186}, \c{286}, \c{386}, \c{486}, \c{PENT} and \c{P6}
6740 denote the lowest processor type that supports the instruction. Most
6741 instructions run on all processors above the given type; those that
6742 do not are documented. The Pentium II contains no additional
6743 instructions beyond the P6 (Pentium Pro); from the point of view of
6744 its instruction set, it can be thought of as a P6 with MMX
6747 \b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will
6748 run on the AMD K6-2 and later processors. ATHLON extensions to the
6749 3DNow! instruction set are documented as such.
6751 \b \c{CYRIX} indicates that the instruction is specific to Cyrix
6752 processors, for example the extra MMX instructions in the Cyrix
6753 extended MMX instruction set.
6755 \b \c{FPU} indicates that the instruction is a floating-point one,
6756 and will only run on machines with a coprocessor (automatically
6757 including 486DX, Pentium and above).
6759 \b \c{KATMAI} indicates that the instruction was introduced as part
6760 of the Katmai New Instruction set. These instructions are available
6761 on the Pentium III and later processors. Those which are not
6762 specifically SSE instructions are also available on the AMD Athlon.
6764 \b \c{MMX} indicates that the instruction is an MMX one, and will
6765 run on MMX-capable Pentium processors and the Pentium II.
6767 \b \c{PRIV} indicates that the instruction is a protected-mode
6768 management instruction. Many of these may only be used in protected
6769 mode, or only at privilege level zero.
6771 \b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming
6772 SIMD Extension instruction. These instructions operate on multiple
6773 values in a single operation. SSE was introduced with the Pentium III
6774 and SSE2 was introduced with the Pentium 4.
6776 \b \c{UNDOC} indicates that the instruction is an undocumented one,
6777 and not part of the official Intel Architecture; it may or may not
6778 be supported on any given machine.
6780 \b \c{WILLAMETTE} indicates that the instruction was introduced as
6781 part of the new instruction set in the Pentium 4 and Intel Xeon
6782 processors. These instructions are also known as SSE2 instructions.
6785 \H{iref-inst} x86 Instruction Set
6788 \S{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII
6795 \c AAD ; D5 0A [8086]
6796 \c AAD imm ; D5 ib [8086]
6798 \c AAM ; D4 0A [8086]
6799 \c AAM imm ; D4 ib [8086]
6801 These instructions are used in conjunction with the add, subtract,
6802 multiply and divide instructions to perform binary-coded decimal
6803 arithmetic in \e{unpacked} (one BCD digit per byte - easy to
6804 translate to and from \c{ASCII}, hence the instruction names) form.
6805 There are also packed BCD instructions \c{DAA} and \c{DAS}: see
6808 \b \c{AAA} (ASCII Adjust After Addition) should be used after a
6809 one-byte \c{ADD} instruction whose destination was the \c{AL}
6810 register: by means of examining the value in the low nibble of
6811 \c{AL} and also the auxiliary carry flag \c{AF}, it determines
6812 whether the addition has overflowed, and adjusts it (and sets
6813 the carry flag) if so. You can add long BCD strings together
6814 by doing \c{ADD}/\c{AAA} on the low digits, then doing
6815 \c{ADC}/\c{AAA} on each subsequent digit.
6817 \b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to
6818 \c{AAA}, but is for use after \c{SUB} instructions rather than
6821 \b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you
6822 have multiplied two decimal digits together and left the result
6823 in \c{AL}: it divides \c{AL} by ten and stores the quotient in
6824 \c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be
6825 changed by specifying an operand to the instruction: a particularly
6826 handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL}
6827 to be separated into \c{AH} and \c{AL}.
6829 \b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse
6830 operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to
6831 \c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can
6835 \S{insADC} \i\c{ADC}: Add with Carry
6837 \c ADC r/m8,reg8 ; 10 /r [8086]
6838 \c ADC r/m16,reg16 ; o16 11 /r [8086]
6839 \c ADC r/m32,reg32 ; o32 11 /r [386]
6841 \c ADC reg8,r/m8 ; 12 /r [8086]
6842 \c ADC reg16,r/m16 ; o16 13 /r [8086]
6843 \c ADC reg32,r/m32 ; o32 13 /r [386]
6845 \c ADC r/m8,imm8 ; 80 /2 ib [8086]
6846 \c ADC r/m16,imm16 ; o16 81 /2 iw [8086]
6847 \c ADC r/m32,imm32 ; o32 81 /2 id [386]
6849 \c ADC r/m16,imm8 ; o16 83 /2 ib [8086]
6850 \c ADC r/m32,imm8 ; o32 83 /2 ib [386]
6852 \c ADC AL,imm8 ; 14 ib [8086]
6853 \c ADC AX,imm16 ; o16 15 iw [8086]
6854 \c ADC EAX,imm32 ; o32 15 id [386]
6856 \c{ADC} performs integer addition: it adds its two operands
6857 together, plus the value of the carry flag, and leaves the result in
6858 its destination (first) operand. The destination operand can be a
6859 register or a memory location. The source operand can be a register,
6860 a memory location or an immediate value.
6862 The flags are set according to the result of the operation: in
6863 particular, the carry flag is affected and can be used by a
6864 subsequent \c{ADC} instruction.
6866 In the forms with an 8-bit immediate second operand and a longer
6867 first operand, the second operand is considered to be signed, and is
6868 sign-extended to the length of the first operand. In these cases,
6869 the \c{BYTE} qualifier is necessary to force NASM to generate this
6870 form of the instruction.
6872 To add two numbers without also adding the contents of the carry
6873 flag, use \c{ADD} (\k{insADD}).
6876 \S{insADD} \i\c{ADD}: Add Integers
6878 \c ADD r/m8,reg8 ; 00 /r [8086]
6879 \c ADD r/m16,reg16 ; o16 01 /r [8086]
6880 \c ADD r/m32,reg32 ; o32 01 /r [386]
6882 \c ADD reg8,r/m8 ; 02 /r [8086]
6883 \c ADD reg16,r/m16 ; o16 03 /r [8086]
6884 \c ADD reg32,r/m32 ; o32 03 /r [386]
6886 \c ADD r/m8,imm8 ; 80 /0 ib [8086]
6887 \c ADD r/m16,imm16 ; o16 81 /0 iw [8086]
6888 \c ADD r/m32,imm32 ; o32 81 /0 id [386]
6890 \c ADD r/m16,imm8 ; o16 83 /0 ib [8086]
6891 \c ADD r/m32,imm8 ; o32 83 /0 ib [386]
6893 \c ADD AL,imm8 ; 04 ib [8086]
6894 \c ADD AX,imm16 ; o16 05 iw [8086]
6895 \c ADD EAX,imm32 ; o32 05 id [386]
6897 \c{ADD} performs integer addition: it adds its two operands
6898 together, and leaves the result in its destination (first) operand.
6899 The destination operand can be a register or a memory location.
6900 The source operand can be a register, a memory location or an
6903 The flags are set according to the result of the operation: in
6904 particular, the carry flag is affected and can be used by a
6905 subsequent \c{ADC} instruction.
6907 In the forms with an 8-bit immediate second operand and a longer
6908 first operand, the second operand is considered to be signed, and is
6909 sign-extended to the length of the first operand. In these cases,
6910 the \c{BYTE} qualifier is necessary to force NASM to generate this
6911 form of the instruction.
6914 \S{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values
6916 \c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2]
6918 \c{ADDPD} performs addition on each of two packed double-precision
6921 \c dst[0-63] := dst[0-63] + src[0-63],
6922 \c dst[64-127] := dst[64-127] + src[64-127].
6924 The destination is an \c{XMM} register. The source operand can be
6925 either an \c{XMM} register or a 128-bit memory location.
6928 \S{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values
6930 \c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE]
6932 \c{ADDPS} performs addition on each of four packed single-precision
6935 \c dst[0-31] := dst[0-31] + src[0-31],
6936 \c dst[32-63] := dst[32-63] + src[32-63],
6937 \c dst[64-95] := dst[64-95] + src[64-95],
6938 \c dst[96-127] := dst[96-127] + src[96-127].
6940 The destination is an \c{XMM} register. The source operand can be
6941 either an \c{XMM} register or a 128-bit memory location.
6944 \S{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values
6946 \c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE]
6948 \c{ADDSD} adds the low double-precision FP values from the source
6949 and destination operands and stores the double-precision FP result
6950 in the destination operand.
6952 \c dst[0-63] := dst[0-63] + src[0-63],
6953 \c dst[64-127) remains unchanged.
6955 The destination is an \c{XMM} register. The source operand can be
6956 either an \c{XMM} register or a 64-bit memory location.
6959 \S{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values
6961 \c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2]
6963 \c{ADDSS} adds the low single-precision FP values from the source
6964 and destination operands and stores the single-precision FP result
6965 in the destination operand.
6967 \c dst[0-31] := dst[0-31] + src[0-31],
6968 \c dst[32-127] remains unchanged.
6970 The destination is an \c{XMM} register. The source operand can be
6971 either an \c{XMM} register or a 32-bit memory location.
6974 \S{insAND} \i\c{AND}: Bitwise AND
6976 \c AND r/m8,reg8 ; 20 /r [8086]
6977 \c AND r/m16,reg16 ; o16 21 /r [8086]
6978 \c AND r/m32,reg32 ; o32 21 /r [386]
6980 \c AND reg8,r/m8 ; 22 /r [8086]
6981 \c AND reg16,r/m16 ; o16 23 /r [8086]
6982 \c AND reg32,r/m32 ; o32 23 /r [386]
6984 \c AND r/m8,imm8 ; 80 /4 ib [8086]
6985 \c AND r/m16,imm16 ; o16 81 /4 iw [8086]
6986 \c AND r/m32,imm32 ; o32 81 /4 id [386]
6988 \c AND r/m16,imm8 ; o16 83 /4 ib [8086]
6989 \c AND r/m32,imm8 ; o32 83 /4 ib [386]
6991 \c AND AL,imm8 ; 24 ib [8086]
6992 \c AND AX,imm16 ; o16 25 iw [8086]
6993 \c AND EAX,imm32 ; o32 25 id [386]
6995 \c{AND} performs a bitwise AND operation between its two operands
6996 (i.e. each bit of the result is 1 if and only if the corresponding
6997 bits of the two inputs were both 1), and stores the result in the
6998 destination (first) operand. The destination operand can be a
6999 register or a memory location. The source operand can be a register,
7000 a memory location or an immediate value.
7002 In the forms with an 8-bit immediate second operand and a longer
7003 first operand, the second operand is considered to be signed, and is
7004 sign-extended to the length of the first operand. In these cases,
7005 the \c{BYTE} qualifier is necessary to force NASM to generate this
7006 form of the instruction.
7008 The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same
7009 operation on the 64-bit \c{MMX} registers.
7012 \S{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of
7013 Packed Double-Precision FP Values
7015 \c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2]
7017 \c{ANDNPD} inverts the bits of the two double-precision
7018 floating-point values in the destination register, and then
7019 performs a logical AND between the two double-precision
7020 floating-point values in the source operand and the temporary
7021 inverted result, storing the result in the destination register.
7023 \c dst[0-63] := src[0-63] AND NOT dst[0-63],
7024 \c dst[64-127] := src[64-127] AND NOT dst[64-127].
7026 The destination is an \c{XMM} register. The source operand can be
7027 either an \c{XMM} register or a 128-bit memory location.
7030 \S{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of
7031 Packed Single-Precision FP Values
7033 \c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE]
7035 \c{ANDNPS} inverts the bits of the four single-precision
7036 floating-point values in the destination register, and then
7037 performs a logical AND between the four single-precision
7038 floating-point values in the source operand and the temporary
7039 inverted result, storing the result in the destination register.
7041 \c dst[0-31] := src[0-31] AND NOT dst[0-31],
7042 \c dst[32-63] := src[32-63] AND NOT dst[32-63],
7043 \c dst[64-95] := src[64-95] AND NOT dst[64-95],
7044 \c dst[96-127] := src[96-127] AND NOT dst[96-127].
7046 The destination is an \c{XMM} register. The source operand can be
7047 either an \c{XMM} register or a 128-bit memory location.
7050 \S{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP
7052 \c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2]
7054 \c{ANDPD} performs a bitwise logical AND of the two double-precision
7055 floating point values in the source and destination operand, and
7056 stores the result in the destination register.
7058 \c dst[0-63] := src[0-63] AND dst[0-63],
7059 \c dst[64-127] := src[64-127] AND dst[64-127].
7061 The destination is an \c{XMM} register. The source operand can be
7062 either an \c{XMM} register or a 128-bit memory location.
7065 \S{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP
7067 \c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE]
7069 \c{ANDPS} performs a bitwise logical AND of the four single-precision
7070 floating point values in the source and destination operand, and
7071 stores the result in the destination register.
7073 \c dst[0-31] := src[0-31] AND dst[0-31],
7074 \c dst[32-63] := src[32-63] AND dst[32-63],
7075 \c dst[64-95] := src[64-95] AND dst[64-95],
7076 \c dst[96-127] := src[96-127] AND dst[96-127].
7078 The destination is an \c{XMM} register. The source operand can be
7079 either an \c{XMM} register or a 128-bit memory location.
7082 \S{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector
7084 \c ARPL r/m16,reg16 ; 63 /r [286,PRIV]
7086 \c{ARPL} expects its two word operands to be segment selectors. It
7087 adjusts the \i\c{RPL} (requested privilege level - stored in the bottom
7088 two bits of the selector) field of the destination (first) operand
7089 to ensure that it is no less (i.e. no more privileged than) the \c{RPL}
7090 field of the source operand. The zero flag is set if and only if a
7091 change had to be made.
7094 \S{insBOUND} \i\c{BOUND}: Check Array Index against Bounds
7096 \c BOUND reg16,mem ; o16 62 /r [186]
7097 \c BOUND reg32,mem ; o32 62 /r [386]
7099 \c{BOUND} expects its second operand to point to an area of memory
7100 containing two signed values of the same size as its first operand
7101 (i.e. two words for the 16-bit form; two doublewords for the 32-bit
7102 form). It performs two signed comparisons: if the value in the
7103 register passed as its first operand is less than the first of the
7104 in-memory values, or is greater than or equal to the second, it
7105 throws a \c{BR} exception. Otherwise, it does nothing.
7108 \S{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan
7110 \c BSF reg16,r/m16 ; o16 0F BC /r [386]
7111 \c BSF reg32,r/m32 ; o32 0F BC /r [386]
7113 \c BSR reg16,r/m16 ; o16 0F BD /r [386]
7114 \c BSR reg32,r/m32 ; o32 0F BD /r [386]
7116 \b \c{BSF} searches for the least significant set bit in its source
7117 (second) operand, and if it finds one, stores the index in
7118 its destination (first) operand. If no set bit is found, the
7119 contents of the destination operand are undefined. If the source
7120 operand is zero, the zero flag is set.
7122 \b \c{BSR} performs the same function, but searches from the top
7123 instead, so it finds the most significant set bit.
7125 Bit indices are from 0 (least significant) to 15 or 31 (most
7126 significant). The destination operand can only be a register.
7127 The source operand can be a register or a memory location.
7130 \S{insBSWAP} \i\c{BSWAP}: Byte Swap
7132 \c BSWAP reg32 ; o32 0F C8+r [486]
7134 \c{BSWAP} swaps the order of the four bytes of a 32-bit register:
7135 bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with
7136 bits 16-23. There is no explicit 16-bit equivalent: to byte-swap
7137 \c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP}
7138 is used with a 16-bit register, the result is undefined.
7141 \S{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test
7143 \c BT r/m16,reg16 ; o16 0F A3 /r [386]
7144 \c BT r/m32,reg32 ; o32 0F A3 /r [386]
7145 \c BT r/m16,imm8 ; o16 0F BA /4 ib [386]
7146 \c BT r/m32,imm8 ; o32 0F BA /4 ib [386]
7148 \c BTC r/m16,reg16 ; o16 0F BB /r [386]
7149 \c BTC r/m32,reg32 ; o32 0F BB /r [386]
7150 \c BTC r/m16,imm8 ; o16 0F BA /7 ib [386]
7151 \c BTC r/m32,imm8 ; o32 0F BA /7 ib [386]
7153 \c BTR r/m16,reg16 ; o16 0F B3 /r [386]
7154 \c BTR r/m32,reg32 ; o32 0F B3 /r [386]
7155 \c BTR r/m16,imm8 ; o16 0F BA /6 ib [386]
7156 \c BTR r/m32,imm8 ; o32 0F BA /6 ib [386]
7158 \c BTS r/m16,reg16 ; o16 0F AB /r [386]
7159 \c BTS r/m32,reg32 ; o32 0F AB /r [386]
7160 \c BTS r/m16,imm ; o16 0F BA /5 ib [386]
7161 \c BTS r/m32,imm ; o32 0F BA /5 ib [386]
7163 These instructions all test one bit of their first operand, whose
7164 index is given by the second operand, and store the value of that
7165 bit into the carry flag. Bit indices are from 0 (least significant)
7166 to 15 or 31 (most significant).
7168 In addition to storing the original value of the bit into the carry
7169 flag, \c{BTR} also resets (clears) the bit in the operand itself.
7170 \c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does
7171 not modify its operands.
7173 The destination can be a register or a memory location. The source can
7174 be a register or an immediate value.
7176 If the destination operand is a register, the bit offset should be
7177 in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands).
7178 An immediate value outside these ranges will be taken modulo 16/32
7181 If the destination operand is a memory location, then an immediate
7182 bit offset follows the same rules as for a register. If the bit offset
7183 is in a register, then it can be anything within the signed range of
7184 the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1)
7187 \S{insCALL} \i\c{CALL}: Call Subroutine
7189 \c CALL imm ; E8 rw/rd [8086]
7190 \c CALL imm:imm16 ; o16 9A iw iw [8086]
7191 \c CALL imm:imm32 ; o32 9A id iw [386]
7192 \c CALL FAR mem16 ; o16 FF /3 [8086]
7193 \c CALL FAR mem32 ; o32 FF /3 [386]
7194 \c CALL r/m16 ; o16 FF /2 [8086]
7195 \c CALL r/m32 ; o32 FF /2 [386]
7197 \c{CALL} calls a subroutine, by means of pushing the current
7198 instruction pointer (\c{IP}) and optionally \c{CS} as well on the
7199 stack, and then jumping to a given address.
7201 \c{CS} is pushed as well as \c{IP} if and only if the call is a far
7202 call, i.e. a destination segment address is specified in the
7203 instruction. The forms involving two colon-separated arguments are
7204 far calls; so are the \c{CALL FAR mem} forms.
7206 The immediate \i{near call} takes one of two forms (\c{call imm16/imm32},
7207 determined by the current segment size limit. For 16-bit operands,
7208 you would use \c{CALL 0x1234}, and for 32-bit operands you would use
7209 \c{CALL 0x12345678}. The value passed as an operand is a relative offset.
7211 You can choose between the two immediate \i{far call} forms
7212 (\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords:
7213 \c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}.
7215 The \c{CALL FAR mem} forms execute a far call by loading the
7216 destination address out of memory. The address loaded consists of 16
7217 or 32 bits of offset (depending on the operand size), and 16 bits of
7218 segment. The operand size may be overridden using \c{CALL WORD FAR
7219 mem} or \c{CALL DWORD FAR mem}.
7221 The \c{CALL r/m} forms execute a \i{near call} (within the same
7222 segment), loading the destination address out of memory or out of a
7223 register. The keyword \c{NEAR} may be specified, for clarity, in
7224 these forms, but is not necessary. Again, operand size can be
7225 overridden using \c{CALL WORD mem} or \c{CALL DWORD mem}.
7227 As a convenience, NASM does not require you to call a far procedure
7228 symbol by coding the cumbersome \c{CALL SEG routine:routine}, but
7229 instead allows the easier synonym \c{CALL FAR routine}.
7231 The \c{CALL r/m} forms given above are near calls; NASM will accept
7232 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
7233 is not strictly necessary.
7236 \S{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions
7238 \c CBW ; o16 98 [8086]
7239 \c CWDE ; o32 98 [386]
7241 \c CWD ; o16 99 [8086]
7242 \c CDQ ; o32 99 [386]
7244 All these instructions sign-extend a short value into a longer one,
7245 by replicating the top bit of the original value to fill the
7248 \c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of
7249 \c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into
7250 \c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating
7251 the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends
7252 \c{EAX} into \c{EDX:EAX}.
7255 \S{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags
7260 \c CLTS ; 0F 06 [286,PRIV]
7262 These instructions clear various flags. \c{CLC} clears the carry
7263 flag; \c{CLD} clears the direction flag; \c{CLI} clears the
7264 interrupt flag (thus disabling interrupts); and \c{CLTS} clears the
7265 task-switched (\c{TS}) flag in \c{CR0}.
7267 To set the carry, direction, or interrupt flags, use the \c{STC},
7268 \c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry
7269 flag, use \c{CMC} (\k{insCMC}).
7272 \S{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line
7274 \c CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2]
7276 \c{CLFLUSH} invalidates the cache line that contains the linear address
7277 specified by the source operand from all levels of the processor cache
7278 hierarchy (data and instruction). If, at any level of the cache
7279 hierarchy, the line is inconsistent with memory (dirty) it is written
7280 to memory before invalidation. The source operand points to a
7281 byte-sized memory location.
7283 Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be
7284 present on all processors which have \c{SSE2} support, and it may be
7285 supported on other processors; the \c{CPUID} instruction (\k{insCPUID})
7286 will return a bit which indicates support for the \c{CLFLUSH} instruction.
7289 \S{insCMC} \i\c{CMC}: Complement Carry Flag
7293 \c{CMC} changes the value of the carry flag: if it was 0, it sets it
7294 to 1, and vice versa.
7297 \S{insCMOVcc} \i\c{CMOVcc}: Conditional Move
7299 \c CMOVcc reg16,r/m16 ; o16 0F 40+cc /r [P6]
7300 \c CMOVcc reg32,r/m32 ; o32 0F 40+cc /r [P6]
7302 \c{CMOV} moves its source (second) operand into its destination
7303 (first) operand if the given condition code is satisfied; otherwise
7306 For a list of condition codes, see \k{iref-cc}.
7308 Although the \c{CMOV} instructions are flagged \c{P6} and above, they
7309 may not be supported by all Pentium Pro processors; the \c{CPUID}
7310 instruction (\k{insCPUID}) will return a bit which indicates whether
7311 conditional moves are supported.
7314 \S{insCMP} \i\c{CMP}: Compare Integers
7316 \c CMP r/m8,reg8 ; 38 /r [8086]
7317 \c CMP r/m16,reg16 ; o16 39 /r [8086]
7318 \c CMP r/m32,reg32 ; o32 39 /r [386]
7320 \c CMP reg8,r/m8 ; 3A /r [8086]
7321 \c CMP reg16,r/m16 ; o16 3B /r [8086]
7322 \c CMP reg32,r/m32 ; o32 3B /r [386]
7324 \c CMP r/m8,imm8 ; 80 /0 ib [8086]
7325 \c CMP r/m16,imm16 ; o16 81 /0 iw [8086]
7326 \c CMP r/m32,imm32 ; o32 81 /0 id [386]
7328 \c CMP r/m16,imm8 ; o16 83 /0 ib [8086]
7329 \c CMP r/m32,imm8 ; o32 83 /0 ib [386]
7331 \c CMP AL,imm8 ; 3C ib [8086]
7332 \c CMP AX,imm16 ; o16 3D iw [8086]
7333 \c CMP EAX,imm32 ; o32 3D id [386]
7335 \c{CMP} performs a `mental' subtraction of its second operand from
7336 its first operand, and affects the flags as if the subtraction had
7337 taken place, but does not store the result of the subtraction
7340 In the forms with an 8-bit immediate second operand and a longer
7341 first operand, the second operand is considered to be signed, and is
7342 sign-extended to the length of the first operand. In these cases,
7343 the \c{BYTE} qualifier is necessary to force NASM to generate this
7344 form of the instruction.
7346 The destination operand can be a register or a memory location. The
7347 source can be a register, memory location or an immediate value of
7348 the same size as the destination.
7351 \S{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare
7352 \I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD}
7353 \I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD}
7355 \c CMPPD xmm1,xmm2/mem128,imm8 ; 66 0F C2 /r ib [WILLAMETTE,SSE2]
7357 \c CMPEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 00 [WILLAMETTE,SSE2]
7358 \c CMPLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 01 [WILLAMETTE,SSE2]
7359 \c CMPLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 02 [WILLAMETTE,SSE2]
7360 \c CMPUNORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 03 [WILLAMETTE,SSE2]
7361 \c CMPNEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 04 [WILLAMETTE,SSE2]
7362 \c CMPNLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 05 [WILLAMETTE,SSE2]
7363 \c CMPNLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 06 [WILLAMETTE,SSE2]
7364 \c CMPORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 07 [WILLAMETTE,SSE2]
7366 The \c{CMPccPD} instructions compare the two packed double-precision
7367 FP values in the source and destination operands, and returns the
7368 result of the comparison in the destination register. The result of
7369 each comparison is a quadword mask of all 1s (comparison true) or
7370 all 0s (comparison false).
7372 The destination is an \c{XMM} register. The source can be either an
7373 \c{XMM} register or a 128-bit memory location.
7375 The third operand is an 8-bit immediate value, of which the low 3
7376 bits define the type of comparison. For ease of programming, the
7377 8 two-operand pseudo-instructions are provided, with the third
7378 operand already filled in. The \I{Condition Predicates}
7379 \c{Condition Predicates} are:
7383 \c LE 2 Less-than-or-equal
7384 \c UNORD 3 Unordered
7386 \c NLT 5 Not-less-than
7387 \c NLE 6 Not-less-than-or-equal
7390 For more details of the comparison predicates, and details of how
7391 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7394 \S{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare
7395 \I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS}
7396 \I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS}
7398 \c CMPPS xmm1,xmm2/mem128,imm8 ; 0F C2 /r ib [KATMAI,SSE]
7400 \c CMPEQPS xmm1,xmm2/mem128 ; 0F C2 /r 00 [KATMAI,SSE]
7401 \c CMPLTPS xmm1,xmm2/mem128 ; 0F C2 /r 01 [KATMAI,SSE]
7402 \c CMPLEPS xmm1,xmm2/mem128 ; 0F C2 /r 02 [KATMAI,SSE]
7403 \c CMPUNORDPS xmm1,xmm2/mem128 ; 0F C2 /r 03 [KATMAI,SSE]
7404 \c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE]
7405 \c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE]
7406 \c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE]
7407 \c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE]
7409 The \c{CMPccPS} instructions compare the two packed single-precision
7410 FP values in the source and destination operands, and returns the
7411 result of the comparison in the destination register. The result of
7412 each comparison is a doubleword mask of all 1s (comparison true) or
7413 all 0s (comparison false).
7415 The destination is an \c{XMM} register. The source can be either an
7416 \c{XMM} register or a 128-bit memory location.
7418 The third operand is an 8-bit immediate value, of which the low 3
7419 bits define the type of comparison. For ease of programming, the
7420 8 two-operand pseudo-instructions are provided, with the third
7421 operand already filled in. The \I{Condition Predicates}
7422 \c{Condition Predicates} are:
7426 \c LE 2 Less-than-or-equal
7427 \c UNORD 3 Unordered
7429 \c NLT 5 Not-less-than
7430 \c NLE 6 Not-less-than-or-equal
7433 For more details of the comparison predicates, and details of how
7434 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7437 \S{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings
7439 \c CMPSB ; A6 [8086]
7440 \c CMPSW ; o16 A7 [8086]
7441 \c CMPSD ; o32 A7 [386]
7443 \c{CMPSB} compares the byte at \c{[DS:SI]} or \c{[DS:ESI]} with the
7444 byte at \c{[ES:DI]} or \c{[ES:EDI]}, and sets the flags accordingly.
7445 It then increments or decrements (depending on the direction flag:
7446 increments if the flag is clear, decrements if it is set) \c{SI} and
7447 \c{DI} (or \c{ESI} and \c{EDI}).
7449 The registers used are \c{SI} and \c{DI} if the address size is 16
7450 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
7451 an address size not equal to the current \c{BITS} setting, you can
7452 use an explicit \i\c{a16} or \i\c{a32} prefix.
7454 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
7455 overridden by using a segment register name as a prefix (for
7456 example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]}
7457 or \c{[EDI]} cannot be overridden.
7459 \c{CMPSW} and \c{CMPSD} work in the same way, but they compare a
7460 word or a doubleword instead of a byte, and increment or decrement
7461 the addressing registers by 2 or 4 instead of 1.
7463 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
7464 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
7465 \c{ECX} - again, the address size chooses which) times until the
7466 first unequal or equal byte is found.
7469 \S{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare
7470 \I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD}
7471 \I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD}
7473 \c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2]
7475 \c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2]
7476 \c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2]
7477 \c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2]
7478 \c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2]
7479 \c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2]
7480 \c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2]
7481 \c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2]
7482 \c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2]
7484 The \c{CMPccSD} instructions compare the low-order double-precision
7485 FP values in the source and destination operands, and returns the
7486 result of the comparison in the destination register. The result of
7487 each comparison is a quadword mask of all 1s (comparison true) or
7488 all 0s (comparison false).
7490 The destination is an \c{XMM} register. The source can be either an
7491 \c{XMM} register or a 128-bit memory location.
7493 The third operand is an 8-bit immediate value, of which the low 3
7494 bits define the type of comparison. For ease of programming, the
7495 8 two-operand pseudo-instructions are provided, with the third
7496 operand already filled in. The \I{Condition Predicates}
7497 \c{Condition Predicates} are:
7501 \c LE 2 Less-than-or-equal
7502 \c UNORD 3 Unordered
7504 \c NLT 5 Not-less-than
7505 \c NLE 6 Not-less-than-or-equal
7508 For more details of the comparison predicates, and details of how
7509 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7512 \S{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare
7513 \I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS}
7514 \I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS}
7516 \c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE]
7518 \c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE]
7519 \c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE]
7520 \c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE]
7521 \c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE]
7522 \c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE]
7523 \c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE]
7524 \c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE]
7525 \c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE]
7527 The \c{CMPccSS} instructions compare the low-order single-precision
7528 FP values in the source and destination operands, and returns the
7529 result of the comparison in the destination register. The result of
7530 each comparison is a doubleword mask of all 1s (comparison true) or
7531 all 0s (comparison false).
7533 The destination is an \c{XMM} register. The source can be either an
7534 \c{XMM} register or a 128-bit memory location.
7536 The third operand is an 8-bit immediate value, of which the low 3
7537 bits define the type of comparison. For ease of programming, the
7538 8 two-operand pseudo-instructions are provided, with the third
7539 operand already filled in. The \I{Condition Predicates}
7540 \c{Condition Predicates} are:
7544 \c LE 2 Less-than-or-equal
7545 \c UNORD 3 Unordered
7547 \c NLT 5 Not-less-than
7548 \c NLE 6 Not-less-than-or-equal
7551 For more details of the comparison predicates, and details of how
7552 to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
7555 \S{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange
7557 \c CMPXCHG r/m8,reg8 ; 0F B0 /r [PENT]
7558 \c CMPXCHG r/m16,reg16 ; o16 0F B1 /r [PENT]
7559 \c CMPXCHG r/m32,reg32 ; o32 0F B1 /r [PENT]
7561 \c CMPXCHG486 r/m8,reg8 ; 0F A6 /r [486,UNDOC]
7562 \c CMPXCHG486 r/m16,reg16 ; o16 0F A7 /r [486,UNDOC]
7563 \c CMPXCHG486 r/m32,reg32 ; o32 0F A7 /r [486,UNDOC]
7565 These two instructions perform exactly the same operation; however,
7566 apparently some (not all) 486 processors support it under a
7567 non-standard opcode, so NASM provides the undocumented
7568 \c{CMPXCHG486} form to generate the non-standard opcode.
7570 \c{CMPXCHG} compares its destination (first) operand to the value in
7571 \c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the
7572 instruction). If they are equal, it copies its source (second)
7573 operand into the destination and sets the zero flag. Otherwise, it
7574 clears the zero flag and copies the destination register to AL, AX or EAX.
7576 The destination can be either a register or a memory location. The
7577 source is a register.
7579 \c{CMPXCHG} is intended to be used for atomic operations in
7580 multitasking or multiprocessor environments. To safely update a
7581 value in shared memory, for example, you might load the value into
7582 \c{EAX}, load the updated value into \c{EBX}, and then execute the
7583 instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not
7584 changed since being loaded, it is updated with your desired new
7585 value, and the zero flag is set to let you know it has worked. (The
7586 \c{LOCK} prefix prevents another processor doing anything in the
7587 middle of this operation: it guarantees atomicity.) However, if
7588 another processor has modified the value in between your load and
7589 your attempted store, the store does not happen, and you are
7590 notified of the failure by a cleared zero flag, so you can go round
7594 \S{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes
7596 \c CMPXCHG8B mem ; 0F C7 /1 [PENT]
7598 This is a larger and more unwieldy version of \c{CMPXCHG}: it
7599 compares the 64-bit (eight-byte) value stored at \c{[mem]} with the
7600 value in \c{EDX:EAX}. If they are equal, it sets the zero flag and
7601 stores \c{ECX:EBX} into the memory area. If they are unequal, it
7602 clears the zero flag and stores the memory contents into \c{EDX:EAX}.
7604 \c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic
7605 execution. This is useful in multi-processor and multi-tasking
7609 \S{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
7611 \c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2]
7613 \c{COMISD} compares the low-order double-precision FP value in the
7614 two source operands. ZF, PF and CF are set according to the result.
7615 OF, AF and AF are cleared. The unordered result is returned if either
7616 source is a NaN (QNaN or SNaN).
7618 The destination operand is an \c{XMM} register. The source can be either
7619 an \c{XMM} register or a memory location.
7621 The flags are set according to the following rules:
7623 \c Result Flags Values
7625 \c UNORDERED: ZF,PF,CF <-- 111;
7626 \c GREATER_THAN: ZF,PF,CF <-- 000;
7627 \c LESS_THAN: ZF,PF,CF <-- 001;
7628 \c EQUAL: ZF,PF,CF <-- 100;
7631 \S{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
7633 \c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE]
7635 \c{COMISS} compares the low-order single-precision FP value in the
7636 two source operands. ZF, PF and CF are set according to the result.
7637 OF, AF and AF are cleared. The unordered result is returned if either
7638 source is a NaN (QNaN or SNaN).
7640 The destination operand is an \c{XMM} register. The source can be either
7641 an \c{XMM} register or a memory location.
7643 The flags are set according to the following rules:
7645 \c Result Flags Values
7647 \c UNORDERED: ZF,PF,CF <-- 111;
7648 \c GREATER_THAN: ZF,PF,CF <-- 000;
7649 \c LESS_THAN: ZF,PF,CF <-- 001;
7650 \c EQUAL: ZF,PF,CF <-- 100;
7653 \S{insCPUID} \i\c{CPUID}: Get CPU Identification Code
7655 \c CPUID ; 0F A2 [PENT]
7657 \c{CPUID} returns various information about the processor it is
7658 being executed on. It fills the four registers \c{EAX}, \c{EBX},
7659 \c{ECX} and \c{EDX} with information, which varies depending on the
7660 input contents of \c{EAX}.
7662 \c{CPUID} also acts as a barrier to serialise instruction execution:
7663 executing the \c{CPUID} instruction guarantees that all the effects
7664 (memory modification, flag modification, register modification) of
7665 previous instructions have been completed before the next
7666 instruction gets fetched.
7668 The information returned is as follows:
7670 \b If \c{EAX} is zero on input, \c{EAX} on output holds the maximum
7671 acceptable input value of \c{EAX}, and \c{EBX:EDX:ECX} contain the
7672 string \c{"GenuineIntel"} (or not, if you have a clone processor).
7673 That is to say, \c{EBX} contains \c{"Genu"} (in NASM's own sense of
7674 character constants, described in \k{chrconst}), \c{EDX} contains
7675 \c{"ineI"} and \c{ECX} contains \c{"ntel"}.
7677 \b If \c{EAX} is one on input, \c{EAX} on output contains version
7678 information about the processor, and \c{EDX} contains a set of
7679 feature flags, showing the presence and absence of various features.
7680 For example, bit 8 is set if the \c{CMPXCHG8B} instruction
7681 (\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional
7682 move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported,
7683 and bit 23 is set if \c{MMX} instructions are supported.
7685 \b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX}
7686 all contain information about caches and TLBs (Translation Lookahead
7689 For more information on the data returned from \c{CPUID}, see the
7690 documentation from Intel and other processor manufacturers.
7693 \S{insCVTDQ2PD} \i\c{CVTDQ2PD}:
7694 Packed Signed INT32 to Packed Double-Precision FP Conversion
7696 \c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2]
7698 \c{CVTDQ2PD} converts two packed signed doublewords from the source
7699 operand to two packed double-precision FP values in the destination
7702 The destination operand is an \c{XMM} register. The source can be
7703 either an \c{XMM} register or a 64-bit memory location. If the
7704 source is a register, the packed integers are in the low quadword.
7707 \S{insCVTDQ2PS} \i\c{CVTDQ2PS}:
7708 Packed Signed INT32 to Packed Single-Precision FP Conversion
7710 \c CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2]
7712 \c{CVTDQ2PS} converts four packed signed doublewords from the source
7713 operand to four packed single-precision FP values in the destination
7716 The destination operand is an \c{XMM} register. The source can be
7717 either an \c{XMM} register or a 128-bit memory location.
7719 For more details of this instruction, see the Intel Processor manuals.
7722 \S{insCVTPD2DQ} \i\c{CVTPD2DQ}:
7723 Packed Double-Precision FP to Packed Signed INT32 Conversion
7725 \c CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2]
7727 \c{CVTPD2DQ} converts two packed double-precision FP values from the
7728 source operand to two packed signed doublewords in the low quadword
7729 of the destination operand. The high quadword of the destination is
7732 The destination operand is an \c{XMM} register. The source can be
7733 either an \c{XMM} register or a 128-bit memory location.
7735 For more details of this instruction, see the Intel Processor manuals.
7738 \S{insCVTPD2PI} \i\c{CVTPD2PI}:
7739 Packed Double-Precision FP to Packed Signed INT32 Conversion
7741 \c CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2]
7743 \c{CVTPD2PI} converts two packed double-precision FP values from the
7744 source operand to two packed signed doublewords in the destination
7747 The destination operand is an \c{MMX} register. The source can be
7748 either an \c{XMM} register or a 128-bit memory location.
7750 For more details of this instruction, see the Intel Processor manuals.
7753 \S{insCVTPD2PS} \i\c{CVTPD2PS}:
7754 Packed Double-Precision FP to Packed Single-Precision FP Conversion
7756 \c CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2]
7758 \c{CVTPD2PS} converts two packed double-precision FP values from the
7759 source operand to two packed single-precision FP values in the low
7760 quadword of the destination operand. The high quadword of the
7761 destination is set to all 0s.
7763 The destination operand is an \c{XMM} register. The source can be
7764 either an \c{XMM} register or a 128-bit memory location.
7766 For more details of this instruction, see the Intel Processor manuals.
7769 \S{insCVTPI2PD} \i\c{CVTPI2PD}:
7770 Packed Signed INT32 to Packed Double-Precision FP Conversion
7772 \c CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2]
7774 \c{CVTPI2PD} converts two packed signed doublewords from the source
7775 operand to two packed double-precision FP values in the destination
7778 The destination operand is an \c{XMM} register. The source can be
7779 either an \c{MMX} register or a 64-bit memory location.
7781 For more details of this instruction, see the Intel Processor manuals.
7784 \S{insCVTPI2PS} \i\c{CVTPI2PS}:
7785 Packed Signed INT32 to Packed Single-FP Conversion
7787 \c CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE]
7789 \c{CVTPI2PS} converts two packed signed doublewords from the source
7790 operand to two packed single-precision FP values in the low quadword
7791 of the destination operand. The high quadword of the destination
7794 The destination operand is an \c{XMM} register. The source can be
7795 either an \c{MMX} register or a 64-bit memory location.
7797 For more details of this instruction, see the Intel Processor manuals.
7800 \S{insCVTPS2DQ} \i\c{CVTPS2DQ}:
7801 Packed Single-Precision FP to Packed Signed INT32 Conversion
7803 \c CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2]
7805 \c{CVTPS2DQ} converts four packed single-precision FP values from the
7806 source operand to four packed signed doublewords in the destination operand.
7808 The destination operand is an \c{XMM} register. The source can be
7809 either an \c{XMM} register or a 128-bit memory location.
7811 For more details of this instruction, see the Intel Processor manuals.
7814 \S{insCVTPS2PD} \i\c{CVTPS2PD}:
7815 Packed Single-Precision FP to Packed Double-Precision FP Conversion
7817 \c CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2]
7819 \c{CVTPS2PD} converts two packed single-precision FP values from the
7820 source operand to two packed double-precision FP values in the destination
7823 The destination operand is an \c{XMM} register. The source can be
7824 either an \c{XMM} register or a 64-bit memory location. If the source
7825 is a register, the input values are in the low quadword.
7827 For more details of this instruction, see the Intel Processor manuals.
7830 \S{insCVTPS2PI} \i\c{CVTPS2PI}:
7831 Packed Single-Precision FP to Packed Signed INT32 Conversion
7833 \c CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE]
7835 \c{CVTPS2PI} converts two packed single-precision FP values from
7836 the source operand to two packed signed doublewords in the destination
7839 The destination operand is an \c{MMX} register. The source can be
7840 either an \c{XMM} register or a 64-bit memory location. If the
7841 source is a register, the input values are in the low quadword.
7843 For more details of this instruction, see the Intel Processor manuals.
7846 \S{insCVTSD2SI} \i\c{CVTSD2SI}:
7847 Scalar Double-Precision FP to Signed INT32 Conversion
7849 \c CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2]
7851 \c{CVTSD2SI} converts a double-precision FP value from the source
7852 operand to a signed doubleword in the destination operand.
7854 The destination operand is a general purpose register. The source can be
7855 either an \c{XMM} register or a 64-bit memory location. If the
7856 source is a register, the input value is in the low quadword.
7858 For more details of this instruction, see the Intel Processor manuals.
7861 \S{insCVTSD2SS} \i\c{CVTSD2SS}:
7862 Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
7864 \c CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE]
7866 \c{CVTSD2SS} converts a double-precision FP value from the source
7867 operand to a single-precision FP value in the low doubleword of the
7868 destination operand. The upper 3 doublewords are left unchanged.
7870 The destination operand is an \c{XMM} register. The source can be
7871 either an \c{XMM} register or a 64-bit memory location. If the
7872 source is a register, the input value is in the low quadword.
7874 For more details of this instruction, see the Intel Processor manuals.
7877 \S{insCVTSI2SD} \i\c{CVTSI2SD}:
7878 Signed INT32 to Scalar Double-Precision FP Conversion
7880 \c CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2]
7882 \c{CVTSI2SD} converts a signed doubleword from the source operand to
7883 a double-precision FP value in the low quadword of the destination
7884 operand. The high quadword is left unchanged.
7886 The destination operand is an \c{XMM} register. The source can be either
7887 a general purpose register or a 32-bit memory location.
7889 For more details of this instruction, see the Intel Processor manuals.
7892 \S{insCVTSI2SS} \i\c{CVTSI2SS}:
7893 Signed INT32 to Scalar Single-Precision FP Conversion
7895 \c CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE]
7897 \c{CVTSI2SS} converts a signed doubleword from the source operand to a
7898 single-precision FP value in the low doubleword of the destination operand.
7899 The upper 3 doublewords are left unchanged.
7901 The destination operand is an \c{XMM} register. The source can be either
7902 a general purpose register or a 32-bit memory location.
7904 For more details of this instruction, see the Intel Processor manuals.
7907 \S{insCVTSS2SD} \i\c{CVTSS2SD}:
7908 Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
7910 \c CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2]
7912 \c{CVTSS2SD} converts a single-precision FP value from the source operand
7913 to a double-precision FP value in the low quadword of the destination
7914 operand. The upper quadword is left unchanged.
7916 The destination operand is an \c{XMM} register. The source can be either
7917 an \c{XMM} register or a 32-bit memory location. If the source is a
7918 register, the input value is contained in the low doubleword.
7920 For more details of this instruction, see the Intel Processor manuals.
7923 \S{insCVTSS2SI} \i\c{CVTSS2SI}:
7924 Scalar Single-Precision FP to Signed INT32 Conversion
7926 \c CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE]
7928 \c{CVTSS2SI} converts a single-precision FP value from the source
7929 operand to a signed doubleword in the destination operand.
7931 The destination operand is a general purpose register. The source can be
7932 either an \c{XMM} register or a 32-bit memory location. If the
7933 source is a register, the input value is in the low doubleword.
7935 For more details of this instruction, see the Intel Processor manuals.
7938 \S{insCVTTPD2DQ} \i\c{CVTTPD2DQ}:
7939 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7941 \c CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2]
7943 \c{CVTTPD2DQ} converts two packed double-precision FP values in the source
7944 operand to two packed single-precision FP values in the destination operand.
7945 If the result is inexact, it is truncated (rounded toward zero). The high
7946 quadword is set to all 0s.
7948 The destination operand is an \c{XMM} register. The source can be
7949 either an \c{XMM} register or a 128-bit memory location.
7951 For more details of this instruction, see the Intel Processor manuals.
7954 \S{insCVTTPD2PI} \i\c{CVTTPD2PI}:
7955 Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
7957 \c CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2]
7959 \c{CVTTPD2PI} converts two packed double-precision FP values in the source
7960 operand to two packed single-precision FP values in the destination operand.
7961 If the result is inexact, it is truncated (rounded toward zero).
7963 The destination operand is an \c{MMX} register. The source can be
7964 either an \c{XMM} register or a 128-bit memory location.
7966 For more details of this instruction, see the Intel Processor manuals.
7969 \S{insCVTTPS2DQ} \i\c{CVTTPS2DQ}:
7970 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7972 \c CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2]
7974 \c{CVTTPS2DQ} converts four packed single-precision FP values in the source
7975 operand to four packed signed doublewords in the destination operand.
7976 If the result is inexact, it is truncated (rounded toward zero).
7978 The destination operand is an \c{XMM} register. The source can be
7979 either an \c{XMM} register or a 128-bit memory location.
7981 For more details of this instruction, see the Intel Processor manuals.
7984 \S{insCVTTPS2PI} \i\c{CVTTPS2PI}:
7985 Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
7987 \c CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE]
7989 \c{CVTTPS2PI} converts two packed single-precision FP values in the source
7990 operand to two packed signed doublewords in the destination operand.
7991 If the result is inexact, it is truncated (rounded toward zero). If
7992 the source is a register, the input values are in the low quadword.
7994 The destination operand is an \c{MMX} register. The source can be
7995 either an \c{XMM} register or a 64-bit memory location. If the source
7996 is a register, the input value is in the low quadword.
7998 For more details of this instruction, see the Intel Processor manuals.
8001 \S{insCVTTSD2SI} \i\c{CVTTSD2SI}:
8002 Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
8004 \c CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2]
8006 \c{CVTTSD2SI} converts a double-precision FP value in the source operand
8007 to a signed doubleword in the destination operand. If the result is
8008 inexact, it is truncated (rounded toward zero).
8010 The destination operand is a general purpose register. The source can be
8011 either an \c{XMM} register or a 64-bit memory location. If the source is a
8012 register, the input value is in the low quadword.
8014 For more details of this instruction, see the Intel Processor manuals.
8017 \S{insCVTTSS2SI} \i\c{CVTTSS2SI}:
8018 Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
8020 \c CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE]
8022 \c{CVTTSS2SI} converts a single-precision FP value in the source operand
8023 to a signed doubleword in the destination operand. If the result is
8024 inexact, it is truncated (rounded toward zero).
8026 The destination operand is a general purpose register. The source can be
8027 either an \c{XMM} register or a 32-bit memory location. If the source is a
8028 register, the input value is in the low doubleword.
8030 For more details of this instruction, see the Intel Processor manuals.
8033 \S{insDAA} \i\c{DAA}, \i\c{DAS}: Decimal Adjustments
8038 These instructions are used in conjunction with the add and subtract
8039 instructions to perform binary-coded decimal arithmetic in
8040 \e{packed} (one BCD digit per nibble) form. For the unpacked
8041 equivalents, see \k{insAAA}.
8043 \c{DAA} should be used after a one-byte \c{ADD} instruction whose
8044 destination was the \c{AL} register: by means of examining the value
8045 in the \c{AL} and also the auxiliary carry flag \c{AF}, it
8046 determines whether either digit of the addition has overflowed, and
8047 adjusts it (and sets the carry and auxiliary-carry flags) if so. You
8048 can add long BCD strings together by doing \c{ADD}/\c{DAA} on the
8049 low two digits, then doing \c{ADC}/\c{DAA} on each subsequent pair
8052 \c{DAS} works similarly to \c{DAA}, but is for use after \c{SUB}
8053 instructions rather than \c{ADD}.
8056 \S{insDEC} \i\c{DEC}: Decrement Integer
8058 \c DEC reg16 ; o16 48+r [8086]
8059 \c DEC reg32 ; o32 48+r [386]
8060 \c DEC r/m8 ; FE /1 [8086]
8061 \c DEC r/m16 ; o16 FF /1 [8086]
8062 \c DEC r/m32 ; o32 FF /1 [386]
8064 \c{DEC} subtracts 1 from its operand. It does \e{not} affect the
8065 carry flag: to affect the carry flag, use \c{SUB something,1} (see
8066 \k{insSUB}). \c{DEC} affects all the other flags according to the result.
8068 This instruction can be used with a \c{LOCK} prefix to allow atomic
8071 See also \c{INC} (\k{insINC}).
8074 \S{insDIV} \i\c{DIV}: Unsigned Integer Divide
8076 \c DIV r/m8 ; F6 /6 [8086]
8077 \c DIV r/m16 ; o16 F7 /6 [8086]
8078 \c DIV r/m32 ; o32 F7 /6 [386]
8080 \c{DIV} performs unsigned integer division. The explicit operand
8081 provided is the divisor; the dividend and destination operands are
8082 implicit, in the following way:
8084 \b For \c{DIV r/m8}, \c{AX} is divided by the given operand; the
8085 quotient is stored in \c{AL} and the remainder in \c{AH}.
8087 \b For \c{DIV r/m16}, \c{DX:AX} is divided by the given operand; the
8088 quotient is stored in \c{AX} and the remainder in \c{DX}.
8090 \b For \c{DIV r/m32}, \c{EDX:EAX} is divided by the given operand;
8091 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
8093 Signed integer division is performed by the \c{IDIV} instruction:
8097 \S{insDIVPD} \i\c{DIVPD}: Packed Double-Precision FP Divide
8099 \c DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2]
8101 \c{DIVPD} divides the two packed double-precision FP values in
8102 the destination operand by the two packed double-precision FP
8103 values in the source operand, and stores the packed double-precision
8104 results in the destination register.
8106 The destination is an \c{XMM} register. The source operand can be
8107 either an \c{XMM} register or a 128-bit memory location.
8109 \c dst[0-63] := dst[0-63] / src[0-63],
8110 \c dst[64-127] := dst[64-127] / src[64-127].
8113 \S{insDIVPS} \i\c{DIVPS}: Packed Single-Precision FP Divide
8115 \c DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE]
8117 \c{DIVPS} divides the four packed single-precision FP values in
8118 the destination operand by the four packed single-precision FP
8119 values in the source operand, and stores the packed single-precision
8120 results in the destination register.
8122 The destination is an \c{XMM} register. The source operand can be
8123 either an \c{XMM} register or a 128-bit memory location.
8125 \c dst[0-31] := dst[0-31] / src[0-31],
8126 \c dst[32-63] := dst[32-63] / src[32-63],
8127 \c dst[64-95] := dst[64-95] / src[64-95],
8128 \c dst[96-127] := dst[96-127] / src[96-127].
8131 \S{insDIVSD} \i\c{DIVSD}: Scalar Double-Precision FP Divide
8133 \c DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2]
8135 \c{DIVSD} divides the low-order double-precision FP value in the
8136 destination operand by the low-order double-precision FP value in
8137 the source operand, and stores the double-precision result in the
8138 destination register.
8140 The destination is an \c{XMM} register. The source operand can be
8141 either an \c{XMM} register or a 64-bit memory location.
8143 \c dst[0-63] := dst[0-63] / src[0-63],
8144 \c dst[64-127] remains unchanged.
8147 \S{insDIVSS} \i\c{DIVSS}: Scalar Single-Precision FP Divide
8149 \c DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE]
8151 \c{DIVSS} divides the low-order single-precision FP value in the
8152 destination operand by the low-order single-precision FP value in
8153 the source operand, and stores the single-precision result in the
8154 destination register.
8156 The destination is an \c{XMM} register. The source operand can be
8157 either an \c{XMM} register or a 32-bit memory location.
8159 \c dst[0-31] := dst[0-31] / src[0-31],
8160 \c dst[32-127] remains unchanged.
8163 \S{insEMMS} \i\c{EMMS}: Empty MMX State
8165 \c EMMS ; 0F 77 [PENT,MMX]
8167 \c{EMMS} sets the FPU tag word (marking which floating-point registers
8168 are available) to all ones, meaning all registers are available for
8169 the FPU to use. It should be used after executing \c{MMX} instructions
8170 and before executing any subsequent floating-point operations.
8173 \S{insENTER} \i\c{ENTER}: Create Stack Frame
8175 \c ENTER imm,imm ; C8 iw ib [186]
8177 \c{ENTER} constructs a \i\c{stack frame} for a high-level language
8178 procedure call. The first operand (the \c{iw} in the opcode
8179 definition above refers to the first operand) gives the amount of
8180 stack space to allocate for local variables; the second (the \c{ib}
8181 above) gives the nesting level of the procedure (for languages like
8182 Pascal, with nested procedures).
8184 The function of \c{ENTER}, with a nesting level of zero, is
8187 \c PUSH EBP ; or PUSH BP in 16 bits
8188 \c MOV EBP,ESP ; or MOV BP,SP in 16 bits
8189 \c SUB ESP,operand1 ; or SUB SP,operand1 in 16 bits
8191 This creates a stack frame with the procedure parameters accessible
8192 upwards from \c{EBP}, and local variables accessible downwards from
8195 With a nesting level of one, the stack frame created is 4 (or 2)
8196 bytes bigger, and the value of the final frame pointer \c{EBP} is
8197 accessible in memory at \c{[EBP-4]}.
8199 This allows \c{ENTER}, when called with a nesting level of two, to
8200 look at the stack frame described by the \e{previous} value of
8201 \c{EBP}, find the frame pointer at offset -4 from that, and push it
8202 along with its new frame pointer, so that when a level-two procedure
8203 is called from within a level-one procedure, \c{[EBP-4]} holds the
8204 frame pointer of the most recent level-one procedure call and
8205 \c{[EBP-8]} holds that of the most recent level-two call. And so on,
8206 for nesting levels up to 31.
8208 Stack frames created by \c{ENTER} can be destroyed by the \c{LEAVE}
8209 instruction: see \k{insLEAVE}.
8212 \S{insF2XM1} \i\c{F2XM1}: Calculate 2**X-1
8214 \c F2XM1 ; D9 F0 [8086,FPU]
8216 \c{F2XM1} raises 2 to the power of \c{ST0}, subtracts one, and
8217 stores the result back into \c{ST0}. The initial contents of \c{ST0}
8218 must be a number in the range -1.0 to +1.0.
8221 \S{insFABS} \i\c{FABS}: Floating-Point Absolute Value
8223 \c FABS ; D9 E1 [8086,FPU]
8225 \c{FABS} computes the absolute value of \c{ST0},by clearing the sign
8226 bit, and stores the result back in \c{ST0}.
8229 \S{insFADD} \i\c{FADD}, \i\c{FADDP}: Floating-Point Addition
8231 \c FADD mem32 ; D8 /0 [8086,FPU]
8232 \c FADD mem64 ; DC /0 [8086,FPU]
8234 \c FADD fpureg ; D8 C0+r [8086,FPU]
8235 \c FADD ST0,fpureg ; D8 C0+r [8086,FPU]
8237 \c FADD TO fpureg ; DC C0+r [8086,FPU]
8238 \c FADD fpureg,ST0 ; DC C0+r [8086,FPU]
8240 \c FADDP fpureg ; DE C0+r [8086,FPU]
8241 \c FADDP fpureg,ST0 ; DE C0+r [8086,FPU]
8243 \b \c{FADD}, given one operand, adds the operand to \c{ST0} and stores
8244 the result back in \c{ST0}. If the operand has the \c{TO} modifier,
8245 the result is stored in the register given rather than in \c{ST0}.
8247 \b \c{FADDP} performs the same function as \c{FADD TO}, but pops the
8248 register stack after storing the result.
8250 The given two-operand forms are synonyms for the one-operand forms.
8252 To add an integer value to \c{ST0}, use the c{FIADD} instruction
8256 \S{insFBLD} \i\c{FBLD}, \i\c{FBSTP}: BCD Floating-Point Load and Store
8258 \c FBLD mem80 ; DF /4 [8086,FPU]
8259 \c FBSTP mem80 ; DF /6 [8086,FPU]
8261 \c{FBLD} loads an 80-bit (ten-byte) packed binary-coded decimal
8262 number from the given memory address, converts it to a real, and
8263 pushes it on the register stack. \c{FBSTP} stores the value of
8264 \c{ST0}, in packed BCD, at the given address and then pops the
8268 \S{insFCHS} \i\c{FCHS}: Floating-Point Change Sign
8270 \c FCHS ; D9 E0 [8086,FPU]
8272 \c{FCHS} negates the number in \c{ST0}, by inverting the sign bit:
8273 negative numbers become positive, and vice versa.
8276 \S{insFCLEX} \i\c{FCLEX}, \c{FNCLEX}: Clear Floating-Point Exceptions
8278 \c FCLEX ; 9B DB E2 [8086,FPU]
8279 \c FNCLEX ; DB E2 [8086,FPU]
8281 \c{FCLEX} clears any floating-point exceptions which may be pending.
8282 \c{FNCLEX} does the same thing but doesn't wait for previous
8283 floating-point operations (including the \e{handling} of pending
8284 exceptions) to finish first.
8287 \S{insFCMOVB} \i\c{FCMOVcc}: Floating-Point Conditional Move
8289 \c FCMOVB fpureg ; DA C0+r [P6,FPU]
8290 \c FCMOVB ST0,fpureg ; DA C0+r [P6,FPU]
8292 \c FCMOVE fpureg ; DA C8+r [P6,FPU]
8293 \c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU]
8295 \c FCMOVBE fpureg ; DA D0+r [P6,FPU]
8296 \c FCMOVBE ST0,fpureg ; DA D0+r [P6,FPU]
8298 \c FCMOVU fpureg ; DA D8+r [P6,FPU]
8299 \c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU]
8301 \c FCMOVNB fpureg ; DB C0+r [P6,FPU]
8302 \c FCMOVNB ST0,fpureg ; DB C0+r [P6,FPU]
8304 \c FCMOVNE fpureg ; DB C8+r [P6,FPU]
8305 \c FCMOVNE ST0,fpureg ; DB C8+r [P6,FPU]
8307 \c FCMOVNBE fpureg ; DB D0+r [P6,FPU]
8308 \c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU]
8310 \c FCMOVNU fpureg ; DB D8+r [P6,FPU]
8311 \c FCMOVNU ST0,fpureg ; DB D8+r [P6,FPU]
8313 The \c{FCMOV} instructions perform conditional move operations: each
8314 of them moves the contents of the given register into \c{ST0} if its
8315 condition is satisfied, and does nothing if not.
8317 The conditions are not the same as the standard condition codes used
8318 with conditional jump instructions. The conditions \c{B}, \c{BE},
8319 \c{NB}, \c{NBE}, \c{E} and \c{NE} are exactly as normal, but none of
8320 the other standard ones are supported. Instead, the condition \c{U}
8321 and its counterpart \c{NU} are provided; the \c{U} condition is
8322 satisfied if the last two floating-point numbers compared were
8323 \e{unordered}, i.e. they were not equal but neither one could be
8324 said to be greater than the other, for example if they were NaNs.
8325 (The flag state which signals this is the setting of the parity
8326 flag: so the \c{U} condition is notionally equivalent to \c{PE}, and
8327 \c{NU} is equivalent to \c{PO}.)
8329 The \c{FCMOV} conditions test the main processor's status flags, not
8330 the FPU status flags, so using \c{FCMOV} directly after \c{FCOM}
8331 will not work. Instead, you should either use \c{FCOMI} which writes
8332 directly to the main CPU flags word, or use \c{FSTSW} to extract the
8335 Although the \c{FCMOV} instructions are flagged \c{P6} above, they
8336 may not be supported by all Pentium Pro processors; the \c{CPUID}
8337 instruction (\k{insCPUID}) will return a bit which indicates whether
8338 conditional moves are supported.
8341 \S{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI},
8342 \i\c{FCOMIP}: Floating-Point Compare
8344 \c FCOM mem32 ; D8 /2 [8086,FPU]
8345 \c FCOM mem64 ; DC /2 [8086,FPU]
8346 \c FCOM fpureg ; D8 D0+r [8086,FPU]
8347 \c FCOM ST0,fpureg ; D8 D0+r [8086,FPU]
8349 \c FCOMP mem32 ; D8 /3 [8086,FPU]
8350 \c FCOMP mem64 ; DC /3 [8086,FPU]
8351 \c FCOMP fpureg ; D8 D8+r [8086,FPU]
8352 \c FCOMP ST0,fpureg ; D8 D8+r [8086,FPU]
8354 \c FCOMPP ; DE D9 [8086,FPU]
8356 \c FCOMI fpureg ; DB F0+r [P6,FPU]
8357 \c FCOMI ST0,fpureg ; DB F0+r [P6,FPU]
8359 \c FCOMIP fpureg ; DF F0+r [P6,FPU]
8360 \c FCOMIP ST0,fpureg ; DF F0+r [P6,FPU]
8362 \c{FCOM} compares \c{ST0} with the given operand, and sets the FPU
8363 flags accordingly. \c{ST0} is treated as the left-hand side of the
8364 comparison, so that the carry flag is set (for a `less-than' result)
8365 if \c{ST0} is less than the given operand.
8367 \c{FCOMP} does the same as \c{FCOM}, but pops the register stack
8368 afterwards. \c{FCOMPP} compares \c{ST0} with \c{ST1} and then pops
8369 the register stack twice.
8371 \c{FCOMI} and \c{FCOMIP} work like the corresponding forms of
8372 \c{FCOM} and \c{FCOMP}, but write their results directly to the CPU
8373 flags register rather than the FPU status word, so they can be
8374 immediately followed by conditional jump or conditional move
8377 The \c{FCOM} instructions differ from the \c{FUCOM} instructions
8378 (\k{insFUCOM}) only in the way they handle quiet NaNs: \c{FUCOM}
8379 will handle them silently and set the condition code flags to an
8380 `unordered' result, whereas \c{FCOM} will generate an exception.
8383 \S{insFCOS} \i\c{FCOS}: Cosine
8385 \c FCOS ; D9 FF [386,FPU]
8387 \c{FCOS} computes the cosine of \c{ST0} (in radians), and stores the
8388 result in \c{ST0}. The absolute value of \c{ST0} must be less than 2**63.
8390 See also \c{FSINCOS} (\k{insFSIN}).
8393 \S{insFDECSTP} \i\c{FDECSTP}: Decrement Floating-Point Stack Pointer
8395 \c FDECSTP ; D9 F6 [8086,FPU]
8397 \c{FDECSTP} decrements the `top' field in the floating-point status
8398 word. This has the effect of rotating the FPU register stack by one,
8399 as if the contents of \c{ST7} had been pushed on the stack. See also
8400 \c{FINCSTP} (\k{insFINCSTP}).
8403 \S{insFDISI} \i\c{FxDISI}, \i\c{FxENI}: Disable and Enable Floating-Point Interrupts
8405 \c FDISI ; 9B DB E1 [8086,FPU]
8406 \c FNDISI ; DB E1 [8086,FPU]
8408 \c FENI ; 9B DB E0 [8086,FPU]
8409 \c FNENI ; DB E0 [8086,FPU]
8411 \c{FDISI} and \c{FENI} disable and enable floating-point interrupts.
8412 These instructions are only meaningful on original 8087 processors:
8413 the 287 and above treat them as no-operation instructions.
8415 \c{FNDISI} and \c{FNENI} do the same thing as \c{FDISI} and \c{FENI}
8416 respectively, but without waiting for the floating-point processor
8417 to finish what it was doing first.
8420 \S{insFDIV} \i\c{FDIV}, \i\c{FDIVP}, \i\c{FDIVR}, \i\c{FDIVRP}: Floating-Point Division
8422 \c FDIV mem32 ; D8 /6 [8086,FPU]
8423 \c FDIV mem64 ; DC /6 [8086,FPU]
8425 \c FDIV fpureg ; D8 F0+r [8086,FPU]
8426 \c FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
8428 \c FDIV TO fpureg ; DC F8+r [8086,FPU]
8429 \c FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
8431 \c FDIVR mem32 ; D8 /0 [8086,FPU]
8432 \c FDIVR mem64 ; DC /0 [8086,FPU]
8434 \c FDIVR fpureg ; D8 F8+r [8086,FPU]
8435 \c FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
8437 \c FDIVR TO fpureg ; DC F0+r [8086,FPU]
8438 \c FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
8440 \c FDIVP fpureg ; DE F8+r [8086,FPU]
8441 \c FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
8443 \c FDIVRP fpureg ; DE F0+r [8086,FPU]
8444 \c FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
8446 \b \c{FDIV} divides \c{ST0} by the given operand and stores the result
8447 back in \c{ST0}, unless the \c{TO} qualifier is given, in which case
8448 it divides the given operand by \c{ST0} and stores the result in the
8451 \b \c{FDIVR} does the same thing, but does the division the other way
8452 up: so if \c{TO} is not given, it divides the given operand by
8453 \c{ST0} and stores the result in \c{ST0}, whereas if \c{TO} is given
8454 it divides \c{ST0} by its operand and stores the result in the
8457 \b \c{FDIVP} operates like \c{FDIV TO}, but pops the register stack
8458 once it has finished.
8460 \b \c{FDIVRP} operates like \c{FDIVR TO}, but pops the register stack
8461 once it has finished.
8463 For FP/Integer divisions, see \c{FIDIV} (\k{insFIDIV}).
8466 \S{insFEMMS} \i\c{FEMMS}: Faster Enter/Exit of the MMX or floating-point state
8468 \c FEMMS ; 0F 0E [PENT,3DNOW]
8470 \c{FEMMS} can be used in place of the \c{EMMS} instruction on
8471 processors which support the 3DNow! instruction set. Following
8472 execution of \c{FEMMS}, the state of the \c{MMX/FP} registers
8473 is undefined, and this allows a faster context switch between
8474 \c{FP} and \c{MMX} instructions. The \c{FEMMS} instruction can
8475 also be used \e{before} executing \c{MMX} instructions
8478 \S{insFFREE} \i\c{FFREE}: Flag Floating-Point Register as Unused
8480 \c FFREE fpureg ; DD C0+r [8086,FPU]
8481 \c FFREEP fpureg ; DF C0+r [286,FPU,UNDOC]
8483 \c{FFREE} marks the given register as being empty.
8485 \c{FFREEP} marks the given register as being empty, and then
8486 pops the register stack.
8489 \S{insFIADD} \i\c{FIADD}: Floating-Point/Integer Addition
8491 \c FIADD mem16 ; DE /0 [8086,FPU]
8492 \c FIADD mem32 ; DA /0 [8086,FPU]
8494 \c{FIADD} adds the 16-bit or 32-bit integer stored in the given
8495 memory location to \c{ST0}, storing the result in \c{ST0}.
8498 \S{insFICOM} \i\c{FICOM}, \i\c{FICOMP}: Floating-Point/Integer Compare
8500 \c FICOM mem16 ; DE /2 [8086,FPU]
8501 \c FICOM mem32 ; DA /2 [8086,FPU]
8503 \c FICOMP mem16 ; DE /3 [8086,FPU]
8504 \c FICOMP mem32 ; DA /3 [8086,FPU]
8506 \c{FICOM} compares \c{ST0} with the 16-bit or 32-bit integer stored
8507 in the given memory location, and sets the FPU flags accordingly.
8508 \c{FICOMP} does the same, but pops the register stack afterwards.
8511 \S{insFIDIV} \i\c{FIDIV}, \i\c{FIDIVR}: Floating-Point/Integer Division
8513 \c FIDIV mem16 ; DE /6 [8086,FPU]
8514 \c FIDIV mem32 ; DA /6 [8086,FPU]
8516 \c FIDIVR mem16 ; DE /7 [8086,FPU]
8517 \c FIDIVR mem32 ; DA /7 [8086,FPU]
8519 \c{FIDIV} divides \c{ST0} by the 16-bit or 32-bit integer stored in
8520 the given memory location, and stores the result in \c{ST0}.
8521 \c{FIDIVR} does the division the other way up: it divides the
8522 integer by \c{ST0}, but still stores the result in \c{ST0}.
8525 \S{insFILD} \i\c{FILD}, \i\c{FIST}, \i\c{FISTP}: Floating-Point/Integer Conversion
8527 \c FILD mem16 ; DF /0 [8086,FPU]
8528 \c FILD mem32 ; DB /0 [8086,FPU]
8529 \c FILD mem64 ; DF /5 [8086,FPU]
8531 \c FIST mem16 ; DF /2 [8086,FPU]
8532 \c FIST mem32 ; DB /2 [8086,FPU]
8534 \c FISTP mem16 ; DF /3 [8086,FPU]
8535 \c FISTP mem32 ; DB /3 [8086,FPU]
8536 \c FISTP mem64 ; DF /7 [8086,FPU]
8538 \c{FILD} loads an integer out of a memory location, converts it to a
8539 real, and pushes it on the FPU register stack. \c{FIST} converts
8540 \c{ST0} to an integer and stores that in memory; \c{FISTP} does the
8541 same as \c{FIST}, but pops the register stack afterwards.
8544 \S{insFIMUL} \i\c{FIMUL}: Floating-Point/Integer Multiplication
8546 \c FIMUL mem16 ; DE /1 [8086,FPU]
8547 \c FIMUL mem32 ; DA /1 [8086,FPU]
8549 \c{FIMUL} multiplies \c{ST0} by the 16-bit or 32-bit integer stored
8550 in the given memory location, and stores the result in \c{ST0}.
8553 \S{insFINCSTP} \i\c{FINCSTP}: Increment Floating-Point Stack Pointer
8555 \c FINCSTP ; D9 F7 [8086,FPU]
8557 \c{FINCSTP} increments the `top' field in the floating-point status
8558 word. This has the effect of rotating the FPU register stack by one,
8559 as if the register stack had been popped; however, unlike the
8560 popping of the stack performed by many FPU instructions, it does not
8561 flag the new \c{ST7} (previously \c{ST0}) as empty. See also
8562 \c{FDECSTP} (\k{insFDECSTP}).
8565 \S{insFINIT} \i\c{FINIT}, \i\c{FNINIT}: Initialise Floating-Point Unit
8567 \c FINIT ; 9B DB E3 [8086,FPU]
8568 \c FNINIT ; DB E3 [8086,FPU]
8570 \c{FINIT} initialises the FPU to its default state. It flags all
8571 registers as empty, without actually change their values, clears
8572 the top of stack pointer. \c{FNINIT} does the same, without first
8573 waiting for pending exceptions to clear.
8576 \S{insFISUB} \i\c{FISUB}: Floating-Point/Integer Subtraction
8578 \c FISUB mem16 ; DE /4 [8086,FPU]
8579 \c FISUB mem32 ; DA /4 [8086,FPU]
8581 \c FISUBR mem16 ; DE /5 [8086,FPU]
8582 \c FISUBR mem32 ; DA /5 [8086,FPU]
8584 \c{FISUB} subtracts the 16-bit or 32-bit integer stored in the given
8585 memory location from \c{ST0}, and stores the result in \c{ST0}.
8586 \c{FISUBR} does the subtraction the other way round, i.e. it
8587 subtracts \c{ST0} from the given integer, but still stores the
8591 \S{insFLD} \i\c{FLD}: Floating-Point Load
8593 \c FLD mem32 ; D9 /0 [8086,FPU]
8594 \c FLD mem64 ; DD /0 [8086,FPU]
8595 \c FLD mem80 ; DB /5 [8086,FPU]
8596 \c FLD fpureg ; D9 C0+r [8086,FPU]
8598 \c{FLD} loads a floating-point value out of the given register or
8599 memory location, and pushes it on the FPU register stack.
8602 \S{insFLD1} \i\c{FLDxx}: Floating-Point Load Constants
8604 \c FLD1 ; D9 E8 [8086,FPU]
8605 \c FLDL2E ; D9 EA [8086,FPU]
8606 \c FLDL2T ; D9 E9 [8086,FPU]
8607 \c FLDLG2 ; D9 EC [8086,FPU]
8608 \c FLDLN2 ; D9 ED [8086,FPU]
8609 \c FLDPI ; D9 EB [8086,FPU]
8610 \c FLDZ ; D9 EE [8086,FPU]
8612 These instructions push specific standard constants on the FPU
8615 \c Instruction Constant pushed
8618 \c FLDL2E base-2 logarithm of e
8619 \c FLDL2T base-2 log of 10
8620 \c FLDLG2 base-10 log of 2
8621 \c FLDLN2 base-e log of 2
8626 \S{insFLDCW} \i\c{FLDCW}: Load Floating-Point Control Word
8628 \c FLDCW mem16 ; D9 /5 [8086,FPU]
8630 \c{FLDCW} loads a 16-bit value out of memory and stores it into the
8631 FPU control word (governing things like the rounding mode, the
8632 precision, and the exception masks). See also \c{FSTCW}
8633 (\k{insFSTCW}). If exceptions are enabled and you don't want to
8634 generate one, use \c{FCLEX} or \c{FNCLEX} (\k{insFCLEX}) before
8635 loading the new control word.
8638 \S{insFLDENV} \i\c{FLDENV}: Load Floating-Point Environment
8640 \c FLDENV mem ; D9 /4 [8086,FPU]
8642 \c{FLDENV} loads the FPU operating environment (control word, status
8643 word, tag word, instruction pointer, data pointer and last opcode)
8644 from memory. The memory area is 14 or 28 bytes long, depending on
8645 the CPU mode at the time. See also \c{FSTENV} (\k{insFSTENV}).
8648 \S{insFMUL} \i\c{FMUL}, \i\c{FMULP}: Floating-Point Multiply
8650 \c FMUL mem32 ; D8 /1 [8086,FPU]
8651 \c FMUL mem64 ; DC /1 [8086,FPU]
8653 \c FMUL fpureg ; D8 C8+r [8086,FPU]
8654 \c FMUL ST0,fpureg ; D8 C8+r [8086,FPU]
8656 \c FMUL TO fpureg ; DC C8+r [8086,FPU]
8657 \c FMUL fpureg,ST0 ; DC C8+r [8086,FPU]
8659 \c FMULP fpureg ; DE C8+r [8086,FPU]
8660 \c FMULP fpureg,ST0 ; DE C8+r [8086,FPU]
8662 \c{FMUL} multiplies \c{ST0} by the given operand, and stores the
8663 result in \c{ST0}, unless the \c{TO} qualifier is used in which case
8664 it stores the result in the operand. \c{FMULP} performs the same
8665 operation as \c{FMUL TO}, and then pops the register stack.
8668 \S{insFNOP} \i\c{FNOP}: Floating-Point No Operation
8670 \c FNOP ; D9 D0 [8086,FPU]
8672 \c{FNOP} does nothing.
8675 \S{insFPATAN} \i\c{FPATAN}, \i\c{FPTAN}: Arctangent and Tangent
8677 \c FPATAN ; D9 F3 [8086,FPU]
8678 \c FPTAN ; D9 F2 [8086,FPU]
8680 \c{FPATAN} computes the arctangent, in radians, of the result of
8681 dividing \c{ST1} by \c{ST0}, stores the result in \c{ST1}, and pops
8682 the register stack. It works like the C \c{atan2} function, in that
8683 changing the sign of both \c{ST0} and \c{ST1} changes the output
8684 value by pi (so it performs true rectangular-to-polar coordinate
8685 conversion, with \c{ST1} being the Y coordinate and \c{ST0} being
8686 the X coordinate, not merely an arctangent).
8688 \c{FPTAN} computes the tangent of the value in \c{ST0} (in radians),
8689 and stores the result back into \c{ST0}.
8691 The absolute value of \c{ST0} must be less than 2**63.
8694 \S{insFPREM} \i\c{FPREM}, \i\c{FPREM1}: Floating-Point Partial Remainder
8696 \c FPREM ; D9 F8 [8086,FPU]
8697 \c FPREM1 ; D9 F5 [386,FPU]
8699 These instructions both produce the remainder obtained by dividing
8700 \c{ST0} by \c{ST1}. This is calculated, notionally, by dividing
8701 \c{ST0} by \c{ST1}, rounding the result to an integer, multiplying
8702 by \c{ST1} again, and computing the value which would need to be
8703 added back on to the result to get back to the original value in
8706 The two instructions differ in the way the notional round-to-integer
8707 operation is performed. \c{FPREM} does it by rounding towards zero,
8708 so that the remainder it returns always has the same sign as the
8709 original value in \c{ST0}; \c{FPREM1} does it by rounding to the
8710 nearest integer, so that the remainder always has at most half the
8711 magnitude of \c{ST1}.
8713 Both instructions calculate \e{partial} remainders, meaning that
8714 they may not manage to provide the final result, but might leave
8715 intermediate results in \c{ST0} instead. If this happens, they will
8716 set the C2 flag in the FPU status word; therefore, to calculate a
8717 remainder, you should repeatedly execute \c{FPREM} or \c{FPREM1}
8718 until C2 becomes clear.
8721 \S{insFRNDINT} \i\c{FRNDINT}: Floating-Point Round to Integer
8723 \c FRNDINT ; D9 FC [8086,FPU]
8725 \c{FRNDINT} rounds the contents of \c{ST0} to an integer, according
8726 to the current rounding mode set in the FPU control word, and stores
8727 the result back in \c{ST0}.
8730 \S{insFRSTOR} \i\c{FSAVE}, \i\c{FRSTOR}: Save/Restore Floating-Point State
8732 \c FSAVE mem ; 9B DD /6 [8086,FPU]
8733 \c FNSAVE mem ; DD /6 [8086,FPU]
8735 \c FRSTOR mem ; DD /4 [8086,FPU]
8737 \c{FSAVE} saves the entire floating-point unit state, including all
8738 the information saved by \c{FSTENV} (\k{insFSTENV}) plus the
8739 contents of all the registers, to a 94 or 108 byte area of memory
8740 (depending on the CPU mode). \c{FRSTOR} restores the floating-point
8741 state from the same area of memory.
8743 \c{FNSAVE} does the same as \c{FSAVE}, without first waiting for
8744 pending floating-point exceptions to clear.
8747 \S{insFSCALE} \i\c{FSCALE}: Scale Floating-Point Value by Power of Two
8749 \c FSCALE ; D9 FD [8086,FPU]
8751 \c{FSCALE} scales a number by a power of two: it rounds \c{ST1}
8752 towards zero to obtain an integer, then multiplies \c{ST0} by two to
8753 the power of that integer, and stores the result in \c{ST0}.
8756 \S{insFSETPM} \i\c{FSETPM}: Set Protected Mode
8758 \c FSETPM ; DB E4 [286,FPU]
8760 This instruction initialises protected mode on the 287 floating-point
8761 coprocessor. It is only meaningful on that processor: the 387 and
8762 above treat the instruction as a no-operation.
8765 \S{insFSIN} \i\c{FSIN}, \i\c{FSINCOS}: Sine and Cosine
8767 \c FSIN ; D9 FE [386,FPU]
8768 \c FSINCOS ; D9 FB [386,FPU]
8770 \c{FSIN} calculates the sine of \c{ST0} (in radians) and stores the
8771 result in \c{ST0}. \c{FSINCOS} does the same, but then pushes the
8772 cosine of the same value on the register stack, so that the sine
8773 ends up in \c{ST1} and the cosine in \c{ST0}. \c{FSINCOS} is faster
8774 than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in succession.
8776 The absolute value of \c{ST0} must be less than 2**63.
8779 \S{insFSQRT} \i\c{FSQRT}: Floating-Point Square Root
8781 \c FSQRT ; D9 FA [8086,FPU]
8783 \c{FSQRT} calculates the square root of \c{ST0} and stores the
8787 \S{insFST} \i\c{FST}, \i\c{FSTP}: Floating-Point Store
8789 \c FST mem32 ; D9 /2 [8086,FPU]
8790 \c FST mem64 ; DD /2 [8086,FPU]
8791 \c FST fpureg ; DD D0+r [8086,FPU]
8793 \c FSTP mem32 ; D9 /3 [8086,FPU]
8794 \c FSTP mem64 ; DD /3 [8086,FPU]
8795 \c FSTP mem80 ; DB /7 [8086,FPU]
8796 \c FSTP fpureg ; DD D8+r [8086,FPU]
8798 \c{FST} stores the value in \c{ST0} into the given memory location
8799 or other FPU register. \c{FSTP} does the same, but then pops the
8803 \S{insFSTCW} \i\c{FSTCW}: Store Floating-Point Control Word
8805 \c FSTCW mem16 ; 9B D9 /7 [8086,FPU]
8806 \c FNSTCW mem16 ; D9 /7 [8086,FPU]
8808 \c{FSTCW} stores the \c{FPU} control word (governing things like the
8809 rounding mode, the precision, and the exception masks) into a 2-byte
8810 memory area. See also \c{FLDCW} (\k{insFLDCW}).
8812 \c{FNSTCW} does the same thing as \c{FSTCW}, without first waiting
8813 for pending floating-point exceptions to clear.
8816 \S{insFSTENV} \i\c{FSTENV}: Store Floating-Point Environment
8818 \c FSTENV mem ; 9B D9 /6 [8086,FPU]
8819 \c FNSTENV mem ; D9 /6 [8086,FPU]
8821 \c{FSTENV} stores the \c{FPU} operating environment (control word,
8822 status word, tag word, instruction pointer, data pointer and last
8823 opcode) into memory. The memory area is 14 or 28 bytes long,
8824 depending on the CPU mode at the time. See also \c{FLDENV}
8827 \c{FNSTENV} does the same thing as \c{FSTENV}, without first waiting
8828 for pending floating-point exceptions to clear.
8831 \S{insFSTSW} \i\c{FSTSW}: Store Floating-Point Status Word
8833 \c FSTSW mem16 ; 9B DD /7 [8086,FPU]
8834 \c FSTSW AX ; 9B DF E0 [286,FPU]
8836 \c FNSTSW mem16 ; DD /7 [8086,FPU]
8837 \c FNSTSW AX ; DF E0 [286,FPU]
8839 \c{FSTSW} stores the \c{FPU} status word into \c{AX} or into a 2-byte
8842 \c{FNSTSW} does the same thing as \c{FSTSW}, without first waiting
8843 for pending floating-point exceptions to clear.
8846 \S{insFSUB} \i\c{FSUB}, \i\c{FSUBP}, \i\c{FSUBR}, \i\c{FSUBRP}: Floating-Point Subtract
8848 \c FSUB mem32 ; D8 /4 [8086,FPU]
8849 \c FSUB mem64 ; DC /4 [8086,FPU]
8851 \c FSUB fpureg ; D8 E0+r [8086,FPU]
8852 \c FSUB ST0,fpureg ; D8 E0+r [8086,FPU]
8854 \c FSUB TO fpureg ; DC E8+r [8086,FPU]
8855 \c FSUB fpureg,ST0 ; DC E8+r [8086,FPU]
8857 \c FSUBR mem32 ; D8 /5 [8086,FPU]
8858 \c FSUBR mem64 ; DC /5 [8086,FPU]
8860 \c FSUBR fpureg ; D8 E8+r [8086,FPU]
8861 \c FSUBR ST0,fpureg ; D8 E8+r [8086,FPU]
8863 \c FSUBR TO fpureg ; DC E0+r [8086,FPU]
8864 \c FSUBR fpureg,ST0 ; DC E0+r [8086,FPU]
8866 \c FSUBP fpureg ; DE E8+r [8086,FPU]
8867 \c FSUBP fpureg,ST0 ; DE E8+r [8086,FPU]
8869 \c FSUBRP fpureg ; DE E0+r [8086,FPU]
8870 \c FSUBRP fpureg,ST0 ; DE E0+r [8086,FPU]
8872 \b \c{FSUB} subtracts the given operand from \c{ST0} and stores the
8873 result back in \c{ST0}, unless the \c{TO} qualifier is given, in
8874 which case it subtracts \c{ST0} from the given operand and stores
8875 the result in the operand.
8877 \b \c{FSUBR} does the same thing, but does the subtraction the other
8878 way up: so if \c{TO} is not given, it subtracts \c{ST0} from the given
8879 operand and stores the result in \c{ST0}, whereas if \c{TO} is given
8880 it subtracts its operand from \c{ST0} and stores the result in the
8883 \b \c{FSUBP} operates like \c{FSUB TO}, but pops the register stack
8884 once it has finished.
8886 \b \c{FSUBRP} operates like \c{FSUBR TO}, but pops the register stack
8887 once it has finished.
8890 \S{insFTST} \i\c{FTST}: Test \c{ST0} Against Zero
8892 \c FTST ; D9 E4 [8086,FPU]
8894 \c{FTST} compares \c{ST0} with zero and sets the FPU flags
8895 accordingly. \c{ST0} is treated as the left-hand side of the
8896 comparison, so that a `less-than' result is generated if \c{ST0} is
8900 \S{insFUCOM} \i\c{FUCOMxx}: Floating-Point Unordered Compare
8902 \c FUCOM fpureg ; DD E0+r [386,FPU]
8903 \c FUCOM ST0,fpureg ; DD E0+r [386,FPU]
8905 \c FUCOMP fpureg ; DD E8+r [386,FPU]
8906 \c FUCOMP ST0,fpureg ; DD E8+r [386,FPU]
8908 \c FUCOMPP ; DA E9 [386,FPU]
8910 \c FUCOMI fpureg ; DB E8+r [P6,FPU]
8911 \c FUCOMI ST0,fpureg ; DB E8+r [P6,FPU]
8913 \c FUCOMIP fpureg ; DF E8+r [P6,FPU]
8914 \c FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU]
8916 \b \c{FUCOM} compares \c{ST0} with the given operand, and sets the
8917 FPU flags accordingly. \c{ST0} is treated as the left-hand side of
8918 the comparison, so that the carry flag is set (for a `less-than'
8919 result) if \c{ST0} is less than the given operand.
8921 \b \c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack
8922 afterwards. \c{FUCOMPP} compares \c{ST0} with \c{ST1} and then pops
8923 the register stack twice.
8925 \b \c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of
8926 \c{FUCOM} and \c{FUCOMP}, but write their results directly to the CPU
8927 flags register rather than the FPU status word, so they can be
8928 immediately followed by conditional jump or conditional move
8931 The \c{FUCOM} instructions differ from the \c{FCOM} instructions
8932 (\k{insFCOM}) only in the way they handle quiet NaNs: \c{FUCOM} will
8933 handle them silently and set the condition code flags to an
8934 `unordered' result, whereas \c{FCOM} will generate an exception.
8937 \S{insFXAM} \i\c{FXAM}: Examine Class of Value in \c{ST0}
8939 \c FXAM ; D9 E5 [8086,FPU]
8941 \c{FXAM} sets the FPU flags \c{C3}, \c{C2} and \c{C0} depending on
8942 the type of value stored in \c{ST0}:
8944 \c Register contents Flags
8946 \c Unsupported format 000
8948 \c Finite number 010
8951 \c Empty register 101
8954 Additionally, the \c{C1} flag is set to the sign of the number.
8957 \S{insFXCH} \i\c{FXCH}: Floating-Point Exchange
8959 \c FXCH ; D9 C9 [8086,FPU]
8960 \c FXCH fpureg ; D9 C8+r [8086,FPU]
8961 \c FXCH fpureg,ST0 ; D9 C8+r [8086,FPU]
8962 \c FXCH ST0,fpureg ; D9 C8+r [8086,FPU]
8964 \c{FXCH} exchanges \c{ST0} with a given FPU register. The no-operand
8965 form exchanges \c{ST0} with \c{ST1}.
8968 \S{insFXRSTOR} \i\c{FXRSTOR}: Restore \c{FP}, \c{MMX} and \c{SSE} State
8970 \c FXRSTOR memory ; 0F AE /1 [P6,SSE,FPU]
8972 The \c{FXRSTOR} instruction reloads the \c{FPU}, \c{MMX} and \c{SSE}
8973 state (environment and registers), from the 512 byte memory area defined
8974 by the source operand. This data should have been written by a previous
8978 \S{insFXSAVE} \i\c{FXSAVE}: Store \c{FP}, \c{MMX} and \c{SSE} State
8980 \c FXSAVE memory ; 0F AE /0 [P6,SSE,FPU]
8982 \c{FXSAVE}The FXSAVE instruction writes the current \c{FPU}, \c{MMX}
8983 and \c{SSE} technology states (environment and registers), to the
8984 512 byte memory area defined by the destination operand. It does this
8985 without checking for pending unmasked floating-point exceptions
8986 (similar to the operation of \c{FNSAVE}).
8988 Unlike the \c{FSAVE/FNSAVE} instructions, the processor retains the
8989 contents of the \c{FPU}, \c{MMX} and \c{SSE} state in the processor
8990 after the state has been saved. This instruction has been optimised
8991 to maximize floating-point save performance.
8994 \S{insFXTRACT} \i\c{FXTRACT}: Extract Exponent and Significand
8996 \c FXTRACT ; D9 F4 [8086,FPU]
8998 \c{FXTRACT} separates the number in \c{ST0} into its exponent and
8999 significand (mantissa), stores the exponent back into \c{ST0}, and
9000 then pushes the significand on the register stack (so that the
9001 significand ends up in \c{ST0}, and the exponent in \c{ST1}).
9004 \S{insFYL2X} \i\c{FYL2X}, \i\c{FYL2XP1}: Compute Y times Log2(X) or Log2(X+1)
9006 \c FYL2X ; D9 F1 [8086,FPU]
9007 \c FYL2XP1 ; D9 F9 [8086,FPU]
9009 \c{FYL2X} multiplies \c{ST1} by the base-2 logarithm of \c{ST0},
9010 stores the result in \c{ST1}, and pops the register stack (so that
9011 the result ends up in \c{ST0}). \c{ST0} must be non-zero and
9014 \c{FYL2XP1} works the same way, but replacing the base-2 log of
9015 \c{ST0} with that of \c{ST0} plus one. This time, \c{ST0} must have
9016 magnitude no greater than 1 minus half the square root of two.
9019 \S{insHLT} \i\c{HLT}: Halt Processor
9021 \c HLT ; F4 [8086,PRIV]
9023 \c{HLT} puts the processor into a halted state, where it will
9024 perform no more operations until restarted by an interrupt or a
9027 On the 286 and later processors, this is a privileged instruction.
9030 \S{insIBTS} \i\c{IBTS}: Insert Bit String
9032 \c IBTS r/m16,reg16 ; o16 0F A7 /r [386,UNDOC]
9033 \c IBTS r/m32,reg32 ; o32 0F A7 /r [386,UNDOC]
9035 The implied operation of this instruction is:
9037 \c IBTS r/m16,AX,CL,reg16
9038 \c IBTS r/m32,EAX,CL,reg32
9040 Writes a bit string from the source operand to the destination.
9041 \c{CL} indicates the number of bits to be copied, from the low bits
9042 of the source. \c{(E)AX} indicates the low order bit offset in the
9043 destination that is written to. For example, if \c{CL} is set to 4
9044 and \c{AX} (for 16-bit code) is set to 5, bits 0-3 of \c{src} will
9045 be copied to bits 5-8 of \c{dst}. This instruction is very poorly
9046 documented, and I have been unable to find any official source of
9047 documentation on it.
9049 \c{IBTS} is supported only on the early Intel 386s, and conflicts
9050 with the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM
9051 supports it only for completeness. Its counterpart is \c{XBTS}
9055 \S{insIDIV} \i\c{IDIV}: Signed Integer Divide
9057 \c IDIV r/m8 ; F6 /7 [8086]
9058 \c IDIV r/m16 ; o16 F7 /7 [8086]
9059 \c IDIV r/m32 ; o32 F7 /7 [386]
9061 \c{IDIV} performs signed integer division. The explicit operand
9062 provided is the divisor; the dividend and destination operands
9063 are implicit, in the following way:
9065 \b For \c{IDIV r/m8}, \c{AX} is divided by the given operand;
9066 the quotient is stored in \c{AL} and the remainder in \c{AH}.
9068 \b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand;
9069 the quotient is stored in \c{AX} and the remainder in \c{DX}.
9071 \b For \c{IDIV r/m32}, \c{EDX:EAX} is divided by the given operand;
9072 the quotient is stored in \c{EAX} and the remainder in \c{EDX}.
9074 Unsigned integer division is performed by the \c{DIV} instruction:
9078 \S{insIMUL} \i\c{IMUL}: Signed Integer Multiply
9080 \c IMUL r/m8 ; F6 /5 [8086]
9081 \c IMUL r/m16 ; o16 F7 /5 [8086]
9082 \c IMUL r/m32 ; o32 F7 /5 [386]
9084 \c IMUL reg16,r/m16 ; o16 0F AF /r [386]
9085 \c IMUL reg32,r/m32 ; o32 0F AF /r [386]
9087 \c IMUL reg16,imm8 ; o16 6B /r ib [186]
9088 \c IMUL reg16,imm16 ; o16 69 /r iw [186]
9089 \c IMUL reg32,imm8 ; o32 6B /r ib [386]
9090 \c IMUL reg32,imm32 ; o32 69 /r id [386]
9092 \c IMUL reg16,r/m16,imm8 ; o16 6B /r ib [186]
9093 \c IMUL reg16,r/m16,imm16 ; o16 69 /r iw [186]
9094 \c IMUL reg32,r/m32,imm8 ; o32 6B /r ib [386]
9095 \c IMUL reg32,r/m32,imm32 ; o32 69 /r id [386]
9097 \c{IMUL} performs signed integer multiplication. For the
9098 single-operand form, the other operand and destination are
9099 implicit, in the following way:
9101 \b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand;
9102 the product is stored in \c{AX}.
9104 \b For \c{IMUL r/m16}, \c{AX} is multiplied by the given operand;
9105 the product is stored in \c{DX:AX}.
9107 \b For \c{IMUL r/m32}, \c{EAX} is multiplied by the given operand;
9108 the product is stored in \c{EDX:EAX}.
9110 The two-operand form multiplies its two operands and stores the
9111 result in the destination (first) operand. The three-operand
9112 form multiplies its last two operands and stores the result in
9115 The two-operand form with an immediate second operand is in
9116 fact a shorthand for the three-operand form, as can be seen by
9117 examining the opcode descriptions: in the two-operand form, the
9118 code \c{/r} takes both its register and \c{r/m} parts from the
9119 same operand (the first one).
9121 In the forms with an 8-bit immediate operand and another longer
9122 source operand, the immediate operand is considered to be signed,
9123 and is sign-extended to the length of the other source operand.
9124 In these cases, the \c{BYTE} qualifier is necessary to force
9125 NASM to generate this form of the instruction.
9127 Unsigned integer multiplication is performed by the \c{MUL}
9128 instruction: see \k{insMUL}.
9131 \S{insIN} \i\c{IN}: Input from I/O Port
9133 \c IN AL,imm8 ; E4 ib [8086]
9134 \c IN AX,imm8 ; o16 E5 ib [8086]
9135 \c IN EAX,imm8 ; o32 E5 ib [386]
9136 \c IN AL,DX ; EC [8086]
9137 \c IN AX,DX ; o16 ED [8086]
9138 \c IN EAX,DX ; o32 ED [386]
9140 \c{IN} reads a byte, word or doubleword from the specified I/O port,
9141 and stores it in the given destination register. The port number may
9142 be specified as an immediate value if it is between 0 and 255, and
9143 otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}).
9146 \S{insINC} \i\c{INC}: Increment Integer
9148 \c INC reg16 ; o16 40+r [8086]
9149 \c INC reg32 ; o32 40+r [386]
9150 \c INC r/m8 ; FE /0 [8086]
9151 \c INC r/m16 ; o16 FF /0 [8086]
9152 \c INC r/m32 ; o32 FF /0 [386]
9154 \c{INC} adds 1 to its operand. It does \e{not} affect the carry
9155 flag: to affect the carry flag, use \c{ADD something,1} (see
9156 \k{insADD}). \c{INC} affects all the other flags according to the result.
9158 This instruction can be used with a \c{LOCK} prefix to allow atomic execution.
9160 See also \c{DEC} (\k{insDEC}).
9163 \S{insINSB} \i\c{INSB}, \i\c{INSW}, \i\c{INSD}: Input String from I/O Port
9166 \c INSW ; o16 6D [186]
9167 \c INSD ; o32 6D [386]
9169 \c{INSB} inputs a byte from the I/O port specified in \c{DX} and
9170 stores it at \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or
9171 decrements (depending on the direction flag: increments if the flag
9172 is clear, decrements if it is set) \c{DI} or \c{EDI}.
9174 The register used is \c{DI} if the address size is 16 bits, and
9175 \c{EDI} if it is 32 bits. If you need to use an address size not
9176 equal to the current \c{BITS} setting, you can use an explicit
9177 \i\c{a16} or \i\c{a32} prefix.
9179 Segment override prefixes have no effect for this instruction: the
9180 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
9183 \c{INSW} and \c{INSD} work in the same way, but they input a word or
9184 a doubleword instead of a byte, and increment or decrement the
9185 addressing register by 2 or 4 instead of 1.
9187 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
9188 \c{ECX} - again, the address size chooses which) times.
9190 See also \c{OUTSB}, \c{OUTSW} and \c{OUTSD} (\k{insOUTSB}).
9193 \S{insINT} \i\c{INT}: Software Interrupt
9195 \c INT imm8 ; CD ib [8086]
9197 \c{INT} causes a software interrupt through a specified vector
9198 number from 0 to 255.
9200 The code generated by the \c{INT} instruction is always two bytes
9201 long: although there are short forms for some \c{INT} instructions,
9202 NASM does not generate them when it sees the \c{INT} mnemonic. In
9203 order to generate single-byte breakpoint instructions, use the
9204 \c{INT3} or \c{INT1} instructions (see \k{insINT1}) instead.
9207 \S{insINT1} \i\c{INT3}, \i\c{INT1}, \i\c{ICEBP}, \i\c{INT01}: Breakpoints
9214 \c INT03 ; CC [8086]
9216 \c{INT1} and \c{INT3} are short one-byte forms of the instructions
9217 \c{INT 1} and \c{INT 3} (see \k{insINT}). They perform a similar
9218 function to their longer counterparts, but take up less code space.
9219 They are used as breakpoints by debuggers.
9221 \b \c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is
9222 an instruction used by in-circuit emulators (ICEs). It is present,
9223 though not documented, on some processors down to the 286, but is
9224 only documented for the Pentium Pro. \c{INT3} is the instruction
9225 normally used as a breakpoint by debuggers.
9227 \b \c{INT3}, and its synonym \c{INT03}, is not precisely equivalent to
9228 \c{INT 3}: the short form, since it is designed to be used as a
9229 breakpoint, bypasses the normal \c{IOPL} checks in virtual-8086 mode,
9230 and also does not go through interrupt redirection.
9233 \S{insINTO} \i\c{INTO}: Interrupt if Overflow
9237 \c{INTO} performs an \c{INT 4} software interrupt (see \k{insINT})
9238 if and only if the overflow flag is set.
9241 \S{insINVD} \i\c{INVD}: Invalidate Internal Caches
9243 \c INVD ; 0F 08 [486]
9245 \c{INVD} invalidates and empties the processor's internal caches,
9246 and causes the processor to instruct external caches to do the same.
9247 It does not write the contents of the caches back to memory first:
9248 any modified data held in the caches will be lost. To write the data
9249 back first, use \c{WBINVD} (\k{insWBINVD}).
9252 \S{insINVLPG} \i\c{INVLPG}: Invalidate TLB Entry
9254 \c INVLPG mem ; 0F 01 /7 [486]
9256 \c{INVLPG} invalidates the translation lookahead buffer (TLB) entry
9257 associated with the supplied memory address.
9260 \S{insIRET} \i\c{IRET}, \i\c{IRETW}, \i\c{IRETD}: Return from Interrupt
9263 \c IRETW ; o16 CF [8086]
9264 \c IRETD ; o32 CF [386]
9266 \c{IRET} returns from an interrupt (hardware or software) by means
9267 of popping \c{IP} (or \c{EIP}), \c{CS} and the flags off the stack
9268 and then continuing execution from the new \c{CS:IP}.
9270 \c{IRETW} pops \c{IP}, \c{CS} and the flags as 2 bytes each, taking
9271 6 bytes off the stack in total. \c{IRETD} pops \c{EIP} as 4 bytes,
9272 pops a further 4 bytes of which the top two are discarded and the
9273 bottom two go into \c{CS}, and pops the flags as 4 bytes as well,
9274 taking 12 bytes off the stack.
9276 \c{IRET} is a shorthand for either \c{IRETW} or \c{IRETD}, depending
9277 on the default \c{BITS} setting at the time.
9280 \S{insJcc} \i\c{Jcc}: Conditional Branch
9282 \c Jcc imm ; 70+cc rb [8086]
9283 \c Jcc NEAR imm ; 0F 80+cc rw/rd [386]
9285 The \i{conditional jump} instructions execute a near (same segment)
9286 jump if and only if their conditions are satisfied. For example,
9287 \c{JNZ} jumps only if the zero flag is not set.
9289 The ordinary form of the instructions has only a 128-byte range; the
9290 \c{NEAR} form is a 386 extension to the instruction set, and can
9291 span the full size of a segment. NASM will not override your choice
9292 of jump instruction: if you want \c{Jcc NEAR}, you have to use the
9295 The \c{SHORT} keyword is allowed on the first form of the
9296 instruction, for clarity, but is not necessary.
9298 For details of the condition codes, see \k{iref-cc}.
9301 \S{insJCXZ} \i\c{JCXZ}, \i\c{JECXZ}: Jump if CX/ECX Zero
9303 \c JCXZ imm ; a16 E3 rb [8086]
9304 \c JECXZ imm ; a32 E3 rb [386]
9306 \c{JCXZ} performs a short jump (with maximum range 128 bytes) if and
9307 only if the contents of the \c{CX} register is 0. \c{JECXZ} does the
9308 same thing, but with \c{ECX}.
9311 \S{insJMP} \i\c{JMP}: Jump
9313 \c JMP imm ; E9 rw/rd [8086]
9314 \c JMP SHORT imm ; EB rb [8086]
9315 \c JMP imm:imm16 ; o16 EA iw iw [8086]
9316 \c JMP imm:imm32 ; o32 EA id iw [386]
9317 \c JMP FAR mem ; o16 FF /5 [8086]
9318 \c JMP FAR mem32 ; o32 FF /5 [386]
9319 \c JMP r/m16 ; o16 FF /4 [8086]
9320 \c JMP r/m32 ; o32 FF /4 [386]
9322 \c{JMP} jumps to a given address. The address may be specified as an
9323 absolute segment and offset, or as a relative jump within the
9326 \c{JMP SHORT imm} has a maximum range of 128 bytes, since the
9327 displacement is specified as only 8 bits, but takes up less code
9328 space. NASM does not choose when to generate \c{JMP SHORT} for you:
9329 you must explicitly code \c{SHORT} every time you want a short jump.
9331 You can choose between the two immediate \i{far jump} forms (\c{JMP
9332 imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: \c{JMP
9333 WORD 0x1234:0x5678}) or \c{JMP DWORD 0x1234:0x56789abc}.
9335 The \c{JMP FAR mem} forms execute a far jump by loading the
9336 destination address out of memory. The address loaded consists of 16
9337 or 32 bits of offset (depending on the operand size), and 16 bits of
9338 segment. The operand size may be overridden using \c{JMP WORD FAR
9339 mem} or \c{JMP DWORD FAR mem}.
9341 The \c{JMP r/m} forms execute a \i{near jump} (within the same
9342 segment), loading the destination address out of memory or out of a
9343 register. The keyword \c{NEAR} may be specified, for clarity, in
9344 these forms, but is not necessary. Again, operand size can be
9345 overridden using \c{JMP WORD mem} or \c{JMP DWORD mem}.
9347 As a convenience, NASM does not require you to jump to a far symbol
9348 by coding the cumbersome \c{JMP SEG routine:routine}, but instead
9349 allows the easier synonym \c{JMP FAR routine}.
9351 The \c{CALL r/m} forms given above are near calls; NASM will accept
9352 the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
9353 is not strictly necessary.
9356 \S{insLAHF} \i\c{LAHF}: Load AH from Flags
9360 \c{LAHF} sets the \c{AH} register according to the contents of the
9361 low byte of the flags word.
9363 The operation of \c{LAHF} is:
9365 \c AH <-- SF:ZF:0:AF:0:PF:1:CF
9367 See also \c{SAHF} (\k{insSAHF}).
9370 \S{insLAR} \i\c{LAR}: Load Access Rights
9372 \c LAR reg16,r/m16 ; o16 0F 02 /r [286,PRIV]
9373 \c LAR reg32,r/m32 ; o32 0F 02 /r [286,PRIV]
9375 \c{LAR} takes the segment selector specified by its source (second)
9376 operand, finds the corresponding segment descriptor in the GDT or
9377 LDT, and loads the access-rights byte of the descriptor into its
9378 destination (first) operand.
9381 \S{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension
9384 \c LDMXCSR mem32 ; 0F AE /2 [KATMAI,SSE]
9386 \c{LDMXCSR} loads 32-bits of data from the specified memory location
9387 into the \c{MXCSR} control/status register. \c{MXCSR} is used to
9388 enable masked/unmasked exception handling, to set rounding modes,
9389 to set flush-to-zero mode, and to view exception status flags.
9391 For details of the \c{MXCSR} register, see the Intel processor docs.
9393 See also \c{STMXCSR} (\k{insSTMXCSR}
9396 \S{insLDS} \i\c{LDS}, \i\c{LES}, \i\c{LFS}, \i\c{LGS}, \i\c{LSS}: Load Far Pointer
9398 \c LDS reg16,mem ; o16 C5 /r [8086]
9399 \c LDS reg32,mem ; o32 C5 /r [386]
9401 \c LES reg16,mem ; o16 C4 /r [8086]
9402 \c LES reg32,mem ; o32 C4 /r [386]
9404 \c LFS reg16,mem ; o16 0F B4 /r [386]
9405 \c LFS reg32,mem ; o32 0F B4 /r [386]
9407 \c LGS reg16,mem ; o16 0F B5 /r [386]
9408 \c LGS reg32,mem ; o32 0F B5 /r [386]
9410 \c LSS reg16,mem ; o16 0F B2 /r [386]
9411 \c LSS reg32,mem ; o32 0F B2 /r [386]
9413 These instructions load an entire far pointer (16 or 32 bits of
9414 offset, plus 16 bits of segment) out of memory in one go. \c{LDS},
9415 for example, loads 16 or 32 bits from the given memory address into
9416 the given register (depending on the size of the register), then
9417 loads the \e{next} 16 bits from memory into \c{DS}. \c{LES},
9418 \c{LFS}, \c{LGS} and \c{LSS} work in the same way but use the other
9422 \S{insLEA} \i\c{LEA}: Load Effective Address
9424 \c LEA reg16,mem ; o16 8D /r [8086]
9425 \c LEA reg32,mem ; o32 8D /r [386]
9427 \c{LEA}, despite its syntax, does not access memory. It calculates
9428 the effective address specified by its second operand as if it were
9429 going to load or store data from it, but instead it stores the
9430 calculated address into the register specified by its first operand.
9431 This can be used to perform quite complex calculations (e.g. \c{LEA
9432 EAX,[EBX+ECX*4+100]}) in one instruction.
9434 \c{LEA}, despite being a purely arithmetic instruction which
9435 accesses no memory, still requires square brackets around its second
9436 operand, as if it were a memory reference.
9438 The size of the calculation is the current \e{address} size, and the
9439 size that the result is stored as is the current \e{operand} size.
9440 If the address and operand size are not the same, then if the
9441 addressing mode was 32-bits, the low 16-bits are stored, and if the
9442 address was 16-bits, it is zero-extended to 32-bits before storing.
9445 \S{insLEAVE} \i\c{LEAVE}: Destroy Stack Frame
9449 \c{LEAVE} destroys a stack frame of the form created by the
9450 \c{ENTER} instruction (see \k{insENTER}). It is functionally
9451 equivalent to \c{MOV ESP,EBP} followed by \c{POP EBP} (or \c{MOV
9452 SP,BP} followed by \c{POP BP} in 16-bit mode).
9455 \S{insLFENCE} \i\c{LFENCE}: Load Fence
9457 \c LFENCE ; 0F AE /5 [WILLAMETTE,SSE2]
9459 \c{LFENCE} performs a serialising operation on all loads from memory
9460 that were issued before the \c{LFENCE} instruction. This guarantees that
9461 all memory reads before the \c{LFENCE} instruction are visible before any
9462 reads after the \c{LFENCE} instruction.
9464 \c{LFENCE} is ordered respective to other \c{LFENCE} instruction, \c{MFENCE},
9465 any memory read and any other serialising instruction (such as \c{CPUID}).
9467 Weakly ordered memory types can be used to achieve higher processor
9468 performance through such techniques as out-of-order issue and
9469 speculative reads. The degree to which a consumer of data recognizes
9470 or knows that the data is weakly ordered varies among applications
9471 and may be unknown to the producer of this data. The \c{LFENCE}
9472 instruction provides a performance-efficient way of ensuring load
9473 ordering between routines that produce weakly-ordered results and
9474 routines that consume that data.
9476 \c{LFENCE} uses the following ModRM encoding:
9479 \c Reg/Opcode (5:3) = 101B
9482 All other ModRM encodings are defined to be reserved, and use
9483 of these encodings risks incompatibility with future processors.
9485 See also \c{SFENCE} (\k{insSFENCE}) and \c{MFENCE} (\k{insMFENCE}).
9488 \S{insLGDT} \i\c{LGDT}, \i\c{LIDT}, \i\c{LLDT}: Load Descriptor Tables
9490 \c LGDT mem ; 0F 01 /2 [286,PRIV]
9491 \c LIDT mem ; 0F 01 /3 [286,PRIV]
9492 \c LLDT r/m16 ; 0F 00 /2 [286,PRIV]
9494 \c{LGDT} and \c{LIDT} both take a 6-byte memory area as an operand:
9495 they load a 32-bit linear address and a 16-bit size limit from that
9496 area (in the opposite order) into the \c{GDTR} (global descriptor table
9497 register) or \c{IDTR} (interrupt descriptor table register). These are
9498 the only instructions which directly use \e{linear} addresses, rather
9499 than segment/offset pairs.
9501 \c{LLDT} takes a segment selector as an operand. The processor looks
9502 up that selector in the GDT and stores the limit and base address
9503 given there into the \c{LDTR} (local descriptor table register).
9505 See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}).
9508 \S{insLMSW} \i\c{LMSW}: Load/Store Machine Status Word
9510 \c LMSW r/m16 ; 0F 01 /6 [286,PRIV]
9512 \c{LMSW} loads the bottom four bits of the source operand into the
9513 bottom four bits of the \c{CR0} control register (or the Machine
9514 Status Word, on 286 processors). See also \c{SMSW} (\k{insSMSW}).
9517 \S{insLOADALL} \i\c{LOADALL}, \i\c{LOADALL286}: Load Processor State
9519 \c LOADALL ; 0F 07 [386,UNDOC]
9520 \c LOADALL286 ; 0F 05 [286,UNDOC]
9522 This instruction, in its two different-opcode forms, is apparently
9523 supported on most 286 processors, some 386 and possibly some 486.
9524 The opcode differs between the 286 and the 386.
9526 The function of the instruction is to load all information relating
9527 to the state of the processor out of a block of memory: on the 286,
9528 this block is located implicitly at absolute address \c{0x800}, and
9529 on the 386 and 486 it is at \c{[ES:EDI]}.
9532 \S{insLODSB} \i\c{LODSB}, \i\c{LODSW}, \i\c{LODSD}: Load from String
9534 \c LODSB ; AC [8086]
9535 \c LODSW ; o16 AD [8086]
9536 \c LODSD ; o32 AD [386]
9538 \c{LODSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} into \c{AL}.
9539 It then increments or decrements (depending on the direction flag:
9540 increments if the flag is clear, decrements if it is set) \c{SI} or
9543 The register used is \c{SI} if the address size is 16 bits, and
9544 \c{ESI} if it is 32 bits. If you need to use an address size not
9545 equal to the current \c{BITS} setting, you can use an explicit
9546 \i\c{a16} or \i\c{a32} prefix.
9548 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
9549 overridden by using a segment register name as a prefix (for
9550 example, \c{ES LODSB}).
9552 \c{LODSW} and \c{LODSD} work in the same way, but they load a
9553 word or a doubleword instead of a byte, and increment or decrement
9554 the addressing registers by 2 or 4 instead of 1.
9557 \S{insLOOP} \i\c{LOOP}, \i\c{LOOPE}, \i\c{LOOPZ}, \i\c{LOOPNE}, \i\c{LOOPNZ}: Loop with Counter
9559 \c LOOP imm ; E2 rb [8086]
9560 \c LOOP imm,CX ; a16 E2 rb [8086]
9561 \c LOOP imm,ECX ; a32 E2 rb [386]
9563 \c LOOPE imm ; E1 rb [8086]
9564 \c LOOPE imm,CX ; a16 E1 rb [8086]
9565 \c LOOPE imm,ECX ; a32 E1 rb [386]
9566 \c LOOPZ imm ; E1 rb [8086]
9567 \c LOOPZ imm,CX ; a16 E1 rb [8086]
9568 \c LOOPZ imm,ECX ; a32 E1 rb [386]
9570 \c LOOPNE imm ; E0 rb [8086]
9571 \c LOOPNE imm,CX ; a16 E0 rb [8086]
9572 \c LOOPNE imm,ECX ; a32 E0 rb [386]
9573 \c LOOPNZ imm ; E0 rb [8086]
9574 \c LOOPNZ imm,CX ; a16 E0 rb [8086]
9575 \c LOOPNZ imm,ECX ; a32 E0 rb [386]
9577 \c{LOOP} decrements its counter register (either \c{CX} or \c{ECX} -
9578 if one is not specified explicitly, the \c{BITS} setting dictates
9579 which is used) by one, and if the counter does not become zero as a
9580 result of this operation, it jumps to the given label. The jump has
9581 a range of 128 bytes.
9583 \c{LOOPE} (or its synonym \c{LOOPZ}) adds the additional condition
9584 that it only jumps if the counter is nonzero \e{and} the zero flag
9585 is set. Similarly, \c{LOOPNE} (and \c{LOOPNZ}) jumps only if the
9586 counter is nonzero and the zero flag is clear.
9589 \S{insLSL} \i\c{LSL}: Load Segment Limit
9591 \c LSL reg16,r/m16 ; o16 0F 03 /r [286,PRIV]
9592 \c LSL reg32,r/m32 ; o32 0F 03 /r [286,PRIV]
9594 \c{LSL} is given a segment selector in its source (second) operand;
9595 it computes the segment limit value by loading the segment limit
9596 field from the associated segment descriptor in the \c{GDT} or \c{LDT}.
9597 (This involves shifting left by 12 bits if the segment limit is
9598 page-granular, and not if it is byte-granular; so you end up with a
9599 byte limit in either case.) The segment limit obtained is then
9600 loaded into the destination (first) operand.
9603 \S{insLTR} \i\c{LTR}: Load Task Register
9605 \c LTR r/m16 ; 0F 00 /3 [286,PRIV]
9607 \c{LTR} looks up the segment base and limit in the GDT or LDT
9608 descriptor specified by the segment selector given as its operand,
9609 and loads them into the Task Register.
9612 \S{insMASKMOVDQU} \i\c{MASKMOVDQU}: Byte Mask Write
9614 \c MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2]
9616 \c{MASKMOVDQU} stores data from xmm1 to the location specified by
9617 \c{ES:(E)DI}. The size of the store depends on the address-size
9618 attribute. The most significant bit in each byte of the mask
9619 register xmm2 is used to selectively write the data (0 = no write,
9620 1 = write) on a per-byte basis.
9623 \S{insMASKMOVQ} \i\c{MASKMOVQ}: Byte Mask Write
9625 \c MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX]
9627 \c{MASKMOVQ} stores data from mm1 to the location specified by
9628 \c{ES:(E)DI}. The size of the store depends on the address-size
9629 attribute. The most significant bit in each byte of the mask
9630 register mm2 is used to selectively write the data (0 = no write,
9631 1 = write) on a per-byte basis.
9634 \S{insMAXPD} \i\c{MAXPD}: Return Packed Double-Precision FP Maximum
9636 \c MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2]
9638 \c{MAXPD} performs a SIMD compare of the packed double-precision
9639 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9640 of each pair of values in xmm1. If the values being compared are
9641 both zeroes, source2 (xmm2/m128) would be returned. If source2
9642 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9643 destination (i.e., a QNaN version of the SNaN is not returned).
9646 \S{insMAXPS} \i\c{MAXPS}: Return Packed Single-Precision FP Maximum
9648 \c MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE]
9650 \c{MAXPS} performs a SIMD compare of the packed single-precision
9651 FP numbers from xmm1 and xmm2/mem, and stores the maximum values
9652 of each pair of values in xmm1. If the values being compared are
9653 both zeroes, source2 (xmm2/m128) would be returned. If source2
9654 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9655 destination (i.e., a QNaN version of the SNaN is not returned).
9658 \S{insMAXSD} \i\c{MAXSD}: Return Scalar Double-Precision FP Maximum
9660 \c MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2]
9662 \c{MAXSD} compares the low-order double-precision FP numbers from
9663 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9664 values being compared are both zeroes, source2 (xmm2/m64) would
9665 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9666 forwarded unchanged to the destination (i.e., a QNaN version of
9667 the SNaN is not returned). The high quadword of the destination
9671 \S{insMAXSS} \i\c{MAXSS}: Return Scalar Single-Precision FP Maximum
9673 \c MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE]
9675 \c{MAXSS} compares the low-order single-precision FP numbers from
9676 xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the
9677 values being compared are both zeroes, source2 (xmm2/m32) would
9678 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9679 forwarded unchanged to the destination (i.e., a QNaN version of
9680 the SNaN is not returned). The high three doublewords of the
9681 destination are left unchanged.
9684 \S{insMFENCE} \i\c{MFENCE}: Memory Fence
9686 \c MFENCE ; 0F AE /6 [WILLAMETTE,SSE2]
9688 \c{MFENCE} performs a serialising operation on all loads from memory
9689 and writes to memory that were issued before the \c{MFENCE} instruction.
9690 This guarantees that all memory reads and writes before the \c{MFENCE}
9691 instruction are completed before any reads and writes after the
9692 \c{MFENCE} instruction.
9694 \c{MFENCE} is ordered respective to other \c{MFENCE} instructions,
9695 \c{LFENCE}, \c{SFENCE}, any memory read and any other serialising
9696 instruction (such as \c{CPUID}).
9698 Weakly ordered memory types can be used to achieve higher processor
9699 performance through such techniques as out-of-order issue, speculative
9700 reads, write-combining, and write-collapsing. The degree to which a
9701 consumer of data recognizes or knows that the data is weakly ordered
9702 varies among applications and may be unknown to the producer of this
9703 data. The \c{MFENCE} instruction provides a performance-efficient way
9704 of ensuring load and store ordering between routines that produce
9705 weakly-ordered results and routines that consume that data.
9707 \c{MFENCE} uses the following ModRM encoding:
9710 \c Reg/Opcode (5:3) = 110B
9713 All other ModRM encodings are defined to be reserved, and use
9714 of these encodings risks incompatibility with future processors.
9716 See also \c{LFENCE} (\k{insLFENCE}) and \c{SFENCE} (\k{insSFENCE}).
9719 \S{insMINPD} \i\c{MINPD}: Return Packed Double-Precision FP Minimum
9721 \c MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2]
9723 \c{MINPD} performs a SIMD compare of the packed double-precision
9724 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9725 of each pair of values in xmm1. If the values being compared are
9726 both zeroes, source2 (xmm2/m128) would be returned. If source2
9727 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9728 destination (i.e., a QNaN version of the SNaN is not returned).
9731 \S{insMINPS} \i\c{MINPS}: Return Packed Single-Precision FP Minimum
9733 \c MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE]
9735 \c{MINPS} performs a SIMD compare of the packed single-precision
9736 FP numbers from xmm1 and xmm2/mem, and stores the minimum values
9737 of each pair of values in xmm1. If the values being compared are
9738 both zeroes, source2 (xmm2/m128) would be returned. If source2
9739 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the
9740 destination (i.e., a QNaN version of the SNaN is not returned).
9743 \S{insMINSD} \i\c{MINSD}: Return Scalar Double-Precision FP Minimum
9745 \c MINSD xmm1,xmm2/m64 ; F2 0F 5D /r [WILLAMETTE,SSE2]
9747 \c{MINSD} compares the low-order double-precision FP numbers from
9748 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9749 values being compared are both zeroes, source2 (xmm2/m64) would
9750 be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is
9751 forwarded unchanged to the destination (i.e., a QNaN version of
9752 the SNaN is not returned). The high quadword of the destination
9756 \S{insMINSS} \i\c{MINSS}: Return Scalar Single-Precision FP Minimum
9758 \c MINSS xmm1,xmm2/m32 ; F3 0F 5D /r [KATMAI,SSE]
9760 \c{MINSS} compares the low-order single-precision FP numbers from
9761 xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the
9762 values being compared are both zeroes, source2 (xmm2/m32) would
9763 be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is
9764 forwarded unchanged to the destination (i.e., a QNaN version of
9765 the SNaN is not returned). The high three doublewords of the
9766 destination are left unchanged.
9769 \S{insMOV} \i\c{MOV}: Move Data
9771 \c MOV r/m8,reg8 ; 88 /r [8086]
9772 \c MOV r/m16,reg16 ; o16 89 /r [8086]
9773 \c MOV r/m32,reg32 ; o32 89 /r [386]
9774 \c MOV reg8,r/m8 ; 8A /r [8086]
9775 \c MOV reg16,r/m16 ; o16 8B /r [8086]
9776 \c MOV reg32,r/m32 ; o32 8B /r [386]
9778 \c MOV reg8,imm8 ; B0+r ib [8086]
9779 \c MOV reg16,imm16 ; o16 B8+r iw [8086]
9780 \c MOV reg32,imm32 ; o32 B8+r id [386]
9781 \c MOV r/m8,imm8 ; C6 /0 ib [8086]
9782 \c MOV r/m16,imm16 ; o16 C7 /0 iw [8086]
9783 \c MOV r/m32,imm32 ; o32 C7 /0 id [386]
9785 \c MOV AL,memoffs8 ; A0 ow/od [8086]
9786 \c MOV AX,memoffs16 ; o16 A1 ow/od [8086]
9787 \c MOV EAX,memoffs32 ; o32 A1 ow/od [386]
9788 \c MOV memoffs8,AL ; A2 ow/od [8086]
9789 \c MOV memoffs16,AX ; o16 A3 ow/od [8086]
9790 \c MOV memoffs32,EAX ; o32 A3 ow/od [386]
9792 \c MOV r/m16,segreg ; o16 8C /r [8086]
9793 \c MOV r/m32,segreg ; o32 8C /r [386]
9794 \c MOV segreg,r/m16 ; o16 8E /r [8086]
9795 \c MOV segreg,r/m32 ; o32 8E /r [386]
9797 \c MOV reg32,CR0/2/3/4 ; 0F 20 /r [386]
9798 \c MOV reg32,DR0/1/2/3/6/7 ; 0F 21 /r [386]
9799 \c MOV reg32,TR3/4/5/6/7 ; 0F 24 /r [386]
9800 \c MOV CR0/2/3/4,reg32 ; 0F 22 /r [386]
9801 \c MOV DR0/1/2/3/6/7,reg32 ; 0F 23 /r [386]
9802 \c MOV TR3/4/5/6/7,reg32 ; 0F 26 /r [386]
9804 \c{MOV} copies the contents of its source (second) operand into its
9805 destination (first) operand.
9807 In all forms of the \c{MOV} instruction, the two operands are the
9808 same size, except for moving between a segment register and an
9809 \c{r/m32} operand. These instructions are treated exactly like the
9810 corresponding 16-bit equivalent (so that, for example, \c{MOV
9811 DS,EAX} functions identically to \c{MOV DS,AX} but saves a prefix
9812 when in 32-bit mode), except that when a segment register is moved
9813 into a 32-bit destination, the top two bytes of the result are
9816 \c{MOV} may not use \c{CS} as a destination.
9818 \c{CR4} is only a supported register on the Pentium and above.
9820 Test registers are supported on 386/486 processors and on some
9821 non-Intel Pentium class processors.
9824 \S{insMOVAPD} \i\c{MOVAPD}: Move Aligned Packed Double-Precision FP Values
9826 \c MOVAPD xmm1,xmm2/mem128 ; 66 0F 28 /r [WILLAMETTE,SSE2]
9827 \c MOVAPD xmm1/mem128,xmm2 ; 66 0F 29 /r [WILLAMETTE,SSE2]
9829 \c{MOVAPD} moves a double quadword containing 2 packed double-precision
9830 FP values from the source operand to the destination. When the source
9831 or destination operand is a memory location, it must be aligned on a
9834 To move data in and out of memory locations that are not known to be on
9835 16-byte boundaries, use the \c{MOVUPD} instruction (\k{insMOVUPD}).
9838 \S{insMOVAPS} \i\c{MOVAPS}: Move Aligned Packed Single-Precision FP Values
9840 \c MOVAPS xmm1,xmm2/mem128 ; 0F 28 /r [KATMAI,SSE]
9841 \c MOVAPS xmm1/mem128,xmm2 ; 0F 29 /r [KATMAI,SSE]
9843 \c{MOVAPS} moves a double quadword containing 4 packed single-precision
9844 FP values from the source operand to the destination. When the source
9845 or destination operand is a memory location, it must be aligned on a
9848 To move data in and out of memory locations that are not known to be on
9849 16-byte boundaries, use the \c{MOVUPS} instruction (\k{insMOVUPS}).
9852 \S{insMOVD} \i\c{MOVD}: Move Doubleword to/from MMX Register
9854 \c MOVD mm,r/m32 ; 0F 6E /r [PENT,MMX]
9855 \c MOVD r/m32,mm ; 0F 7E /r [PENT,MMX]
9856 \c MOVD xmm,r/m32 ; 66 0F 6E /r [WILLAMETTE,SSE2]
9857 \c MOVD r/m32,xmm ; 66 0F 7E /r [WILLAMETTE,SSE2]
9859 \c{MOVD} copies 32 bits from its source (second) operand into its
9860 destination (first) operand. When the destination is a 64-bit \c{MMX}
9861 register or a 128-bit \c{XMM} register, the input value is zero-extended
9862 to fill the destination register.
9865 \S{insMOVDQ2Q} \i\c{MOVDQ2Q}: Move Quadword from XMM to MMX register.
9867 \c MOVDQ2Q mm,xmm ; F2 OF D6 /r [WILLAMETTE,SSE2]
9869 \c{MOVDQ2Q} moves the low quadword from the source operand to the
9870 destination operand.
9873 \S{insMOVDQA} \i\c{MOVDQA}: Move Aligned Double Quadword
9875 \c MOVDQA xmm1,xmm2/m128 ; 66 OF 6F /r [WILLAMETTE,SSE2]
9876 \c MOVDQA xmm1/m128,xmm2 ; 66 OF 7F /r [WILLAMETTE,SSE2]
9878 \c{MOVDQA} moves a double quadword from the source operand to the
9879 destination operand. When the source or destination operand is a
9880 memory location, it must be aligned to a 16-byte boundary.
9882 To move a double quadword to or from unaligned memory locations,
9883 use the \c{MOVDQU} instruction (\k{insMOVDQU}).
9886 \S{insMOVDQU} \i\c{MOVDQU}: Move Unaligned Double Quadword
9888 \c MOVDQU xmm1,xmm2/m128 ; F3 OF 6F /r [WILLAMETTE,SSE2]
9889 \c MOVDQU xmm1/m128,xmm2 ; F3 OF 7F /r [WILLAMETTE,SSE2]
9891 \c{MOVDQU} moves a double quadword from the source operand to the
9892 destination operand. When the source or destination operand is a
9893 memory location, the memory may be unaligned.
9895 To move a double quadword to or from known aligned memory locations,
9896 use the \c{MOVDQA} instruction (\k{insMOVDQA}).
9899 \S{insMOVHLPS} \i\c{MOVHLPS}: Move Packed Single-Precision FP High to Low
9901 \c MOVHLPS xmm1,xmm2 ; OF 12 /r [KATMAI,SSE]
9903 \c{MOVHLPS} moves the two packed single-precision FP values from the
9904 high quadword of the source register xmm2 to the low quadword of the
9905 destination register, xmm2. The upper quadword of xmm1 is left unchanged.
9907 The operation of this instruction is:
9909 \c dst[0-63] := src[64-127],
9910 \c dst[64-127] remains unchanged.
9913 \S{insMOVHPD} \i\c{MOVHPD}: Move High Packed Double-Precision FP
9915 \c MOVHPD xmm,m64 ; 66 OF 16 /r [WILLAMETTE,SSE2]
9916 \c MOVHPD m64,xmm ; 66 OF 17 /r [WILLAMETTE,SSE2]
9918 \c{MOVHPD} moves a double-precision FP value between the source and
9919 destination operands. One of the operands is a 64-bit memory location,
9920 the other is the high quadword of an \c{XMM} register.
9922 The operation of this instruction is:
9924 \c mem[0-63] := xmm[64-127];
9928 \c xmm[0-63] remains unchanged;
9929 \c xmm[64-127] := mem[0-63].
9932 \S{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-Precision FP
9934 \c MOVHPS xmm,m64 ; 0F 16 /r [KATMAI,SSE]
9935 \c MOVHPS m64,xmm ; 0F 17 /r [KATMAI,SSE]
9937 \c{MOVHPS} moves two packed single-precision FP values between the source
9938 and destination operands. One of the operands is a 64-bit memory location,
9939 the other is the high quadword of an \c{XMM} register.
9941 The operation of this instruction is:
9943 \c mem[0-63] := xmm[64-127];
9947 \c xmm[0-63] remains unchanged;
9948 \c xmm[64-127] := mem[0-63].
9951 \S{insMOVLHPS} \i\c{MOVLHPS}: Move Packed Single-Precision FP Low to High
9953 \c MOVLHPS xmm1,xmm2 ; OF 16 /r [KATMAI,SSE]
9955 \c{MOVLHPS} moves the two packed single-precision FP values from the
9956 low quadword of the source register xmm2 to the high quadword of the
9957 destination register, xmm2. The low quadword of xmm1 is left unchanged.
9959 The operation of this instruction is:
9961 \c dst[0-63] remains unchanged;
9962 \c dst[64-127] := src[0-63].
9964 \S{insMOVLPD} \i\c{MOVLPD}: Move Low Packed Double-Precision FP
9966 \c MOVLPD xmm,m64 ; 66 OF 12 /r [WILLAMETTE,SSE2]
9967 \c MOVLPD m64,xmm ; 66 OF 13 /r [WILLAMETTE,SSE2]
9969 \c{MOVLPD} moves a double-precision FP value between the source and
9970 destination operands. One of the operands is a 64-bit memory location,
9971 the other is the low quadword of an \c{XMM} register.
9973 The operation of this instruction is:
9975 \c mem(0-63) := xmm(0-63);
9979 \c xmm(0-63) := mem(0-63);
9980 \c xmm(64-127) remains unchanged.
9982 \S{insMOVLPS} \i\c{MOVLPS}: Move Low Packed Single-Precision FP
9984 \c MOVLPS xmm,m64 ; OF 12 /r [KATMAI,SSE]
9985 \c MOVLPS m64,xmm ; OF 13 /r [KATMAI,SSE]
9987 \c{MOVLPS} moves two packed single-precision FP values between the source
9988 and destination operands. One of the operands is a 64-bit memory location,
9989 the other is the low quadword of an \c{XMM} register.
9991 The operation of this instruction is:
9993 \c mem(0-63) := xmm(0-63);
9997 \c xmm(0-63) := mem(0-63);
9998 \c xmm(64-127) remains unchanged.
10001 \S{insMOVMSKPD} \i\c{MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask
10003 \c MOVMSKPD reg32,xmm ; 66 0F 50 /r [WILLAMETTE,SSE2]
10005 \c{MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant
10006 bits of each double-precision FP number of the source operand.
10009 \S{insMOVMSKPS} \i\c{MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask
10011 \c MOVMSKPS reg32,xmm ; 0F 50 /r [KATMAI,SSE]
10013 \c{MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant
10014 bits of each single-precision FP number of the source operand.
10017 \S{insMOVNTDQ} \i\c{MOVNTDQ}: Move Double Quadword Non Temporal
10019 \c MOVNTDQ m128,xmm ; 66 0F E7 /r [WILLAMETTE,SSE2]
10021 \c{MOVNTDQ} moves the double quadword from the \c{XMM} source
10022 register to the destination memory location, using a non-temporal
10023 hint. This store instruction minimizes cache pollution.
10026 \S{insMOVNTI} \i\c{MOVNTI}: Move Doubleword Non Temporal
10028 \c MOVNTI m32,reg32 ; 0F C3 /r [WILLAMETTE,SSE2]
10030 \c{MOVNTI} moves the doubleword in the source register
10031 to the destination memory location, using a non-temporal
10032 hint. This store instruction minimizes cache pollution.
10035 \S{insMOVNTPD} \i\c{MOVNTPD}: Move Aligned Four Packed Single-Precision
10036 FP Values Non Temporal
10038 \c MOVNTPD m128,xmm ; 66 0F 2B /r [WILLAMETTE,SSE2]
10040 \c{MOVNTPD} moves the double quadword from the \c{XMM} source
10041 register to the destination memory location, using a non-temporal
10042 hint. This store instruction minimizes cache pollution. The memory
10043 location must be aligned to a 16-byte boundary.
10046 \S{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-Precision
10047 FP Values Non Temporal
10049 \c MOVNTPS m128,xmm ; 0F 2B /r [KATMAI,SSE]
10051 \c{MOVNTPS} moves the double quadword from the \c{XMM} source
10052 register to the destination memory location, using a non-temporal
10053 hint. This store instruction minimizes cache pollution. The memory
10054 location must be aligned to a 16-byte boundary.
10057 \S{insMOVNTQ} \i\c{MOVNTQ}: Move Quadword Non Temporal
10059 \c MOVNTQ m64,mm ; 0F E7 /r [KATMAI,MMX]
10061 \c{MOVNTQ} moves the quadword in the \c{MMX} source register
10062 to the destination memory location, using a non-temporal
10063 hint. This store instruction minimizes cache pollution.
10066 \S{insMOVQ} \i\c{MOVQ}: Move Quadword to/from MMX Register
10068 \c MOVQ mm1,mm2/m64 ; 0F 6F /r [PENT,MMX]
10069 \c MOVQ mm1/m64,mm2 ; 0F 7F /r [PENT,MMX]
10071 \c MOVQ xmm1,xmm2/m64 ; F3 0F 7E /r [WILLAMETTE,SSE2]
10072 \c MOVQ xmm1/m64,xmm2 ; 66 0F D6 /r [WILLAMETTE,SSE2]
10074 \c{MOVQ} copies 64 bits from its source (second) operand into its
10075 destination (first) operand. When the source is an \c{XMM} register,
10076 the low quadword is moved. When the destination is an \c{XMM} register,
10077 the destination is the low quadword, and the high quadword is cleared.
10080 \S{insMOVQ2DQ} \i\c{MOVQ2DQ}: Move Quadword from MMX to XMM register.
10082 \c MOVQ2DQ xmm,mm ; F3 OF D6 /r [WILLAMETTE,SSE2]
10084 \c{MOVQ2DQ} moves the quadword from the source operand to the low
10085 quadword of the destination operand, and clears the high quadword.
10088 \S{insMOVSB} \i\c{MOVSB}, \i\c{MOVSW}, \i\c{MOVSD}: Move String
10090 \c MOVSB ; A4 [8086]
10091 \c MOVSW ; o16 A5 [8086]
10092 \c MOVSD ; o32 A5 [386]
10094 \c{MOVSB} copies the byte at \c{[DS:SI]} or \c{[DS:ESI]} to
10095 \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or decrements
10096 (depending on the direction flag: increments if the flag is clear,
10097 decrements if it is set) \c{SI} and \c{DI} (or \c{ESI} and \c{EDI}).
10099 The registers used are \c{SI} and \c{DI} if the address size is 16
10100 bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
10101 an address size not equal to the current \c{BITS} setting, you can
10102 use an explicit \i\c{a16} or \i\c{a32} prefix.
10104 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
10105 overridden by using a segment register name as a prefix (for
10106 example, \c{es movsb}). The use of \c{ES} for the store to \c{[DI]}
10107 or \c{[EDI]} cannot be overridden.
10109 \c{MOVSW} and \c{MOVSD} work in the same way, but they copy a word
10110 or a doubleword instead of a byte, and increment or decrement the
10111 addressing registers by 2 or 4 instead of 1.
10113 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
10114 \c{ECX} - again, the address size chooses which) times.
10117 \S{insMOVSD} \i\c{MOVSD}: Move Scalar Double-Precision FP Value
10119 \c MOVSD xmm1,xmm2/m64 ; F2 0F 10 /r [WILLAMETTE,SSE2]
10120 \c MOVSD xmm1/m64,xmm2 ; F2 0F 11 /r [WILLAMETTE,SSE2]
10122 \c{MOVSD} moves a double-precision FP value from the source operand
10123 to the destination operand. When the source or destination is a
10124 register, the low-order FP value is read or written.
10127 \S{insMOVSS} \i\c{MOVSS}: Move Scalar Single-Precision FP Value
10129 \c MOVSS xmm1,xmm2/m32 ; F3 0F 10 /r [KATMAI,SSE]
10130 \c MOVSS xmm1/m32,xmm2 ; F3 0F 11 /r [KATMAI,SSE]
10132 \c{MOVSS} moves a single-precision FP value from the source operand
10133 to the destination operand. When the source or destination is a
10134 register, the low-order FP value is read or written.
10137 \S{insMOVSX} \i\c{MOVSX}, \i\c{MOVZX}: Move Data with Sign or Zero Extend
10139 \c MOVSX reg16,r/m8 ; o16 0F BE /r [386]
10140 \c MOVSX reg32,r/m8 ; o32 0F BE /r [386]
10141 \c MOVSX reg32,r/m16 ; o32 0F BF /r [386]
10143 \c MOVZX reg16,r/m8 ; o16 0F B6 /r [386]
10144 \c MOVZX reg32,r/m8 ; o32 0F B6 /r [386]
10145 \c MOVZX reg32,r/m16 ; o32 0F B7 /r [386]
10147 \c{MOVSX} sign-extends its source (second) operand to the length of
10148 its destination (first) operand, and copies the result into the
10149 destination operand. \c{MOVZX} does the same, but zero-extends
10150 rather than sign-extending.
10153 \S{insMOVUPD} \i\c{MOVUPD}: Move Unaligned Packed Double-Precision FP Values
10155 \c MOVUPD xmm1,xmm2/mem128 ; 66 0F 10 /r [WILLAMETTE,SSE2]
10156 \c MOVUPD xmm1/mem128,xmm2 ; 66 0F 11 /r [WILLAMETTE,SSE2]
10158 \c{MOVUPD} moves a double quadword containing 2 packed double-precision
10159 FP values from the source operand to the destination. This instruction
10160 makes no assumptions about alignment of memory operands.
10162 To move data in and out of memory locations that are known to be on 16-byte
10163 boundaries, use the \c{MOVAPD} instruction (\k{insMOVAPD}).
10166 \S{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Packed Single-Precision FP Values
10168 \c MOVUPS xmm1,xmm2/mem128 ; 0F 10 /r [KATMAI,SSE]
10169 \c MOVUPS xmm1/mem128,xmm2 ; 0F 11 /r [KATMAI,SSE]
10171 \c{MOVUPS} moves a double quadword containing 4 packed single-precision
10172 FP values from the source operand to the destination. This instruction
10173 makes no assumptions about alignment of memory operands.
10175 To move data in and out of memory locations that are known to be on 16-byte
10176 boundaries, use the \c{MOVAPS} instruction (\k{insMOVAPS}).
10179 \S{insMUL} \i\c{MUL}: Unsigned Integer Multiply
10181 \c MUL r/m8 ; F6 /4 [8086]
10182 \c MUL r/m16 ; o16 F7 /4 [8086]
10183 \c MUL r/m32 ; o32 F7 /4 [386]
10185 \c{MUL} performs unsigned integer multiplication. The other operand
10186 to the multiplication, and the destination operand, are implicit, in
10189 \b For \c{MUL r/m8}, \c{AL} is multiplied by the given operand; the
10190 product is stored in \c{AX}.
10192 \b For \c{MUL r/m16}, \c{AX} is multiplied by the given operand;
10193 the product is stored in \c{DX:AX}.
10195 \b For \c{MUL r/m32}, \c{EAX} is multiplied by the given operand;
10196 the product is stored in \c{EDX:EAX}.
10198 Signed integer multiplication is performed by the \c{IMUL}
10199 instruction: see \k{insIMUL}.
10202 \S{insMULPD} \i\c{MULPD}: Packed Single-FP Multiply
10204 \c MULPD xmm1,xmm2/mem128 ; 66 0F 59 /r [WILLAMETTE,SSE2]
10206 \c{MULPD} performs a SIMD multiply of the packed double-precision FP
10207 values in both operands, and stores the results in the destination register.
10210 \S{insMULPS} \i\c{MULPS}: Packed Single-FP Multiply
10212 \c MULPS xmm1,xmm2/mem128 ; 0F 59 /r [KATMAI,SSE]
10214 \c{MULPS} performs a SIMD multiply of the packed single-precision FP
10215 values in both operands, and stores the results in the destination register.
10218 \S{insMULSD} \i\c{MULSD}: Scalar Single-FP Multiply
10220 \c MULSD xmm1,xmm2/mem32 ; F2 0F 59 /r [WILLAMETTE,SSE2]
10222 \c{MULSD} multiplies the lowest double-precision FP values of both
10223 operands, and stores the result in the low quadword of xmm1.
10226 \S{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply
10228 \c MULSS xmm1,xmm2/mem32 ; F3 0F 59 /r [KATMAI,SSE]
10230 \c{MULSS} multiplies the lowest single-precision FP values of both
10231 operands, and stores the result in the low doubleword of xmm1.
10234 \S{insNEG} \i\c{NEG}, \i\c{NOT}: Two's and One's Complement
10236 \c NEG r/m8 ; F6 /3 [8086]
10237 \c NEG r/m16 ; o16 F7 /3 [8086]
10238 \c NEG r/m32 ; o32 F7 /3 [386]
10240 \c NOT r/m8 ; F6 /2 [8086]
10241 \c NOT r/m16 ; o16 F7 /2 [8086]
10242 \c NOT r/m32 ; o32 F7 /2 [386]
10244 \c{NEG} replaces the contents of its operand by the two's complement
10245 negation (invert all the bits and then add one) of the original
10246 value. \c{NOT}, similarly, performs one's complement (inverts all
10250 \S{insNOP} \i\c{NOP}: No Operation
10254 \c{NOP} performs no operation. Its opcode is the same as that
10255 generated by \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the
10256 processor mode; see \k{insXCHG}).
10259 \S{insOR} \i\c{OR}: Bitwise OR
10261 \c OR r/m8,reg8 ; 08 /r [8086]
10262 \c OR r/m16,reg16 ; o16 09 /r [8086]
10263 \c OR r/m32,reg32 ; o32 09 /r [386]
10265 \c OR reg8,r/m8 ; 0A /r [8086]
10266 \c OR reg16,r/m16 ; o16 0B /r [8086]
10267 \c OR reg32,r/m32 ; o32 0B /r [386]
10269 \c OR r/m8,imm8 ; 80 /1 ib [8086]
10270 \c OR r/m16,imm16 ; o16 81 /1 iw [8086]
10271 \c OR r/m32,imm32 ; o32 81 /1 id [386]
10273 \c OR r/m16,imm8 ; o16 83 /1 ib [8086]
10274 \c OR r/m32,imm8 ; o32 83 /1 ib [386]
10276 \c OR AL,imm8 ; 0C ib [8086]
10277 \c OR AX,imm16 ; o16 0D iw [8086]
10278 \c OR EAX,imm32 ; o32 0D id [386]
10280 \c{OR} performs a bitwise OR operation between its two operands
10281 (i.e. each bit of the result is 1 if and only if at least one of the
10282 corresponding bits of the two inputs was 1), and stores the result
10283 in the destination (first) operand.
10285 In the forms with an 8-bit immediate second operand and a longer
10286 first operand, the second operand is considered to be signed, and is
10287 sign-extended to the length of the first operand. In these cases,
10288 the \c{BYTE} qualifier is necessary to force NASM to generate this
10289 form of the instruction.
10291 The MMX instruction \c{POR} (see \k{insPOR}) performs the same
10292 operation on the 64-bit MMX registers.
10295 \S{insORPD} \i\c{ORPD}: Bit-wise Logical OR of Double-Precision FP Data
10297 \c ORPD xmm1,xmm2/m128 ; 66 0F 56 /r [WILLAMETTE,SSE2]
10299 \c{ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem,
10300 and stores the result in xmm1. If the source operand is a memory
10301 location, it must be aligned to a 16-byte boundary.
10304 \S{insORPS} \i\c{ORPS}: Bit-wise Logical OR of Single-Precision FP Data
10306 \c ORPS xmm1,xmm2/m128 ; 0F 56 /r [KATMAI,SSE]
10308 \c{ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem,
10309 and stores the result in xmm1. If the source operand is a memory
10310 location, it must be aligned to a 16-byte boundary.
10313 \S{insOUT} \i\c{OUT}: Output Data to I/O Port
10315 \c OUT imm8,AL ; E6 ib [8086]
10316 \c OUT imm8,AX ; o16 E7 ib [8086]
10317 \c OUT imm8,EAX ; o32 E7 ib [386]
10318 \c OUT DX,AL ; EE [8086]
10319 \c OUT DX,AX ; o16 EF [8086]
10320 \c OUT DX,EAX ; o32 EF [386]
10322 \c{OUT} writes the contents of the given source register to the
10323 specified I/O port. The port number may be specified as an immediate
10324 value if it is between 0 and 255, and otherwise must be stored in
10325 \c{DX}. See also \c{IN} (\k{insIN}).
10328 \S{insOUTSB} \i\c{OUTSB}, \i\c{OUTSW}, \i\c{OUTSD}: Output String to I/O Port
10330 \c OUTSB ; 6E [186]
10331 \c OUTSW ; o16 6F [186]
10332 \c OUTSD ; o32 6F [386]
10334 \c{OUTSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} and writes
10335 it to the I/O port specified in \c{DX}. It then increments or
10336 decrements (depending on the direction flag: increments if the flag
10337 is clear, decrements if it is set) \c{SI} or \c{ESI}.
10339 The register used is \c{SI} if the address size is 16 bits, and
10340 \c{ESI} if it is 32 bits. If you need to use an address size not
10341 equal to the current \c{BITS} setting, you can use an explicit
10342 \i\c{a16} or \i\c{a32} prefix.
10344 The segment register used to load from \c{[SI]} or \c{[ESI]} can be
10345 overridden by using a segment register name as a prefix (for
10346 example, \c{es outsb}).
10348 \c{OUTSW} and \c{OUTSD} work in the same way, but they output a
10349 word or a doubleword instead of a byte, and increment or decrement
10350 the addressing registers by 2 or 4 instead of 1.
10352 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
10353 \c{ECX} - again, the address size chooses which) times.
10356 \S{insPACKSSDW} \i\c{PACKSSDW}, \i\c{PACKSSWB}, \i\c{PACKUSWB}: Pack Data
10358 \c PACKSSDW mm1,mm2/m64 ; 0F 6B /r [PENT,MMX]
10359 \c PACKSSWB mm1,mm2/m64 ; 0F 63 /r [PENT,MMX]
10360 \c PACKUSWB mm1,mm2/m64 ; 0F 67 /r [PENT,MMX]
10362 \c PACKSSDW xmm1,xmm2/m128 ; 66 0F 6B /r [WILLAMETTE,SSE2]
10363 \c PACKSSWB xmm1,xmm2/m128 ; 66 0F 63 /r [WILLAMETTE,SSE2]
10364 \c PACKUSWB xmm1,xmm2/m128 ; 66 0F 67 /r [WILLAMETTE,SSE2]
10366 All these instructions start by combining the source and destination
10367 operands, and then splitting the result in smaller sections which it
10368 then packs into the destination register. The \c{MMX} versions pack
10369 two 64-bit operands into one 64-bit register, while the \c{SSE}
10370 versions pack two 128-bit operands into one 128-bit register.
10372 \b \c{PACKSSWB} splits the combined value into words, and then reduces
10373 the words to bytes, using signed saturation. It then packs the bytes
10374 into the destination register in the same order the words were in.
10376 \b \c{PACKSSDW} performs the same operation as \c{PACKSSWB}, except that
10377 it reduces doublewords to words, then packs them into the destination
10380 \b \c{PACKUSWB} performs the same operation as \c{PACKSSWB}, except that
10381 it uses unsigned saturation when reducing the size of the elements.
10383 To perform signed saturation on a number, it is replaced by the largest
10384 signed number (\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too
10385 small it is replaced by the smallest signed number (\c{8000h} or
10386 \c{80h}) that will fit. To perform unsigned saturation, the input is
10387 treated as unsigned, and the input is replaced by the largest unsigned
10388 number that will fit.
10391 \S{insPADDB} \i\c{PADDB}, \i\c{PADDW}, \i\c{PADDD}: Add Packed Integers
10393 \c PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX]
10394 \c PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX]
10395 \c PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX]
10397 \c PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2]
10398 \c PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2]
10399 \c PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2]
10401 \c{PADDx} performs packed addition of the two operands, storing the
10402 result in the destination (first) operand.
10404 \b \c{PADDB} treats the operands as packed bytes, and adds each byte
10407 \b \c{PADDW} treats the operands as packed words;
10409 \b \c{PADDD} treats its operands as packed doublewords.
10411 When an individual result is too large to fit in its destination, it
10412 is wrapped around and the low bits are stored, with the carry bit
10416 \S{insPADDQ} \i\c{PADDQ}: Add Packed Quadword Integers
10418 \c PADDQ mm1,mm2/m64 ; 0F D4 /r [PENT,MMX]
10420 \c PADDQ xmm1,xmm2/m128 ; 66 0F D4 /r [WILLAMETTE,SSE2]
10422 \c{PADDQ} adds the quadwords in the source and destination operands, and
10423 stores the result in the destination register.
10425 When an individual result is too large to fit in its destination, it
10426 is wrapped around and the low bits are stored, with the carry bit
10430 \S{insPADDSB} \i\c{PADDSB}, \i\c{PADDSW}: Add Packed Signed Integers With Saturation
10432 \c PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX]
10433 \c PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX]
10435 \c PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2]
10436 \c PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2]
10438 \c{PADDSx} performs packed addition of the two operands, storing the
10439 result in the destination (first) operand.
10440 \c{PADDSB} treats the operands as packed bytes, and adds each byte
10441 individually; and \c{PADDSW} treats the operands as packed words.
10443 When an individual result is too large to fit in its destination, a
10444 saturated value is stored. The resulting value is the value with the
10445 largest magnitude of the same sign as the result which will fit in
10446 the available space.
10449 \S{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit Destination
10451 \c PADDSIW mmxreg,r/m64 ; 0F 51 /r [CYRIX,MMX]
10453 \c{PADDSIW}, specific to the Cyrix extensions to the MMX instruction
10454 set, performs the same function as \c{PADDSW}, except that the result
10455 is placed in an implied register.
10457 To work out the implied register, invert the lowest bit in the register
10458 number. So \c{PADDSIW MM0,MM2} would put the result in \c{MM1}, but
10459 \c{PADDSIW MM1,MM2} would put the result in \c{MM0}.
10462 \S{insPADDUSB} \i\c{PADDUSB}, \i\c{PADDUSW}: Add Packed Unsigned Integers With Saturation
10464 \c PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX]
10465 \c PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX]
10467 \c PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2]
10468 \c PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2]
10470 \c{PADDUSx} performs packed addition of the two operands, storing the
10471 result in the destination (first) operand.
10472 \c{PADDUSB} treats the operands as packed bytes, and adds each byte
10473 individually; and \c{PADDUSW} treats the operands as packed words.
10475 When an individual result is too large to fit in its destination, a
10476 saturated value is stored. The resulting value is the maximum value
10477 that will fit in the available space.
10480 \S{insPAND} \i\c{PAND}, \i\c{PANDN}: MMX Bitwise AND and AND-NOT
10482 \c PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX]
10483 \c PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX]
10485 \c PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2]
10486 \c PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2]
10489 \c{PAND} performs a bitwise AND operation between its two operands
10490 (i.e. each bit of the result is 1 if and only if the corresponding
10491 bits of the two inputs were both 1), and stores the result in the
10492 destination (first) operand.
10494 \c{PANDN} performs the same operation, but performs a one's
10495 complement operation on the destination (first) operand first.
10498 \S{insPAUSE} \i\c{PAUSE}: Spin Loop Hint
10500 \c PAUSE ; F3 90 [WILLAMETTE,SSE2]
10502 \c{PAUSE} provides a hint to the processor that the following code
10503 is a spin loop. This improves processor performance by bypassing
10504 possible memory order violations. On older processors, this instruction
10505 operates as a \c{NOP}.
10508 \S{insPAVEB} \i\c{PAVEB}: MMX Packed Average
10510 \c PAVEB mmxreg,r/m64 ; 0F 50 /r [CYRIX,MMX]
10512 \c{PAVEB}, specific to the Cyrix MMX extensions, treats its two
10513 operands as vectors of eight unsigned bytes, and calculates the
10514 average of the corresponding bytes in the operands. The resulting
10515 vector of eight averages is stored in the first operand.
10517 This opcode maps to \c{MOVMSKPS r32, xmm} on processors that support
10518 the SSE instruction set.
10521 \S{insPAVGB} \i\c{PAVGB} \i\c{PAVGW}: Average Packed Integers
10523 \c PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX]
10524 \c PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM]
10526 \c PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2]
10527 \c PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2]
10529 \c{PAVGB} and \c{PAVGW} add the unsigned data elements of the source
10530 operand to the unsigned data elements of the destination register,
10531 then adds 1 to the temporary results. The results of the add are then
10532 each independently right-shifted by one bit position. The high order
10533 bits of each element are filled with the carry bits of the corresponding
10536 \b \c{PAVGB} operates on packed unsigned bytes, and
10538 \b \c{PAVGW} operates on packed unsigned words.
10541 \S{insPAVGUSB} \i\c{PAVGUSB}: Average of unsigned packed 8-bit values
10543 \c PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW]
10545 \c{PAVGUSB} adds the unsigned data elements of the source operand to
10546 the unsigned data elements of the destination register, then adds 1
10547 to the temporary results. The results of the add are then each
10548 independently right-shifted by one bit position. The high order bits
10549 of each element are filled with the carry bits of the corresponding
10552 This instruction performs exactly the same operations as the \c{PAVGB}
10553 \c{MMX} instruction (\k{insPAVGB}).
10556 \S{insPCMPEQB} \i\c{PCMPxx}: Compare Packed Integers.
10558 \c PCMPEQB mm1,mm2/m64 ; 0F 74 /r [PENT,MMX]
10559 \c PCMPEQW mm1,mm2/m64 ; 0F 75 /r [PENT,MMX]
10560 \c PCMPEQD mm1,mm2/m64 ; 0F 76 /r [PENT,MMX]
10562 \c PCMPGTB mm1,mm2/m64 ; 0F 64 /r [PENT,MMX]
10563 \c PCMPGTW mm1,mm2/m64 ; 0F 65 /r [PENT,MMX]
10564 \c PCMPGTD mm1,mm2/m64 ; 0F 66 /r [PENT,MMX]
10566 \c PCMPEQB xmm1,xmm2/m128 ; 66 0F 74 /r [WILLAMETTE,SSE2]
10567 \c PCMPEQW xmm1,xmm2/m128 ; 66 0F 75 /r [WILLAMETTE,SSE2]
10568 \c PCMPEQD xmm1,xmm2/m128 ; 66 0F 76 /r [WILLAMETTE,SSE2]
10570 \c PCMPGTB xmm1,xmm2/m128 ; 66 0F 64 /r [WILLAMETTE,SSE2]
10571 \c PCMPGTW xmm1,xmm2/m128 ; 66 0F 65 /r [WILLAMETTE,SSE2]
10572 \c PCMPGTD xmm1,xmm2/m128 ; 66 0F 66 /r [WILLAMETTE,SSE2]
10574 The \c{PCMPxx} instructions all treat their operands as vectors of
10575 bytes, words, or doublewords; corresponding elements of the source
10576 and destination are compared, and the corresponding element of the
10577 destination (first) operand is set to all zeros or all ones
10578 depending on the result of the comparison.
10580 \b \c{PCMPxxB} treats the operands as vectors of bytes;
10582 \b \c{PCMPxxW} treats the operands as vectors of words;
10584 \b \c{PCMPxxD} treats the operands as vectors of doublewords;
10586 \b \c{PCMPEQx} sets the corresponding element of the destination
10587 operand to all ones if the two elements compared are equal;
10589 \b \c{PCMPGTx} sets the destination element to all ones if the element
10590 of the first (destination) operand is greater (treated as a signed
10591 integer) than that of the second (source) operand.
10594 \S{insPDISTIB} \i\c{PDISTIB}: MMX Packed Distance and Accumulate
10595 with Implied Register
10597 \c PDISTIB mm,m64 ; 0F 54 /r [CYRIX,MMX]
10599 \c{PDISTIB}, specific to the Cyrix MMX extensions, treats its two
10600 input operands as vectors of eight unsigned bytes. For each byte
10601 position, it finds the absolute difference between the bytes in that
10602 position in the two input operands, and adds that value to the byte
10603 in the same position in the implied output register. The addition is
10604 saturated to an unsigned byte in the same way as \c{PADDUSB}.
10606 To work out the implied register, invert the lowest bit in the register
10607 number. So \c{PDISTIB MM0,M64} would put the result in \c{MM1}, but
10608 \c{PDISTIB MM1,M64} would put the result in \c{MM0}.
10610 Note that \c{PDISTIB} cannot take a register as its second source
10615 \c dstI[0-7] := dstI[0-7] + ABS(src0[0-7] - src1[0-7]),
10616 \c dstI[8-15] := dstI[8-15] + ABS(src0[8-15] - src1[8-15]),
10619 \c dstI[56-63] := dstI[56-63] + ABS(src0[56-63] - src1[56-63]).
10622 \S{insPEXTRW} \i\c{PEXTRW}: Extract Word
10624 \c PEXTRW reg32,mm,imm8 ; 0F C5 /r ib [KATMAI,MMX]
10625 \c PEXTRW reg32,xmm,imm8 ; 66 0F C5 /r ib [WILLAMETTE,SSE2]
10627 \c{PEXTRW} moves the word in the source register (second operand)
10628 that is pointed to by the count operand (third operand), into the
10629 lower half of a 32-bit general purpose register. The upper half of
10630 the register is cleared to all 0s.
10632 When the source operand is an \c{MMX} register, the two least
10633 significant bits of the count specify the source word. When it is
10634 an \c{SSE} register, the three least significant bits specify the
10638 \S{insPF2ID} \i\c{PF2ID}: Packed Single-Precision FP to Integer Convert
10640 \c PF2ID mm1,mm2/m64 ; 0F 0F /r 1D [PENT,3DNOW]
10642 \c{PF2ID} converts two single-precision FP values in the source operand
10643 to signed 32-bit integers, using truncation, and stores them in the
10644 destination operand. Source values that are outside the range supported
10645 by the destination are saturated to the largest absolute value of the
10649 \S{insPF2IW} \i\c{PF2IW}: Packed Single-Precision FP to Integer Word Convert
10651 \c PF2IW mm1,mm2/m64 ; 0F 0F /r 1C [PENT,3DNOW]
10653 \c{PF2IW} converts two single-precision FP values in the source operand
10654 to signed 16-bit integers, using truncation, and stores them in the
10655 destination operand. Source values that are outside the range supported
10656 by the destination are saturated to the largest absolute value of the
10659 \b In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits
10662 \b In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended
10663 to 32-bits before storing.
10666 \S{insPFACC} \i\c{PFACC}: Packed Single-Precision FP Accumulate
10668 \c PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW]
10670 \c{PFACC} adds the two single-precision FP values from the destination
10671 operand together, then adds the two single-precision FP values from the
10672 source operand, and places the results in the low and high doublewords
10673 of the destination operand.
10677 \c dst[0-31] := dst[0-31] + dst[32-63],
10678 \c dst[32-63] := src[0-31] + src[32-63].
10681 \S{insPFADD} \i\c{PFADD}: Packed Single-Precision FP Addition
10683 \c PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW]
10685 \c{PFADD} performs addition on each of two packed single-precision
10688 \c dst[0-31] := dst[0-31] + src[0-31],
10689 \c dst[32-63] := dst[32-63] + src[32-63].
10692 \S{insPFCMP} \i\c{PFCMPxx}: Packed Single-Precision FP Compare
10693 \I\c{PFCMPEQ} \I\c{PFCMPGE} \I\c{PFCMPGT}
10695 \c PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW]
10696 \c PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW]
10697 \c PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW]
10699 The \c{PFCMPxx} instructions compare the packed single-point FP values
10700 in the source and destination operands, and set the destination
10701 according to the result. If the condition is true, the destination is
10702 set to all 1s, otherwise it's set to all 0s.
10704 \b \c{PFCMPEQ} tests whether dst == src;
10706 \b \c{PFCMPGE} tests whether dst >= src;
10708 \b \c{PFCMPGT} tests whether dst > src.
10711 \S{insPFMAX} \i\c{PFMAX}: Packed Single-Precision FP Maximum
10713 \c PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW]
10715 \c{PFMAX} returns the higher of each pair of single-precision FP values.
10716 If the higher value is zero, it is returned as positive zero.
10719 \S{insPFMIN} \i\c{PFMIN}: Packed Single-Precision FP Minimum
10721 \c PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW]
10723 \c{PFMIN} returns the lower of each pair of single-precision FP values.
10724 If the lower value is zero, it is returned as positive zero.
10727 \S{insPFMUL} \i\c{PFMUL}: Packed Single-Precision FP Multiply
10729 \c PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW]
10731 \c{PFMUL} returns the product of each pair of single-precision FP values.
10733 \c dst[0-31] := dst[0-31] * src[0-31],
10734 \c dst[32-63] := dst[32-63] * src[32-63].
10737 \S{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Negative Accumulate
10739 \c PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW]
10741 \c{PFNACC} performs a negative accumulate of the two single-precision
10742 FP values in the source and destination registers. The result of the
10743 accumulate from the destination register is stored in the low doubleword
10744 of the destination, and the result of the source accumulate is stored in
10745 the high doubleword of the destination register.
10749 \c dst[0-31] := dst[0-31] - dst[32-63],
10750 \c dst[32-63] := src[0-31] - src[32-63].
10753 \S{insPFPNACC} \i\c{PFPNACC}: Packed Single-Precision FP Mixed Accumulate
10755 \c PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW]
10757 \c{PFPNACC} performs a positive accumulate of the two single-precision
10758 FP values in the source register and a negative accumulate of the
10759 destination register. The result of the accumulate from the destination
10760 register is stored in the low doubleword of the destination, and the
10761 result of the source accumulate is stored in the high doubleword of the
10762 destination register.
10766 \c dst[0-31] := dst[0-31] - dst[32-63],
10767 \c dst[32-63] := src[0-31] + src[32-63].
10770 \S{insPFRCP} \i\c{PFRCP}: Packed Single-Precision FP Reciprocal Approximation
10772 \c PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW]
10774 \c{PFRCP} performs a low precision estimate of the reciprocal of the
10775 low-order single-precision FP value in the source operand, storing the
10776 result in both halves of the destination register. The result is accurate
10779 For higher precision reciprocals, this instruction should be followed by
10780 two more instructions: \c{PFRCPIT1} (\k{insPFRCPIT1}) and \c{PFRCPIT2}
10781 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10782 see the AMD 3DNow! technology manual.
10785 \S{insPFRCPIT1} \i\c{PFRCPIT1}: Packed Single-Precision FP Reciprocal,
10786 First Iteration Step
10788 \c PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW]
10790 \c{PFRCPIT1} performs the first intermediate step in the calculation of
10791 the reciprocal of a single-precision FP value. The first source value
10792 (\c{mm1} is the original value, and the second source value (\c{mm2/m64}
10793 is the result of a \c{PFRCP} instruction.
10795 For the final step in a reciprocal, returning the full 24-bit accuracy
10796 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10797 more details, see the AMD 3DNow! technology manual.
10800 \S{insPFRCPIT2} \i\c{PFRCPIT2}: Packed Single-Precision FP
10801 Reciprocal/ Reciprocal Square Root, Second Iteration Step
10803 \c PFRCPIT2 mm1,mm2/m64 ; 0F 0F /r B6 [PENT,3DNOW]
10805 \c{PFRCPIT2} performs the second and final intermediate step in the
10806 calculation of a reciprocal or reciprocal square root, refining the
10807 values returned by the \c{PFRCP} and \c{PFRSQRT} instructions,
10810 The first source value (\c{mm1}) is the output of either a \c{PFRCPIT1}
10811 or a \c{PFRSQIT1} instruction, and the second source is the output of
10812 either the \c{PFRCP} or the \c{PFRSQRT} instruction. For more details,
10813 see the AMD 3DNow! technology manual.
10816 \S{insPFRSQIT1} \i\c{PFRSQIT1}: Packed Single-Precision FP Reciprocal
10817 Square Root, First Iteration Step
10819 \c PFRSQIT1 mm1,mm2/m64 ; 0F 0F /r A7 [PENT,3DNOW]
10821 \c{PFRSQIT1} performs the first intermediate step in the calculation of
10822 the reciprocal square root of a single-precision FP value. The first
10823 source value (\c{mm1} is the square of the result of a \c{PFRSQRT}
10824 instruction, and the second source value (\c{mm2/m64} is the original
10827 For the final step in a calculation, returning the full 24-bit accuracy
10828 of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For
10829 more details, see the AMD 3DNow! technology manual.
10832 \S{insPFRSQRT} \i\c{PFRSQRT}: Packed Single-Precision FP Reciprocal
10833 Square Root Approximation
10835 \c PFRSQRT mm1,mm2/m64 ; 0F 0F /r 97 [PENT,3DNOW]
10837 \c{PFRSQRT} performs a low precision estimate of the reciprocal square
10838 root of the low-order single-precision FP value in the source operand,
10839 storing the result in both halves of the destination register. The result
10840 is accurate to 15 bits.
10842 For higher precision reciprocals, this instruction should be followed by
10843 two more instructions: \c{PFRSQIT1} (\k{insPFRSQIT1}) and \c{PFRCPIT2}
10844 (\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details,
10845 see the AMD 3DNow! technology manual.
10848 \S{insPFSUB} \i\c{PFSUB}: Packed Single-Precision FP Subtract
10850 \c PFSUB mm1,mm2/m64 ; 0F 0F /r 9A [PENT,3DNOW]
10852 \c{PFSUB} subtracts the single-precision FP values in the source from
10853 those in the destination, and stores the result in the destination
10856 \c dst[0-31] := dst[0-31] - src[0-31],
10857 \c dst[32-63] := dst[32-63] - src[32-63].
10860 \S{insPFSUBR} \i\c{PFSUBR}: Packed Single-Precision FP Reverse Subtract
10862 \c PFSUBR mm1,mm2/m64 ; 0F 0F /r AA [PENT,3DNOW]
10864 \c{PFSUBR} subtracts the single-precision FP values in the destination
10865 from those in the source, and stores the result in the destination
10868 \c dst[0-31] := src[0-31] - dst[0-31],
10869 \c dst[32-63] := src[32-63] - dst[32-63].
10872 \S{insPI2FD} \i\c{PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert
10874 \c PI2FD mm1,mm2/m64 ; 0F 0F /r 0D [PENT,3DNOW]
10876 \c{PF2ID} converts two signed 32-bit integers in the source operand
10877 to single-precision FP values, using truncation of significant digits,
10878 and stores them in the destination operand.
10881 \S{insPF2IW} \i\c{PF2IW}: Packed Word Integer to Single-Precision FP Convert
10883 \c PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW]
10885 \c{PF2IW} converts two signed 16-bit integers in the source operand
10886 to single-precision FP values, and stores them in the destination
10887 operand. The input values are in the low word of each doubleword.
10890 \S{insPINSRW} \i\c{PINSRW}: Insert Word
10892 \c PINSRW mm,r16/r32/m16,imm8 ;0F C4 /r ib [KATMAI,MMX]
10893 \c PINSRW xmm,r16/r32/m16,imm8 ;66 0F C4 /r ib [WILLAMETTE,SSE2]
10895 \c{PINSRW} loads a word from a 16-bit register (or the low half of a
10896 32-bit register), or from memory, and loads it to the word position
10897 in the destination register, pointed at by the count operand (third
10898 operand). If the destination is an \c{MMX} register, the low two bits
10899 of the count byte are used, if it is an \c{XMM} register the low 3
10900 bits are used. The insertion is done in such a way that the other
10901 words from the destination register are left untouched.
10904 \S{insPMACHRIW} \i\c{PMACHRIW}: Packed Multiply and Accumulate with Rounding
10906 \c PMACHRIW mm,m64 ; 0F 5E /r [CYRIX,MMX]
10908 \c{PMACHRIW} takes two packed 16-bit integer inputs, multiplies the
10909 values in the inputs, rounds on bit 15 of each result, then adds bits
10910 15-30 of each result to the corresponding position of the \e{implied}
10911 destination register.
10913 The operation of this instruction is:
10915 \c dstI[0-15] := dstI[0-15] + (mm[0-15] *m64[0-15]
10916 \c + 0x00004000)[15-30],
10917 \c dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31]
10918 \c + 0x00004000)[15-30],
10919 \c dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47]
10920 \c + 0x00004000)[15-30],
10921 \c dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63]
10922 \c + 0x00004000)[15-30].
10924 Note that \c{PMACHRIW} cannot take a register as its second source
10928 \S{insPMADDWD} \i\c{PMADDWD}: MMX Packed Multiply and Add
10930 \c PMADDWD mm1,mm2/m64 ; 0F F5 /r [PENT,MMX]
10931 \c PMADDWD xmm1,xmm2/m128 ; 66 0F F5 /r [WILLAMETTE,SSE2]
10933 \c{PMADDWD} treats its two inputs as vectors of signed words. It
10934 multiplies corresponding elements of the two operands, giving doubleword
10935 results. These are then added together in pairs and stored in the
10936 destination operand.
10938 The operation of this instruction is:
10940 \c dst[0-31] := (dst[0-15] * src[0-15])
10941 \c + (dst[16-31] * src[16-31]);
10942 \c dst[32-63] := (dst[32-47] * src[32-47])
10943 \c + (dst[48-63] * src[48-63]);
10945 The following apply to the \c{SSE} version of the instruction:
10947 \c dst[64-95] := (dst[64-79] * src[64-79])
10948 \c + (dst[80-95] * src[80-95]);
10949 \c dst[96-127] := (dst[96-111] * src[96-111])
10950 \c + (dst[112-127] * src[112-127]).
10953 \S{insPMAGW} \i\c{PMAGW}: MMX Packed Magnitude
10955 \c PMAGW mm1,mm2/m64 ; 0F 52 /r [CYRIX,MMX]
10957 \c{PMAGW}, specific to the Cyrix MMX extensions, treats both its
10958 operands as vectors of four signed words. It compares the absolute
10959 values of the words in corresponding positions, and sets each word
10960 of the destination (first) operand to whichever of the two words in
10961 that position had the larger absolute value.
10964 \S{insPMAXSW} \i\c{PMAXSW}: Packed Signed Integer Word Maximum
10966 \c PMAXSW mm1,mm2/m64 ; 0F EE /r [KATMAI,MMX]
10967 \c PMAXSW xmm1,xmm2/m128 ; 66 0F EE /r [WILLAMETTE,SSE2]
10969 \c{PMAXSW} compares each pair of words in the two source operands, and
10970 for each pair it stores the maximum value in the destination register.
10973 \S{insPMAXUB} \i\c{PMAXUB}: Packed Unsigned Integer Byte Maximum
10975 \c PMAXUB mm1,mm2/m64 ; 0F DE /r [KATMAI,MMX]
10976 \c PMAXUB xmm1,xmm2/m128 ; 66 0F DE /r [WILLAMETTE,SSE2]
10978 \c{PMAXUB} compares each pair of bytes in the two source operands, and
10979 for each pair it stores the maximum value in the destination register.
10982 \S{insPMINSW} \i\c{PMINSW}: Packed Signed Integer Word Minimum
10984 \c PMINSW mm1,mm2/m64 ; 0F EA /r [KATMAI,MMX]
10985 \c PMINSW xmm1,xmm2/m128 ; 66 0F EA /r [WILLAMETTE,SSE2]
10987 \c{PMINSW} compares each pair of words in the two source operands, and
10988 for each pair it stores the minimum value in the destination register.
10991 \S{insPMINUB} \i\c{PMINUB}: Packed Unsigned Integer Byte Minimum
10993 \c PMINUB mm1,mm2/m64 ; 0F DA /r [KATMAI,MMX]
10994 \c PMINUB xmm1,xmm2/m128 ; 66 0F DA /r [WILLAMETTE,SSE2]
10996 \c{PMINUB} compares each pair of bytes in the two source operands, and
10997 for each pair it stores the minimum value in the destination register.
11000 \S{insPMOVMSKB} \i\c{PMOVMSKB}: Move Byte Mask To Integer
11002 \c PMOVMSKB reg32,mm ; 0F D7 /r [KATMAI,MMX]
11003 \c PMOVMSKB reg32,xmm ; 66 0F D7 /r [WILLAMETTE,SSE2]
11005 \c{PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most
11006 significant bits of each byte of source operand (8-bits for an
11007 \c{MMX} register, 16-bits for an \c{XMM} register).
11010 \S{insPMULHRW} \i\c{PMULHRWC}, \i\c{PMULHRIW}: Multiply Packed 16-bit Integers
11011 With Rounding, and Store High Word
11013 \c PMULHRWC mm1,mm2/m64 ; 0F 59 /r [CYRIX,MMX]
11014 \c PMULHRIW mm1,mm2/m64 ; 0F 5D /r [CYRIX,MMX]
11016 These instructions take two packed 16-bit integer inputs, multiply the
11017 values in the inputs, round on bit 15 of each result, then store bits
11018 15-30 of each result to the corresponding position of the destination
11021 \b For \c{PMULHRWC}, the destination is the first source operand.
11023 \b For \c{PMULHRIW}, the destination is an implied register (worked out
11024 as described for \c{PADDSIW} (\k{insPADDSIW})).
11026 The operation of this instruction is:
11028 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00004000)[15-30]
11029 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30]
11030 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30]
11031 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30]
11033 See also \c{PMULHRWA} (\k{insPMULHRWA}) for a 3DNow! version of this
11037 \S{insPMULHRWA} \i\c{PMULHRWA}: Multiply Packed 16-bit Integers
11038 With Rounding, and Store High Word
11040 \c PMULHRWA mm1,mm2/m64 ; 0F 0F /r B7 [PENT,3DNOW]
11042 \c{PMULHRWA} takes two packed 16-bit integer inputs, multiplies
11043 the values in the inputs, rounds on bit 16 of each result, then
11044 stores bits 16-31 of each result to the corresponding position
11045 of the destination register.
11047 The operation of this instruction is:
11049 \c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00008000)[16-31];
11050 \c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31];
11051 \c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31];
11052 \c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31].
11054 See also \c{PMULHRWC} (\k{insPMULHRW}) for a Cyrix version of this
11058 \S{insPMULHUW} \i\c{PMULHUW}: Multiply Packed 16-bit Integers,
11059 and Store High Word
11061 \c PMULHUW mm1,mm2/m64 ; 0F E4 /r [KATMAI,MMX]
11062 \c PMULHUW xmm1,xmm2/m128 ; 66 0F E4 /r [WILLAMETTE,SSE2]
11064 \c{PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies
11065 the values in the inputs, then stores bits 16-31 of each result to the
11066 corresponding position of the destination register.
11069 \S{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: Multiply Packed 16-bit Integers,
11072 \c PMULHW mm1,mm2/m64 ; 0F E5 /r [PENT,MMX]
11073 \c PMULLW mm1,mm2/m64 ; 0F D5 /r [PENT,MMX]
11075 \c PMULHW xmm1,xmm2/m128 ; 66 0F E5 /r [WILLAMETTE,SSE2]
11076 \c PMULLW xmm1,xmm2/m128 ; 66 0F D5 /r [WILLAMETTE,SSE2]
11078 \c{PMULxW} takes two packed unsigned 16-bit integer inputs, and
11079 multiplies the values in the inputs, forming doubleword results.
11081 \b \c{PMULHW} then stores the top 16 bits of each doubleword in the
11082 destination (first) operand;
11084 \b \c{PMULLW} stores the bottom 16 bits of each doubleword in the
11085 destination operand.
11088 \S{insPMULUDQ} \i\c{PMULUDQ}: Multiply Packed Unsigned
11089 32-bit Integers, and Store.
11091 \c PMULUDQ mm1,mm2/m64 ; 0F F4 /r [WILLAMETTE,SSE2]
11092 \c PMULUDQ xmm1,xmm2/m128 ; 66 0F F4 /r [WILLAMETTE,SSE2]
11094 \c{PMULUDQ} takes two packed unsigned 32-bit integer inputs, and
11095 multiplies the values in the inputs, forming quadword results. The
11096 source is either an unsigned doubleword in the low doubleword of a
11097 64-bit operand, or it's two unsigned doublewords in the first and
11098 third doublewords of a 128-bit operand. This produces either one or
11099 two 64-bit results, which are stored in the respective quadword
11100 locations of the destination register.
11104 \c dst[0-63] := dst[0-31] * src[0-31];
11105 \c dst[64-127] := dst[64-95] * src[64-95].
11108 \S{insPMVccZB} \i\c{PMVccZB}: MMX Packed Conditional Move
11110 \c PMVZB mmxreg,mem64 ; 0F 58 /r [CYRIX,MMX]
11111 \c PMVNZB mmxreg,mem64 ; 0F 5A /r [CYRIX,MMX]
11112 \c PMVLZB mmxreg,mem64 ; 0F 5B /r [CYRIX,MMX]
11113 \c PMVGEZB mmxreg,mem64 ; 0F 5C /r [CYRIX,MMX]
11115 These instructions, specific to the Cyrix MMX extensions, perform
11116 parallel conditional moves. The two input operands are treated as
11117 vectors of eight bytes. Each byte of the destination (first) operand
11118 is either written from the corresponding byte of the source (second)
11119 operand, or left alone, depending on the value of the byte in the
11120 \e{implied} operand (specified in the same way as \c{PADDSIW}, in
11123 \b \c{PMVZB} performs each move if the corresponding byte in the
11124 implied operand is zero;
11126 \b \c{PMVNZB} moves if the byte is non-zero;
11128 \b \c{PMVLZB} moves if the byte is less than zero;
11130 \b \c{PMVGEZB} moves if the byte is greater than or equal to zero.
11132 Note that these instructions cannot take a register as their second
11136 \S{insPOP} \i\c{POP}: Pop Data from Stack
11138 \c POP reg16 ; o16 58+r [8086]
11139 \c POP reg32 ; o32 58+r [386]
11141 \c POP r/m16 ; o16 8F /0 [8086]
11142 \c POP r/m32 ; o32 8F /0 [386]
11144 \c POP CS ; 0F [8086,UNDOC]
11145 \c POP DS ; 1F [8086]
11146 \c POP ES ; 07 [8086]
11147 \c POP SS ; 17 [8086]
11148 \c POP FS ; 0F A1 [386]
11149 \c POP GS ; 0F A9 [386]
11151 \c{POP} loads a value from the stack (from \c{[SS:SP]} or
11152 \c{[SS:ESP]}) and then increments the stack pointer.
11154 The address-size attribute of the instruction determines whether
11155 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11156 override the default given by the \c{BITS} setting, you can use an
11157 \i\c{a16} or \i\c{a32} prefix.
11159 The operand-size attribute of the instruction determines whether the
11160 stack pointer is incremented by 2 or 4: this means that segment
11161 register pops in \c{BITS 32} mode will pop 4 bytes off the stack and
11162 discard the upper two of them. If you need to override that, you can
11163 use an \i\c{o16} or \i\c{o32} prefix.
11165 The above opcode listings give two forms for general-purpose
11166 register pop instructions: for example, \c{POP BX} has the two forms
11167 \c{5B} and \c{8F C3}. NASM will always generate the shorter form
11168 when given \c{POP BX}. NDISASM will disassemble both.
11170 \c{POP CS} is not a documented instruction, and is not supported on
11171 any processor above the 8086 (since they use \c{0Fh} as an opcode
11172 prefix for instruction set extensions). However, at least some 8086
11173 processors do support it, and so NASM generates it for completeness.
11176 \S{insPOPA} \i\c{POPAx}: Pop All General-Purpose Registers
11179 \c POPAW ; o16 61 [186]
11180 \c POPAD ; o32 61 [386]
11182 \b \c{POPAW} pops a word from the stack into each of, successively,
11183 \c{DI}, \c{SI}, \c{BP}, nothing (it discards a word from the stack
11184 which was a placeholder for \c{SP}), \c{BX}, \c{DX}, \c{CX} and
11185 \c{AX}. It is intended to reverse the operation of \c{PUSHAW} (see
11186 \k{insPUSHA}), but it ignores the value for \c{SP} that was pushed
11187 on the stack by \c{PUSHAW}.
11189 \b \c{POPAD} pops twice as much data, and places the results in
11190 \c{EDI}, \c{ESI}, \c{EBP}, nothing (placeholder for \c{ESP}),
11191 \c{EBX}, \c{EDX}, \c{ECX} and \c{EAX}. It reverses the operation of
11194 \c{POPA} is an alias mnemonic for either \c{POPAW} or \c{POPAD},
11195 depending on the current \c{BITS} setting.
11197 Note that the registers are popped in reverse order of their numeric
11198 values in opcodes (see \k{iref-rv}).
11201 \S{insPOPF} \i\c{POPFx}: Pop Flags Register
11203 \c POPF ; 9D [8086]
11204 \c POPFW ; o16 9D [8086]
11205 \c POPFD ; o32 9D [386]
11207 \b \c{POPFW} pops a word from the stack and stores it in the bottom 16
11208 bits of the flags register (or the whole flags register, on
11209 processors below a 386).
11211 \b \c{POPFD} pops a doubleword and stores it in the entire flags register.
11213 \c{POPF} is an alias mnemonic for either \c{POPFW} or \c{POPFD},
11214 depending on the current \c{BITS} setting.
11216 See also \c{PUSHF} (\k{insPUSHF}).
11219 \S{insPOR} \i\c{POR}: MMX Bitwise OR
11221 \c POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX]
11222 \c POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2]
11224 \c{POR} performs a bitwise OR operation between its two operands
11225 (i.e. each bit of the result is 1 if and only if at least one of the
11226 corresponding bits of the two inputs was 1), and stores the result
11227 in the destination (first) operand.
11230 \S{insPREFETCH} \i\c{PREFETCH}: Prefetch Data Into Caches
11232 \c PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW]
11233 \c PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW]
11235 \c{PREFETCH} and \c{PREFETCHW} fetch the line of data from memory that
11236 contains the specified byte. \c{PREFETCHW} performs differently on the
11237 Athlon to earlier processors.
11239 For more details, see the 3DNow! Technology Manual.
11242 \S{insPREFETCHh} \i\c{PREFETCHh}: Prefetch Data Into Caches
11243 \I\c{PREFETCHNTA} \I\c{PREFETCHT0} \I\c{PREFETCHT1} \I\c{PREFETCHT2}
11245 \c PREFETCHNTA m8 ; 0F 18 /0 [KATMAI]
11246 \c PREFETCHT0 m8 ; 0F 18 /1 [KATMAI]
11247 \c PREFETCHT1 m8 ; 0F 18 /2 [KATMAI]
11248 \c PREFETCHT2 m8 ; 0F 18 /3 [KATMAI]
11250 The \c{PREFETCHh} instructions fetch the line of data from memory
11251 that contains the specified byte. It is placed in the cache
11252 according to rules specified by locality hints \c{h}:
11256 \b \c{T0} (temporal data) - prefetch data into all levels of the
11259 \b \c{T1} (temporal data with respect to first level cache) -
11260 prefetch data into level 2 cache and higher.
11262 \b \c{T2} (temporal data with respect to second level cache) -
11263 prefetch data into level 2 cache and higher.
11265 \b \c{NTA} (non-temporal data with respect to all cache levels) -
11266 prefetch data into non-temporal cache structure and into a
11267 location close to the processor, minimizing cache pollution.
11269 Note that this group of instructions doesn't provide a guarantee
11270 that the data will be in the cache when it is needed. For more
11271 details, see the Intel IA32 Software Developer Manual, Volume 2.
11274 \S{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences
11276 \c PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX]
11277 \c PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2]
11279 \c{PSADBW} The PSADBW instruction computes the absolute value of the
11280 difference of the packed unsigned bytes in the two source operands.
11281 These differences are then summed to produce a word result in the lower
11282 16-bit field of the destination register; the rest of the register is
11283 cleared. The destination operand is an \c{MMX} or an \c{XMM} register.
11284 The source operand can either be a register or a memory operand.
11287 \S{insPSHUFD} \i\c{PSHUFD}: Shuffle Packed Doublewords
11289 \c PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2]
11291 \c{PSHUFD} shuffles the doublewords in the source (second) operand
11292 according to the encoding specified by imm8, and stores the result
11293 in the destination (first) operand.
11295 Bits 0 and 1 of imm8 encode the source position of the doubleword to
11296 be copied to position 0 in the destination operand. Bits 2 and 3
11297 encode for position 1, bits 4 and 5 encode for position 2, and bits
11298 6 and 7 encode for position 3. For example, an encoding of 10 in
11299 bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of
11300 the source operand will be copied to bits 0-31 of the destination.
11303 \S{insPSHUFHW} \i\c{PSHUFHW}: Shuffle Packed High Words
11305 \c PSHUFHW xmm1,xmm2/m128,imm8 ; F3 0F 70 /r ib [WILLAMETTE,SSE2]
11307 \c{PSHUFW} shuffles the words in the high quadword of the source
11308 (second) operand according to the encoding specified by imm8, and
11309 stores the result in the high quadword of the destination (first)
11312 The operation of this instruction is similar to the \c{PSHUFW}
11313 instruction, except that the source and destination are the top
11314 quadword of a 128-bit operand, instead of being 64-bit operands.
11315 The low quadword is copied from the source to the destination
11316 without any changes.
11319 \S{insPSHUFLW} \i\c{PSHUFLW}: Shuffle Packed Low Words
11321 \c PSHUFLW xmm1,xmm2/m128,imm8 ; F2 0F 70 /r ib [WILLAMETTE,SSE2]
11323 \c{PSHUFLW} shuffles the words in the low quadword of the source
11324 (second) operand according to the encoding specified by imm8, and
11325 stores the result in the low quadword of the destination (first)
11328 The operation of this instruction is similar to the \c{PSHUFW}
11329 instruction, except that the source and destination are the low
11330 quadword of a 128-bit operand, instead of being 64-bit operands.
11331 The high quadword is copied from the source to the destination
11332 without any changes.
11335 \S{insPSHUFW} \i\c{PSHUFW}: Shuffle Packed Words
11337 \c PSHUFW mm1,mm2/m64,imm8 ; 0F 70 /r ib [KATMAI,MMX]
11339 \c{PSHUFW} shuffles the words in the source (second) operand
11340 according to the encoding specified by imm8, and stores the result
11341 in the destination (first) operand.
11343 Bits 0 and 1 of imm8 encode the source position of the word to be
11344 copied to position 0 in the destination operand. Bits 2 and 3 encode
11345 for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7
11346 encode for position 3. For example, an encoding of 10 in bits 0 and 1
11347 of imm8 indicates that the word at bits 32-47 of the source operand
11348 will be copied to bits 0-15 of the destination.
11351 \S{insPSLLD} \i\c{PSLLx}: Packed Data Bit Shift Left Logical
11353 \c PSLLW mm1,mm2/m64 ; 0F F1 /r [PENT,MMX]
11354 \c PSLLW mm,imm8 ; 0F 71 /6 ib [PENT,MMX]
11356 \c PSLLW xmm1,xmm2/m128 ; 66 0F F1 /r [WILLAMETTE,SSE2]
11357 \c PSLLW xmm,imm8 ; 66 0F 71 /6 ib [WILLAMETTE,SSE2]
11359 \c PSLLD mm1,mm2/m64 ; 0F F2 /r [PENT,MMX]
11360 \c PSLLD mm,imm8 ; 0F 72 /6 ib [PENT,MMX]
11362 \c PSLLD xmm1,xmm2/m128 ; 66 0F F2 /r [WILLAMETTE,SSE2]
11363 \c PSLLD xmm,imm8 ; 66 0F 72 /6 ib [WILLAMETTE,SSE2]
11365 \c PSLLQ mm1,mm2/m64 ; 0F F3 /r [PENT,MMX]
11366 \c PSLLQ mm,imm8 ; 0F 73 /6 ib [PENT,MMX]
11368 \c PSLLQ xmm1,xmm2/m128 ; 66 0F F3 /r [WILLAMETTE,SSE2]
11369 \c PSLLQ xmm,imm8 ; 66 0F 73 /6 ib [WILLAMETTE,SSE2]
11371 \c PSLLDQ xmm1,imm8 ; 66 0F 73 /7 ib [PENT,MMX]
11373 \c{PSLLx} performs logical left shifts of the data elements in the
11374 destination (first) operand, moving each bit in the separate elements
11375 left by the number of bits specified in the source (second) operand,
11376 clearing the low-order bits as they are vacated.
11378 \b \c{PSLLW} shifts word sized elements.
11380 \b \c{PSLLD} shifts doubleword sized elements.
11382 \b \c{PSLLQ} shifts quadword sized elements.
11384 \b \c{PSLLDQ} shifts double quadword sized elements.
11387 \S{insPSRAD} \i\c{PSRAx}: Packed Data Bit Shift Right Arithmetic
11389 \c PSRAW mm1,mm2/m64 ; 0F E1 /r [PENT,MMX]
11390 \c PSRAW mm,imm8 ; 0F 71 /4 ib [PENT,MMX]
11392 \c PSRAW xmm1,xmm2/m128 ; 66 0F E1 /r [WILLAMETTE,SSE2]
11393 \c PSRAW xmm,imm8 ; 66 0F 71 /4 ib [WILLAMETTE,SSE2]
11395 \c PSRAD mm1,mm2/m64 ; 0F E2 /r [PENT,MMX]
11396 \c PSRAD mm,imm8 ; 0F 72 /4 ib [PENT,MMX]
11398 \c PSRAD xmm1,xmm2/m128 ; 66 0F E2 /r [WILLAMETTE,SSE2]
11399 \c PSRAD xmm,imm8 ; 66 0F 72 /4 ib [WILLAMETTE,SSE2]
11401 \c{PSRAx} performs arithmetic right shifts of the data elements in the
11402 destination (first) operand, moving each bit in the separate elements
11403 right by the number of bits specified in the source (second) operand,
11404 setting the high-order bits to the value of the original sign bit.
11406 \b \c{PSRAW} shifts word sized elements.
11408 \b \c{PSRAD} shifts doubleword sized elements.
11411 \S{insPSRLD} \i\c{PSRLx}: Packed Data Bit Shift Right Logical
11413 \c PSRLW mm1,mm2/m64 ; 0F D1 /r [PENT,MMX]
11414 \c PSRLW mm,imm8 ; 0F 71 /2 ib [PENT,MMX]
11416 \c PSRLW xmm1,xmm2/m128 ; 66 0F D1 /r [WILLAMETTE,SSE2]
11417 \c PSRLW xmm,imm8 ; 66 0F 71 /2 ib [WILLAMETTE,SSE2]
11419 \c PSRLD mm1,mm2/m64 ; 0F D2 /r [PENT,MMX]
11420 \c PSRLD mm,imm8 ; 0F 72 /2 ib [PENT,MMX]
11422 \c PSRLD xmm1,xmm2/m128 ; 66 0F D2 /r [WILLAMETTE,SSE2]
11423 \c PSRLD xmm,imm8 ; 66 0F 72 /2 ib [WILLAMETTE,SSE2]
11425 \c PSRLQ mm1,mm2/m64 ; 0F D3 /r [PENT,MMX]
11426 \c PSRLQ mm,imm8 ; 0F 73 /2 ib [PENT,MMX]
11428 \c PSRLQ xmm1,xmm2/m128 ; 66 0F D3 /r [WILLAMETTE,SSE2]
11429 \c PSRLQ xmm,imm8 ; 66 0F 73 /2 ib [WILLAMETTE,SSE2]
11431 \c PSRLDQ xmm1,imm8 ; 66 0F 73 /3 ib [WILLAMETTE,SSE2]
11433 \c{PSRLx} performs logical right shifts of the data elements in the
11434 destination (first) operand, moving each bit in the separate elements
11435 right by the number of bits specified in the source (second) operand,
11436 clearing the high-order bits as they are vacated.
11438 \b \c{PSRLW} shifts word sized elements.
11440 \b \c{PSRLD} shifts doubleword sized elements.
11442 \b \c{PSRLQ} shifts quadword sized elements.
11444 \b \c{PSRLDQ} shifts double quadword sized elements.
11447 \S{insPSUBB} \i\c{PSUBx}: Subtract Packed Integers
11449 \c PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX]
11450 \c PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX]
11451 \c PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX]
11452 \c PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2]
11454 \c PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2]
11455 \c PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2]
11456 \c PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2]
11457 \c PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2]
11459 \c{PSUBx} subtracts packed integers in the source operand from those
11460 in the destination operand. It doesn't differentiate between signed
11461 and unsigned integers, and doesn't set any of the flags.
11463 \b \c{PSUBB} operates on byte sized elements.
11465 \b \c{PSUBW} operates on word sized elements.
11467 \b \c{PSUBD} operates on doubleword sized elements.
11469 \b \c{PSUBQ} operates on quadword sized elements.
11472 \S{insPSUBSB} \i\c{PSUBSxx}, \i\c{PSUBUSx}: Subtract Packed Integers With Saturation
11474 \c PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX]
11475 \c PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX]
11477 \c PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2]
11478 \c PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2]
11480 \c PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX]
11481 \c PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX]
11483 \c PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2]
11484 \c PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2]
11486 \c{PSUBSx} and \c{PSUBUSx} subtracts packed integers in the source
11487 operand from those in the destination operand, and use saturation for
11488 results that are outside the range supported by the destination operand.
11490 \b \c{PSUBSB} operates on signed bytes, and uses signed saturation on the
11493 \b \c{PSUBSW} operates on signed words, and uses signed saturation on the
11496 \b \c{PSUBUSB} operates on unsigned bytes, and uses signed saturation on
11499 \b \c{PSUBUSW} operates on unsigned words, and uses signed saturation on
11503 \S{insPSUBSIW} \i\c{PSUBSIW}: MMX Packed Subtract with Saturation to
11504 Implied Destination
11506 \c PSUBSIW mm1,mm2/m64 ; 0F 55 /r [CYRIX,MMX]
11508 \c{PSUBSIW}, specific to the Cyrix extensions to the MMX instruction
11509 set, performs the same function as \c{PSUBSW}, except that the
11510 result is not placed in the register specified by the first operand,
11511 but instead in the implied destination register, specified as for
11512 \c{PADDSIW} (\k{insPADDSIW}).
11515 \S{insPSWAPD} \i\c{PSWAPD}: Swap Packed Data
11518 \c PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW]
11520 \c{PSWAPD} swaps the packed doublewords in the source operand, and
11521 stores the result in the destination operand.
11523 In the \c{K6-2} and \c{K6-III} processors, this opcode uses the
11524 mnemonic \c{PSWAPW}, and it swaps the order of words when copying
11525 from the source to the destination.
11527 The operation in the \c{K6-2} and \c{K6-III} processors is
11529 \c dst[0-15] = src[48-63];
11530 \c dst[16-31] = src[32-47];
11531 \c dst[32-47] = src[16-31];
11532 \c dst[48-63] = src[0-15].
11534 The operation in the \c{K6-x+}, \c{ATHLON} and later processors is:
11536 \c dst[0-31] = src[32-63];
11537 \c dst[32-63] = src[0-31].
11540 \S{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack and Interleave Data
11542 \c PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX]
11543 \c PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX]
11544 \c PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX]
11546 \c PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2]
11547 \c PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2]
11548 \c PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2]
11549 \c PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2]
11551 \c PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX]
11552 \c PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX]
11553 \c PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX]
11555 \c PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2]
11556 \c PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2]
11557 \c PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2]
11558 \c PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2]
11560 \c{PUNPCKxx} all treat their operands as vectors, and produce a new
11561 vector generated by interleaving elements from the two inputs. The
11562 \c{PUNPCKHxx} instructions start by throwing away the bottom half of
11563 each input operand, and the \c{PUNPCKLxx} instructions throw away
11566 The remaining elements, are then interleaved into the destination,
11567 alternating elements from the second (source) operand and the first
11568 (destination) operand: so the leftmost part of each element in the
11569 result always comes from the second operand, and the rightmost from
11572 \b \c{PUNPCKxBW} works a byte at a time, producing word sized output
11575 \b \c{PUNPCKxWD} works a word at a time, producing doubleword sized
11578 \b \c{PUNPCKxDQ} works a doubleword at a time, producing quadword sized
11581 \b \c{PUNPCKxQDQ} works a quadword at a time, producing double quadword
11582 sized output elements.
11584 So, for example, for \c{MMX} operands, if the first operand held
11585 \c{0x7A6A5A4A3A2A1A0A} and the second held \c{0x7B6B5B4B3B2B1B0B},
11588 \b \c{PUNPCKHBW} would return \c{0x7B7A6B6A5B5A4B4A}.
11590 \b \c{PUNPCKHWD} would return \c{0x7B6B7A6A5B4B5A4A}.
11592 \b \c{PUNPCKHDQ} would return \c{0x7B6B5B4B7A6A5A4A}.
11594 \b \c{PUNPCKLBW} would return \c{0x3B3A2B2A1B1A0B0A}.
11596 \b \c{PUNPCKLWD} would return \c{0x3B2B3A2A1B0B1A0A}.
11598 \b \c{PUNPCKLDQ} would return \c{0x3B2B1B0B3A2A1A0A}.
11601 \S{insPUSH} \i\c{PUSH}: Push Data on Stack
11603 \c PUSH reg16 ; o16 50+r [8086]
11604 \c PUSH reg32 ; o32 50+r [386]
11606 \c PUSH r/m16 ; o16 FF /6 [8086]
11607 \c PUSH r/m32 ; o32 FF /6 [386]
11609 \c PUSH CS ; 0E [8086]
11610 \c PUSH DS ; 1E [8086]
11611 \c PUSH ES ; 06 [8086]
11612 \c PUSH SS ; 16 [8086]
11613 \c PUSH FS ; 0F A0 [386]
11614 \c PUSH GS ; 0F A8 [386]
11616 \c PUSH imm8 ; 6A ib [186]
11617 \c PUSH imm16 ; o16 68 iw [186]
11618 \c PUSH imm32 ; o32 68 id [386]
11620 \c{PUSH} decrements the stack pointer (\c{SP} or \c{ESP}) by 2 or 4,
11621 and then stores the given value at \c{[SS:SP]} or \c{[SS:ESP]}.
11623 The address-size attribute of the instruction determines whether
11624 \c{SP} or \c{ESP} is used as the stack pointer: to deliberately
11625 override the default given by the \c{BITS} setting, you can use an
11626 \i\c{a16} or \i\c{a32} prefix.
11628 The operand-size attribute of the instruction determines whether the
11629 stack pointer is decremented by 2 or 4: this means that segment
11630 register pushes in \c{BITS 32} mode will push 4 bytes on the stack,
11631 of which the upper two are undefined. If you need to override that,
11632 you can use an \i\c{o16} or \i\c{o32} prefix.
11634 The above opcode listings give two forms for general-purpose
11635 \i{register push} instructions: for example, \c{PUSH BX} has the two
11636 forms \c{53} and \c{FF F3}. NASM will always generate the shorter
11637 form when given \c{PUSH BX}. NDISASM will disassemble both.
11639 Unlike the undocumented and barely supported \c{POP CS}, \c{PUSH CS}
11640 is a perfectly valid and sensible instruction, supported on all
11643 The instruction \c{PUSH SP} may be used to distinguish an 8086 from
11644 later processors: on an 8086, the value of \c{SP} stored is the
11645 value it has \e{after} the push instruction, whereas on later
11646 processors it is the value \e{before} the push instruction.
11649 \S{insPUSHA} \i\c{PUSHAx}: Push All General-Purpose Registers
11651 \c PUSHA ; 60 [186]
11652 \c PUSHAD ; o32 60 [386]
11653 \c PUSHAW ; o16 60 [186]
11655 \c{PUSHAW} pushes, in succession, \c{AX}, \c{CX}, \c{DX}, \c{BX},
11656 \c{SP}, \c{BP}, \c{SI} and \c{DI} on the stack, decrementing the
11657 stack pointer by a total of 16.
11659 \c{PUSHAD} pushes, in succession, \c{EAX}, \c{ECX}, \c{EDX},
11660 \c{EBX}, \c{ESP}, \c{EBP}, \c{ESI} and \c{EDI} on the stack,
11661 decrementing the stack pointer by a total of 32.
11663 In both cases, the value of \c{SP} or \c{ESP} pushed is its
11664 \e{original} value, as it had before the instruction was executed.
11666 \c{PUSHA} is an alias mnemonic for either \c{PUSHAW} or \c{PUSHAD},
11667 depending on the current \c{BITS} setting.
11669 Note that the registers are pushed in order of their numeric values
11670 in opcodes (see \k{iref-rv}).
11672 See also \c{POPA} (\k{insPOPA}).
11675 \S{insPUSHF} \i\c{PUSHFx}: Push Flags Register
11677 \c PUSHF ; 9C [8086]
11678 \c PUSHFD ; o32 9C [386]
11679 \c PUSHFW ; o16 9C [8086]
11681 \b \c{PUSHFW} pops a word from the stack and stores it in the
11682 bottom 16 bits of the flags register (or the whole flags register,
11683 on processors below a 386).
11685 \b \c{PUSHFD} pops a doubleword and stores it in the entire flags
11688 \c{PUSHF} is an alias mnemonic for either \c{PUSHFW} or \c{PUSHFD},
11689 depending on the current \c{BITS} setting.
11691 See also \c{POPF} (\k{insPOPF}).
11694 \S{insPXOR} \i\c{PXOR}: MMX Bitwise XOR
11696 \c PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX]
11697 \c PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2]
11699 \c{PXOR} performs a bitwise XOR operation between its two operands
11700 (i.e. each bit of the result is 1 if and only if exactly one of the
11701 corresponding bits of the two inputs was 1), and stores the result
11702 in the destination (first) operand.
11705 \S{insRCL} \i\c{RCL}, \i\c{RCR}: Bitwise Rotate through Carry Bit
11707 \c RCL r/m8,1 ; D0 /2 [8086]
11708 \c RCL r/m8,CL ; D2 /2 [8086]
11709 \c RCL r/m8,imm8 ; C0 /2 ib [186]
11710 \c RCL r/m16,1 ; o16 D1 /2 [8086]
11711 \c RCL r/m16,CL ; o16 D3 /2 [8086]
11712 \c RCL r/m16,imm8 ; o16 C1 /2 ib [186]
11713 \c RCL r/m32,1 ; o32 D1 /2 [386]
11714 \c RCL r/m32,CL ; o32 D3 /2 [386]
11715 \c RCL r/m32,imm8 ; o32 C1 /2 ib [386]
11717 \c RCR r/m8,1 ; D0 /3 [8086]
11718 \c RCR r/m8,CL ; D2 /3 [8086]
11719 \c RCR r/m8,imm8 ; C0 /3 ib [186]
11720 \c RCR r/m16,1 ; o16 D1 /3 [8086]
11721 \c RCR r/m16,CL ; o16 D3 /3 [8086]
11722 \c RCR r/m16,imm8 ; o16 C1 /3 ib [186]
11723 \c RCR r/m32,1 ; o32 D1 /3 [386]
11724 \c RCR r/m32,CL ; o32 D3 /3 [386]
11725 \c RCR r/m32,imm8 ; o32 C1 /3 ib [386]
11727 \c{RCL} and \c{RCR} perform a 9-bit, 17-bit or 33-bit bitwise
11728 rotation operation, involving the given source/destination (first)
11729 operand and the carry bit. Thus, for example, in the operation
11730 \c{RCL AL,1}, a 9-bit rotation is performed in which \c{AL} is
11731 shifted left by 1, the top bit of \c{AL} moves into the carry flag,
11732 and the original value of the carry flag is placed in the low bit of
11735 The number of bits to rotate by is given by the second operand. Only
11736 the bottom five bits of the rotation count are considered by
11737 processors above the 8086.
11739 You can force the longer (286 and upwards, beginning with a \c{C1}
11740 byte) form of \c{RCL foo,1} by using a \c{BYTE} prefix: \c{RCL
11741 foo,BYTE 1}. Similarly with \c{RCR}.
11744 \S{insRCPPS} \i\c{RCPPS}: Packed Single-Precision FP Reciprocal
11746 \c RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE]
11748 \c{RCPPS} returns an approximation of the reciprocal of the packed
11749 single-precision FP values from xmm2/m128. The maximum error for this
11750 approximation is: |Error| <= 1.5 x 2^-12
11753 \S{insRCPSS} \i\c{RCPSS}: Scalar Single-Precision FP Reciprocal
11755 \c RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE]
11757 \c{RCPSS} returns an approximation of the reciprocal of the lower
11758 single-precision FP value from xmm2/m32; the upper three fields are
11759 passed through from xmm1. The maximum error for this approximation is:
11760 |Error| <= 1.5 x 2^-12
11763 \S{insRDMSR} \i\c{RDMSR}: Read Model-Specific Registers
11765 \c RDMSR ; 0F 32 [PENT,PRIV]
11767 \c{RDMSR} reads the processor Model-Specific Register (MSR) whose
11768 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11769 See also \c{WRMSR} (\k{insWRMSR}).
11772 \S{insRDPMC} \i\c{RDPMC}: Read Performance-Monitoring Counters
11774 \c RDPMC ; 0F 33 [P6]
11776 \c{RDPMC} reads the processor performance-monitoring counter whose
11777 index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}.
11779 This instruction is available on P6 and later processors and on MMX
11783 \S{insRDSHR} \i\c{RDSHR}: Read SMM Header Pointer Register
11785 \c RDSHR r/m32 ; 0F 36 /0 [386,CYRIX,SMM]
11787 \c{RDSHR} reads the contents of the SMM header pointer register and
11788 saves it to the destination operand, which can be either a 32 bit
11789 memory location or a 32 bit register.
11791 See also \c{WRSHR} (\k{insWRSHR}).
11794 \S{insRDTSC} \i\c{RDTSC}: Read Time-Stamp Counter
11796 \c RDTSC ; 0F 31 [PENT]
11798 \c{RDTSC} reads the processor's time-stamp counter into \c{EDX:EAX}.
11801 \S{insRET} \i\c{RET}, \i\c{RETF}, \i\c{RETN}: Return from Procedure Call
11804 \c RET imm16 ; C2 iw [8086]
11806 \c RETF ; CB [8086]
11807 \c RETF imm16 ; CA iw [8086]
11809 \c RETN ; C3 [8086]
11810 \c RETN imm16 ; C2 iw [8086]
11812 \b \c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from
11813 the stack and transfer control to the new address. Optionally, if a
11814 numeric second operand is provided, they increment the stack pointer
11815 by a further \c{imm16} bytes after popping the return address.
11817 \b \c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it
11818 then pops \c{CS}, and \e{then} increments the stack pointer by the
11819 optional argument if present.
11822 \S{insROL} \i\c{ROL}, \i\c{ROR}: Bitwise Rotate
11824 \c ROL r/m8,1 ; D0 /0 [8086]
11825 \c ROL r/m8,CL ; D2 /0 [8086]
11826 \c ROL r/m8,imm8 ; C0 /0 ib [186]
11827 \c ROL r/m16,1 ; o16 D1 /0 [8086]
11828 \c ROL r/m16,CL ; o16 D3 /0 [8086]
11829 \c ROL r/m16,imm8 ; o16 C1 /0 ib [186]
11830 \c ROL r/m32,1 ; o32 D1 /0 [386]
11831 \c ROL r/m32,CL ; o32 D3 /0 [386]
11832 \c ROL r/m32,imm8 ; o32 C1 /0 ib [386]
11834 \c ROR r/m8,1 ; D0 /1 [8086]
11835 \c ROR r/m8,CL ; D2 /1 [8086]
11836 \c ROR r/m8,imm8 ; C0 /1 ib [186]
11837 \c ROR r/m16,1 ; o16 D1 /1 [8086]
11838 \c ROR r/m16,CL ; o16 D3 /1 [8086]
11839 \c ROR r/m16,imm8 ; o16 C1 /1 ib [186]
11840 \c ROR r/m32,1 ; o32 D1 /1 [386]
11841 \c ROR r/m32,CL ; o32 D3 /1 [386]
11842 \c ROR r/m32,imm8 ; o32 C1 /1 ib [386]
11844 \c{ROL} and \c{ROR} perform a bitwise rotation operation on the given
11845 source/destination (first) operand. Thus, for example, in the
11846 operation \c{ROL AL,1}, an 8-bit rotation is performed in which
11847 \c{AL} is shifted left by 1 and the original top bit of \c{AL} moves
11848 round into the low bit.
11850 The number of bits to rotate by is given by the second operand. Only
11851 the bottom five bits of the rotation count are considered by processors
11854 You can force the longer (286 and upwards, beginning with a \c{C1}
11855 byte) form of \c{ROL foo,1} by using a \c{BYTE} prefix: \c{ROL
11856 foo,BYTE 1}. Similarly with \c{ROR}.
11859 \S{insRSDC} \i\c{RSDC}: Restore Segment Register and Descriptor
11861 \c RSDC segreg,m80 ; 0F 79 /r [486,CYRIX,SMM]
11863 \c{RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80,
11864 and sets up its descriptor.
11867 \S{insRSLDT} \i\c{RSLDT}: Restore Segment Register and Descriptor
11869 \c RSLDT m80 ; 0F 7B /0 [486,CYRIX,SMM]
11871 \c{RSLDT} restores the Local Descriptor Table (LDTR) from mem80.
11874 \S{insRSM} \i\c{RSM}: Resume from System-Management Mode
11876 \c RSM ; 0F AA [PENT]
11878 \c{RSM} returns the processor to its normal operating mode when it
11879 was in System-Management Mode.
11882 \S{insRSQRTPS} \i\c{RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal
11884 \c RSQRTPS xmm1,xmm2/m128 ; 0F 52 /r [KATMAI,SSE]
11886 \c{RSQRTPS} computes the approximate reciprocals of the square
11887 roots of the packed single-precision floating-point values in the
11888 source and stores the results in xmm1. The maximum error for this
11889 approximation is: |Error| <= 1.5 x 2^-12
11892 \S{insRSQRTSS} \i\c{RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal
11894 \c RSQRTSS xmm1,xmm2/m128 ; F3 0F 52 /r [KATMAI,SSE]
11896 \c{RSQRTSS} returns an approximation of the reciprocal of the
11897 square root of the lowest order single-precision FP value from
11898 the source, and stores it in the low doubleword of the destination
11899 register. The upper three fields of xmm1 are preserved. The maximum
11900 error for this approximation is: |Error| <= 1.5 x 2^-12
11903 \S{insRSTS} \i\c{RSTS}: Restore TSR and Descriptor
11905 \c RSTS m80 ; 0F 7D /0 [486,CYRIX,SMM]
11907 \c{RSTS} restores Task State Register (TSR) from mem80.
11910 \S{insSAHF} \i\c{SAHF}: Store AH to Flags
11912 \c SAHF ; 9E [8086]
11914 \c{SAHF} sets the low byte of the flags word according to the
11915 contents of the \c{AH} register.
11917 The operation of \c{SAHF} is:
11919 \c AH --> SF:ZF:0:AF:0:PF:1:CF
11921 See also \c{LAHF} (\k{insLAHF}).
11924 \S{insSAL} \i\c{SAL}, \i\c{SAR}: Bitwise Arithmetic Shifts
11926 \c SAL r/m8,1 ; D0 /4 [8086]
11927 \c SAL r/m8,CL ; D2 /4 [8086]
11928 \c SAL r/m8,imm8 ; C0 /4 ib [186]
11929 \c SAL r/m16,1 ; o16 D1 /4 [8086]
11930 \c SAL r/m16,CL ; o16 D3 /4 [8086]
11931 \c SAL r/m16,imm8 ; o16 C1 /4 ib [186]
11932 \c SAL r/m32,1 ; o32 D1 /4 [386]
11933 \c SAL r/m32,CL ; o32 D3 /4 [386]
11934 \c SAL r/m32,imm8 ; o32 C1 /4 ib [386]
11936 \c SAR r/m8,1 ; D0 /7 [8086]
11937 \c SAR r/m8,CL ; D2 /7 [8086]
11938 \c SAR r/m8,imm8 ; C0 /7 ib [186]
11939 \c SAR r/m16,1 ; o16 D1 /7 [8086]
11940 \c SAR r/m16,CL ; o16 D3 /7 [8086]
11941 \c SAR r/m16,imm8 ; o16 C1 /7 ib [186]
11942 \c SAR r/m32,1 ; o32 D1 /7 [386]
11943 \c SAR r/m32,CL ; o32 D3 /7 [386]
11944 \c SAR r/m32,imm8 ; o32 C1 /7 ib [386]
11946 \c{SAL} and \c{SAR} perform an arithmetic shift operation on the given
11947 source/destination (first) operand. The vacated bits are filled with
11948 zero for \c{SAL}, and with copies of the original high bit of the
11949 source operand for \c{SAR}.
11951 \c{SAL} is a synonym for \c{SHL} (see \k{insSHL}). NASM will
11952 assemble either one to the same code, but NDISASM will always
11953 disassemble that code as \c{SHL}.
11955 The number of bits to shift by is given by the second operand. Only
11956 the bottom five bits of the shift count are considered by processors
11959 You can force the longer (286 and upwards, beginning with a \c{C1}
11960 byte) form of \c{SAL foo,1} by using a \c{BYTE} prefix: \c{SAL
11961 foo,BYTE 1}. Similarly with \c{SAR}.
11964 \S{insSALC} \i\c{SALC}: Set AL from Carry Flag
11966 \c SALC ; D6 [8086,UNDOC]
11968 \c{SALC} is an early undocumented instruction similar in concept to
11969 \c{SETcc} (\k{insSETcc}). Its function is to set \c{AL} to zero if
11970 the carry flag is clear, or to \c{0xFF} if it is set.
11973 \S{insSBB} \i\c{SBB}: Subtract with Borrow
11975 \c SBB r/m8,reg8 ; 18 /r [8086]
11976 \c SBB r/m16,reg16 ; o16 19 /r [8086]
11977 \c SBB r/m32,reg32 ; o32 19 /r [386]
11979 \c SBB reg8,r/m8 ; 1A /r [8086]
11980 \c SBB reg16,r/m16 ; o16 1B /r [8086]
11981 \c SBB reg32,r/m32 ; o32 1B /r [386]
11983 \c SBB r/m8,imm8 ; 80 /3 ib [8086]
11984 \c SBB r/m16,imm16 ; o16 81 /3 iw [8086]
11985 \c SBB r/m32,imm32 ; o32 81 /3 id [386]
11987 \c SBB r/m16,imm8 ; o16 83 /3 ib [8086]
11988 \c SBB r/m32,imm8 ; o32 83 /3 ib [386]
11990 \c SBB AL,imm8 ; 1C ib [8086]
11991 \c SBB AX,imm16 ; o16 1D iw [8086]
11992 \c SBB EAX,imm32 ; o32 1D id [386]
11994 \c{SBB} performs integer subtraction: it subtracts its second
11995 operand, plus the value of the carry flag, from its first, and
11996 leaves the result in its destination (first) operand. The flags are
11997 set according to the result of the operation: in particular, the
11998 carry flag is affected and can be used by a subsequent \c{SBB}
12001 In the forms with an 8-bit immediate second operand and a longer
12002 first operand, the second operand is considered to be signed, and is
12003 sign-extended to the length of the first operand. In these cases,
12004 the \c{BYTE} qualifier is necessary to force NASM to generate this
12005 form of the instruction.
12007 To subtract one number from another without also subtracting the
12008 contents of the carry flag, use \c{SUB} (\k{insSUB}).
12011 \S{insSCASB} \i\c{SCASB}, \i\c{SCASW}, \i\c{SCASD}: Scan String
12013 \c SCASB ; AE [8086]
12014 \c SCASW ; o16 AF [8086]
12015 \c SCASD ; o32 AF [386]
12017 \c{SCASB} compares the byte in \c{AL} with the byte at \c{[ES:DI]}
12018 or \c{[ES:EDI]}, and sets the flags accordingly. It then increments
12019 or decrements (depending on the direction flag: increments if the
12020 flag is clear, decrements if it is set) \c{DI} (or \c{EDI}).
12022 The register used is \c{DI} if the address size is 16 bits, and
12023 \c{EDI} if it is 32 bits. If you need to use an address size not
12024 equal to the current \c{BITS} setting, you can use an explicit
12025 \i\c{a16} or \i\c{a32} prefix.
12027 Segment override prefixes have no effect for this instruction: the
12028 use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be
12031 \c{SCASW} and \c{SCASD} work in the same way, but they compare a
12032 word to \c{AX} or a doubleword to \c{EAX} instead of a byte to
12033 \c{AL}, and increment or decrement the addressing registers by 2 or
12036 The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
12037 \c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
12038 \c{ECX} - again, the address size chooses which) times until the
12039 first unequal or equal byte is found.
12042 \S{insSETcc} \i\c{SETcc}: Set Register from Condition
12044 \c SETcc r/m8 ; 0F 90+cc /2 [386]
12046 \c{SETcc} sets the given 8-bit operand to zero if its condition is
12047 not satisfied, and to 1 if it is.
12050 \S{insSFENCE} \i\c{SFENCE}: Store Fence
12052 \c SFENCE ; 0F AE /7 [KATMAI]
12054 \c{SFENCE} performs a serialising operation on all writes to memory
12055 that were issued before the \c{SFENCE} instruction. This guarantees that
12056 all memory writes before the \c{SFENCE} instruction are visible before any
12057 writes after the \c{SFENCE} instruction.
12059 \c{SFENCE} is ordered respective to other \c{SFENCE} instruction, \c{MFENCE},
12060 any memory write and any other serialising instruction (such as \c{CPUID}).
12062 Weakly ordered memory types can be used to achieve higher processor
12063 performance through such techniques as out-of-order issue,
12064 write-combining, and write-collapsing. The degree to which a consumer
12065 of data recognizes or knows that the data is weakly ordered varies
12066 among applications and may be unknown to the producer of this data.
12067 The \c{SFENCE} instruction provides a performance-efficient way of
12068 insuring store ordering between routines that produce weakly-ordered
12069 results and routines that consume this data.
12071 \c{SFENCE} uses the following ModRM encoding:
12074 \c Reg/Opcode (5:3) = 111B
12075 \c R/M (2:0) = 000B
12077 All other ModRM encodings are defined to be reserved, and use
12078 of these encodings risks incompatibility with future processors.
12080 See also \c{LFENCE} (\k{insLFENCE}) and \c{MFENCE} (\k{insMFENCE}).
12083 \S{insSGDT} \i\c{SGDT}, \i\c{SIDT}, \i\c{SLDT}: Store Descriptor Table Pointers
12085 \c SGDT mem ; 0F 01 /0 [286,PRIV]
12086 \c SIDT mem ; 0F 01 /1 [286,PRIV]
12087 \c SLDT r/m16 ; 0F 00 /0 [286,PRIV]
12089 \c{SGDT} and \c{SIDT} both take a 6-byte memory area as an operand:
12090 they store the contents of the GDTR (global descriptor table
12091 register) or IDTR (interrupt descriptor table register) into that
12092 area as a 32-bit linear address and a 16-bit size limit from that
12093 area (in that order). These are the only instructions which directly
12094 use \e{linear} addresses, rather than segment/offset pairs.
12096 \c{SLDT} stores the segment selector corresponding to the LDT (local
12097 descriptor table) into the given operand.
12099 See also \c{LGDT}, \c{LIDT} and \c{LLDT} (\k{insLGDT}).
12102 \S{insSHL} \i\c{SHL}, \i\c{SHR}: Bitwise Logical Shifts
12104 \c SHL r/m8,1 ; D0 /4 [8086]
12105 \c SHL r/m8,CL ; D2 /4 [8086]
12106 \c SHL r/m8,imm8 ; C0 /4 ib [186]
12107 \c SHL r/m16,1 ; o16 D1 /4 [8086]
12108 \c SHL r/m16,CL ; o16 D3 /4 [8086]
12109 \c SHL r/m16,imm8 ; o16 C1 /4 ib [186]
12110 \c SHL r/m32,1 ; o32 D1 /4 [386]
12111 \c SHL r/m32,CL ; o32 D3 /4 [386]
12112 \c SHL r/m32,imm8 ; o32 C1 /4 ib [386]
12114 \c SHR r/m8,1 ; D0 /5 [8086]
12115 \c SHR r/m8,CL ; D2 /5 [8086]
12116 \c SHR r/m8,imm8 ; C0 /5 ib [186]
12117 \c SHR r/m16,1 ; o16 D1 /5 [8086]
12118 \c SHR r/m16,CL ; o16 D3 /5 [8086]
12119 \c SHR r/m16,imm8 ; o16 C1 /5 ib [186]
12120 \c SHR r/m32,1 ; o32 D1 /5 [386]
12121 \c SHR r/m32,CL ; o32 D3 /5 [386]
12122 \c SHR r/m32,imm8 ; o32 C1 /5 ib [386]
12124 \c{SHL} and \c{SHR} perform a logical shift operation on the given
12125 source/destination (first) operand. The vacated bits are filled with
12128 A synonym for \c{SHL} is \c{SAL} (see \k{insSAL}). NASM will
12129 assemble either one to the same code, but NDISASM will always
12130 disassemble that code as \c{SHL}.
12132 The number of bits to shift by is given by the second operand. Only
12133 the bottom five bits of the shift count are considered by processors
12136 You can force the longer (286 and upwards, beginning with a \c{C1}
12137 byte) form of \c{SHL foo,1} by using a \c{BYTE} prefix: \c{SHL
12138 foo,BYTE 1}. Similarly with \c{SHR}.
12141 \S{insSHLD} \i\c{SHLD}, \i\c{SHRD}: Bitwise Double-Precision Shifts
12143 \c SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386]
12144 \c SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386]
12145 \c SHLD r/m16,reg16,CL ; o16 0F A5 /r [386]
12146 \c SHLD r/m16,reg32,CL ; o32 0F A5 /r [386]
12148 \c SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386]
12149 \c SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386]
12150 \c SHRD r/m16,reg16,CL ; o16 0F AD /r [386]
12151 \c SHRD r/m32,reg32,CL ; o32 0F AD /r [386]
12153 \b \c{SHLD} performs a double-precision left shift. It notionally
12154 places its second operand to the right of its first, then shifts
12155 the entire bit string thus generated to the left by a number of
12156 bits specified in the third operand. It then updates only the
12157 \e{first} operand according to the result of this. The second
12158 operand is not modified.
12160 \b \c{SHRD} performs the corresponding right shift: it notionally
12161 places the second operand to the \e{left} of the first, shifts the
12162 whole bit string right, and updates only the first operand.
12164 For example, if \c{EAX} holds \c{0x01234567} and \c{EBX} holds
12165 \c{0x89ABCDEF}, then the instruction \c{SHLD EAX,EBX,4} would update
12166 \c{EAX} to hold \c{0x12345678}. Under the same conditions, \c{SHRD
12167 EAX,EBX,4} would update \c{EAX} to hold \c{0xF0123456}.
12169 The number of bits to shift by is given by the third operand. Only
12170 the bottom five bits of the shift count are considered.
12173 \S{insSHUFPD} \i\c{SHUFPD}: Shuffle Packed Double-Precision FP Values
12175 \c SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2]
12177 \c{SHUFPD} moves one of the packed double-precision FP values from
12178 the destination operand into the low quadword of the destination
12179 operand; the upper quadword is generated by moving one of the
12180 double-precision FP values from the source operand into the
12181 destination. The select (third) operand selects which of the values
12182 are moved to the destination register.
12184 The select operand is an 8-bit immediate: bit 0 selects which value
12185 is moved from the destination operand to the result (where 0 selects
12186 the low quadword and 1 selects the high quadword) and bit 1 selects
12187 which value is moved from the source operand to the result.
12188 Bits 2 through 7 of the shuffle operand are reserved.
12191 \S{insSHUFPS} \i\c{SHUFPS}: Shuffle Packed Single-Precision FP Values
12193 \c SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE]
12195 \c{SHUFPS} moves two of the packed single-precision FP values from
12196 the destination operand into the low quadword of the destination
12197 operand; the upper quadword is generated by moving two of the
12198 single-precision FP values from the source operand into the
12199 destination. The select (third) operand selects which of the
12200 values are moved to the destination register.
12202 The select operand is an 8-bit immediate: bits 0 and 1 select the
12203 value to be moved from the destination operand the low doubleword of
12204 the result, bits 2 and 3 select the value to be moved from the
12205 destination operand the second doubleword of the result, bits 4 and
12206 5 select the value to be moved from the source operand the third
12207 doubleword of the result, and bits 6 and 7 select the value to be
12208 moved from the source operand to the high doubleword of the result.
12211 \S{insSMI} \i\c{SMI}: System Management Interrupt
12213 \c SMI ; F1 [386,UNDOC]
12215 \c{SMI} puts some AMD processors into SMM mode. It is available on some
12216 386 and 486 processors, and is only available when DR7 bit 12 is set,
12217 otherwise it generates an Int 1.
12220 \S{insSMINT} \i\c{SMINT}, \i\c{SMINTOLD}: Software SMM Entry (CYRIX)
12222 \c SMINT ; 0F 38 [PENT,CYRIX]
12223 \c SMINTOLD ; 0F 7E [486,CYRIX]
12225 \c{SMINT} puts the processor into SMM mode. The CPU state information is
12226 saved in the SMM memory header, and then execution begins at the SMM base
12229 \c{SMINTOLD} is the same as \c{SMINT}, but was the opcode used on the 486.
12231 This pair of opcodes are specific to the Cyrix and compatible range of
12232 processors (Cyrix, IBM, Via).
12235 \S{insSMSW} \i\c{SMSW}: Store Machine Status Word
12237 \c SMSW r/m16 ; 0F 01 /4 [286,PRIV]
12239 \c{SMSW} stores the bottom half of the \c{CR0} control register (or
12240 the Machine Status Word, on 286 processors) into the destination
12241 operand. See also \c{LMSW} (\k{insLMSW}).
12243 For 32-bit code, this would use the low 16-bits of the specified
12244 register (or a 16bit memory location), without needing an operand
12245 size override byte.
12248 \S{insSQRTPD} \i\c{SQRTPD}: Packed Double-Precision FP Square Root
12250 \c SQRTPD xmm1,xmm2/m128 ; 66 0F 51 /r [WILLAMETTE,SSE2]
12252 \c{SQRTPD} calculates the square root of the packed double-precision
12253 FP value from the source operand, and stores the double-precision
12254 results in the destination register.
12257 \S{insSQRTPS} \i\c{SQRTPS}: Packed Single-Precision FP Square Root
12259 \c SQRTPS xmm1,xmm2/m128 ; 0F 51 /r [KATMAI,SSE]
12261 \c{SQRTPS} calculates the square root of the packed single-precision
12262 FP value from the source operand, and stores the single-precision
12263 results in the destination register.
12266 \S{insSQRTSD} \i\c{SQRTSD}: Scalar Double-Precision FP Square Root
12268 \c SQRTSD xmm1,xmm2/m128 ; F2 0F 51 /r [WILLAMETTE,SSE2]
12270 \c{SQRTSD} calculates the square root of the low-order double-precision
12271 FP value from the source operand, and stores the double-precision
12272 result in the destination register. The high-quadword remains unchanged.
12275 \S{insSQRTSS} \i\c{SQRTSS}: Scalar Single-Precision FP Square Root
12277 \c SQRTSS xmm1,xmm2/m128 ; F3 0F 51 /r [KATMAI,SSE]
12279 \c{SQRTSS} calculates the square root of the low-order single-precision
12280 FP value from the source operand, and stores the single-precision
12281 result in the destination register. The three high doublewords remain
12285 \S{insSTC} \i\c{STC}, \i\c{STD}, \i\c{STI}: Set Flags
12291 These instructions set various flags. \c{STC} sets the carry flag;
12292 \c{STD} sets the direction flag; and \c{STI} sets the interrupt flag
12293 (thus enabling interrupts).
12295 To clear the carry, direction, or interrupt flags, use the \c{CLC},
12296 \c{CLD} and \c{CLI} instructions (\k{insCLC}). To invert the carry
12297 flag, use \c{CMC} (\k{insCMC}).
12300 \S{insSTMXCSR} \i\c{STMXCSR}: Store Streaming SIMD Extension
12303 \c STMXCSR m32 ; 0F AE /3 [KATMAI,SSE]
12305 \c{STMXCSR} stores the contents of the \c{MXCSR} control/status
12306 register to the specified memory location. \c{MXCSR} is used to
12307 enable masked/unmasked exception handling, to set rounding modes,
12308 to set flush-to-zero mode, and to view exception status flags.
12309 The reserved bits in the \c{MXCSR} register are stored as 0s.
12311 For details of the \c{MXCSR} register, see the Intel processor docs.
12313 See also \c{LDMXCSR} (\k{insLDMXCSR}).
12316 \S{insSTOSB} \i\c{STOSB}, \i\c{STOSW}, \i\c{STOSD}: Store Byte to String
12318 \c STOSB ; AA [8086]
12319 \c STOSW ; o16 AB [8086]
12320 \c STOSD ; o32 AB [386]
12322 \c{STOSB} stores the byte in \c{AL} at \c{[ES:DI]} or \c{[ES:EDI]},
12323 and sets the flags accordingly. It then increments or decrements
12324 (depending on the direction flag: increments if the flag is clear,
12325 decrements if it is set) \c{DI} (or \c{EDI}).
12327 The register used is \c{DI} if the address size is 16 bits, and
12328 \c{EDI} if it is 32 bits. If you need to use an address size not
12329 equal to the current \c{BITS} setting, you can use an explicit
12330 \i\c{a16} or \i\c{a32} prefix.
12332 Segment override prefixes have no effect for this instruction: the
12333 use of \c{ES} for the store to \c{[DI]} or \c{[EDI]} cannot be
12336 \c{STOSW} and \c{STOSD} work in the same way, but they store the
12337 word in \c{AX} or the doubleword in \c{EAX} instead of the byte in
12338 \c{AL}, and increment or decrement the addressing registers by 2 or
12341 The \c{REP} prefix may be used to repeat the instruction \c{CX} (or
12342 \c{ECX} - again, the address size chooses which) times.
12345 \S{insSTR} \i\c{STR}: Store Task Register
12347 \c STR r/m16 ; 0F 00 /1 [286,PRIV]
12349 \c{STR} stores the segment selector corresponding to the contents of
12350 the Task Register into its operand. When the operand size is a 16-bit
12351 register, the upper 16-bits are cleared to 0s. When the destination
12352 operand is a memory location, 16 bits are written regardless of the
12356 \S{insSUB} \i\c{SUB}: Subtract Integers
12358 \c SUB r/m8,reg8 ; 28 /r [8086]
12359 \c SUB r/m16,reg16 ; o16 29 /r [8086]
12360 \c SUB r/m32,reg32 ; o32 29 /r [386]
12362 \c SUB reg8,r/m8 ; 2A /r [8086]
12363 \c SUB reg16,r/m16 ; o16 2B /r [8086]
12364 \c SUB reg32,r/m32 ; o32 2B /r [386]
12366 \c SUB r/m8,imm8 ; 80 /5 ib [8086]
12367 \c SUB r/m16,imm16 ; o16 81 /5 iw [8086]
12368 \c SUB r/m32,imm32 ; o32 81 /5 id [386]
12370 \c SUB r/m16,imm8 ; o16 83 /5 ib [8086]
12371 \c SUB r/m32,imm8 ; o32 83 /5 ib [386]
12373 \c SUB AL,imm8 ; 2C ib [8086]
12374 \c SUB AX,imm16 ; o16 2D iw [8086]
12375 \c SUB EAX,imm32 ; o32 2D id [386]
12377 \c{SUB} performs integer subtraction: it subtracts its second
12378 operand from its first, and leaves the result in its destination
12379 (first) operand. The flags are set according to the result of the
12380 operation: in particular, the carry flag is affected and can be used
12381 by a subsequent \c{SBB} instruction (\k{insSBB}).
12383 In the forms with an 8-bit immediate second operand and a longer
12384 first operand, the second operand is considered to be signed, and is
12385 sign-extended to the length of the first operand. In these cases,
12386 the \c{BYTE} qualifier is necessary to force NASM to generate this
12387 form of the instruction.
12390 \S{insSUBPD} \i\c{SUBPD}: Packed Double-Precision FP Subtract
12392 \c SUBPD xmm1,xmm2/m128 ; 66 0F 5C /r [WILLAMETTE,SSE2]
12394 \c{SUBPD} subtracts the packed double-precision FP values of
12395 the source operand from those of the destination operand, and
12396 stores the result in the destination operation.
12399 \S{insSUBPS} \i\c{SUBPS}: Packed Single-Precision FP Subtract
12401 \c SUBPS xmm1,xmm2/m128 ; 0F 5C /r [KATMAI,SSE]
12403 \c{SUBPS} subtracts the packed single-precision FP values of
12404 the source operand from those of the destination operand, and
12405 stores the result in the destination operation.
12408 \S{insSUBSD} \i\c{SUBSD}: Scalar Single-FP Subtract
12410 \c SUBSD xmm1,xmm2/m128 ; F2 0F 5C /r [WILLAMETTE,SSE2]
12412 \c{SUBSD} subtracts the low-order double-precision FP value of
12413 the source operand from that of the destination operand, and
12414 stores the result in the destination operation. The high
12415 quadword is unchanged.
12418 \S{insSUBSS} \i\c{SUBSS}: Scalar Single-FP Subtract
12420 \c SUBSS xmm1,xmm2/m128 ; F3 0F 5C /r [KATMAI,SSE]
12422 \c{SUBSS} subtracts the low-order single-precision FP value of
12423 the source operand from that of the destination operand, and
12424 stores the result in the destination operation. The three high
12425 doublewords are unchanged.
12428 \S{insSVDC} \i\c{SVDC}: Save Segment Register and Descriptor
12430 \c SVDC m80,segreg ; 0F 78 /r [486,CYRIX,SMM]
12432 \c{SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its
12433 descriptor to mem80.
12436 \S{insSVLDT} \i\c{SVLDT}: Save LDTR and Descriptor
12438 \c SVLDT m80 ; 0F 7A /0 [486,CYRIX,SMM]
12440 \c{SVLDT} saves the Local Descriptor Table (LDTR) to mem80.
12443 \S{insSVTS} \i\c{SVTS}: Save TSR and Descriptor
12445 \c SVTS m80 ; 0F 7C /0 [486,CYRIX,SMM]
12447 \c{SVTS} saves the Task State Register (TSR) to mem80.
12450 \S{insSYSCALL} \i\c{SYSCALL}: Call Operating System
12452 \c SYSCALL ; 0F 05 [P6,AMD]
12454 \c{SYSCALL} provides a fast method of transferring control to a fixed
12455 entry point in an operating system.
12457 \b The \c{EIP} register is copied into the \c{ECX} register.
12459 \b Bits [31-0] of the 64-bit SYSCALL/SYSRET Target Address Register
12460 (\c{STAR}) are copied into the \c{EIP} register.
12462 \b Bits [47-32] of the \c{STAR} register specify the selector that is
12463 copied into the \c{CS} register.
12465 \b Bits [47-32]+1000b of the \c{STAR} register specify the selector that
12466 is copied into the SS register.
12468 The \c{CS} and \c{SS} registers should not be modified by the operating
12469 system between the execution of the \c{SYSCALL} instruction and its
12470 corresponding \c{SYSRET} instruction.
12472 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12473 (AMD document number 21086.pdf).
12476 \S{insSYSENTER} \i\c{SYSENTER}: Fast System Call
12478 \c SYSENTER ; 0F 34 [P6]
12480 \c{SYSENTER} executes a fast call to a level 0 system procedure or
12481 routine. Before using this instruction, various MSRs need to be set
12484 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12485 privilege level 0 code segment. (This value is also used to compute
12486 the segment selector of the privilege level 0 stack segment.)
12488 \b \c{SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege
12489 level 0 code segment to the first instruction of the selected operating
12490 procedure or routine.
12492 \b \c{SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the
12493 privilege level 0 stack.
12495 \c{SYSENTER} performs the following sequence of operations:
12497 \b Loads the segment selector from the \c{SYSENTER_CS_MSR} into the
12500 \b Loads the instruction pointer from the \c{SYSENTER_EIP_MSR} into
12501 the \c{EIP} register.
12503 \b Adds 8 to the value in \c{SYSENTER_CS_MSR} and loads it into the
12506 \b Loads the stack pointer from the \c{SYSENTER_ESP_MSR} into the
12509 \b Switches to privilege level 0.
12511 \b Clears the \c{VM} flag in the \c{EFLAGS} register, if the flag
12514 \b Begins executing the selected system procedure.
12516 In particular, note that this instruction des not save the values of
12517 \c{CS} or \c{(E)IP}. If you need to return to the calling code, you
12518 need to write your code to cater for this.
12520 For more information, see the Intel Architecture Software Developer's
12524 \S{insSYSEXIT} \i\c{SYSEXIT}: Fast Return From System Call
12526 \c SYSEXIT ; 0F 35 [P6,PRIV]
12528 \c{SYSEXIT} executes a fast return to privilege level 3 user code.
12529 This instruction is a companion instruction to the \c{SYSENTER}
12530 instruction, and can only be executed by privilege level 0 code.
12531 Various registers need to be set up before calling this instruction:
12533 \b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the
12534 privilege level 0 code segment in which the processor is currently
12535 executing. (This value is used to compute the segment selectors for
12536 the privilege level 3 code and stack segments.)
12538 \b \c{EDX} contains the 32-bit offset into the privilege level 3 code
12539 segment to the first instruction to be executed in the user code.
12541 \b \c{ECX} contains the 32-bit stack pointer for the privilege level 3
12544 \c{SYSEXIT} performs the following sequence of operations:
12546 \b Adds 16 to the value in \c{SYSENTER_CS_MSR} and loads the sum into
12547 the \c{CS} selector register.
12549 \b Loads the instruction pointer from the \c{EDX} register into the
12552 \b Adds 24 to the value in \c{SYSENTER_CS_MSR} and loads the sum
12553 into the \c{SS} selector register.
12555 \b Loads the stack pointer from the \c{ECX} register into the \c{ESP}
12558 \b Switches to privilege level 3.
12560 \b Begins executing the user code at the \c{EIP} address.
12562 For more information on the use of the \c{SYSENTER} and \c{SYSEXIT}
12563 instructions, see the Intel Architecture Software Developer's
12567 \S{insSYSRET} \i\c{SYSRET}: Return From Operating System
12569 \c SYSRET ; 0F 07 [P6,AMD,PRIV]
12571 \c{SYSRET} is the return instruction used in conjunction with the
12572 \c{SYSCALL} instruction to provide fast entry/exit to an operating system.
12574 \b The \c{ECX} register, which points to the next sequential instruction
12575 after the corresponding \c{SYSCALL} instruction, is copied into the \c{EIP}
12578 \b Bits [63-48] of the \c{STAR} register specify the selector that is copied
12579 into the \c{CS} register.
12581 \b Bits [63-48]+1000b of the \c{STAR} register specify the selector that is
12582 copied into the \c{SS} register.
12584 \b Bits [1-0] of the \c{SS} register are set to 11b (RPL of 3) regardless of
12585 the value of bits [49-48] of the \c{STAR} register.
12587 The \c{CS} and \c{SS} registers should not be modified by the operating
12588 system between the execution of the \c{SYSCALL} instruction and its
12589 corresponding \c{SYSRET} instruction.
12591 For more information, see the \c{SYSCALL and SYSRET Instruction Specification}
12592 (AMD document number 21086.pdf).
12595 \S{insTEST} \i\c{TEST}: Test Bits (notional bitwise AND)
12597 \c TEST r/m8,reg8 ; 84 /r [8086]
12598 \c TEST r/m16,reg16 ; o16 85 /r [8086]
12599 \c TEST r/m32,reg32 ; o32 85 /r [386]
12601 \c TEST r/m8,imm8 ; F6 /0 ib [8086]
12602 \c TEST r/m16,imm16 ; o16 F7 /0 iw [8086]
12603 \c TEST r/m32,imm32 ; o32 F7 /0 id [386]
12605 \c TEST AL,imm8 ; A8 ib [8086]
12606 \c TEST AX,imm16 ; o16 A9 iw [8086]
12607 \c TEST EAX,imm32 ; o32 A9 id [386]
12609 \c{TEST} performs a `mental' bitwise AND of its two operands, and
12610 affects the flags as if the operation had taken place, but does not
12611 store the result of the operation anywhere.
12614 \S{insUCOMISD} \i\c{UCOMISD}: Unordered Scalar Double-Precision FP
12615 compare and set EFLAGS
12617 \c UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2]
12619 \c{UCOMISD} compares the low-order double-precision FP numbers in the
12620 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12621 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12622 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12623 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12624 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12627 \S{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-Precision FP
12628 compare and set EFLAGS
12630 \c UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE]
12632 \c{UCOMISS} compares the low-order single-precision FP numbers in the
12633 two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the
12634 \c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits
12635 in the \c{EFLAGS} register are zeroed out. The unordered predicate
12636 (\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source
12637 operand is a \c{NaN} (\c{qNaN} or \c{sNaN}).
12640 \S{insUD2} \i\c{UD0}, \i\c{UD1}, \i\c{UD2}: Undefined Instruction
12642 \c UD0 ; 0F FF [186,UNDOC]
12643 \c UD1 ; 0F B9 [186,UNDOC]
12644 \c UD2 ; 0F 0B [186]
12646 \c{UDx} can be used to generate an invalid opcode exception, for testing
12649 \c{UD0} is specifically documented by AMD as being reserved for this
12652 \c{UD1} is documented by Intel as being available for this purpose.
12654 \c{UD2} is specifically documented by Intel as being reserved for this
12655 purpose. Intel document this as the preferred method of generating an
12656 invalid opcode exception.
12658 All these opcodes can be used to generate invalid opcode exceptions on
12659 all currently available processors.
12662 \S{insUMOV} \i\c{UMOV}: User Move Data
12664 \c UMOV r/m8,reg8 ; 0F 10 /r [386,UNDOC]
12665 \c UMOV r/m16,reg16 ; o16 0F 11 /r [386,UNDOC]
12666 \c UMOV r/m32,reg32 ; o32 0F 11 /r [386,UNDOC]
12668 \c UMOV reg8,r/m8 ; 0F 12 /r [386,UNDOC]
12669 \c UMOV reg16,r/m16 ; o16 0F 13 /r [386,UNDOC]
12670 \c UMOV reg32,r/m32 ; o32 0F 13 /r [386,UNDOC]
12672 This undocumented instruction is used by in-circuit emulators to
12673 access user memory (as opposed to host memory). It is used just like
12674 an ordinary memory/register or register/register \c{MOV}
12675 instruction, but accesses user space.
12677 This instruction is only available on some AMD and IBM 386 and 486
12681 \S{insUNPCKHPD} \i\c{UNPCKHPD}: Unpack and Interleave High Packed
12682 Double-Precision FP Values
12684 \c UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2]
12686 \c{UNPCKHPD} performs an interleaved unpack of the high-order data
12687 elements of the source and destination operands, saving the result
12688 in \c{xmm1}. It ignores the lower half of the sources.
12690 The operation of this instruction is:
12692 \c dst[63-0] := dst[127-64];
12693 \c dst[127-64] := src[127-64].
12696 \S{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack and Interleave High Packed
12697 Single-Precision FP Values
12699 \c UNPCKHPS xmm1,xmm2/m128 ; 0F 15 /r [KATMAI,SSE]
12701 \c{UNPCKHPS} performs an interleaved unpack of the high-order data
12702 elements of the source and destination operands, saving the result
12703 in \c{xmm1}. It ignores the lower half of the sources.
12705 The operation of this instruction is:
12707 \c dst[31-0] := dst[95-64];
12708 \c dst[63-32] := src[95-64];
12709 \c dst[95-64] := dst[127-96];
12710 \c dst[127-96] := src[127-96].
12713 \S{insUNPCKLPD} \i\c{UNPCKLPD}: Unpack and Interleave Low Packed
12714 Double-Precision FP Data
12716 \c UNPCKLPD xmm1,xmm2/m128 ; 66 0F 14 /r [WILLAMETTE,SSE2]
12718 \c{UNPCKLPD} performs an interleaved unpack of the low-order data
12719 elements of the source and destination operands, saving the result
12720 in \c{xmm1}. It ignores the lower half of the sources.
12722 The operation of this instruction is:
12724 \c dst[63-0] := dst[63-0];
12725 \c dst[127-64] := src[63-0].
12728 \S{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack and Interleave Low Packed
12729 Single-Precision FP Data
12731 \c UNPCKLPS xmm1,xmm2/m128 ; 0F 14 /r [KATMAI,SSE]
12733 \c{UNPCKLPS} performs an interleaved unpack of the low-order data
12734 elements of the source and destination operands, saving the result
12735 in \c{xmm1}. It ignores the lower half of the sources.
12737 The operation of this instruction is:
12739 \c dst[31-0] := dst[31-0];
12740 \c dst[63-32] := src[31-0];
12741 \c dst[95-64] := dst[63-32];
12742 \c dst[127-96] := src[63-32].
12745 \S{insVERR} \i\c{VERR}, \i\c{VERW}: Verify Segment Readability/Writability
12747 \c VERR r/m16 ; 0F 00 /4 [286,PRIV]
12749 \c VERW r/m16 ; 0F 00 /5 [286,PRIV]
12751 \b \c{VERR} sets the zero flag if the segment specified by the selector
12752 in its operand can be read from at the current privilege level.
12753 Otherwise it is cleared.
12755 \b \c{VERW} sets the zero flag if the segment can be written.
12758 \S{insWAIT} \i\c{WAIT}: Wait for Floating-Point Processor
12760 \c WAIT ; 9B [8086]
12761 \c FWAIT ; 9B [8086]
12763 \c{WAIT}, on 8086 systems with a separate 8087 FPU, waits for the
12764 FPU to have finished any operation it is engaged in before
12765 continuing main processor operations, so that (for example) an FPU
12766 store to main memory can be guaranteed to have completed before the
12767 CPU tries to read the result back out.
12769 On higher processors, \c{WAIT} is unnecessary for this purpose, and
12770 it has the alternative purpose of ensuring that any pending unmasked
12771 FPU exceptions have happened before execution continues.
12774 \S{insWBINVD} \i\c{WBINVD}: Write Back and Invalidate Cache
12776 \c WBINVD ; 0F 09 [486]
12778 \c{WBINVD} invalidates and empties the processor's internal caches,
12779 and causes the processor to instruct external caches to do the same.
12780 It writes the contents of the caches back to memory first, so no
12781 data is lost. To flush the caches quickly without bothering to write
12782 the data back first, use \c{INVD} (\k{insINVD}).
12785 \S{insWRMSR} \i\c{WRMSR}: Write Model-Specific Registers
12787 \c WRMSR ; 0F 30 [PENT]
12789 \c{WRMSR} writes the value in \c{EDX:EAX} to the processor
12790 Model-Specific Register (MSR) whose index is stored in \c{ECX}.
12791 See also \c{RDMSR} (\k{insRDMSR}).
12794 \S{insWRSHR} \i\c{WRSHR}: Write SMM Header Pointer Register
12796 \c WRSHR r/m32 ; 0F 37 /0 [386,CYRIX,SMM]
12798 \c{WRSHR} loads the contents of either a 32-bit memory location or a
12799 32-bit register into the SMM header pointer register.
12801 See also \c{RDSHR} (\k{insRDSHR}).
12804 \S{insXADD} \i\c{XADD}: Exchange and Add
12806 \c XADD r/m8,reg8 ; 0F C0 /r [486]
12807 \c XADD r/m16,reg16 ; o16 0F C1 /r [486]
12808 \c XADD r/m32,reg32 ; o32 0F C1 /r [486]
12810 \c{XADD} exchanges the values in its two operands, and then adds
12811 them together and writes the result into the destination (first)
12812 operand. This instruction can be used with a \c{LOCK} prefix for
12813 multi-processor synchronisation purposes.
12816 \S{insXBTS} \i\c{XBTS}: Extract Bit String
12818 \c XBTS reg16,r/m16 ; o16 0F A6 /r [386,UNDOC]
12819 \c XBTS reg32,r/m32 ; o32 0F A6 /r [386,UNDOC]
12821 The implied operation of this instruction is:
12823 \c XBTS r/m16,reg16,AX,CL
12824 \c XBTS r/m32,reg32,EAX,CL
12826 Writes a bit string from the source operand to the destination. \c{CL}
12827 indicates the number of bits to be copied, and \c{(E)AX} indicates the
12828 low order bit offset in the source. The bits are written to the low
12829 order bits of the destination register. For example, if \c{CL} is set
12830 to 4 and \c{AX} (for 16-bit code) is set to 5, bits 5-8 of \c{src} will
12831 be copied to bits 0-3 of \c{dst}. This instruction is very poorly
12832 documented, and I have been unable to find any official source of
12833 documentation on it.
12835 \c{XBTS} is supported only on the early Intel 386s, and conflicts with
12836 the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM supports it
12837 only for completeness. Its counterpart is \c{IBTS} (see \k{insIBTS}).
12840 \S{insXCHG} \i\c{XCHG}: Exchange
12842 \c XCHG reg8,r/m8 ; 86 /r [8086]
12843 \c XCHG reg16,r/m8 ; o16 87 /r [8086]
12844 \c XCHG reg32,r/m32 ; o32 87 /r [386]
12846 \c XCHG r/m8,reg8 ; 86 /r [8086]
12847 \c XCHG r/m16,reg16 ; o16 87 /r [8086]
12848 \c XCHG r/m32,reg32 ; o32 87 /r [386]
12850 \c XCHG AX,reg16 ; o16 90+r [8086]
12851 \c XCHG EAX,reg32 ; o32 90+r [386]
12852 \c XCHG reg16,AX ; o16 90+r [8086]
12853 \c XCHG reg32,EAX ; o32 90+r [386]
12855 \c{XCHG} exchanges the values in its two operands. It can be used
12856 with a \c{LOCK} prefix for purposes of multi-processor
12859 \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the \c{BITS}
12860 setting) generates the opcode \c{90h}, and so is a synonym for
12861 \c{NOP} (\k{insNOP}).
12864 \S{insXLATB} \i\c{XLATB}: Translate Byte in Lookup Table
12866 \c XLAT ; D7 [8086]
12867 \c XLATB ; D7 [8086]
12869 \c{XLATB} adds the value in \c{AL}, treated as an unsigned byte, to
12870 \c{BX} or \c{EBX}, and loads the byte from the resulting address (in
12871 the segment specified by \c{DS}) back into \c{AL}.
12873 The base register used is \c{BX} if the address size is 16 bits, and
12874 \c{EBX} if it is 32 bits. If you need to use an address size not
12875 equal to the current \c{BITS} setting, you can use an explicit
12876 \i\c{a16} or \i\c{a32} prefix.
12878 The segment register used to load from \c{[BX+AL]} or \c{[EBX+AL]}
12879 can be overridden by using a segment register name as a prefix (for
12880 example, \c{es xlatb}).
12883 \S{insXOR} \i\c{XOR}: Bitwise Exclusive OR
12885 \c XOR r/m8,reg8 ; 30 /r [8086]
12886 \c XOR r/m16,reg16 ; o16 31 /r [8086]
12887 \c XOR r/m32,reg32 ; o32 31 /r [386]
12889 \c XOR reg8,r/m8 ; 32 /r [8086]
12890 \c XOR reg16,r/m16 ; o16 33 /r [8086]
12891 \c XOR reg32,r/m32 ; o32 33 /r [386]
12893 \c XOR r/m8,imm8 ; 80 /6 ib [8086]
12894 \c XOR r/m16,imm16 ; o16 81 /6 iw [8086]
12895 \c XOR r/m32,imm32 ; o32 81 /6 id [386]
12897 \c XOR r/m16,imm8 ; o16 83 /6 ib [8086]
12898 \c XOR r/m32,imm8 ; o32 83 /6 ib [386]
12900 \c XOR AL,imm8 ; 34 ib [8086]
12901 \c XOR AX,imm16 ; o16 35 iw [8086]
12902 \c XOR EAX,imm32 ; o32 35 id [386]
12904 \c{XOR} performs a bitwise XOR operation between its two operands
12905 (i.e. each bit of the result is 1 if and only if exactly one of the
12906 corresponding bits of the two inputs was 1), and stores the result
12907 in the destination (first) operand.
12909 In the forms with an 8-bit immediate second operand and a longer
12910 first operand, the second operand is considered to be signed, and is
12911 sign-extended to the length of the first operand. In these cases,
12912 the \c{BYTE} qualifier is necessary to force NASM to generate this
12913 form of the instruction.
12915 The \c{MMX} instruction \c{PXOR} (see \k{insPXOR}) performs the same
12916 operation on the 64-bit \c{MMX} registers.
12919 \S{insXORPD} \i\c{XORPD}: Bitwise Logical XOR of Double-Precision FP Values
12921 \c XORPD xmm1,xmm2/m128 ; 66 0F 57 /r [WILLAMETTE,SSE2]
12923 \c{XORPD} returns a bit-wise logical XOR between the source and
12924 destination operands, storing the result in the destination operand.
12927 \S{insXORPS} \i\c{XORPS}: Bitwise Logical XOR of Single-Precision FP Values
12929 \c XORPS xmm1,xmm2/m128 ; 0F 57 /r [KATMAI,SSE]
12931 \c{XORPS} returns a bit-wise logical XOR between the source and
12932 destination operands, storing the result in the destination operand.