5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
9 env OPENSSL_ia32cap=... <application>
13 OpenSSL supports a range of x86[_64] instruction set extensions. These
14 extensions are denoted by individual bits in capability vector returned
15 by processor in EDX:ECX register pair after executing CPUID instruction
16 with EAX=1 input value (see Intel Application Note #241618). This vector
17 is copied to memory upon toolkit initialization and used to choose
18 between different code paths to provide optimal performance across wide
19 range of processors. For the moment of this writing following bits are
24 =item bit #4 denoting presence of Time-Stamp Counter.
26 =item bit #19 denoting availability of CLFLUSH instruction;
28 =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
30 =item bit #23 denoting MMX support;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
34 =item bit #25 denoting SSE support;
36 =item bit #26 denoting SSE2 support;
38 =item bit #28 denoting Hyperthreading, which is used to distinguish
39 cores with shared cache;
41 =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
45 =item bit #41 denoting SSSE3, Supplemental SSE3, support;
47 =item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
49 =item bit #54 denoting availability of MOVBE instruction;
51 =item bit #57 denoting AES-NI instruction set extension;
53 =item bit #58, XSAVE bit, lack of which in combination with MOVBE is used
54 to identify Atom Silvermont core;
56 =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
58 =item bit #60 denoting AVX extension;
60 =item bit #62 denoting availability of RDRAND instruction;
64 For example, in 32-bit application context clearing bit #26 at run-time
65 disables high-performance SSE2 code present in the crypto library, while
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
67 bank. You might have to do the latter if target OpenSSL application is
68 executed on SSE2 capable CPU, but under control of OS that does not
69 enable XMM registers. Historically address of the capability vector copy
70 was exposed to application through OPENSSL_ia32cap_loc(), but not
71 anymore. Now the only way to affect the capability detection is to set
72 OPENSSL_ia32cap environment variable prior target application start. To
73 give a specific example, on Intel P4 processor 'env
74 OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env
75 OPENSSL_ia32cap=~0x1000000 apps/openssl' would achieve the desired
76 effect. Alternatively you can reconfigure the toolkit with no-sse2
79 Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
80 variable" terms. The truth is that it's not copied from CPUID output
81 verbatim, but is adjusted to reflect whether or not the data cache is
82 actually shared between logical cores. This in turn affects the decision
83 on whether or not expensive countermeasures against cache-timing attacks
84 are applied, most notably in AES assembler module.
86 The capability vector is further extended with EBX value returned by
87 CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
91 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
93 =item bit #64+5 denoting availability of AVX2 instructions;
95 =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
98 =item bit #64+16 denoting availability of AVX512F extension;
100 =item bit #64+18 denoting availability of RDSEED instruction;
102 =item bit #64+19 denoting availability of ADCX and ADOX instructions;
104 =item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
105 aka AVX512IFMA extension;
107 =item bit #64+29 denoting availability of SHA extension;
109 =item bit #64+30 denoting availability of AVX512BW extension;
111 =item bit #64+31 denoting availability of AVX512VL extension;
113 =item bit #64+41 denoting availability of VAES extension;
115 =item bit #64+42 denoting availability of VPCLMULQDQ extension;
119 To control this extended capability word use ':' as delimiter when
120 setting up OPENSSL_ia32cap environment variable. For example assigning
121 ':~0x20' would disable AVX2 code paths, and ':0' - all post-AVX
124 It should be noted that whether or not some of the most "fancy"
125 extension code paths are actually assembled depends on current assembler
126 version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA extension code
127 paths are always assembled. Apart from that, minimum assembler version
128 requirements are summarized in below table:
130 Extension | GNU as | nasm | llvm
131 ------------+--------+--------+--------
132 AVX | 2.19 | 2.09 | 3.0
133 AVX2 | 2.22 | 2.10 | 3.1
134 ADCX/ADOX | 2.23 | 2.10 | 3.3
135 AVX512 | 2.25 | 2.11.8 | see NOTES
136 AVX512IFMA | 2.26 | 2.11.8 | see NOTES
137 VAES | 2.30 | 2.13.3 |
141 Even though AVX512 support was implemented in llvm 3.6, compilation of
142 assembly modules apparently requires explicit -march flag. But then
143 compiler generates processor-specific code, which in turn contradicts
144 the mere idea of run-time switch execution facilitated by the variable
145 in question. Till the limitation is lifted, it's possible to work around
146 the problem by making build procedure use following script:
149 exec clang -no-integrated-as "$@"
151 instead of real clang. In which case it doesn't matter which clang
152 version is used, as it is GNU assembler version that will be checked.
160 Copyright 2004-2020 The OpenSSL Project Authors. All Rights Reserved.
162 Licensed under the OpenSSL license (the "License"). You may not use
163 this file except in compliance with the License. You can obtain a copy
164 in the file LICENSE in the source distribution or at
165 L<https://www.openssl.org/source/license.html>.