1 Freescale ColdFire DSPI controller
4 - compatible : "fsl,mcf-dspi"
5 - #address-cells: <1>, as required by generic SPI binding
6 - #size-cells: <0>, also as required by generic SPI binding
7 - reg : offset and length of the register set for the device
10 - spi-max-frequency : max supported spi frequency
11 - num-cs : the number of the chipselect signals
12 - spi-mode: spi motorola mode, 0 to 3
13 - ctar-params: CTAR0 to 7 register configuration, as an array
14 of 8 integer fields for each register, where each register
15 is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
16 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
17 select and the start of clock signal, at the start of a transfer.
18 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
19 signal and deactivating chip select, at the end of a transfer.
23 dspi0: dspi@fc05c000 {
24 compatible = "fsl,mcf-dspi";
27 reg = <0xfc05c000 0x100>;
28 spi-max-frequency = <50000000>;
31 ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
32 <7, 0, 0, 0, 0, 0, 1, 6>,
33 <7, 0, 0, 0, 0, 0, 1, 6>;