1 TI K3 R5F processor subsystems
2 ==============================
4 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex
5 R5F processor subsystems/clusters (R5FSS). The dual core cluster can be
6 used either in a LockStep mode providing safety/fault tolerance features
7 or in a Split mode providing two individual compute cores for doubling
8 the compute capacity. These are used together with other processors
9 present on the SoC to achieve various system level goals.
11 R5F Sub-System Device Node:
12 ===========================
13 Each Dual-Core R5F sub-system is represented as a single DTS node representing
14 the cluster, with a pair of child DT nodes representing the individual R5F
15 cores. Each node has a number of required or optional properties that enable
16 the OS running on the host processor to perform the device management of the
17 remote processor and to communicate with the remote processor.
21 The following are the mandatory properties:
23 - compatible: Should be one of the following,
24 "ti,am654-r5fss" for R5F clusters/subsystems on
26 "ti,j721e-r5fss" for R5F clusters/subsystems on
28 "ti,j7200-r5fss" for R5F clusters/subsystems on
30 - power-domains: Should contain a phandle to a PM domain provider node
31 and an args specifier containing the R5FSS device id
32 value. This property is as per the binding,
33 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
34 - #address-cells: Should be 1
35 - #size-cells: Should be 1
36 - ranges: Standard ranges definition providing translations for
37 R5F TCM address spaces
41 - lockstep-mode: Configuration Mode for the Dual R5F cores within the R5F
42 cluster. Should be either a value of 1 (LockStep mode) or
43 0 (Split mode), default is LockStep mode if omitted.
46 R5F Processor Child Nodes:
47 ==========================
48 The R5F Sub-System device node should define two R5F child nodes, each node
49 representing a TI instantiation of the Arm Cortex R5F core. There are some
50 specific integration differences for the IP like the usage of a Region Address
51 Translator (RAT) for translating the larger SoC bus addresses into a 32-bit
52 address space for the processor.
56 The following are the mandatory properties:
58 - compatible: Should be one of the following,
59 "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
60 "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
61 "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
62 - reg: Should contain an entry for each value in 'reg-names'.
63 Each entry should have the memory region's start address
64 and the size of the region, the representation matching
65 the parent node's '#address-cells' and '#size-cells' values.
66 - reg-names: Should contain strings with the following names, each
67 representing a specific internal memory region, and
68 should be defined in this order,
70 - ti,sci: Should be a phandle to the TI-SCI System Controller node
71 - ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
72 R5F Core. Please refer to the corresponding System
73 Controller documentation for valid values for the R5F
75 - ti,sci-proc-ids: Should contain 2 integer values. The first cell should
76 contain the TI-SCI processor id for the R5F core device
77 and the second cell should contain the TI-SCI host id to
78 which the processor control ownership should be
80 - resets: Should contain the phandle to the reset controller node
81 managing the resets for this device, and a reset
82 specifier. Please refer to the following reset bindings
83 for the reset argument specifier,
84 Documentation/devicetree/bindings/reset/ti,sci-reset.txt
85 for AM65x, J721E and J7200 SoCs
89 The following properties are optional properties for each of the R5F cores:
91 - atcm-enable: R5F core configuration mode dictating if ATCM should be
92 enabled. Should be either a value of 1 (enabled) or
93 0 (disabled), default is disabled if omitted. R5F view
94 of ATCM dictated by loczrama property.
95 - btcm-enable: R5F core configuration mode dictating if BTCM should be
96 enabled. Should be either a value of 1 (enabled) or
97 0 (disabled), default is enabled if omitted. R5F view
98 of BTCM dictated by loczrama property.
99 - loczrama: R5F core configuration mode dictating which TCM should
100 appear at address 0 (from core's view). Should be either
101 a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default
102 value is 1 if omitted.
107 /* AM65x remoteproc alias */
109 remoteproc0 = &mcu_r5fss0_core0;
112 cbass_main: interconnect@100000 {
113 compatible = "simple-bus";
114 #address-cells = <2>;
116 ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
117 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
118 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
120 cbass_mcu: interconnect@28380000 {
121 compatible = "simple-bus";
122 #address-cells = <2>;
124 ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
125 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
126 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
128 /* AM65x MCU R5FSS node */
129 mcu_r5fss0: r5fss@41000000 {
130 compatible = "ti,am654-r5fss";
131 power-domains = <&k3_pds 129>;
133 #address-cells = <1>;
135 ranges = <0x41000000 0x00 0x41000000 0x20000>,
136 <0x41400000 0x00 0x41400000 0x20000>;
138 mcu_r5f0: r5f@41000000 {
139 compatible = "ti,am654-r5f";
140 reg = <0x41000000 0x00008000>,
141 <0x41010000 0x00008000>;
142 reg-names = "atcm", "btcm";
144 ti,sci-dev-id = <159>;
145 ti,sci-proc-ids = <0x01 0xFF>;
146 resets = <&k3_reset 159 1>;
152 mcu_r5f1: r5f@41400000 {
153 compatible = "ti,am654-r5f";
154 reg = <0x41400000 0x00008000>,
155 <0x41410000 0x00008000>;
156 reg-names = "atcm", "btcm";
158 ti,sci-dev-id = <245>;
159 ti,sci-proc-ids = <0x02 0xFF>;
160 resets = <&k3_reset 245 1>;