1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
13 | / 1|________________|
14 |_ PHY port#2 ----| |________________
16 |_ UTMI switch_______| OTG controller
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
27 - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
28 - #address-cells: number of address cells for phys sub-nodes, must be <1>
29 - #size-cells: number of size cells for phys sub-nodes, must be <0>
32 - assigned-clocks: phandle + clock specifier for the PLL phy clock
33 - assigned-clock-parents: the PLL phy clock parent
34 - resets: phandle + reset specifier
36 Required nodes: one sub-node per port the controller provides.
43 - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
44 see phy-bindings.txt in the same directory.
45 - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
46 port#1 and must be <1> for PHY port#2, to select USB controller
49 - vbus-supply: phandle to the regulator providing 5V vbus to the USB connector
52 usbphyc: usb-phy@5a006000 {
53 compatible = "st,stm32mp1-usbphyc";
54 reg = <0x5a006000 0x1000>;
55 clocks = <&rcc_clk USBPHY_K>;
56 resets = <&rcc_rst USBPHY_R>;
60 usbphyc_port0: usb-phy@0 {
62 phy-supply = <&vdd_usb>;
63 vdda1v1-supply = <®11>;
64 vdda1v8-supply = <®18>
68 usbphyc_port1: usb-phy@1 {
70 phy-supply = <&vdd_usb>;
71 vdda1v1-supply = <®11>;
72 vdda1v8-supply = <®18>