2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
7 Required properties (controller (parent) node):
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 - clocks : (deprecated, use port's clocks instead) a list of phandle +
11 clock-specifier pairs, one for each entry in clock-names
12 - clock-names : (deprecated, use port's one instead) must contain
13 "u3phya_ref": for reference clock of usb3.0 analog phy.
15 Required nodes : a sub-node is required for each port the controller
16 provides. Address range information including the usual
17 'reg' property is used inside these nodes to describe
18 the controller's topology.
20 Optional properties (controller (parent) node):
21 - reg : offset and length of register shared by multiple ports,
22 exclude port's private register.
23 - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
25 - mediatek,src-coef : coefficient for slew rate calibrate, depends on
28 Required properties (port (child) node):
29 - reg : address and length of the register set for the port.
30 - clocks : a list of phandle + clock-specifier pairs, one for each
32 - clock-names : must contain
33 "ref": 48M reference clock for HighSpeed analog phy; and 26M
34 reference clock for SuperSpeed analog phy, sometimes is
35 24M, 25M or 27M, depended on platform.
36 - #phy-cells : should be 1 (See second example)
37 cell after port phandle is phy type from:
45 u3phy2: usb-phy@1a244000 {
46 compatible = "mediatek,generic-tphy-v1";
47 reg = <0x1a244000 0x0700>;
53 u2port1: usb-phy@1a244800 {
54 reg = <0x1a244800 0x0100>;
55 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
61 u3port1: usb-phy@1a244900 {
62 reg = <0x1a244900 0x0700>;
70 Specifying phy control of devices
71 ---------------------------------
73 Device nodes should specify the configuration required in their "phys"
74 property, containing a phandle to the phy port node and a device type;
75 phy-names for each port are optional.
79 #include <dt-bindings/phy/phy.h>
83 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
84 phy-names = "usb2-0", "usb3-0";