doc/device-tree-bindings/misc/intel,baytrail-fsp.txt

   1 Intel Bay Trail FSP UPD Binding
   2 ===============================
   3
   4 The device tree node which describes the overriding of the Intel Bay Trail FSP
   5 UPD data for configuring the SoC.
   6
   7 All properties can be found within the `upd-region` struct in
   8 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
   9 Intel's FSP Binary Configuration Tool for Bay Trail.  This list of properties is
  10 matched up to Intel's E3800 FSPv4 release.
  11
  12 # Boolean properties:
  13
  14 - fsp,enable-sdio
  15 - fsp,enable-sdcard
  16 - fsp,enable-hsuart0
  17 - fsp,enable-hsuart1
  18 - fsp,enable-spi
  19 - fsp,enable-sata
  20 - fsp,enable-azalia
  21 - fsp,enable-xhci
  22 - fsp,enable-lpe
  23 - fsp,lpss-sio-enable-pci-mode
  24 - fsp,enable-dma0
  25 - fsp,enable-dma1
  26 - fsp,enable-i2-c0
  27 - fsp,enable-i2-c1
  28 - fsp,enable-i2-c2
  29 - fsp,enable-i2-c3
  30 - fsp,enable-i2-c4
  31 - fsp,enable-i2-c5
  32 - fsp,enable-i2-c6
  33 - fsp,enable-pwm0
  34 - fsp,enable-pwm1
  35 - fsp,enable-hsi
  36 - fsp,mrc-debug-msg
  37 - fsp,isp-enable
  38 - fsp,scc-enable-pci-mode
  39 - fsp,igd-render-standby
  40 - fsp,txe-uma-enable
  41 - fsp,emmc45-ddr50-enabled
  42 - fsp,emmc45-hs200-enabled
  43 - fsp,enable-igd
  44 - fsp,enable-memory-down
  45
  46 If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
  47 "fsp,memory-down-params{};" to specify how your memory is configured.  If you do
  48 not set "fsp,enable-memory-down", then the DIMM SPD information will be
  49 discovered by the FSP and used to setup main memory.
  50
  51
  52 # Integer properties:
  53
  54 - fsp,mrc-init-tseg-size
  55 - fsp,mrc-init-mmio-size
  56 - fsp,mrc-init-spd-addr1
  57 - fsp,mrc-init-spd-addr2
  58 - fsp,emmc-boot-mode
  59 - fsp,sata-mode
  60 - fsp,igd-dvmt50-pre-alloc
  61 - fsp,aperture-size
  62 - fsp,gtt-size
  63 - fsp,serial-debug-port-address
  64 - fsp,serial-debug-port-type
  65 - fsp,os-selection
  66 - fsp,emmc45-retune-timer-value
  67
  68 - fsp,memory-down-params {
  69
  70         # Boolean properties:
  71
  72         - fsp,dimm-0-enable
  73         - fsp,dimm-1-enable
  74
  75         # Integer properties:
  76
  77         - fsp,dram-speed:
  78           0x0: "800 MHz"
  79           0x1: "1066 MHz"
  80           0x2: "1333 MHz"
  81           0x3: "1600 MHz"
  82
  83         - fsp,dram-type
  84           0x0: "DDR3"
  85           0x1: "DDR3L"
  86           0x2: "DDR3U"
  87           0x4: "LPDDR2"
  88           0x5: "LPDDR3"
  89           0x6: "DDR4"
  90
  91         - fsp,dimm-width
  92           0x0: "x8"
  93           0x1: "x16"
  94           0x2: "x32"
  95
  96         - fsp,dimm-density
  97           0x0: "1 Gbit"
  98           0x1: "2 Gbit"
  99           0x2: "4 Gbit"
 100           0x3: "8 Gbit"
 101
 102         - fsp,dimm-bus-width
 103           0x0: "8 bits"
 104           0x1: "16 bits"
 105           0x2: "32 bits"
 106           0x3: "64 bits"
 107
 108         - fsp,dimm-sides
 109           0x0: "1 rank"
 110           0x1: "2 ranks"
 111
 112         - fsp,dimm-tcl
 113         - fsp,dimm-trpt-rcd
 114         - fsp,dimm-twr
 115         - fsp,dimm-twtr
 116         - fsp,dimm-trrd
 117         - fsp,dimm-trtp
 118         - fsp,dimm-tfaw
 119 };
 120
 121
 122 Example (from MinnowMax Dual Core):
 123 -----------------------------------
 124
 125 / {
 126         ...
 127
 128         fsp {
 129                 compatible = "intel,baytrail-fsp";
 130                 fsp,mrc-init-tseg-size = <0>;
 131                 fsp,mrc-init-mmio-size = <0x800>;
 132                 fsp,mrc-init-spd-addr1 = <0xa0>;
 133                 fsp,mrc-init-spd-addr2 = <0xa2>;
 134                 fsp,emmc-boot-mode = <2>;
 135                 fsp,enable-sdio;
 136                 fsp,enable-sdcard;
 137                 fsp,enable-hsuart1;
 138                 fsp,enable-spi;
 139                 fsp,enable-sata;
 140                 fsp,sata-mode = <1>;
 141                 fsp,enable-xhci;
 142                 fsp,enable-lpe;
 143                 fsp,lpss-sio-enable-pci-mode;
 144                 fsp,enable-dma0;
 145                 fsp,enable-dma1;
 146                 fsp,enable-i2c0;
 147                 fsp,enable-i2c1;
 148                 fsp,enable-i2c2;
 149                 fsp,enable-i2c3;
 150                 fsp,enable-i2c4;
 151                 fsp,enable-i2c5;
 152                 fsp,enable-i2c6;
 153                 fsp,enable-pwm0;
 154                 fsp,enable-pwm1;
 155                 fsp,igd-dvmt50-pre-alloc = <2>;
 156                 fsp,aperture-size = <2>;
 157                 fsp,gtt-size = <2>;
 158                 fsp,serial-debug-port-address = <0x3f8>;
 159                 fsp,serial-debug-port-type = <1>;
 160                 fsp,mrc-debug-msg;
 161                 fsp,scc-enable-pci-mode;
 162                 fsp,os-selection = <4>;
 163                 fsp,emmc45-ddr50-enabled;
 164                 fsp,emmc45-retune-timer-value = <8>;
 165                 fsp,enable-igd;
 166                 fsp,enable-memory-down;
 167                 fsp,memory-down-params {
 168                         compatible = "intel,baytrail-fsp-mdp";
 169                         fsp,dram-speed = <1>;
 170                         fsp,dram-type = <1>;
 171                         fsp,dimm-0-enable;
 172                         fsp,dimm-width = <1>;
 173                         fsp,dimm-density = <2>;
 174                         fsp,dimm-bus-width = <3>;
 175                         fsp,dimm-sides = <0>;
 176                         fsp,dimm-tcl = <0xb>;
 177                         fsp,dimm-trpt-rcd = <0xb>;
 178                         fsp,dimm-twr = <0xc>;
 179                         fsp,dimm-twtr = <6>;
 180                         fsp,dimm-trrd = <6>;
 181                         fsp,dimm-trtp = <6>;
 182                         fsp,dimm-tfaw = <0x14>;
 183                 };
 184         };
 185
 186         ...
 187 };