doc/device-tree-bindings/clock/st,stm32mp1.txt

   1 STMicroelectronics STM32MP1 clock tree initialization
   2 =====================================================
   3
   4 The STM32MP1 clock tree initialization is based on device tree information
   5 for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
   6
   7 RCC IP = st,stm32mp1-rcc
   8 ========================
   9
  10 The RCC IP is both a reset and a clock controller but this documentation only
  11 describes the fields added for clock tree initialization which are not present
  12 in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
  13 file.
  14
  15 The added properties for clock tree initialization are:
  16
  17 Required properties:
  18 - st,clksrc : The clock sources configuration array in a platform specific
  19               order.
  20
  21   For the STM32MP15x family there are 9 clock sources selector which are
  22   configured in the following order:
  23         MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
  24
  25   Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
  26   from dt-bindings/clock/stm32mp1-clksrc.h.
  27
  28   Example:
  29         st,clksrc = <
  30                 CLK_MPU_PLL1P
  31                 CLK_AXI_PLL2P
  32                 CLK_MCU_PLL3P
  33                 CLK_PLL12_HSE
  34                 CLK_PLL3_HSE
  35                 CLK_PLL4_HSE
  36                 CLK_RTC_LSE
  37                 CLK_MCO1_DISABLED
  38                 CLK_MCO2_DISABLED
  39         >;
  40
  41 - st,clkdiv : The clock main dividers value specified in an array
  42               in a platform specific order.
  43
  44   When used, it shall describe the whole clock dividers tree.
  45
  46   For the STM32MP15x family there are 11 dividers values expected.
  47   They shall be configured in the following order:
  48                 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
  49
  50   The each divider value uses the DIV coding defined in RCC associated
  51   register RCC_xxxDIVR. In most the case, it is:
  52                 0x0: not divided
  53                 0x1: division by 2
  54                 0x2: division by 4
  55                 0x3: division by 8
  56                 ...
  57
  58   Note that for RTC MCO1 MCO2, the coding is different:
  59                 0x0: not divided
  60                 0x1: division by 2
  61                 0x2: division by 3
  62                 0x3: division by 4
  63                 ...
  64
  65   Example:
  66         st,clkdiv = <
  67                 1 /*MPU*/
  68                 0 /*AXI*/
  69                 0 /*MCU*/
  70                 1 /*APB1*/
  71                 1 /*APB2*/
  72                 1 /*APB3*/
  73                 1 /*APB4*/
  74                 2 /*APB5*/
  75                 23 /*RTC*/
  76                 0 /*MCO1*/
  77                 0 /*MCO2*/
  78         >;
  79
  80 Optional Properties:
  81 - st,pll : A specific PLL configuration, including frequency.
  82
  83   PLL children nodes for PLL1 to PLL4 (see ref manual for details)
  84   are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
  85   PLLx is off when the associated node is absent.
  86
  87   Here are the available properties for each PLL node:
  88
  89     - cfg: The parameters for PLL configuration in the following order:
  90            DIVM DIVN DIVP DIVQ DIVR Output.
  91
  92         DIVx values are defined as in RCC spec:
  93                 0x0: bypass (division by 1)
  94                 0x1: division by 2
  95                 0x2: division by 3
  96                 0x3: division by 4
  97                 ...
  98
  99         Output contains a bitfield for each output value (1:ON/0:OFF)
 100                 BIT(0) => output P : DIVPEN
 101                 BIT(1) => output Q : DIVQEN
 102                 BIT(2) => output R : DIVREN
 103           NB: macro PQR(p,q,r) can be used to build this value
 104               with p,q,r = 0 or 1.
 105
 106     - frac : Fractional part of the multiplication factor
 107              (optional, PLL is in integer mode when absent).
 108
 109     - csg : Clock Spreading Generator (optional) with parameters in the
 110             following order: MOD_PER INC_STEP SSCG_MODE.
 111
 112         MOD_PER: Modulation Period Adjustment
 113         INC_STEP: Modulation Depth Adjustment
 114         SSCG_MODE: Spread spectrum clock generator mode, with associated
 115                    defined from stm32mp1-clksrc.h:
 116                         - SSCG_MODE_CENTER_SPREAD = 0
 117                         - SSCG_MODE_DOWN_SPREAD = 1
 118
 119     Example:
 120         st,pll@0 {
 121                 cfg = < 1 53 0 0 0 1 >;
 122                 frac = < 0x810 >;
 123         };
 124         st,pll@1 {
 125                 cfg = < 1 43 1 0 0 PQR(0,1,1) >;
 126                 csg = < 10 20 1 >;
 127         };
 128         st,pll@2 {
 129                 cfg = < 2 85 3 13 3 0 >;
 130                 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
 131                 };
 132         st,pll@3 {
 133                 cfg = < 2 78 4 7 9 3 >;
 134         };
 135
 136 - st,pkcs : used to configure the peripherals kernel clock selection.
 137
 138   The property is a list of peripheral kernel clock source identifiers defined
 139   by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
 140   dt-bindings/clock/stm32mp1-clksrc.h.
 141
 142   st,pkcs may not list all the kernel clocks and has no ordering requirements.
 143
 144   Example:
 145         st,pkcs = <
 146                 CLK_STGEN_HSE
 147                 CLK_CKPER_HSI
 148                 CLK_USBPHY_PLL2P
 149                 CLK_DSI_PLL2Q
 150                 CLK_I2C46_HSI
 151                 CLK_UART1_HSI
 152                 CLK_UART24_HSI
 153         >;
 154
 155 other clocks = fixed-clock
 156 ==========================
 157
 158 The clock tree is also based on 5 fixed-clock in clocks node
 159 used to define the state of associated ST32MP1 oscillators:
 160   - clk-lsi
 161   - clk-lse
 162   - clk-hsi
 163   - clk-hse
 164   - clk-csi
 165
 166 At boot the clock tree initialization will
 167   - enable oscillators present in device tree
 168   - disable HSI oscillator if the node is absent (always activated by bootrom)
 169
 170 Optional properties :
 171
 172 a) for external oscillator: "clk-lse", "clk-hse"
 173
 174   4 optional fields are managed
 175   - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
 176   - "st,digbypass" configures the bypass mode as full-swing digital
 177     signal (DIGBYP)
 178   - "st,css" activates the clock security system (HSECSSON, LSECSSON)
 179   - "st,drive" (only for LSE) contains the value of the drive for the
 180      oscillator (see LSEDRV_ defined in the file
 181      dt-bindings/clock/stm32mp1-clksrc.h)
 182
 183   Example board file:
 184         / {
 185                 clocks {
 186                         clk_hse: clk-hse {
 187                                 #clock-cells = <0>;
 188                                 compatible = "fixed-clock";
 189                                 clock-frequency = <64000000>;
 190                                 st,bypass;
 191                         };
 192
 193                         clk_lse: clk-lse {
 194                                 #clock-cells = <0>;
 195                                 compatible = "fixed-clock";
 196                                 clock-frequency = <32768>;
 197                                 st,css;
 198                                 st,drive = <LSEDRV_LOWEST>;
 199                         };
 200         };
 201
 202 b) for internal oscillator: "clk-hsi"
 203
 204   Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
 205   In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
 206   doc). So this clock frequency is used to compute the expected HSI_DIV
 207   for the clock tree initialization.
 208
 209   Example with HSIDIV = /1:
 210         / {
 211                 clocks {
 212                         clk_hsi: clk-hsi {
 213                                 #clock-cells = <0>;
 214                                 compatible = "fixed-clock";
 215                                 clock-frequency = <64000000>;
 216                         };
 217         };
 218
 219   Example with HSIDIV = /2
 220         / {
 221                 clocks {
 222                         clk_hsi: clk-hsi {
 223                                 #clock-cells = <0>;
 224                                 compatible = "fixed-clock";
 225                                 clock-frequency = <32000000>;
 226                         };
 227         };
 228
 229 Example of clock tree initialization
 230 ====================================
 231
 232 / {
 233         clocks {
 234                 u-boot,dm-pre-reloc;
 235                 clk_hse: clk-hse {
 236                         u-boot,dm-pre-reloc;
 237                         #clock-cells = <0>;
 238                         compatible = "fixed-clock";
 239                         clock-frequency = <24000000>;
 240                         st,digbypass;
 241                 };
 242
 243                 clk_hsi: clk-hsi {
 244                         u-boot,dm-pre-reloc;
 245                         #clock-cells = <0>;
 246                         compatible = "fixed-clock";
 247                         clock-frequency = <64000000>;
 248                 };
 249
 250                 clk_lse: clk-lse {
 251                         u-boot,dm-pre-reloc;
 252                         #clock-cells = <0>;
 253                         compatible = "fixed-clock";
 254                         clock-frequency = <32768>;
 255                 };
 256
 257                 clk_lsi: clk-lsi {
 258                         u-boot,dm-pre-reloc;
 259                         #clock-cells = <0>;
 260                         compatible = "fixed-clock";
 261                         clock-frequency = <32000>;
 262                 };
 263
 264                 clk_csi: clk-csi {
 265                         u-boot,dm-pre-reloc;
 266                         #clock-cells = <0>;
 267                         compatible = "fixed-clock";
 268                         clock-frequency = <4000000>;
 269                 };
 270         };
 271
 272         soc {
 273
 274                 rcc: rcc@50000000 {
 275                         u-boot,dm-pre-reloc;
 276                         compatible = "st,stm32mp1-rcc", "syscon";
 277                         reg = <0x50000000 0x1000>;
 278                         #clock-cells = <1>;
 279                         #reset-cells = <1>;
 280                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 281
 282                         st,clksrc = <
 283                                 CLK_MPU_PLL1P
 284                                 CLK_AXI_PLL2P
 285                                 CLK_MCU_PLL3P
 286                                 CLK_PLL12_HSE
 287                                 CLK_PLL3_HSE
 288                                 CLK_PLL4_HSE
 289                                 CLK_RTC_LSE
 290                                 CLK_MCO1_DISABLED
 291                                 CLK_MCO2_DISABLED
 292                         >;
 293
 294                         st,clkdiv = <
 295                                 1 /*MPU*/
 296                                 0 /*AXI*/
 297                                 0 /*MCU*/
 298                                 1 /*APB1*/
 299                                 1 /*APB2*/
 300                                 1 /*APB3*/
 301                                 1 /*APB4*/
 302                                 2 /*APB5*/
 303                                 23 /*RTC*/
 304                                 0 /*MCO1*/
 305                                 0 /*MCO2*/
 306                         >;
 307
 308                         st,pkcs = <
 309                                 CLK_CKPER_HSE
 310                                 CLK_FMC_ACLK
 311                                 CLK_QSPI_ACLK
 312                                 CLK_ETH_DISABLED
 313                                 CLK_SDMMC12_PLL4P
 314                                 CLK_DSI_DSIPLL
 315                                 CLK_STGEN_HSE
 316                                 CLK_USBPHY_HSE
 317                                 CLK_SPI2S1_PLL3Q
 318                                 CLK_SPI2S23_PLL3Q
 319                                 CLK_SPI45_HSI
 320                                 CLK_SPI6_HSI
 321                                 CLK_I2C46_HSI
 322                                 CLK_SDMMC3_PLL4P
 323                                 CLK_USBO_USBPHY
 324                                 CLK_ADC_CKPER
 325                                 CLK_CEC_LSE
 326                                 CLK_I2C12_HSI
 327                                 CLK_I2C35_HSI
 328                                 CLK_UART1_HSI
 329                                 CLK_UART24_HSI
 330                                 CLK_UART35_HSI
 331                                 CLK_UART6_HSI
 332                                 CLK_UART78_HSI
 333                                 CLK_SPDIF_PLL4P
 334                                 CLK_FDCAN_PLL4Q
 335                                 CLK_SAI1_PLL3Q
 336                                 CLK_SAI2_PLL3Q
 337                                 CLK_SAI3_PLL3Q
 338                                 CLK_SAI4_PLL3Q
 339                                 CLK_RNG1_LSI
 340                                 CLK_RNG2_LSI
 341                                 CLK_LPTIM1_PCLK1
 342                                 CLK_LPTIM23_PCLK3
 343                                 CLK_LPTIM45_LSE
 344                         >;
 345
 346                         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 347                         pll1: st,pll@0 {
 348                                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 349                                 frac = < 0x800 >;
 350                                 u-boot,dm-pre-reloc;
 351                         };
 352
 353                         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
 354                                                R = 533 (DDR) */
 355                         pll2: st,pll@1 {
 356                                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 357                                 frac = < 0x1400 >;
 358                                 u-boot,dm-pre-reloc;
 359                         };
 360
 361                         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 362                         pll3: st,pll@2 {
 363                                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 364                                 frac = < 0x1a04 >;
 365                                 u-boot,dm-pre-reloc;
 366                         };
 367
 368                         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 369                         pll4: st,pll@3 {
 370                                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 371                                 u-boot,dm-pre-reloc;
 372                         };
 373                 };
 374         };
 375 };