1 .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 .. sectionauthor:: Lokesh Vutla <lokeshvutla@ti.com>
9 The J721e family of SoCs are part of K3 Multicore SoC architecture platform
10 targeting automotive applications. They are designed as a low power, high
11 performance and highly integrated device architecture, adding significant
12 enhancement on processing power, graphics capability, video and imaging
13 processing, virtualization and coherent memory support.
15 The device is partitioned into three functional domains, each containing
16 specific processing cores and peripherals:
18 1. Wake-up (WKUP) domain:
19 * Device Management and Security Controller (DMSC)
21 2. Microcontroller (MCU) domain:
22 * Dual Core ARM Cortex-R5F processor
25 * Dual core 64-bit ARM Cortex-A72
26 * 2 x Dual cortex ARM Cortex-R5 subsystem
27 * 2 x C66x Digital signal processor sub system
28 * C71x Digital signal processor sub-system with MMA.
30 More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
34 * https://www.ti.com/tool/J721EXSOMXEVM
35 * https://www.ti.com/tool/SK-TDA4VM
39 Boot flow is similar to that of AM65x SoC and extending it with remoteproc
40 support. Below is the pictorial representation of boot flow:
42 .. image:: img/boot_diagram_j721e.svg
43 :alt: Boot flow diagram
45 - Here DMSC acts as master and provides all the critical services. R5/A72
46 requests DMSC to get these services done as shown in the above diagram.
52 :start-after: .. k3_rst_include_start_boot_sources
53 :end-before: .. k3_rst_include_end_boot_sources
57 0. Setup the environment variables:
60 :start-after: .. k3_rst_include_start_common_env_vars_desc
61 :end-before: .. k3_rst_include_end_common_env_vars_desc
64 :start-after: .. k3_rst_include_start_board_env_vars_desc
65 :end-before: .. k3_rst_include_end_board_env_vars_desc
67 Set the variables corresponding to this platform:
70 :start-after: .. k3_rst_include_start_common_env_vars_defn
71 :end-before: .. k3_rst_include_end_common_env_vars_defn
74 $ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
75 $ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
76 $ export TFA_BOARD=generic
77 $ # we dont use any extra TFA parameters
78 $ unset TFA_EXTRA_ARGS
79 $ export OPTEE_PLATFORM=k3-j721e
80 $ # we dont use any extra OP-TEE parameters
81 $ unset OPTEE_EXTRA_ARGS
83 .. j721e_evm_rst_include_start_build_steps
85 1. Trusted Firmware-A:
88 :start-after: .. k3_rst_include_start_build_steps_tfa
89 :end-before: .. k3_rst_include_end_build_steps_tfa
95 :start-after: .. k3_rst_include_start_build_steps_optee
96 :end-before: .. k3_rst_include_end_build_steps_optee
103 :start-after: .. k3_rst_include_start_build_steps_spl_r5
104 :end-before: .. k3_rst_include_end_build_steps_spl_r5
109 :start-after: .. k3_rst_include_start_build_steps_uboot
110 :end-before: .. k3_rst_include_end_build_steps_uboot
111 .. j721e_evm_rst_include_end_build_steps
115 In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
116 Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these
121 * tiboot3-j721e-gp-evm.bin, sysfw-j721e-gp-evm.itb from step 4.1
122 * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
126 * tiboot3-j721e_sr2-hs-fs-evm.bin, sysfw-j721e_sr2-hs-fs-evm.itb from step 4.1
127 * tispl.bin, u-boot.img from step 4.2
131 * tiboot3-j721e_sr2-hs-evm.bin, sysfw-j721e_sr2-hs-evm.itb from step 4.1
132 * tispl.bin, u-boot.img from step 4.2
139 .. image:: img/no_multi_cert_tiboot3.bin.svg
140 :alt: tiboot3.bin image format
144 .. image:: img/dm_tispl.bin.svg
145 :alt: tispl.bin image format
149 .. image:: img/sysfw.itb.svg
150 :alt: sysfw.itb image format
197 ROM supports booting from OSPI from offset 0x0.
199 Flashing images to OSPI:
201 Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
202 and sysfw.itb over tftp and then flash those to OSPI at their respective
208 => tftp ${loadaddr} tiboot3.bin
209 => sf update $loadaddr 0x0 $filesize
210 => tftp ${loadaddr} tispl.bin
211 => sf update $loadaddr 0x80000 $filesize
212 => tftp ${loadaddr} u-boot.img
213 => sf update $loadaddr 0x280000 $filesize
214 => tftp ${loadaddr} sysfw.itb
215 => sf update $loadaddr 0x6C0000 $filesize
217 Flash layout for OSPI:
219 .. image:: img/ospi_sysfw.svg
220 :alt: OSPI flash partition layout
225 The J721e u-boot allows firmware to be loaded for the Cortex-R5 subsystem.
226 The CPSW5G in J7200 and CPSW9G in J721E present in MAIN domain is configured
227 and controlled by the ethernet firmware that executes in the MAIN Cortex R5.
228 The default supported environment variables support loading these firmwares
229 from only MMC. "dorprocboot" env variable has to be set for the U-BOOT to load
230 and start the remote cores in the system.
232 J721E common processor board can be attached to a Ethernet QSGMII card and the
233 PHY in the card has to be reset before it can be used for data transfer.
234 "do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to
240 See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
241 detailed setup information.
245 **OpenOCD support since**: v0.12.0
247 If the default package version of OpenOCD in your development
248 environment's distribution needs to be updated, it might be necessary to
249 build OpenOCD from the source.
252 :start-after: .. k3_rst_include_start_openocd_connect_XDS110
253 :end-before: .. k3_rst_include_end_openocd_connect_XDS110
255 To start OpenOCD and connect to the board
259 openocd -f board/ti_j721eevm.cfg