1 .. SPDX-License-Identifier: GPL-2.0+
2 .. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
7 Several of the Sipeed Maix series of boards contain the Kendryte K210 processor,
8 a 64-bit RISC-V CPU produced by Canaan Inc. This processor contains several
9 peripherals to accelerate neural network processing and other "ai" tasks. This
10 includes a "KPU" neural network processor, an audio processor supporting
11 beamforming reception, and a digital video port supporting capture and output at
12 VGA resolution. Other peripherals include 8M of SRAM (accessible with and
13 without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
14 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
15 peripherals vary, but include spi flash; on-board usb-serial bridges; ports for
16 cameras, displays, and sd cards; and ESP32 chips.
18 Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
19 supported, but the boards are fairly similar.
21 Documentation for Maix boards is available from
22 `Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
23 Documentation for the Kendryte K210 is available from
24 `Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
25 details are rather lacking, so most technical reference has been taken from the
26 `standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
36 make CROSS_COMPILE=<your cross compile prefix>
42 kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin
44 The board provides two serial devices, e.g.
46 * /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0
47 * /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0
49 Which one is used for flashing depends on the board.
51 Currently only a small subset of the board features are supported. So we can
52 use the same default configuration and device tree. In the long run we may need
55 ======================== ========================== ========== ==========
56 Board defconfig board_id TTY device
57 ======================== ========================== ========== ==========
58 Sipeed MAIX BiT sipeed_maix_bitm_defconfig bit first
59 Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic first
60 Sipeed MAIXDUINO sipeed_maix_bitm_defconfig maixduino first
61 Sipeed MAIX GO goE second
62 Sipeed MAIX ONE DOCK dan first
63 ======================== ========================== ========== ==========
65 Flashing causes a reboot of the device. Parameter -t specifies that the serial
66 console shall be opened immediately. Boot output should look like the following:
70 U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
73 MMC: spi@53000000:slot@0: 0
82 OpenSBI is an open source supervisor execution environment implementing the
83 RISC-V Supervisor Binary Interface Specification [1]. One of its features is
84 to intercept run-time exceptions, e.g. for unaligned access or illegal
85 instructions, and to emulate the failing instructions.
87 The OpenSBI source can be downloaded via:
91 git clone https://github.com/riscv/opensbi
93 As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base.
94 Furthermore we have to enable building U-Boot for S-mode::
96 CONFIG_TEXT_BASE=0x80020000
99 Both settings are contained in sipeed_maix_smode_defconfig so we can build
104 make sipeed_maix_smode_defconfig
107 To build OpenSBI with U-Boot as a payload:
113 PLATFORM=kendryte/k210 \
115 FW_PAYLOAD_OFFSET=0x20000 \
116 FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin
118 The value of FW_PAYLOAD_OFFSET must match CONFIG_TEXT_BASE - 0x80000000.
120 The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
125 The default boot process is to load and boot the files ``/uImage`` and
126 ``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result
131 U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400)
134 MMC: spi@53000000:slot@0: 0
135 Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
140 Hit any key to stop autoboot: 0
141 1827380 bytes read in 1044 ms (1.7 MiB/s)
142 13428 bytes read in 10 ms (1.3 MiB/s)
143 ## Booting kernel from Legacy Image at 80060000 ...
145 Image Type: RISC-V Linux Kernel Image (uncompressed)
146 Data Size: 1827316 Bytes = 1.7 MiB
147 Load Address: 80000000
148 Entry Point: 80000000
149 Verifying Checksum ... OK
150 ## Flattened Device Tree blob at 80400000
151 Booting using the fdt blob at 0x80400000
153 Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
157 [ 0.000000] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020
158 [ 0.000000] earlycon: sifive0 at MMIO 0x0000000038000000 (options '115200n8')
159 [ 0.000000] printk: bootconsole [sifive0] enabled
160 [ 0.000000] Zone ranges:
161 [ 0.000000] DMA32 [mem 0x0000000080000000-0x00000000807fffff]
162 [ 0.000000] Normal empty
163 [ 0.000000] Movable zone start for each node
164 [ 0.000000] Early memory node ranges
165 [ 0.000000] node 0: [mem 0x0000000080000000-0x00000000807fffff]
166 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000807fffff]
167 [ 0.000000] riscv: ISA extensions acdfgim
168 [ 0.000000] riscv: ELF capabilities acdfim
169 [ 0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
170 [ 0.000000] percpu: Embedded 12 pages/cpu s18848 r0 d30304 u49152
171 [ 0.000000] Built 1 zonelists, mobility grouping off. Total pages: 2020
172 [ 0.000000] Kernel command line: earlycon console=ttySIF0
173 [ 0.000000] Dentry cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
174 [ 0.000000] Inode-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
175 [ 0.000000] Sorting __ex_table...
176 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
177 [ 0.000000] Memory: 6004K/8192K available (1139K kernel code, 126K rwdata, 198K rodata, 90K init, 81K bss, 2188K reserved, 0K cma-reserved)
178 [ 0.000000] rcu: Hierarchical RCU implementation.
179 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
180 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
181 [ 0.000000] riscv-intc: 64 local interrupts mapped
182 [ 0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 contexts.
183 [ 0.000000] random: get_random_bytes called from 0x00000000800019a8 with crng_init=0
184 [ 0.000000] k210-clk: clock-controller
185 [ 0.000000] k210-clk: clock-controller: fixed-rate 26 MHz osc base clock
186 [ 0.000000] clint: clint@2000000: timer running at 7800000 Hz
187 [ 0.000000] clocksource: clint_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
188 [ 0.000014] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
189 [ 0.008450] Console: colour dummy device 80x25
190 [ 0.012494] Calibrating delay loop (skipped), value calculated using timer frequency.. 15.60 BogoMIPS (lpj=31200)
191 [ 0.022693] pid_max: default: 4096 minimum: 301
192 [ 0.027352] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
193 [ 0.034428] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
194 [ 0.045099] rcu: Hierarchical SRCU implementation.
195 [ 0.050048] smp: Bringing up secondary CPUs ...
196 [ 0.055417] smp: Brought up 1 node, 2 CPUs
197 [ 0.059602] devtmpfs: initialized
198 [ 0.082796] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
199 [ 0.091820] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
200 [ 0.098507] pinctrl core: initialized pinctrl subsystem
201 [ 0.140938] clocksource: Switched to clocksource clint_clocksource
202 [ 0.247216] workingset: timestamp_bits=62 max_order=11 bucket_order=0
203 [ 0.277392] k210-fpioa 502b0000.pinmux: K210 FPIOA pin controller
204 [ 0.291724] k210-sysctl 50440000.syscon: K210 system controller
205 [ 0.305317] k210-rst 50440000.syscon:reset-controller: K210 reset controller
206 [ 0.313808] 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0
207 [ 0.322712] printk: console [ttySIF0] enabled
208 [ 0.322712] printk: console [ttySIF0] enabled
209 [ 0.331328] printk: bootconsole [sifive0] disabled
210 [ 0.331328] printk: bootconsole [sifive0] disabled
211 [ 0.353347] Freeing unused kernel memory: 88K
212 [ 0.357004] This architecture does not have kernel memory protection.
213 [ 0.363397] Run /init as init process
215 Loading, Booting, and Storing Images
216 ------------------------------------
226 Use the ``loady`` command to load images over serial.
230 => loady $loadaddr 1500000
231 ## Switch baudrate to 1500000 bps and press ENTER ...
235 *** baud: 1500000 ***
236 ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps...
241 Bytes Sent:2478208 BPS:72937
243 Ymodem sectors/kbytes sent: 0/ 0k
246 *** exit status: 0 ***
247 ## Total Size = 0x0025d052 = 2478162 Bytes
248 ## Switch baudrate to 115200 bps and press ESC ...
255 This command does not set ``$filesize``, so it may need to be set manually.
260 To load an image off of SPI flash, first set up a partition as described in
261 :ref:`k210_partitions`. Then, use ``mtd`` to load that partition
266 SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
267 => mtd read linux $loadaddr
268 Reading 2097152 byte(s) at offset 0x00000000
270 This command does not set ``$filesize``, so it may need to be set manually.
275 The MMC device number is 0. To list partitions on the device, use ``part``:
281 Partition Map for MMC device 0 -- Partition Type: EFI
283 Part Start LBA End LBA Name
287 1 0x00000800 0x039effde "boot"
288 attrs: 0x0000000000000000
289 type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
290 guid: 96161f7d-7113-4cc7-9a24-08ab7fc5cb72
292 To list files, use ``ls``:
299 <DIR> 16384 lost+found
303 To load a file, use ``load``:
307 => load mmc 0:1 $loadaddr uImage
308 1827380 bytes read in 1049 ms (1.7 MiB/s)
316 To run a bare binary, use the ``go`` command:
321 ## Starting application at 0x80000000 ...
322 Example expects ABI version 9
323 Actual U-Boot ABI version 9
328 Hit any key to exit ...
330 Note that this will only start a program on one hart. As-of this writing it is
331 only possible to start a program on multiple harts using the ``bootm`` command.
336 To create a legacy image, use ``tools/mkimage``:
340 $ tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80000000 -e 0x80000000 -n linux -d ../linux-git/arch/riscv/boot/Image uImage
342 Created: Fri Oct 16 17:36:32 2020
343 Image Type: RISC-V Linux Kernel Image (uncompressed)
344 Data Size: 1827316 Bytes = 1784.49 KiB = 1.74 MiB
345 Load Address: 80000000
346 Entry Point: 80000000
348 The ``bootm`` command also requires an FDT, even if the image doesn't require
349 one. After loading the image to ``$loadaddr`` and the FDT to ``$fdt_addr_r``,
354 => bootm $loadaddr - $fdt_addr_r
355 ## Booting kernel from Legacy Image at 80060000 ...
357 Image Type: RISC-V Linux Kernel Image (uncompressed)
358 Data Size: 1827316 Bytes = 1.7 MiB
359 Load Address: 80000000
360 Entry Point: 80000000
361 Verifying Checksum ... OK
362 ## Flattened Device Tree blob at 80400000
363 Booting using the fdt blob at 0x80400000
365 Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
369 The FDT is verified after the kernel is relocated, so it must be loaded high
370 enough so that it won't be overwritten. The default values for ``$loadaddr``
371 and ``$fdt_addr_r`` should provide ample headroom for most use-cases.
379 To flash data to SPI flash, first load it using one of the methods in
380 :ref:`loading`. Addiotionally, create some partitions as described in
381 :ref:`partitions`. Then use the ``mtd`` command:
386 SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
387 => mtd write linux $loadaddr 0 $filesize
388 Writing 2478162 byte(s) at offset 0x00000000
390 Note that in order to write a bootable image, a header and tailer must be added.
395 MMC writes are unsupported for now.
400 Sipeed MAIX boards typically provide around 16 MiB of SPI NOR flash. U-Boot is
401 stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
409 There is no set data layout. The default partition layout only allocates
410 partitions for U-Boot and its default environment
418 - block size: 0x1000 bytes
420 - 0x000000000000-0x000001000000 : "nor0"
421 - 0x000000000000-0x000000100000 : "u-boot"
422 - 0x000000fff000-0x000001000000 : "env"
424 As an example, to allocate 2MiB for Linux and (almost) 13 MiB for other data,
425 set the ``mtdparts`` like:
429 => env set mtdparts nor0:1M(u-boot),2M(linux),0xcff000(data),0x1000@0xfff000(env)
434 - block size: 0x1000 bytes
436 - 0x000000000000-0x000001000000 : "nor0"
437 - 0x000000000000-0x000000100000 : "u-boot"
438 - 0x000000100000-0x000000300000 : "linux"
439 - 0x000000300000-0x000000fff000 : "data"
440 - 0x000000fff000-0x000001000000 : "env"
442 To make these changes permanent, save the environment:
447 Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
450 U-Boot will always load the environment from the last 4 KiB of flash.
455 The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of
456 its 256 input functions to any any of 48 output pins. The following table has
457 the default pin assignments for the BitM.
459 ===== ========== =======
461 ===== ========== =======
474 IO_12 GPIO_4 Green LED
476 IO_14 GPIO_6 Blue LED
480 IO_18 I2S0_SCLK MIC CLK
482 IO_20 I2S0_IN_D0 MIC SD
488 IO_26 SPI1_D1 MMC MISO
489 IO_27 SPI1_SCLK MMC CLK
490 IO_28 SPI1_D0 MMC MOSI
491 IO_29 GPIOHS_13 MMC CS
498 IO_36 GPIOHS_20 Panel CS
499 IO_37 GPIOHS_21 Panel RST
500 IO_38 GPIOHS_22 Panel DC
501 IO_39 SPI0_SCK Panel WR
510 ===== ========== =======
512 Over- and Under-clocking
513 ------------------------
515 To change the clock speed of the K210, you will need to enable
516 ``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
517 section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
522 assigned-clocks = <&sysclk K210_CLK_PLL0>;
523 assigned-clock-rates = <800000000>;
526 There are three PLLs on the K210: PLL0 is the parent of most of the components,
527 including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
528 PLL2 is the parent of the sound processing devices. Note that child clocks of
529 PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
530 running at 800 MHz, then the CPU will run at 400 MHz. This is the example given
531 above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz.
533 It is possible to set PLL2's parent to PLL0. The plls are more accurate when
534 converting between similar frequencies. This makes it easier to get an accurate
535 frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz.
536 On this device, the I2S serial clock runs at 64 times the sample rate.
537 Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If
538 PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's
539 default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This
540 results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If,
541 instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
542 2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136
543 yields a serial clock of about 2.8228 MHz. This results in a sample rate of
544 44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the
550 assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>;
551 assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>;
552 assigned-clock-rates = <390000000>, <383846400>;
555 There are a couple of quirks to the PLLs. First, there are more frequency ratios
556 just above and below 1.0, but there is a small gap around 1.0. To be explicit,
557 if the input frequency is 100 MHz, it would be impossible to have an output of
558 99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO,
559 so higher input/output frequencies will be less accurate than lower ones.
567 1. ``RESET`` pin is deasserted. The pin is connected to the ``RESET`` button. It
568 can also be set to low via either the ``DTR`` or the ``RTS`` line of the
569 serial interface (depending on the board).
570 2. Both harts begin executing at ``0x00001000``.
571 3. Both harts jump to firmware at ``0x88000000``.
572 4. One hart is chosen as a boot hart.
573 5. Firmware reads the value of pin ``IO_16`` (ISP). This pin is connected to the
574 ``BOOT`` button. The pin can equally be set to low via either the ``DTR`` or
575 ``RTS`` line of the serial interface (depending on the board).
577 * If the pin is low, enter ISP mode. This mode allows loading data to ram,
578 writing it to flash, and booting from specific addresses.
579 * If the pin is high, continue boot.
580 6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``.
582 * If byte 0 is 1, the next stage is decrypted using the built-in AES
583 accelerator and the one-time programmable, 128-bit AES key.
584 * Bytes 1 to 4 hold the length of the next stage.
585 * The SHA-256 sum of the next stage is automatically calculated, and verified
586 against the 32 bytes following the next stage.
587 7. The boot hart sends an IPI to the other hart telling it to jump to the next
589 8. The boot hart jumps to ``0x80000000``.
594 The Debug UART is provided with the following settings::
597 CONFIG_DEBUG_UART_SIFIVE=y
598 CONFIG_DEBUG_UART_BASE=0x38000000
599 CONFIG_DEBUG_UART_CLOCK=390000000
604 The MAIX boards can be reset using the DTR and RTS lines of the serial console.
605 How the lines are used depends on the specific board. See the code of kflash.py
608 This is the reset sequence for the MAXDUINO and MAIX BiT with Mic:
610 .. code-block:: python
613 self.device.setDTR(False)
614 self.device.setRTS(False)
616 self.device.setDTR(True)
618 self.device.setDTR(False)
621 and this for the MAIX Bit:
623 .. code-block:: python
626 self.device.setDTR(False)
627 self.device.setRTS(False)
629 self.device.setRTS(True)
631 self.device.setRTS(False)
637 ========== ========= ===========
638 Address Size Description
639 ========== ========= ===========
640 0x00000000 0x1000 debug
641 0x00001000 0x1000 rom
642 0x02000000 0xC000 clint
643 0x0C000000 0x4000000 plic
644 0x38000000 0x1000 uarths
645 0x38001000 0x1000 gpiohs
646 0x40000000 0x400000 sram0 (non-cached)
647 0x40400000 0x200000 sram1 (non-cached)
648 0x40600000 0x200000 airam (non-cached)
649 0x40800000 0xC00000 kpu
650 0x42000000 0x400000 fft
651 0x50000000 0x1000 dmac
652 0x50200000 0x200000 apb0
654 0x50210000 0x100 uart0
655 0x50220000 0x100 uart1
656 0x50230000 0x100 uart2
657 0x50240000 0x100 spi slave
658 0x50250000 0x200 i2s0
660 0x50260000 0x200 i2s1
661 0x50270000 0x200 i2s2
662 0x50280000 0x100 i2c0
663 0x50290000 0x100 i2c1
664 0x502A0000 0x100 i2c2
665 0x502B0000 0x100 fpioa
666 0x502C0000 0x100 sha256
667 0x502D0000 0x100 timer0
668 0x502E0000 0x100 timer1
669 0x502F0000 0x100 timer2
670 0x50400000 0x200000 apb1
671 0x50400000 0x100 wdt0
672 0x50410000 0x100 wdt1
673 0x50420000 0x100 otp control
675 0x50440000 0x100 sysctl
678 0x52000000 0x4000000 apb2
679 0x52000000 0x100 spi0
680 0x53000000 0x100 spi1
681 0x54000000 0x200 spi3
682 0x80000000 0x400000 sram0 (cached)
683 0x80400000 0x200000 sram1 (cached)
684 0x80600000 0x200000 airam (cached)
685 0x88000000 0x20000 otp
686 0x88000000 0xC200 firmware
687 0x8801C000 0x1000 riscv priv spec 1.9 config
688 0x8801D000 0x2000 flattened device tree (contains only addresses and
690 0x8801F000 0x1000 credits
691 ========== ========= ===========
696 [1] https://github.com/riscv/riscv-sbi-doc
697 RISC-V Supervisor Binary Interface Specification