1 U-Boot for UniPhier SoC family
2 ==============================
8 (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-)
10 If you are building U-Boot on Ubuntu, its standard package is recommended.
11 You can install it as follows:
13 $ sudo apt-get install gcc-arm-linux-gnueabi-
15 (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-)
17 You can download pre-built toolchains from:
19 http://www.linaro.org/downloads/
21 (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-)
23 You can download pre-built toolchains from:
25 ftp://www.kernel.org/pub/tools/crosstool/files/bin/
32 $ make ph1_sld3_defconfig
33 $ make CROSS_COMPILE=arm-linux-gnueabi-
35 PH1-LD4 reference board:
36 $ make uniphier_ld4_sld8_defconfig
37 $ make CROSS_COMPILE=arm-linux-gnueabi-
39 PH1-sLD8 reference board:
40 $ make uniphier_ld4_sld8_defconfig
41 $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
44 $ make ph1_pro4_defconfig
45 $ make CROSS_COMPILE=arm-linux-gnueabi-
48 $ make ph1_pro5_defconfig
49 $ make CROSS_COMPILE=arm-linux-gnueabi-
53 $ make CROSS_COMPILE=arm-linux-gnueabi-
56 $ make ph1_ld6b_defconfig
57 $ make CROSS_COMPILE=arm-linux-gnueabi-
59 You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
60 to use your favorite compiler.
63 Burn U-Boot images to NAND
64 --------------------------
66 Write two files to the NAND device as follows:
67 - spl/u-boot-spl-dtb.bin at the offset address 0x00000000
68 - u-boot-dtb.img at the offset address 0x00010000
70 If a TFTP server is available, the images can be easily updated.
71 Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public
72 directory, and then run the following command at the U-Boot command line:
77 UniPhier specific commands
78 --------------------------
80 - pinmon (enabled by CONFIG_CMD_PINMON)
81 shows the boot mode pins that has been latched at the power-on reset
83 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
84 shows the DDR PHY parameters set by the PHY training
94 - LAN (on-board SMSC9118)
96 - EEPROM (connected to the on-board I2C bus)
97 - Support card (SRAM, NOR flash, some peripherals)
103 The recommended bit switch settings are as follows:
105 SW2 OFF(1)/ON(0) Description
106 ------------------------------------------
109 bit 3 <---- SoC Bus Width 16/32
110 bit 4 <---- SERIAL_SEL[0]
111 bit 5 ----> SERIAL_SEL[1]
112 bit 6 ----> BOOTSWAP_EN
114 bit 8 <---- SOC_SERIAL_DISABLE
116 SW8 OFF(1)/ON(0) Description
117 ------------------------------------------
118 bit 1 ----> CS1_SPLIT
120 bit 3 <---- CASE10_ON
121 bit 4 Don't Care Reserve
122 bit 5 Don't Care Reserve
123 bit 6 Don't Care Reserve
125 bit 8 ----> FLASHBUS32_16
127 The BKSZ[1:0] specifies the address range of memory slot and peripherals
130 BKSZ Description RAM slot Peripherals
131 --------------------------------------------------------------------
132 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff
133 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff
134 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff
135 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff
137 Set BSKZ[1:0] to 0b01 for U-Boot.
138 This mode is the most handy because EA[24] is always supported by the save pin
139 mode of the system bus. On the other hand, EA[25] is not supported for some
140 newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
143 Masahiro Yamada <yamada.masahiro@socionext.com>