1 U-Boot for UniPhier SoC family
2 ==============================
8 The UniPhier platform is well tested with Linaro toolchains.
9 You can download pre-built toolchains from:
11 http://www.linaro.org/downloads/
17 The source can be configured and built with the following commands:
20 $ make CROSS_COMPILE=<toolchain-prefix> DEVICE_TREE=<device-tree>
22 The recommended <toolchain-prefix> is `arm-linux-gnueabihf-` for 32bit SoCs,
23 `aarch64-linux-gnu-` for 64bit SoCs, but you may wish to change it to use your
26 The following tables show <defconfig> and <device-tree> for each board.
30 Board | <defconfig> | <device-tree>
31 ---------------|------------------------------|------------------------------
32 sLD3 reference | uniphier_sld3_defconfig | uniphier-sld3-ref (default)
33 LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
34 sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
35 Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default)
36 Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace
37 Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji
38 Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox
39 PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil
40 PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default)
41 LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref
45 Board | <defconfig> | <device-tree>
46 ---------------|-----------------------|----------------------------
47 LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref
48 LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global
49 LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default)
50 LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global
52 For example, to compile the source for PXs2 Vodka board, run the following:
54 $ make uniphier_pxs2_ld6b_defconfig
55 $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka
57 The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is
58 the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`,
59 so the following gives the same result.
61 $ make uniphier_pxs2_ld6b_defconfig
62 $ make CROSS_COMPILE=arm-linux-gnueabihf-
65 Booting 32bit SoC boards
66 ------------------------
68 The build command will generate the following:
72 U-Boot can boot UniPhier 32bit SoC boards by itself. Flash the generated images
73 to the storage device (NAND or eMMC) on your board.
75 - spl/u-boot-spl.bin at the offset address 0x00000000
76 - u-boot.bin at the offset address 0x00020000
78 The `u-boot-with-spl.bin` is the concatenation of the two (with appropriate
79 padding), so you can also do:
81 - u-boot-with-spl.bin at the offset address 0x00000000
83 If a TFTP server is available, the images can be easily updated.
84 Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
85 and run the following command at the U-Boot command line:
87 To update the images in NAND:
91 To update the images in eMMC:
96 Booting 64bit SoC boards
97 ------------------------
99 The build command will generate the following:
102 However, U-Boot is not the first stage loader for UniPhier 64bit SoC boards.
103 U-Boot serves as a non-secure boot loader loaded by [ARM Trusted Firmware],
104 so you need to provide the `u-boot.bin` to the build command of ARM Trusted
107 [ARM Trusted Firmware]: https://github.com/ARM-software/arm-trusted-firmware
110 UniPhier specific commands
111 --------------------------
113 - pinmon (enabled by CONFIG_CMD_PINMON)
114 shows the boot mode pins that has been latched at the power-on reset
116 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
117 shows the DDR PHY parameters set by the PHY training
119 - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
120 shows the DDR Multi PHY parameters set by the PHY training
132 - LAN (on-board SMSC9118)
134 - EEPROM (connected to the on-board I2C bus)
135 - Support card (SRAM, NOR flash, some peripherals)
141 The recommended bit switch settings are as follows:
143 SW2 OFF(1)/ON(0) Description
144 ------------------------------------------
147 bit 3 <---- SoC Bus Width 16/32
148 bit 4 <---- SERIAL_SEL[0]
149 bit 5 ----> SERIAL_SEL[1]
150 bit 6 ----> BOOTSWAP_EN
152 bit 8 <---- SOC_SERIAL_DISABLE
154 SW8 OFF(1)/ON(0) Description
155 ------------------------------------------
156 bit 1 <---- CS1_SPLIT
158 bit 3 <---- CASE10_ON
159 bit 4 Don't Care Reserve
160 bit 5 Don't Care Reserve
161 bit 6 Don't Care Reserve
163 bit 8 ----> FLASHBUS32_16
165 The BKSZ[1:0] specifies the address range of memory slot and peripherals
168 BKSZ Description RAM slot Peripherals
169 --------------------------------------------------------------------
170 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff
171 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff
172 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff
173 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff
175 Set BSKZ[1:0] to 0b01 for U-Boot.
176 This mode is the most handy because EA[24] is always supported by the save pin
177 mode of the system bus. On the other hand, EA[25] is not supported for some
178 newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
181 Masahiro Yamada <yamada.masahiro@socionext.com>