1 Motorola MPC85xxCDS boards
2 --------------------------
4 The CDS family of boards consists of a PCI backplane called the
5 "Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
6 and a CPU daughter card that bolts onto the daughter card.
8 Much of the content of the README.mpc85xxads for the 85xx ADS boards
9 applies to the 85xx CDS boards as well. In particular the toolchain,
10 the switch nomenclature, and the basis for the memory map. There are
11 some differences, though.
17 The Binutils in current ELDK toolchain will not support MPC85xx
18 chip. You need to use binutils-2.14.tar.bz2 (or newer) from
19 http://ftp.gnu.org/gnu/binutils.
21 The 85xx CDS code base is known to compile using:
22 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
28 The memory map for u-boot and linux has been extended w.r.t. the ADS
29 platform to allow for utilization of all 85xx CDS devices. The memory
30 map is setup for linux to operate properly. The linux source when
31 configured for MPC85xx CDS has been updated to reflect the new memory
36 0x0000_0000 0x7fff_ffff DDR 2G
37 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
38 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
39 0xe000_0000 0xe00f_ffff CCSR 1M
40 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
41 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
42 0xf000_0000 0xf7ff_ffff SDRAM 128M
43 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
44 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
45 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
47 (*) The system control registers (CADMUS) start at offset 0xfdb0_4000
48 within the NVRAM/CADMUS region of memory.
54 The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
55 There is a switch which allows the boot-bank to be selected. The switch
56 settings for updating flash are given below.
58 The u-boot commands for copying the boot-bank into the secondary bank are
61 erase ff780000 ff7fffff
62 cp.b fff80000 ff780000 80000
65 U-boot/kermit commands for downloading an image, then copying
66 it into the secondary bank:
71 send <u-boot-bin-image>
75 erase ff780000 ff7fffff
76 cp.b $loadaddr ff780000 80000
79 U-boot commands for downloading an image via tftp and flashing
80 it into the second bank:
82 tftp 10000 <u-boot.bin.image>
83 erase ff780000 ff7fffff
84 cp.b 10000 ff780000 80000
87 After copying the image into the second bank of flash, be sure to toggle
88 SW2[2] on the carrier card before resetting the board in order to set the
89 secondary bank as the boot-bank.
92 Carrier Board Switches
93 ----------------------
95 As a reminder, you should read the README.mpc85xxads too.
97 Most switches on the carrier board should not be changed. The only
98 user-settable switches on the carrier board are used to configure
99 the flash banks and determining the PCI slot.
101 The first two bits of SW2 control how flash is used on the board:
105 SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
106 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
107 10XXXXXX FLASH: Boot promjet, bank 1 available
108 11XXXXXX FLASH: Boot promjet, bank 2 available
110 The boot bank is always mapped to FF80_0000 and listed first by
111 the "flinfo" command. The secondary bank is always FF00_0000.
113 When using PCI, linux needs to know to which slot the CDS carrier is
114 connected.. By convention, the user-specific bits of SW2 are used to
115 convey this information:
119 SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
120 xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
121 xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
122 xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
124 These are cleverly, er, clearly silkscreened as Slot 1 through 4,
125 respectively, on the Arcadia near the support posts.
128 The default setting of all switches on the carrier board is:
133 SW2=0x1111yy x=Flash bank, yy=PCI slot
141 Most switches on the CPU Card should not be changed. However, the
142 frequency can be changed by setting SW3:
146 SW3=XX00XXXX == CORE:CCB 2:1
147 XX01XXXX == CORE:CCB 5:2
148 XX10XXXX == CORE:CCB 3:1
149 XX11XXXX == CORE:CCB 7:2
150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
153 A safe default setting for all switches on the CPU board is:
166 One bank of flash may contain an eDINK image.
171 Flash Bank 1 @ 0xfe000000
172 Flash Bank 2 @ 0xff000000
175 Commands for downloading a u-boot image to memory from edink:
178 time -s 4/8/2004 4:30p
182 transmit /binary <u-boot-bin-image>
186 fu -l 100000 fe780000 80000