Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
[platform/kernel/u-boot.git] / doc / README.fsl-ddr
1 Table of interleaving 2-4 controllers
2 =====================================
3   +--------------+-----------------------------------------------------------+
4   |Configuration |                    Memory Controller                      |
5   |              |       1              2              3             4       |
6   |--------------+--------------+--------------+-----------------------------+
7   | Two memory   | Not Intlv'ed | Not Intlv'ed |                             |
8   | complexes    +--------------+--------------+                             |
9   |              |      2-way Intlv'ed         |                             |
10   |--------------+--------------+--------------+--------------+              |
11   |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |              |
12   | Three memory +--------------+--------------+--------------+              |
13   | complexes    |         2-way Intlv'ed      | Not Intlv'ed |              |
14   |              +-----------------------------+--------------+              |
15   |              |                  3-way Intlv'ed            |              |
16   +--------------+--------------+--------------+--------------+--------------+
17   |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
18   | Four memory  +--------------+--------------+--------------+--------------+
19   | complexes    |       2-way Intlv'ed        |       2-way Intlv'ed        |
20   |              +-----------------------------+-----------------------------+
21   |              |                      4-way Intlv'ed                       |
22   +--------------+-----------------------------------------------------------+
23
24
25 Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
26 ======================================================
27   +-------------+---------------------------------------------------------+
28   |             |                   Rank Interleaving                     |
29   |             +--------+-----------+-----------+------------+-----------+
30   |Memory       |        |           |           |    2x2     |    4x1    |
31   |Controller   |  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32   |Interleaving |        | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
33   +-------------+--------+-----------+-----------+------------+-----------+
34   |None         |  Yes   | Yes       | Yes       | Yes        | Yes       |
35   +-------------+--------+-----------+-----------+------------+-----------+
36   |Cacheline    |  Yes   | Yes       | No        | No, Only(*)| Yes       |
37   |             |CS0 Only|           |           | {CS0+CS1}  |           |
38   +-------------+--------+-----------+-----------+------------+-----------+
39   |Page         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
40   |             |CS0 Only|           |           | {CS0+CS1}  |           |
41   +-------------+--------+-----------+-----------+------------+-----------+
42   |Bank         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
43   |             |CS0 Only|           |           | {CS0+CS1}  |           |
44   +-------------+--------+-----------+-----------+------------+-----------+
45   |Superbank    |  No    | Yes       | No        | No, Only(*)| Yes       |
46   |             |        |           |           | {CS0+CS1}  |           |
47   +-------------+--------+-----------+-----------+------------+-----------+
48  (*) Although the hardware can be configured with memory controller
49  interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
50  from each controller. {CS2+CS3} on each controller are only rank
51  interleaved on that controller.
52
53  For memory controller interleaving, identical DIMMs are suggested. Software
54  doesn't check the size or organization of interleaved DIMMs.
55
56 The ways to configure the ddr interleaving mode
57 ==============================================
58 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
59    under "CONFIG_EXTRA_ENV_SETTINGS", like:
60         #define CONFIG_EXTRA_ENV_SETTINGS                               \
61          "hwconfig=fsl_ddr:ctlr_intlv=bank"                     \
62          ......
63
64 2. Run U-Boot "setenv" command to configure the memory interleaving mode.
65    Either numerical or string value is accepted.
66
67   # disable memory controller interleaving
68   setenv hwconfig "fsl_ddr:ctlr_intlv=null"
69
70   # cacheline interleaving
71   setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
72
73   # page interleaving
74   setenv hwconfig "fsl_ddr:ctlr_intlv=page"
75
76   # bank interleaving
77   setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
78
79   # superbank
80   setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
81
82   # 1KB 3-way interleaving
83   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
84
85   # 4KB 3-way interleaving
86   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
87
88   # 8KB 3-way interleaving
89   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
90
91   # disable bank (chip-select) interleaving
92   setenv hwconfig "fsl_ddr:bank_intlv=null"
93
94   # bank(chip-select) interleaving cs0+cs1
95   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
96
97   # bank(chip-select) interleaving cs2+cs3
98   setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
99
100   # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
101   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
102
103   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
104   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
105
106   # bank(chip-select) interleaving (auto)
107   setenv hwconfig "fsl_ddr:bank_intlv=auto"
108   This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
109   on DIMMs.
110
111 Memory controller address hashing
112 ==================================
113 If the DDR controller supports address hashing, it can be enabled by hwconfig.
114
115 Syntax is:
116 hwconfig=fsl_ddr:addr_hash=true
117
118 Memory controller ECC on/off
119 ============================
120 If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
121 ECC can be turned on/off by hwconfig.
122
123 Syntax is
124 hwconfig=fsl_ddr:ecc=off
125
126
127 Memory address parity on/off
128 ============================
129 address parity can be turned on/off by hwconfig.
130 Syntax is:
131 hwconfig=fsl_ddr:parity=on
132
133
134 Memory testing options for mpc85xx
135 ==================================
136 1. Memory test can be done once U-Boot prompt comes up using mtest, or
137 2. Memory test can be done with Power-On-Self-Test function, activated at
138    compile time.
139
140    In order to enable the POST memory test, CONFIG_POST needs to be
141    defined in board configuraiton header file. By default, POST memory test
142    performs a fast test. A slow test can be enabled by changing the flag at
143    compiling time. To test memory bigger than 2GB, 36BIT support is needed.
144    Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
145    window to physical address so that all physical memory can be tested.
146
147 Combination of hwconfig
148 =======================
149 Hwconfig can be combined with multiple parameters, for example, on a supported
150 platform
151
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
153
154
155 Table for dynamic ODT for DDR3
156 ==============================
157 For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
158 be needed, depending on the configuration. The numbers in the following tables are
159 in Ohms.
160
161 * denotes dynamic ODT
162
163 Two slots system
164 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
165 |     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
166 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
167 |           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
168 +  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
169 |           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
170 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
171 |           |           |  Slot 1  |  off  | 75    | 120   | off  | off   | off  | off   | off  | 30    | 30   |
172 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
173 |           |           |  Slot 2  |  off  | 75    | off   | off  | 30    | 30   | 120   | off  | off   | off  |
174 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
175 |           |           |  Slot 1  |  off  | 75    | 120   | off  | off   | off  | 20    | 20   |       |      |
176 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
177 |           |           |  Slot 2  |  off  | 75    | off   | off  | 20    | 20   | 120  *| off  |       |      |
178 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
179 |           |           |  Slot 1  |  off  | 75    | 120  *| off  |       |      | off   | off  | 20    | 20   |
180 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
181 |           |           |  Slot 2  |  off  | 75    | 20    | 20   |       |      | 120   | off  | off   | off  |
182 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
183 |           |           |  Slot 1  |  off  | 75    | 120  *| off  |       |      | 30    | 30   |       |      |
184 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
185 |           |           |  Slot 2  |  off  | 75    | 30    | 30   |       |      | 120  *| off  |       |      |
186 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
187 | Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 40    | off  | off   | off  |       |      |       |      |
188 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
189 |   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 40    | off  | off   | off  |
190 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
191 |Single Rank|   Empty   |  Slot 1  |  off  | 75    | 40    | off  |       |      |       |      |       |      |
192 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
193 |   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 40    | off  |       |      |
194 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195
196 Single slot system
197 +-------------+------------+---------------+-----------------------------+-----------------------------+
198 |             |            |DRAM controller|     Rank 1   |    Rank 2    |    Rank 3    |    Rank 4    |
199 |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
200 |             |            | Write | Read  | Write | Read | Write | Read | Write | Read | Write | Read |
201 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
202 |             |   R1       | off   | 75    | 120  *| off  | off   | off  | 20    | 20   | off   | off  |
203 |             |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
204 |             |   R2       | off   | 75    | off   | 20   | 120   | off  | 20    | 20   | off   | off  |
205 |  Quad Rank  |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
206 |             |   R3       | off   | 75    | 20    | 20   | off   | off  | 120  *| off  | off   | off  |
207 |             |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
208 |             |   R4       | off   | 75    | 20    | 20   | off   | off  | off   | 20   | 120   | off  |
209 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
210 |             |   R1       | off   | 75    | 40    | off  | off   | off  |
211 |  Dual Rank  |------------+-------+-------+-------+------+-------+------+
212 |             |   R2       | off   | 75    | 40    | off  | off   | off  |
213 +-------------+------------+-------+-------+-------+------+-------+------+
214 | Single Rank |   R1       | off   | 75    | 40    | off  |
215 +-------------+------------+-------+-------+-------+------+
216
217 Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
218           http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
219
220
221 Table for ODT for DDR2
222 ======================
223 Two slots system
224 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
225 |     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
226 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
227 |           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
228 +  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
229 |           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
230 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
231 |           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   | off   | off  |
232 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
233 |           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  | off   | off  |
234 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
235 |           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   |       |      |
236 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
237 |           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  |       |      |
238 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
239 |           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   | off   | off  |
240 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
241 |           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  | off   | off  |
242 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
243 |           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   |       |      |
244 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
245 |           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  |       |      |
246 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
247 | Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 150   | off  | off   | off  |       |      |       |      |
248 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
249 |   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  | off   | off  |
250 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
251 |Single Rank|   Empty   |  Slot 1  |  off  | 75    | 150   | off  |       |      |       |      |       |      |
252 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
253 |   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  |       |      |
254 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
255
256 Single slot system
257 +-------------+------------+---------------+-----------------------------+
258 |             |            |DRAM controller|     Rank 1   |    Rank 2    |
259 |Configuration| Write/Read |-------+-------+-------+------+-------+------+
260 |             |            | Write | Read  | Write | Read | Write | Read |
261 +-------------+------------+-------+-------+-------+------+-------+------+
262 |             |   R1       | off   | 75    | 150   | off  | off   | off  |
263 |  Dual Rank  |------------+-------+-------+-------+------+-------+------+
264 |             |   R2       | off   | 75    | 150   | off  | off   | off  |
265 +-------------+------------+-------+-------+-------+------+-------+------+
266 | Single Rank |   R1       | off   | 75    | 150   | off  |
267 +-------------+------------+-------+-------+-------+------+
268
269 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
270
271
272 Interactive DDR debugging
273 ===========================
274
275 For DDR parameter tuning up and debugging, the interactive DDR debugger can
276 be activated by setting the environment variable "ddr_interactive" to any
277 value.  (The value of ddr_interactive may have a meaning in the future, but,
278 for now, the presence of the variable will cause the debugger to run.)  Once
279 activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
280 controller.  The available commands are printed by typing "help".
281
282 Another way to enter the interactive DDR debugger without setting the
283 environment variable is to send the 'd' character early during the boot
284 process.  To save booting time, no additional delay is added, so the window
285 to send the key press is very short -- basically, it is the time before the
286 memory controller code starts to run.  For example, when rebooting from
287 within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
288 initiate a 'reset' command.  In case of power on/reset, the user can hold
289 down the 'd' key while applying power or hitting the board's reset button.
290
291 The example flow of using interactive debugging is
292 type command "compute" to calculate the parameters from the default
293 type command "print" with arguments to show SPD, options, registers
294 type command "edit" with arguments to change any if desired
295 type command "copy" with arguments to copy controller/dimm settings
296 type command "go" to continue calculation and enable DDR controller
297
298 Additional commands to restart the debugging are:
299 type command "reset" to reset the board
300 type command "recompute" to reload SPD and start over
301
302 Note, check "next_step" to show the flow. For example, after edit opts, the
303 next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
304 STEP_PROGRAM_REGS.  Upon issuing command "go", the debugger will program the
305 DDR controller with the current setting without further calculation and then
306 exit to resume the booting of the machine.
307
308 The detail syntax for each commands are
309
310 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
311         c<n>            - the controller number, eg. c0, c1
312         d<n>            - the DIMM number, eg. d0, d1
313         spd             - print SPD data
314         dimmparms       - DIMM parameters, calculated from SPD
315         commonparms     - lowest common parameters for all DIMMs
316         opts            - options
317         addresses       - address assignment (not implemented yet)
318         regs            - controller registers
319
320 edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
321         c<n>            - the controller number, eg. c0, c1
322         d<n>            - the DIMM number, eg. d0, d1
323         spd             - print SPD data
324         dimmparms       - DIMM parameters, calculated from SPD
325         commonparms     - lowest common parameters for all DIMMs
326         opts            - options
327         addresses       - address assignment (not implemented yet)
328         regs            - controller registers
329         <element>       - name of the modified element
330                           byte number if the object is SPD
331         <value>         - decimal or heximal (prefixed with 0x) numbers
332
333 copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
334         same as for "edit" command
335         DIMM numbers ignored for commonparms, opts, and regs
336
337 reset
338         no arguement    - reset the board
339
340 recompute
341         no argument     - reload SPD and start over
342
343 compute
344         no argument     - recompute from current next_step
345
346 next_step
347         no argument     - show current next_step
348
349 help
350         no argument     - print a list of all commands
351
352 go
353         no argument     - program memory controller(s) and continue with U-Boot
354
355 Examples of debugging flow
356
357         FSL DDR>compute
358         Detected UDIMM UG51U6400N8SU-ACF
359         FSL DDR>print
360         print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
361         FSL DDR>print dimmparms
362         DIMM parameters:  Controller=0 DIMM=0
363         DIMM organization parameters:
364         module part name = UG51U6400N8SU-ACF
365         rank_density = 2147483648 bytes (2048 megabytes)
366         capacity = 4294967296 bytes (4096 megabytes)
367         burst_lengths_bitmask = 0C
368         base_addresss = 0 (00000000 00000000)
369         n_ranks = 2
370         data_width = 64
371         primary_sdram_width = 64
372         ec_sdram_width = 0
373         registered_dimm = 0
374         n_row_addr = 15
375         n_col_addr = 10
376         edc_config = 0
377         n_banks_per_sdram_device = 8
378         tCKmin_X_ps = 1500
379         tCKmin_X_minus_1_ps = 0
380         tCKmin_X_minus_2_ps = 0
381         tCKmax_ps = 0
382         caslat_X = 960
383         tAA_ps = 13125
384         caslat_X_minus_1 = 0
385         caslat_X_minus_2 = 0
386         caslat_lowest_derated = 0
387         tRCD_ps = 13125
388         tRP_ps = 13125
389         tRAS_ps = 36000
390         tWR_ps = 15000
391         tWTR_ps = 7500
392         tRFC_ps = 160000
393         tRRD_ps = 6000
394         tRC_ps = 49125
395         refresh_rate_ps = 7800000
396         tIS_ps = 0
397         tIH_ps = 0
398         tDS_ps = 0
399         tDH_ps = 0
400         tRTP_ps = 7500
401         tDQSQ_max_ps = 0
402         tQHS_ps = 0
403         FSL DDR>edit c0 opts ECC_mode 0
404         FSL DDR>edit c0 regs cs0_bnds 0x000000FF
405         FSL DDR>go
406         2 GiB left unmapped
407         4 GiB (DDR3, 64-bit, CL=9, ECC off)
408                DDR Chip-Select Interleaving Mode: CS0+CS1
409         Testing 0x00000000 - 0x7fffffff
410         Testing 0x80000000 - 0xffffffff
411         Remap DDR 2 GiB left unmapped
412
413         POST memory PASSED
414         Flash: 128 MiB
415         L2:    128 KB enabled
416         Corenet Platform Cache: 1024 KB enabled
417         SERDES: timeout resetting bank 3
418         SRIO1: disabled
419         SRIO2: disabled
420         MMC:  FSL_ESDHC: 0
421         EEPROM: Invalid ID (ff ff ff ff)
422         PCIe1: disabled
423         PCIe2: Root Complex, x1, regs @ 0xfe201000
424           01:00.0     - 8086:10d3 - Network controller
425         PCIe2: Bus 00 - 01
426         PCIe3: disabled
427         In:    serial
428         Out:   serial
429         Err:   serial
430         Net:   Initializing Fman
431         Fman1: Uploading microcode version 101.8.0
432         e1000: 00:1b:21:81:d2:e0
433         FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
434         Warning: e1000#0 MAC addresses don't match:
435         Address in SROM is         00:1b:21:81:d2:e0
436         Address in environment is  00:e0:0c:00:ea:05
437
438         Hit any key to stop autoboot:  0
439         =>