1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t wait; /* WAIT "prefix" present */
50 uint8_t lock; /* Lock prefix present */
51 uint8_t vex[3]; /* VEX prefix present */
52 uint8_t vex_m; /* VEX.M field */
54 uint8_t vex_lp; /* VEX.LP fields */
55 uint32_t rex; /* REX prefix present */
58 #define getu8(x) (*(uint8_t *)(x))
60 /* Littleendian CPU which can handle unaligned references */
61 #define getu16(x) (*(uint16_t *)(x))
62 #define getu32(x) (*(uint32_t *)(x))
63 #define getu64(x) (*(uint64_t *)(x))
65 static uint16_t getu16(uint8_t *data)
67 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
69 static uint32_t getu32(uint8_t *data)
71 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
73 static uint64_t getu64(uint8_t *data)
75 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
79 #define gets8(x) ((int8_t)getu8(x))
80 #define gets16(x) ((int16_t)getu16(x))
81 #define gets32(x) ((int32_t)getu32(x))
82 #define gets64(x) ((int64_t)getu64(x))
84 /* Important: regval must already have been adjusted for rex extensions */
85 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
87 if (!(regflags & (REGISTER|REGMEM)))
88 return 0; /* Registers not permissible?! */
92 if (!(REG_AL & ~regflags))
94 if (!(REG_AX & ~regflags))
96 if (!(REG_EAX & ~regflags))
98 if (!(REG_RAX & ~regflags))
100 if (!(REG_DL & ~regflags))
102 if (!(REG_DX & ~regflags))
104 if (!(REG_EDX & ~regflags))
106 if (!(REG_RDX & ~regflags))
108 if (!(REG_CL & ~regflags))
110 if (!(REG_CX & ~regflags))
112 if (!(REG_ECX & ~regflags))
114 if (!(REG_RCX & ~regflags))
116 if (!(FPU0 & ~regflags))
118 if (!(XMM0 & ~regflags))
120 if (!(YMM0 & ~regflags))
122 if (!(REG_CS & ~regflags))
123 return (regval == 1) ? R_CS : 0;
124 if (!(REG_DESS & ~regflags))
125 return (regval == 0 || regval == 2
126 || regval == 3 ? nasm_rd_sreg[regval] : 0);
127 if (!(REG_FSGS & ~regflags))
128 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
129 if (!(REG_SEG67 & ~regflags))
130 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
132 /* All the entries below look up regval in an 16-entry array */
133 if (regval < 0 || regval > 15)
136 if (!(REG8 & ~regflags)) {
138 return nasm_rd_reg8_rex[regval];
140 return nasm_rd_reg8[regval];
142 if (!(REG16 & ~regflags))
143 return nasm_rd_reg16[regval];
144 if (!(REG32 & ~regflags))
145 return nasm_rd_reg32[regval];
146 if (!(REG64 & ~regflags))
147 return nasm_rd_reg64[regval];
148 if (!(REG_SREG & ~regflags))
149 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
150 if (!(REG_CREG & ~regflags))
151 return nasm_rd_creg[regval];
152 if (!(REG_DREG & ~regflags))
153 return nasm_rd_dreg[regval];
154 if (!(REG_TREG & ~regflags)) {
156 return 0; /* TR registers are ill-defined with rex */
157 return nasm_rd_treg[regval];
159 if (!(FPUREG & ~regflags))
160 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
161 if (!(MMXREG & ~regflags))
162 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
163 if (!(XMMREG & ~regflags))
164 return nasm_rd_xmmreg[regval];
165 if (!(YMMREG & ~regflags))
166 return nasm_rd_ymmreg[regval];
172 * Process a DREX suffix
174 static uint8_t *do_drex(uint8_t *data, insn *ins)
176 uint8_t drex = *data++;
177 operand *dst = &ins->oprs[ins->drexdst];
179 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
180 return NULL; /* OC0 mismatch */
181 ins->rex = (ins->rex & ~7) | (drex & 7);
183 dst->segment = SEG_RMREG;
184 dst->basereg = drex >> 4;
190 * Process an effective address (ModRM) specification.
192 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
193 int segsize, operand * op, insn *ins)
195 int mod, rm, scale, index, base;
199 mod = (modrm >> 6) & 03;
202 if (mod != 3 && rm == 4 && asize != 16)
205 if (ins->rex & REX_D) {
206 data = do_drex(data, ins);
212 if (mod == 3) { /* pure register version */
213 op->basereg = rm+(rex & REX_B ? 8 : 0);
214 op->segment |= SEG_RMREG;
223 * <mod> specifies the displacement size (none, byte or
224 * word), and <rm> specifies the register combination.
225 * Exception: mod=0,rm=6 does not specify [BP] as one might
226 * expect, but instead specifies [disp16].
228 op->indexreg = op->basereg = -1;
229 op->scale = 1; /* always, in 16 bits */
260 if (rm == 6 && mod == 0) { /* special case */
264 mod = 2; /* fake disp16 */
268 op->segment |= SEG_NODISP;
271 op->segment |= SEG_DISP8;
272 op->offset = (int8_t)*data++;
275 op->segment |= SEG_DISP16;
276 op->offset = *data++;
277 op->offset |= ((unsigned)*data++) << 8;
283 * Once again, <mod> specifies displacement size (this time
284 * none, byte or *dword*), while <rm> specifies the base
285 * register. Again, [EBP] is missing, replaced by a pure
286 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
287 * and RIP-relative addressing in 64-bit mode.
290 * indicates not a single base register, but instead the
291 * presence of a SIB byte...
293 int a64 = asize == 64;
298 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
300 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
302 if (rm == 5 && mod == 0) {
304 op->eaflags |= EAF_REL;
305 op->segment |= SEG_RELATIVE;
306 mod = 2; /* fake disp32 */
310 op->disp_size = asize;
313 mod = 2; /* fake disp32 */
316 if (rm == 4) { /* process SIB */
317 scale = (sib >> 6) & 03;
318 index = (sib >> 3) & 07;
321 op->scale = 1 << scale;
323 if (index == 4 && !(rex & REX_X))
324 op->indexreg = -1; /* ESP/RSP cannot be an index */
326 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
328 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
330 if (base == 5 && mod == 0) {
332 mod = 2; /* Fake disp32 */
334 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
336 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
344 op->segment |= SEG_NODISP;
347 op->segment |= SEG_DISP8;
348 op->offset = gets8(data);
352 op->segment |= SEG_DISP32;
353 op->offset = gets32(data);
362 * Determine whether the instruction template in t corresponds to the data
363 * stream in data. Return the number of bytes matched if so.
365 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
367 static int matches(const struct itemplate *t, uint8_t *data,
368 const struct prefix_info *prefix, int segsize, insn *ins)
370 uint8_t *r = (uint8_t *)(t->code);
371 uint8_t *origdata = data;
372 bool a_used = false, o_used = false;
373 enum prefixes drep = 0;
374 enum prefixes dwait = 0;
375 uint8_t lock = prefix->lock;
376 int osize = prefix->osize;
377 int asize = prefix->asize;
380 struct operand *opx, *opy;
382 int s_field_for = -1; /* No 144/154 series code encountered */
384 int regmask = (segsize == 64) ? 15 : 7;
386 for (i = 0; i < MAX_OPERANDS; i++) {
387 ins->oprs[i].segment = ins->oprs[i].disp_size =
388 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
391 ins->rex = prefix->rex;
392 memset(ins->prefixes, 0, sizeof ins->prefixes);
394 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
397 if (prefix->rep == 0xF2)
399 else if (prefix->rep == 0xF3)
402 dwait = prefix->wait ? P_WAIT : 0;
404 while ((c = *r++) != 0) {
405 op1 = (c & 3) + ((opex & 1) << 2);
406 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
407 opx = &ins->oprs[op1];
408 opy = &ins->oprs[op2];
429 int t = *r++, d = *data++;
430 if (d < t || d > t + 7)
433 opx->basereg = (d-t)+
434 (ins->rex & REX_B ? 8 : 0);
435 opx->segment |= SEG_RMREG;
442 opx->offset = (int8_t)*data++;
443 opx->segment |= SEG_SIGNED;
447 opx->offset = *data++;
451 opx->offset = *data++;
455 opx->offset = getu16(data);
461 opx->offset = getu32(data);
464 opx->offset = getu16(data);
467 if (segsize != asize)
468 opx->disp_size = asize;
473 opx->offset = getu32(data);
480 opx->offset = getu16(data);
486 opx->offset = getu32(data);
492 opx->offset = getu64(data);
500 opx->offset = gets8(data++);
501 opx->segment |= SEG_RELATIVE;
505 opx->offset = getu64(data);
510 opx->offset = gets16(data);
512 opx->segment |= SEG_RELATIVE;
513 opx->segment &= ~SEG_32BIT;
517 opx->segment |= SEG_RELATIVE;
519 opx->offset = gets16(data);
521 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
522 } else if (osize == 32) {
523 opx->offset = gets32(data);
525 opx->segment &= ~SEG_64BIT;
526 opx->segment |= SEG_32BIT;
528 if (segsize != osize) {
530 (opx->type & ~SIZE_MASK)
531 | ((osize == 16) ? BITS16 : BITS32);
536 opx->offset = gets32(data);
538 opx->segment |= SEG_32BIT | SEG_RELATIVE;
547 opx->segment |= SEG_RMREG;
548 data = do_ea(data, modrm, asize, segsize, opy, ins);
551 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
556 if (s_field_for == op1) {
557 opx->offset = gets8(data);
560 opx->offset = getu16(data);
567 s_field_for = (*data & 0x02) ? op1 : -1;
568 if ((*data++ & ~0x02) != *r++)
573 if (s_field_for == op1) {
574 opx->offset = gets8(data);
577 opx->offset = getu32(data);
588 ins->rex |= REX_D|REX_OC;
593 data = do_drex(data, ins);
600 uint8_t ximm = *data++;
602 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
603 ins->oprs[c >> 3].segment |= SEG_RMREG;
604 ins->oprs[c & 7].offset = ximm & 15;
610 uint8_t ximm = *data++;
616 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
617 ins->oprs[c >> 4].segment |= SEG_RMREG;
623 uint8_t ximm = *data++;
626 ins->oprs[c].basereg = (ximm >> 4) & regmask;
627 ins->oprs[c].segment |= SEG_RMREG;
641 if (((modrm >> 3) & 07) != (c & 07))
642 return false; /* spare field doesn't match up */
643 data = do_ea(data, modrm, asize, segsize, opy, ins);
654 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
657 if ((vexm & 0x1f) != prefix->vex_m)
660 switch (vexwlp & 030) {
662 if (prefix->rex & REX_W)
666 if (!(prefix->rex & REX_W))
670 case 020: /* VEX.W is a don't care */
677 if ((vexwlp & 007) != prefix->vex_lp)
680 opx->segment |= SEG_RMREG;
681 opx->basereg = prefix->vex_v;
691 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
694 if ((vexm & 0x1f) != prefix->vex_m)
697 switch (vexwlp & 030) {
699 if (ins->rex & REX_W)
703 if (!(ins->rex & REX_W))
707 break; /* Need to do anything special here? */
710 if ((vexwlp & 007) != prefix->vex_lp)
713 if (prefix->vex_v != 0)
735 if (asize != segsize)
749 if (prefix->rex & REX_B)
754 if (prefix->rex & REX_X)
759 if (prefix->rex & REX_R)
764 if (prefix->rex & REX_W)
783 if (osize != (segsize == 16) ? 16 : 32)
790 ins->rex |= REX_W; /* 64-bit only instruction */
796 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
803 int t = *r++, d = *data++;
804 if (d < t || d > t + 15)
807 ins->condition = d - t;
817 if (prefix->rep != 0xF2)
823 if (prefix->rep != 0xF3)
848 if (prefix->wait != 0x9B)
854 ins->oprs[0].basereg = (*data++ >> 3) & 7;
858 if (prefix->osp || prefix->rep)
863 if (!prefix->osp || prefix->rep)
869 if (prefix->osp || prefix->rep != 0xf2)
875 if (prefix->osp || prefix->rep != 0xf3)
903 return false; /* Unknown code */
907 if (!vex_ok && (ins->rex & REX_V))
910 /* REX cannot be combined with DREX or VEX */
911 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
915 * Check for unused rep or a/o prefixes.
917 for (i = 0; i < t->operands; i++) {
918 if (ins->oprs[i].segment != SEG_RMREG)
923 if (ins->prefixes[PPS_LREP])
925 ins->prefixes[PPS_LREP] = P_LOCK;
928 if (ins->prefixes[PPS_LREP])
930 ins->prefixes[PPS_LREP] = drep;
932 ins->prefixes[PPS_WAIT] = dwait;
934 if (osize != ((segsize == 16) ? 16 : 32)) {
935 enum prefixes pfx = 0;
949 if (ins->prefixes[PPS_OSIZE])
951 ins->prefixes[PPS_OSIZE] = pfx;
954 if (!a_used && asize != segsize) {
955 if (ins->prefixes[PPS_ASIZE])
957 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
960 /* Fix: check for redundant REX prefixes */
962 return data - origdata;
965 /* Condition names for disassembly, sorted by x86 code */
966 static const char * const condition_name[16] = {
967 "o", "no", "c", "nc", "z", "nz", "na", "a",
968 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
971 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
972 int32_t offset, int autosync, uint32_t prefer)
974 const struct itemplate * const *p, * const *best_p;
975 const struct disasm_index *ix;
977 int length, best_length = 0;
979 int i, slen, colon, n;
983 uint32_t goodness, best;
985 struct prefix_info prefix;
988 memset(&ins, 0, sizeof ins);
993 memset(&prefix, 0, sizeof prefix);
994 prefix.asize = segsize;
995 prefix.osize = (segsize == 64) ? 32 : segsize;
1002 while (!end_prefix) {
1006 prefix.rep = *data++;
1010 prefix.wait = *data++;
1014 prefix.lock = *data++;
1018 segover = "cs", prefix.seg = *data++;
1021 segover = "ss", prefix.seg = *data++;
1024 segover = "ds", prefix.seg = *data++;
1027 segover = "es", prefix.seg = *data++;
1030 segover = "fs", prefix.seg = *data++;
1033 segover = "gs", prefix.seg = *data++;
1037 prefix.osize = (segsize == 16) ? 32 : 16;
1038 prefix.osp = *data++;
1041 prefix.asize = (segsize == 32) ? 16 : 32;
1042 prefix.asp = *data++;
1047 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1048 prefix.vex[0] = *data++;
1049 prefix.vex[1] = *data++;
1053 if (prefix.vex[0] == 0xc4) {
1054 prefix.vex[2] = *data++;
1055 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1056 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1057 prefix.vex_m = prefix.vex[1] & 0x1f;
1058 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1059 prefix.vex_lp = prefix.vex[2] & 7;
1061 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1063 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1064 prefix.vex_lp = prefix.vex[1] & 7;
1067 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1088 if (segsize == 64) {
1089 prefix.rex = *data++;
1090 if (prefix.rex & REX_W)
1102 best = -1; /* Worst possible */
1104 best_pref = INT_MAX;
1107 return 0; /* No instruction table at all... */
1111 while (ix->n == -1) {
1112 ix = (const struct disasm_index *)ix->p + *dp++;
1115 p = (const struct itemplate * const *)ix->p;
1116 for (n = ix->n; n; n--, p++) {
1117 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1120 * Final check to make sure the types of r/m match up.
1121 * XXX: Need to make sure this is actually correct.
1123 for (i = 0; i < (*p)->operands; i++) {
1124 if (!((*p)->opd[i] & SAME_AS) &&
1126 /* If it's a mem-only EA but we have a
1128 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1129 !(MEMORY & ~(*p)->opd[i])) ||
1130 /* If it's a reg-only EA but we have a memory
1132 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1133 !(REG_EA & ~(*p)->opd[i]) &&
1134 !((*p)->opd[i] & REG_SMASK)) ||
1135 /* Register type mismatch (eg FS vs REG_DESS):
1137 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1138 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1139 !whichreg((*p)->opd[i],
1140 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1148 * Note: we always prefer instructions which incorporate
1149 * prefixes in the instructions themselves. This is to allow
1150 * e.g. PAUSE to be preferred to REP NOP, and deal with
1151 * MMX/SSE instructions where prefixes are used to select
1152 * between MMX and SSE register sets or outright opcode
1157 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1159 for (i = 0; i < MAXPREFIX; i++)
1160 if (tmp_ins.prefixes[i])
1162 if (nprefix < best_pref ||
1163 (nprefix == best_pref && goodness < best)) {
1164 /* This is the best one found so far */
1167 best_pref = nprefix;
1168 best_length = length;
1176 return 0; /* no instruction was matched */
1178 /* Pick the best match */
1180 length = best_length;
1184 /* TODO: snprintf returns the value that the string would have if
1185 * the buffer were long enough, and not the actual length of
1186 * the returned string, so each instance of using the return
1187 * value of snprintf should actually be checked to assure that
1188 * the return value is "sane." Maybe a macro wrapper could
1189 * be used for that purpose.
1191 for (i = 0; i < MAXPREFIX; i++) {
1192 const char *prefix = prefix_name(ins.prefixes[i]);
1194 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1198 if (i >= FIRST_COND_OPCODE)
1199 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1200 nasm_insn_names[i], condition_name[ins.condition]);
1202 slen += snprintf(output + slen, outbufsize - slen, "%s",
1203 nasm_insn_names[i]);
1206 length += data - origdata; /* fix up for prefixes */
1207 for (i = 0; i < (*p)->operands; i++) {
1208 opflags_t t = (*p)->opd[i];
1209 const operand *o = &ins.oprs[i];
1213 o = &ins.oprs[t & ~SAME_AS];
1214 t = (*p)->opd[t & ~SAME_AS];
1217 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1220 if (o->segment & SEG_RELATIVE) {
1221 offs += offset + length;
1223 * sort out wraparound
1225 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1227 else if (segsize != 64)
1231 * add sync marker, if autosync is on
1242 if ((t & (REGISTER | FPUREG)) ||
1243 (o->segment & SEG_RMREG)) {
1245 reg = whichreg(t, o->basereg, ins.rex);
1247 slen += snprintf(output + slen, outbufsize - slen, "to ");
1248 slen += snprintf(output + slen, outbufsize - slen, "%s",
1249 nasm_reg_names[reg-EXPR_REG_START]);
1250 } else if (!(UNITY & ~t)) {
1251 output[slen++] = '1';
1252 } else if (t & IMMEDIATE) {
1255 snprintf(output + slen, outbufsize - slen, "byte ");
1256 if (o->segment & SEG_SIGNED) {
1259 output[slen++] = '-';
1261 output[slen++] = '+';
1263 } else if (t & BITS16) {
1265 snprintf(output + slen, outbufsize - slen, "word ");
1266 } else if (t & BITS32) {
1268 snprintf(output + slen, outbufsize - slen, "dword ");
1269 } else if (t & BITS64) {
1271 snprintf(output + slen, outbufsize - slen, "qword ");
1272 } else if (t & NEAR) {
1274 snprintf(output + slen, outbufsize - slen, "near ");
1275 } else if (t & SHORT) {
1277 snprintf(output + slen, outbufsize - slen, "short ");
1280 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1282 } else if (!(MEM_OFFS & ~t)) {
1284 snprintf(output + slen, outbufsize - slen,
1285 "[%s%s%s0x%"PRIx64"]",
1286 (segover ? segover : ""),
1287 (segover ? ":" : ""),
1288 (o->disp_size == 64 ? "qword " :
1289 o->disp_size == 32 ? "dword " :
1290 o->disp_size == 16 ? "word " : ""), offs);
1292 } else if (!(REGMEM & ~t)) {
1293 int started = false;
1296 snprintf(output + slen, outbufsize - slen, "byte ");
1299 snprintf(output + slen, outbufsize - slen, "word ");
1302 snprintf(output + slen, outbufsize - slen, "dword ");
1305 snprintf(output + slen, outbufsize - slen, "qword ");
1308 snprintf(output + slen, outbufsize - slen, "tword ");
1311 snprintf(output + slen, outbufsize - slen, "oword ");
1314 snprintf(output + slen, outbufsize - slen, "yword ");
1316 slen += snprintf(output + slen, outbufsize - slen, "far ");
1319 snprintf(output + slen, outbufsize - slen, "near ");
1320 output[slen++] = '[';
1322 slen += snprintf(output + slen, outbufsize - slen, "%s",
1323 (o->disp_size == 64 ? "qword " :
1324 o->disp_size == 32 ? "dword " :
1325 o->disp_size == 16 ? "word " :
1327 if (o->eaflags & EAF_REL)
1328 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1331 snprintf(output + slen, outbufsize - slen, "%s:",
1335 if (o->basereg != -1) {
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1340 if (o->indexreg != -1) {
1342 output[slen++] = '+';
1343 slen += snprintf(output + slen, outbufsize - slen, "%s",
1344 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1347 snprintf(output + slen, outbufsize - slen, "*%d",
1353 if (o->segment & SEG_DISP8) {
1355 uint8_t offset = offs;
1356 if ((int8_t)offset < 0) {
1363 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1365 } else if (o->segment & SEG_DISP16) {
1367 uint16_t offset = offs;
1368 if ((int16_t)offset < 0 && started) {
1372 prefix = started ? "+" : "";
1375 snprintf(output + slen, outbufsize - slen,
1376 "%s0x%"PRIx16"", prefix, offset);
1377 } else if (o->segment & SEG_DISP32) {
1378 if (prefix.asize == 64) {
1380 uint64_t offset = (int64_t)(int32_t)offs;
1381 if ((int32_t)offs < 0 && started) {
1385 prefix = started ? "+" : "";
1388 snprintf(output + slen, outbufsize - slen,
1389 "%s0x%"PRIx64"", prefix, offset);
1392 uint32_t offset = offs;
1393 if ((int32_t) offset < 0 && started) {
1397 prefix = started ? "+" : "";
1400 snprintf(output + slen, outbufsize - slen,
1401 "%s0x%"PRIx32"", prefix, offset);
1404 output[slen++] = ']';
1407 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1411 output[slen] = '\0';
1412 if (segover) { /* unused segment override */
1414 int count = slen + 1;
1416 p[count + 3] = p[count];
1417 strncpy(output, segover, 2);
1424 * This is called when we don't have a complete instruction. If it
1425 * is a standalone *single-byte* prefix show it as such, otherwise
1426 * print it as a literal.
1428 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1430 uint8_t byte = *data;
1431 const char *str = NULL;
1465 str = (segsize == 16) ? "o32" : "o16";
1468 str = (segsize == 32) ? "a16" : "a32";
1486 if (segsize == 64) {
1487 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1488 (byte == REX_P) ? "" : ".",
1489 (byte & REX_W) ? "w" : "",
1490 (byte & REX_R) ? "r" : "",
1491 (byte & REX_X) ? "x" : "",
1492 (byte & REX_B) ? "b" : "");
1495 /* else fall through */
1497 snprintf(output, outbufsize, "db 0x%02x", byte);
1502 strcpy(output, str);