1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
57 #define getu8(x) (*(uint8_t *)(x))
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
64 static uint16_t getu16(uint8_t *data)
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
68 static uint32_t getu32(uint8_t *data)
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
72 static uint64_t getu64(uint8_t *data)
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
91 if (!(REG_AL & ~regflags))
93 if (!(REG_AX & ~regflags))
95 if (!(REG_EAX & ~regflags))
97 if (!(REG_RAX & ~regflags))
99 if (!(REG_DL & ~regflags))
101 if (!(REG_DX & ~regflags))
103 if (!(REG_EDX & ~regflags))
105 if (!(REG_RDX & ~regflags))
107 if (!(REG_CL & ~regflags))
109 if (!(REG_CX & ~regflags))
111 if (!(REG_ECX & ~regflags))
113 if (!(REG_RCX & ~regflags))
115 if (!(FPU0 & ~regflags))
117 if (!(XMM0 & ~regflags))
119 if (!(YMM0 & ~regflags))
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
135 if (!(REG8 & ~regflags)) {
137 return nasm_rd_reg8_rex[regval];
139 return nasm_rd_reg8[regval];
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
171 * Process a DREX suffix
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
189 * Process an effective address (ModRM) specification.
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
194 int mod, rm, scale, index, base;
198 mod = (modrm >> 6) & 03;
201 if (mod != 3 && rm == 4 && asize != 16)
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
259 if (rm == 6 && mod == 0) { /* special case */
263 mod = 2; /* fake disp16 */
267 op->segment |= SEG_NODISP;
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
292 int a64 = asize == 64;
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
301 if (rm == 5 && mod == 0) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
309 op->disp_size = asize;
312 mod = 2; /* fake disp32 */
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
320 op->scale = 1 << scale;
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
329 if (base == 5 && mod == 0) {
331 mod = 2; /* Fake disp32 */
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
343 op->segment |= SEG_NODISP;
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
378 struct operand *opx, *opy;
380 int s_field_for = -1; /* No 144/154 series code encountered */
382 int regmask = (segsize == 64) ? 15 : 7;
384 for (i = 0; i < MAX_OPERANDS; i++) {
385 ins->oprs[i].segment = ins->oprs[i].disp_size =
386 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
389 ins->rex = prefix->rex;
390 memset(ins->prefixes, 0, sizeof ins->prefixes);
392 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
395 if (prefix->rep == 0xF2)
397 else if (prefix->rep == 0xF3)
400 while ((c = *r++) != 0) {
401 op1 = (c & 3) + ((opex & 1) << 2);
402 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
403 opx = &ins->oprs[op1];
404 opy = &ins->oprs[op2];
425 int t = *r++, d = *data++;
426 if (d < t || d > t + 7)
429 opx->basereg = (d-t)+
430 (ins->rex & REX_B ? 8 : 0);
431 opx->segment |= SEG_RMREG;
438 opx->offset = (int8_t)*data++;
439 opx->segment |= SEG_SIGNED;
443 opx->offset = *data++;
447 opx->offset = *data++;
451 opx->offset = getu16(data);
457 opx->offset = getu32(data);
460 opx->offset = getu16(data);
463 if (segsize != asize)
464 opx->disp_size = asize;
469 opx->offset = getu32(data);
476 opx->offset = getu16(data);
482 opx->offset = getu32(data);
488 opx->offset = getu64(data);
496 opx->offset = gets8(data++);
497 opx->segment |= SEG_RELATIVE;
501 opx->offset = getu64(data);
506 opx->offset = gets16(data);
508 opx->segment |= SEG_RELATIVE;
509 opx->segment &= ~SEG_32BIT;
513 opx->segment |= SEG_RELATIVE;
515 opx->offset = gets16(data);
517 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
518 } else if (osize == 32) {
519 opx->offset = gets32(data);
521 opx->segment &= ~SEG_64BIT;
522 opx->segment |= SEG_32BIT;
524 if (segsize != osize) {
526 (opx->type & ~SIZE_MASK)
527 | ((osize == 16) ? BITS16 : BITS32);
532 opx->offset = gets32(data);
534 opx->segment |= SEG_32BIT | SEG_RELATIVE;
543 opx->segment |= SEG_RMREG;
544 data = do_ea(data, modrm, asize, segsize, opy, ins);
547 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
552 if (s_field_for == op1) {
553 opx->offset = gets8(data);
556 opx->offset = getu16(data);
563 s_field_for = (*data & 0x02) ? op1 : -1;
564 if ((*data++ & ~0x02) != *r++)
569 if (s_field_for == op1) {
570 opx->offset = gets8(data);
573 opx->offset = getu32(data);
584 ins->rex |= REX_D|REX_OC;
589 data = do_drex(data, ins);
596 uint8_t ximm = *data++;
598 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
599 ins->oprs[c >> 3].segment |= SEG_RMREG;
600 ins->oprs[c & 7].offset = ximm & 15;
606 uint8_t ximm = *data++;
612 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
613 ins->oprs[c >> 4].segment |= SEG_RMREG;
619 uint8_t ximm = *data++;
622 ins->oprs[c].basereg = (ximm >> 4) & regmask;
623 ins->oprs[c].segment |= SEG_RMREG;
637 if (((modrm >> 3) & 07) != (c & 07))
638 return false; /* spare field doesn't match up */
639 data = do_ea(data, modrm, asize, segsize, opy, ins);
650 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
653 if ((vexm & 0x1f) != prefix->vex_m)
656 switch (vexwlp & 030) {
658 if (prefix->rex & REX_W)
662 if (!(prefix->rex & REX_W))
666 case 020: /* VEX.W is a don't care */
673 if ((vexwlp & 007) != prefix->vex_lp)
676 opx->segment |= SEG_RMREG;
677 opx->basereg = prefix->vex_v;
687 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
690 if ((vexm & 0x1f) != prefix->vex_m)
693 switch (vexwlp & 030) {
695 if (ins->rex & REX_W)
699 if (!(ins->rex & REX_W))
703 break; /* Need to do anything special here? */
706 if ((vexwlp & 007) != prefix->vex_lp)
709 if (prefix->vex_v != 0)
731 if (asize != segsize)
745 if (prefix->rex & REX_B)
750 if (prefix->rex & REX_X)
755 if (prefix->rex & REX_R)
760 if (prefix->rex & REX_W)
779 if (osize != (segsize == 16) ? 16 : 32)
786 ins->rex |= REX_W; /* 64-bit only instruction */
792 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
799 int t = *r++, d = *data++;
800 if (d < t || d > t + 15)
803 ins->condition = d - t;
813 if (prefix->rep != 0xF2)
819 if (prefix->rep != 0xF3)
844 ins->oprs[0].basereg = (*data++ >> 3) & 7;
848 if (prefix->osp || prefix->rep)
853 if (!prefix->osp || prefix->rep)
859 if (prefix->osp || prefix->rep != 0xf2)
865 if (prefix->osp || prefix->rep != 0xf3)
893 return false; /* Unknown code */
897 if (!vex_ok && (ins->rex & REX_V))
900 /* REX cannot be combined with DREX or VEX */
901 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
905 * Check for unused rep or a/o prefixes.
907 for (i = 0; i < t->operands; i++) {
908 if (ins->oprs[i].segment != SEG_RMREG)
913 if (ins->prefixes[PPS_LREP])
915 ins->prefixes[PPS_LREP] = P_LOCK;
918 if (ins->prefixes[PPS_LREP])
920 ins->prefixes[PPS_LREP] = drep;
923 if (osize != ((segsize == 16) ? 16 : 32)) {
924 enum prefixes pfx = 0;
938 if (ins->prefixes[PPS_OSIZE])
940 ins->prefixes[PPS_OSIZE] = pfx;
943 if (!a_used && asize != segsize) {
944 if (ins->prefixes[PPS_ASIZE])
946 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
949 /* Fix: check for redundant REX prefixes */
951 return data - origdata;
954 /* Condition names for disassembly, sorted by x86 code */
955 static const char * const condition_name[16] = {
956 "o", "no", "c", "nc", "z", "nz", "na", "a",
957 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
960 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
961 int32_t offset, int autosync, uint32_t prefer)
963 const struct itemplate * const *p, * const *best_p;
964 const struct disasm_index *ix;
966 int length, best_length = 0;
968 int i, slen, colon, n;
972 uint32_t goodness, best;
974 struct prefix_info prefix;
977 memset(&ins, 0, sizeof ins);
982 memset(&prefix, 0, sizeof prefix);
983 prefix.asize = segsize;
984 prefix.osize = (segsize == 64) ? 32 : segsize;
991 while (!end_prefix) {
995 prefix.rep = *data++;
999 prefix.lock = *data++;
1003 segover = "cs", prefix.seg = *data++;
1006 segover = "ss", prefix.seg = *data++;
1009 segover = "ds", prefix.seg = *data++;
1012 segover = "es", prefix.seg = *data++;
1015 segover = "fs", prefix.seg = *data++;
1018 segover = "gs", prefix.seg = *data++;
1022 prefix.osize = (segsize == 16) ? 32 : 16;
1023 prefix.osp = *data++;
1026 prefix.asize = (segsize == 32) ? 16 : 32;
1027 prefix.asp = *data++;
1032 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1033 prefix.vex[0] = *data++;
1034 prefix.vex[1] = *data++;
1038 if (prefix.vex[0] == 0xc4) {
1039 prefix.vex[2] = *data++;
1040 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1041 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1042 prefix.vex_m = prefix.vex[1] & 0x1f;
1043 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1044 prefix.vex_lp = prefix.vex[2] & 7;
1046 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1048 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1049 prefix.vex_lp = prefix.vex[1] & 7;
1052 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1073 if (segsize == 64) {
1074 prefix.rex = *data++;
1075 if (prefix.rex & REX_W)
1087 best = -1; /* Worst possible */
1089 best_pref = INT_MAX;
1092 return 0; /* No instruction table at all... */
1096 while (ix->n == -1) {
1097 ix = (const struct disasm_index *)ix->p + *dp++;
1100 p = (const struct itemplate * const *)ix->p;
1101 for (n = ix->n; n; n--, p++) {
1102 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1105 * Final check to make sure the types of r/m match up.
1106 * XXX: Need to make sure this is actually correct.
1108 for (i = 0; i < (*p)->operands; i++) {
1109 if (!((*p)->opd[i] & SAME_AS) &&
1111 /* If it's a mem-only EA but we have a
1113 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1114 !(MEMORY & ~(*p)->opd[i])) ||
1115 /* If it's a reg-only EA but we have a memory
1117 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1118 !(REG_EA & ~(*p)->opd[i]) &&
1119 !((*p)->opd[i] & REG_SMASK)) ||
1120 /* Register type mismatch (eg FS vs REG_DESS):
1122 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1123 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1124 !whichreg((*p)->opd[i],
1125 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1133 * Note: we always prefer instructions which incorporate
1134 * prefixes in the instructions themselves. This is to allow
1135 * e.g. PAUSE to be preferred to REP NOP, and deal with
1136 * MMX/SSE instructions where prefixes are used to select
1137 * between MMX and SSE register sets or outright opcode
1142 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1144 for (i = 0; i < MAXPREFIX; i++)
1145 if (tmp_ins.prefixes[i])
1147 if (nprefix < best_pref ||
1148 (nprefix == best_pref && goodness < best)) {
1149 /* This is the best one found so far */
1152 best_pref = nprefix;
1153 best_length = length;
1161 return 0; /* no instruction was matched */
1163 /* Pick the best match */
1165 length = best_length;
1169 /* TODO: snprintf returns the value that the string would have if
1170 * the buffer were long enough, and not the actual length of
1171 * the returned string, so each instance of using the return
1172 * value of snprintf should actually be checked to assure that
1173 * the return value is "sane." Maybe a macro wrapper could
1174 * be used for that purpose.
1176 for (i = 0; i < MAXPREFIX; i++)
1177 switch (ins.prefixes[i]) {
1179 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1182 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1185 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1188 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1191 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1194 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1197 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1200 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1203 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1206 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1213 if (i >= FIRST_COND_OPCODE)
1214 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1215 nasm_insn_names[i], condition_name[ins.condition]);
1217 slen += snprintf(output + slen, outbufsize - slen, "%s",
1218 nasm_insn_names[i]);
1221 length += data - origdata; /* fix up for prefixes */
1222 for (i = 0; i < (*p)->operands; i++) {
1223 opflags_t t = (*p)->opd[i];
1224 const operand *o = &ins.oprs[i];
1228 o = &ins.oprs[t & ~SAME_AS];
1229 t = (*p)->opd[t & ~SAME_AS];
1232 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1235 if (o->segment & SEG_RELATIVE) {
1236 offs += offset + length;
1238 * sort out wraparound
1240 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1242 else if (segsize != 64)
1246 * add sync marker, if autosync is on
1257 if ((t & (REGISTER | FPUREG)) ||
1258 (o->segment & SEG_RMREG)) {
1260 reg = whichreg(t, o->basereg, ins.rex);
1262 slen += snprintf(output + slen, outbufsize - slen, "to ");
1263 slen += snprintf(output + slen, outbufsize - slen, "%s",
1264 nasm_reg_names[reg-EXPR_REG_START]);
1265 } else if (!(UNITY & ~t)) {
1266 output[slen++] = '1';
1267 } else if (t & IMMEDIATE) {
1270 snprintf(output + slen, outbufsize - slen, "byte ");
1271 if (o->segment & SEG_SIGNED) {
1274 output[slen++] = '-';
1276 output[slen++] = '+';
1278 } else if (t & BITS16) {
1280 snprintf(output + slen, outbufsize - slen, "word ");
1281 } else if (t & BITS32) {
1283 snprintf(output + slen, outbufsize - slen, "dword ");
1284 } else if (t & BITS64) {
1286 snprintf(output + slen, outbufsize - slen, "qword ");
1287 } else if (t & NEAR) {
1289 snprintf(output + slen, outbufsize - slen, "near ");
1290 } else if (t & SHORT) {
1292 snprintf(output + slen, outbufsize - slen, "short ");
1295 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1297 } else if (!(MEM_OFFS & ~t)) {
1299 snprintf(output + slen, outbufsize - slen,
1300 "[%s%s%s0x%"PRIx64"]",
1301 (segover ? segover : ""),
1302 (segover ? ":" : ""),
1303 (o->disp_size == 64 ? "qword " :
1304 o->disp_size == 32 ? "dword " :
1305 o->disp_size == 16 ? "word " : ""), offs);
1307 } else if (!(REGMEM & ~t)) {
1308 int started = false;
1311 snprintf(output + slen, outbufsize - slen, "byte ");
1314 snprintf(output + slen, outbufsize - slen, "word ");
1317 snprintf(output + slen, outbufsize - slen, "dword ");
1320 snprintf(output + slen, outbufsize - slen, "qword ");
1323 snprintf(output + slen, outbufsize - slen, "tword ");
1326 snprintf(output + slen, outbufsize - slen, "oword ");
1329 snprintf(output + slen, outbufsize - slen, "yword ");
1331 slen += snprintf(output + slen, outbufsize - slen, "far ");
1334 snprintf(output + slen, outbufsize - slen, "near ");
1335 output[slen++] = '[';
1337 slen += snprintf(output + slen, outbufsize - slen, "%s",
1338 (o->disp_size == 64 ? "qword " :
1339 o->disp_size == 32 ? "dword " :
1340 o->disp_size == 16 ? "word " :
1342 if (o->eaflags & EAF_REL)
1343 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1346 snprintf(output + slen, outbufsize - slen, "%s:",
1350 if (o->basereg != -1) {
1351 slen += snprintf(output + slen, outbufsize - slen, "%s",
1352 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1355 if (o->indexreg != -1) {
1357 output[slen++] = '+';
1358 slen += snprintf(output + slen, outbufsize - slen, "%s",
1359 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1362 snprintf(output + slen, outbufsize - slen, "*%d",
1368 if (o->segment & SEG_DISP8) {
1370 uint8_t offset = offs;
1371 if ((int8_t)offset < 0) {
1378 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1380 } else if (o->segment & SEG_DISP16) {
1382 uint16_t offset = offs;
1383 if ((int16_t)offset < 0 && started) {
1387 prefix = started ? "+" : "";
1390 snprintf(output + slen, outbufsize - slen,
1391 "%s0x%"PRIx16"", prefix, offset);
1392 } else if (o->segment & SEG_DISP32) {
1393 if (prefix.asize == 64) {
1395 uint64_t offset = (int64_t)(int32_t)offs;
1396 if ((int32_t)offs < 0 && started) {
1400 prefix = started ? "+" : "";
1403 snprintf(output + slen, outbufsize - slen,
1404 "%s0x%"PRIx64"", prefix, offset);
1407 uint32_t offset = offs;
1408 if ((int32_t) offset < 0 && started) {
1412 prefix = started ? "+" : "";
1415 snprintf(output + slen, outbufsize - slen,
1416 "%s0x%"PRIx32"", prefix, offset);
1419 output[slen++] = ']';
1422 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1426 output[slen] = '\0';
1427 if (segover) { /* unused segment override */
1429 int count = slen + 1;
1431 p[count + 3] = p[count];
1432 strncpy(output, segover, 2);
1438 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1440 snprintf(output, outbufsize, "db 0x%02X", *data);