1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
53 * Flags that go into the `segment' field of `insn' structures
56 #define SEG_RELATIVE 1
63 #define SEG_SIGNED 128
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
86 #define getu8(x) (*(uint8_t *)(x))
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
93 static uint16_t getu16(uint8_t *data)
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 static uint32_t getu32(uint8_t *data)
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 static uint64_t getu64(uint8_t *data)
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
117 static const struct {
120 } specific_registers[] = {
144 if (!(regflags & (REGISTER|REGMEM)))
145 return 0; /* Registers not permissible?! */
147 regflags |= REGISTER;
149 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
150 if (!(specific_registers[i].flags & ~regflags))
151 return specific_registers[i].reg;
153 /* All the entries below look up regval in an 16-entry array */
154 if (regval < 0 || regval > 15)
157 if (!(REG8 & ~regflags)) {
158 if (rex & (REX_P|REX_NH))
159 return nasm_rd_reg8_rex[regval];
161 return nasm_rd_reg8[regval];
163 if (!(REG16 & ~regflags))
164 return nasm_rd_reg16[regval];
165 if (!(REG32 & ~regflags))
166 return nasm_rd_reg32[regval];
167 if (!(REG64 & ~regflags))
168 return nasm_rd_reg64[regval];
169 if (!(REG_SREG & ~regflags))
170 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
171 if (!(REG_CREG & ~regflags))
172 return nasm_rd_creg[regval];
173 if (!(REG_DREG & ~regflags))
174 return nasm_rd_dreg[regval];
175 if (!(REG_TREG & ~regflags)) {
177 return 0; /* TR registers are ill-defined with rex */
178 return nasm_rd_treg[regval];
180 if (!(FPUREG & ~regflags))
181 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
182 if (!(MMXREG & ~regflags))
183 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
184 if (!(XMMREG & ~regflags))
185 return nasm_rd_xmmreg[regval];
186 if (!(YMMREG & ~regflags))
187 return nasm_rd_ymmreg[regval];
193 * Process an effective address (ModRM) specification.
195 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
196 int segsize, enum ea_type type,
197 operand *op, insn *ins)
199 int mod, rm, scale, index, base;
203 mod = (modrm >> 6) & 03;
206 if (mod != 3 && asize != 16 && rm == 4)
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
228 if (type != EA_SCALAR)
231 op->indexreg = op->basereg = -1;
232 op->scale = 1; /* always, in 16 bits */
263 if (rm == 6 && mod == 0) { /* special case */
267 mod = 2; /* fake disp16 */
271 op->segment |= SEG_NODISP;
274 op->segment |= SEG_DISP8;
275 op->offset = (int8_t)*data++;
278 op->segment |= SEG_DISP16;
279 op->offset = *data++;
280 op->offset |= ((unsigned)*data++) << 8;
286 * Once again, <mod> specifies displacement size (this time
287 * none, byte or *dword*), while <rm> specifies the base
288 * register. Again, [EBP] is missing, replaced by a pure
289 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
290 * and RIP-relative addressing in 64-bit mode.
293 * indicates not a single base register, but instead the
294 * presence of a SIB byte...
296 int a64 = asize == 64;
301 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
303 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
305 if (rm == 5 && mod == 0) {
307 op->eaflags |= EAF_REL;
308 op->segment |= SEG_RELATIVE;
309 mod = 2; /* fake disp32 */
313 op->disp_size = asize;
316 mod = 2; /* fake disp32 */
320 if (rm == 4) { /* process SIB */
321 scale = (sib >> 6) & 03;
322 index = (sib >> 3) & 07;
325 op->scale = 1 << scale;
327 if (type == EA_XMMVSIB)
328 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
329 else if (type == EA_YMMVSIB)
330 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
331 else if (index == 4 && !(rex & REX_X))
332 op->indexreg = -1; /* ESP/RSP cannot be an index */
334 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
336 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
338 if (base == 5 && mod == 0) {
340 mod = 2; /* Fake disp32 */
342 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
344 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
348 } else if (type != EA_SCALAR) {
349 /* Can't have VSIB without SIB */
355 op->segment |= SEG_NODISP;
358 op->segment |= SEG_DISP8;
359 op->offset = gets8(data);
363 op->segment |= SEG_DISP32;
364 op->offset = gets32(data);
373 * Determine whether the instruction template in t corresponds to the data
374 * stream in data. Return the number of bytes matched if so.
376 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
378 static int matches(const struct itemplate *t, uint8_t *data,
379 const struct prefix_info *prefix, int segsize, insn *ins)
381 uint8_t *r = (uint8_t *)(t->code);
382 uint8_t *origdata = data;
383 bool a_used = false, o_used = false;
384 enum prefixes drep = 0;
385 enum prefixes dwait = 0;
386 uint8_t lock = prefix->lock;
387 int osize = prefix->osize;
388 int asize = prefix->asize;
391 struct operand *opx, *opy;
394 int regmask = (segsize == 64) ? 15 : 7;
395 enum ea_type eat = EA_SCALAR;
397 for (i = 0; i < MAX_OPERANDS; i++) {
398 ins->oprs[i].segment = ins->oprs[i].disp_size =
399 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
402 ins->rex = prefix->rex;
403 memset(ins->prefixes, 0, sizeof ins->prefixes);
405 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
408 if (prefix->rep == 0xF2)
410 else if (prefix->rep == 0xF3)
413 dwait = prefix->wait ? P_WAIT : 0;
415 while ((c = *r++) != 0) {
416 op1 = (c & 3) + ((opex & 1) << 2);
417 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
418 opx = &ins->oprs[op1];
419 opy = &ins->oprs[op2];
440 int t = *r++, d = *data++;
441 if (d < t || d > t + 7)
444 opx->basereg = (d-t)+
445 (ins->rex & REX_B ? 8 : 0);
446 opx->segment |= SEG_RMREG;
452 opx->offset = (int8_t)*data++;
453 opx->segment |= SEG_SIGNED;
457 opx->offset = *data++;
461 opx->offset = *data++;
465 opx->offset = getu16(data);
471 opx->offset = getu32(data);
474 opx->offset = getu16(data);
477 if (segsize != asize)
478 opx->disp_size = asize;
482 opx->offset = getu32(data);
487 opx->offset = gets32(data);
494 opx->offset = getu16(data);
500 opx->offset = getu32(data);
506 opx->offset = getu64(data);
514 opx->offset = gets8(data++);
515 opx->segment |= SEG_RELATIVE;
519 opx->offset = getu64(data);
524 opx->offset = gets16(data);
526 opx->segment |= SEG_RELATIVE;
527 opx->segment &= ~SEG_32BIT;
530 case4(064): /* rel */
531 opx->segment |= SEG_RELATIVE;
532 /* In long mode rel is always 32 bits, sign extended. */
533 if (segsize == 64 || osize == 32) {
534 opx->offset = gets32(data);
537 opx->segment |= SEG_32BIT;
538 opx->type = (opx->type & ~SIZE_MASK)
539 | (segsize == 64 ? BITS64 : BITS32);
541 opx->offset = gets16(data);
543 opx->segment &= ~SEG_32BIT;
544 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
549 opx->offset = gets32(data);
551 opx->segment |= SEG_32BIT | SEG_RELATIVE;
560 opx->segment |= SEG_RMREG;
561 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
564 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
570 uint8_t ximm = *data++;
572 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
573 ins->oprs[c >> 3].segment |= SEG_RMREG;
574 ins->oprs[c & 7].offset = ximm & 15;
580 uint8_t ximm = *data++;
586 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
587 ins->oprs[c >> 4].segment |= SEG_RMREG;
593 uint8_t ximm = *data++;
595 opx->basereg = (ximm >> 4) & regmask;
596 opx->segment |= SEG_RMREG;
610 if (((modrm >> 3) & 07) != (c & 07))
611 return false; /* spare field doesn't match up */
612 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
625 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
628 if ((vexm & 0x1f) != prefix->vex_m)
631 switch (vexwlp & 060) {
633 if (prefix->rex & REX_W)
637 if (!(prefix->rex & REX_W))
641 case 040: /* VEX.W is a don't care */
648 /* The 010 bit of vexwlp is set if VEX.L is ignored */
649 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
653 if (prefix->vex_v != 0)
656 opx->segment |= SEG_RMREG;
657 opx->basereg = prefix->vex_v;
664 if (prefix->rep == 0xF3)
669 if (prefix->rep == 0xF2)
671 else if (prefix->rep == 0xF3)
676 if (prefix->lock == 0xF0) {
677 if (prefix->rep == 0xF2)
679 else if (prefix->rep == 0xF3)
699 if (asize != segsize)
713 if (prefix->rex & REX_B)
718 if (prefix->rex & REX_X)
723 if (prefix->rex & REX_R)
728 if (prefix->rex & REX_W)
747 if (osize != (segsize == 16) ? 16 : 32)
754 ins->rex |= REX_W; /* 64-bit only instruction */
771 int t = *r++, d = *data++;
772 if (d < t || d > t + 15)
775 ins->condition = d - t;
780 if (prefix->rep == 0xF3)
790 if (prefix->rep != 0xF2)
796 if (prefix->rep != 0xF3)
821 if (prefix->wait != 0x9B)
827 if (prefix->osp || prefix->rep)
832 if (!prefix->osp || prefix->rep)
872 return false; /* Unknown code */
876 if (!vex_ok && (ins->rex & REX_V))
879 /* REX cannot be combined with VEX */
880 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
884 * Check for unused rep or a/o prefixes.
886 for (i = 0; i < t->operands; i++) {
887 if (ins->oprs[i].segment != SEG_RMREG)
892 if (ins->prefixes[PPS_LOCK])
894 ins->prefixes[PPS_LOCK] = P_LOCK;
897 if (ins->prefixes[PPS_REP])
899 ins->prefixes[PPS_REP] = drep;
901 ins->prefixes[PPS_WAIT] = dwait;
903 if (osize != ((segsize == 16) ? 16 : 32)) {
904 enum prefixes pfx = 0;
918 if (ins->prefixes[PPS_OSIZE])
920 ins->prefixes[PPS_OSIZE] = pfx;
923 if (!a_used && asize != segsize) {
924 if (ins->prefixes[PPS_ASIZE])
926 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
929 /* Fix: check for redundant REX prefixes */
931 return data - origdata;
934 /* Condition names for disassembly, sorted by x86 code */
935 static const char * const condition_name[16] = {
936 "o", "no", "c", "nc", "z", "nz", "na", "a",
937 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
940 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
941 int32_t offset, int autosync, uint32_t prefer)
943 const struct itemplate * const *p, * const *best_p;
944 const struct disasm_index *ix;
946 int length, best_length = 0;
948 int i, slen, colon, n;
952 uint32_t goodness, best;
954 struct prefix_info prefix;
957 memset(&ins, 0, sizeof ins);
962 memset(&prefix, 0, sizeof prefix);
963 prefix.asize = segsize;
964 prefix.osize = (segsize == 64) ? 32 : segsize;
971 while (!end_prefix) {
975 prefix.rep = *data++;
979 prefix.wait = *data++;
983 prefix.lock = *data++;
987 segover = "cs", prefix.seg = *data++;
990 segover = "ss", prefix.seg = *data++;
993 segover = "ds", prefix.seg = *data++;
996 segover = "es", prefix.seg = *data++;
999 segover = "fs", prefix.seg = *data++;
1002 segover = "gs", prefix.seg = *data++;
1006 prefix.osize = (segsize == 16) ? 32 : 16;
1007 prefix.osp = *data++;
1010 prefix.asize = (segsize == 32) ? 16 : 32;
1011 prefix.asp = *data++;
1016 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1017 prefix.vex[0] = *data++;
1018 prefix.vex[1] = *data++;
1021 prefix.vex_c = RV_VEX;
1023 if (prefix.vex[0] == 0xc4) {
1024 prefix.vex[2] = *data++;
1025 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1026 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1027 prefix.vex_m = prefix.vex[1] & 0x1f;
1028 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1029 prefix.vex_lp = prefix.vex[2] & 7;
1031 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1033 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1034 prefix.vex_lp = prefix.vex[1] & 7;
1037 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1043 if ((data[1] & 030) != 0 &&
1044 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1045 prefix.vex[0] = *data++;
1046 prefix.vex[1] = *data++;
1047 prefix.vex[2] = *data++;
1050 prefix.vex_c = RV_XOP;
1052 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1053 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1054 prefix.vex_m = prefix.vex[1] & 0x1f;
1055 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1056 prefix.vex_lp = prefix.vex[2] & 7;
1058 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1079 if (segsize == 64) {
1080 prefix.rex = *data++;
1081 if (prefix.rex & REX_W)
1093 best = -1; /* Worst possible */
1095 best_pref = INT_MAX;
1098 return 0; /* No instruction table at all... */
1102 while (ix->n == -1) {
1103 ix = (const struct disasm_index *)ix->p + *dp++;
1106 p = (const struct itemplate * const *)ix->p;
1107 for (n = ix->n; n; n--, p++) {
1108 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1111 * Final check to make sure the types of r/m match up.
1112 * XXX: Need to make sure this is actually correct.
1114 for (i = 0; i < (*p)->operands; i++) {
1116 /* If it's a mem-only EA but we have a
1118 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1119 is_class(MEMORY, (*p)->opd[i])) ||
1120 /* If it's a reg-only EA but we have a memory
1122 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1123 !(REG_EA & ~(*p)->opd[i]) &&
1124 !((*p)->opd[i] & REG_SMASK)) ||
1125 /* Register type mismatch (eg FS vs REG_DESS):
1127 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1128 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1129 !whichreg((*p)->opd[i],
1130 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1138 * Note: we always prefer instructions which incorporate
1139 * prefixes in the instructions themselves. This is to allow
1140 * e.g. PAUSE to be preferred to REP NOP, and deal with
1141 * MMX/SSE instructions where prefixes are used to select
1142 * between MMX and SSE register sets or outright opcode
1147 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1149 for (i = 0; i < MAXPREFIX; i++)
1150 if (tmp_ins.prefixes[i])
1152 if (nprefix < best_pref ||
1153 (nprefix == best_pref && goodness < best)) {
1154 /* This is the best one found so far */
1157 best_pref = nprefix;
1158 best_length = length;
1166 return 0; /* no instruction was matched */
1168 /* Pick the best match */
1170 length = best_length;
1174 /* TODO: snprintf returns the value that the string would have if
1175 * the buffer were long enough, and not the actual length of
1176 * the returned string, so each instance of using the return
1177 * value of snprintf should actually be checked to assure that
1178 * the return value is "sane." Maybe a macro wrapper could
1179 * be used for that purpose.
1181 for (i = 0; i < MAXPREFIX; i++) {
1182 const char *prefix = prefix_name(ins.prefixes[i]);
1184 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1188 if (i >= FIRST_COND_OPCODE)
1189 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1190 nasm_insn_names[i], condition_name[ins.condition]);
1192 slen += snprintf(output + slen, outbufsize - slen, "%s",
1193 nasm_insn_names[i]);
1196 length += data - origdata; /* fix up for prefixes */
1197 for (i = 0; i < (*p)->operands; i++) {
1198 opflags_t t = (*p)->opd[i];
1199 const operand *o = &ins.oprs[i];
1202 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1205 if (o->segment & SEG_RELATIVE) {
1206 offs += offset + length;
1208 * sort out wraparound
1210 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1212 else if (segsize != 64)
1216 * add sync marker, if autosync is on
1227 if ((t & (REGISTER | FPUREG)) ||
1228 (o->segment & SEG_RMREG)) {
1230 reg = whichreg(t, o->basereg, ins.rex);
1232 slen += snprintf(output + slen, outbufsize - slen, "to ");
1233 slen += snprintf(output + slen, outbufsize - slen, "%s",
1234 nasm_reg_names[reg-EXPR_REG_START]);
1235 } else if (!(UNITY & ~t)) {
1236 output[slen++] = '1';
1237 } else if (t & IMMEDIATE) {
1240 snprintf(output + slen, outbufsize - slen, "byte ");
1241 if (o->segment & SEG_SIGNED) {
1244 output[slen++] = '-';
1246 output[slen++] = '+';
1248 } else if (t & BITS16) {
1250 snprintf(output + slen, outbufsize - slen, "word ");
1251 } else if (t & BITS32) {
1253 snprintf(output + slen, outbufsize - slen, "dword ");
1254 } else if (t & BITS64) {
1256 snprintf(output + slen, outbufsize - slen, "qword ");
1257 } else if (t & NEAR) {
1259 snprintf(output + slen, outbufsize - slen, "near ");
1260 } else if (t & SHORT) {
1262 snprintf(output + slen, outbufsize - slen, "short ");
1265 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1267 } else if (!(MEM_OFFS & ~t)) {
1269 snprintf(output + slen, outbufsize - slen,
1270 "[%s%s%s0x%"PRIx64"]",
1271 (segover ? segover : ""),
1272 (segover ? ":" : ""),
1273 (o->disp_size == 64 ? "qword " :
1274 o->disp_size == 32 ? "dword " :
1275 o->disp_size == 16 ? "word " : ""), offs);
1277 } else if (is_class(REGMEM, t)) {
1278 int started = false;
1281 snprintf(output + slen, outbufsize - slen, "byte ");
1284 snprintf(output + slen, outbufsize - slen, "word ");
1287 snprintf(output + slen, outbufsize - slen, "dword ");
1290 snprintf(output + slen, outbufsize - slen, "qword ");
1293 snprintf(output + slen, outbufsize - slen, "tword ");
1296 snprintf(output + slen, outbufsize - slen, "oword ");
1299 snprintf(output + slen, outbufsize - slen, "yword ");
1301 slen += snprintf(output + slen, outbufsize - slen, "far ");
1304 snprintf(output + slen, outbufsize - slen, "near ");
1305 output[slen++] = '[';
1307 slen += snprintf(output + slen, outbufsize - slen, "%s",
1308 (o->disp_size == 64 ? "qword " :
1309 o->disp_size == 32 ? "dword " :
1310 o->disp_size == 16 ? "word " :
1312 if (o->eaflags & EAF_REL)
1313 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1316 snprintf(output + slen, outbufsize - slen, "%s:",
1320 if (o->basereg != -1) {
1321 slen += snprintf(output + slen, outbufsize - slen, "%s",
1322 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1325 if (o->indexreg != -1) {
1327 output[slen++] = '+';
1328 slen += snprintf(output + slen, outbufsize - slen, "%s",
1329 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1332 snprintf(output + slen, outbufsize - slen, "*%d",
1338 if (o->segment & SEG_DISP8) {
1340 uint8_t offset = offs;
1341 if ((int8_t)offset < 0) {
1348 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1350 } else if (o->segment & SEG_DISP16) {
1352 uint16_t offset = offs;
1353 if ((int16_t)offset < 0 && started) {
1357 prefix = started ? "+" : "";
1360 snprintf(output + slen, outbufsize - slen,
1361 "%s0x%"PRIx16"", prefix, offset);
1362 } else if (o->segment & SEG_DISP32) {
1363 if (prefix.asize == 64) {
1365 uint64_t offset = (int64_t)(int32_t)offs;
1366 if ((int32_t)offs < 0 && started) {
1370 prefix = started ? "+" : "";
1373 snprintf(output + slen, outbufsize - slen,
1374 "%s0x%"PRIx64"", prefix, offset);
1377 uint32_t offset = offs;
1378 if ((int32_t) offset < 0 && started) {
1382 prefix = started ? "+" : "";
1385 snprintf(output + slen, outbufsize - slen,
1386 "%s0x%"PRIx32"", prefix, offset);
1389 output[slen++] = ']';
1392 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1396 output[slen] = '\0';
1397 if (segover) { /* unused segment override */
1399 int count = slen + 1;
1401 p[count + 3] = p[count];
1402 strncpy(output, segover, 2);
1409 * This is called when we don't have a complete instruction. If it
1410 * is a standalone *single-byte* prefix show it as such, otherwise
1411 * print it as a literal.
1413 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1415 uint8_t byte = *data;
1416 const char *str = NULL;
1450 str = (segsize == 16) ? "o32" : "o16";
1453 str = (segsize == 32) ? "a16" : "a32";
1471 if (segsize == 64) {
1472 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1473 (byte == REX_P) ? "" : ".",
1474 (byte & REX_W) ? "w" : "",
1475 (byte & REX_R) ? "r" : "",
1476 (byte & REX_X) ? "x" : "",
1477 (byte & REX_B) ? "b" : "");
1480 /* else fall through */
1482 snprintf(output, outbufsize, "db 0x%02x", byte);
1487 snprintf(output, outbufsize, "%s", str);